This is to prepare for switching to generic PciHostBridge driver. We
are going to create a PciHostBridgeLib instance for D0x and fetch
PCI root bridge informance from PlatformPciLib, so we add Segment to
PCI_ROOT_BRIDGE_RESOURCE_APPETURE along with other PCI resource
information. Segment numbers are kept the same as ACPI MCFG.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi....@linaro.org>
---
Silicon/Hisilicon/Include/Library/PlatformPciLib.h | 1 +
Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 8 ++++++++
Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 16
++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
index 9d28fec37546..6725a547d54f 100644
--- a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
+++ b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
@@ -190,6 +190,7 @@ extern UINT64
PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
typedef struct {
+ UINT32 Segment;
UINT64 Ecam;
UINT64 BusBase;
UINT64 BusLimit;
diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
index c58118fe5e7a..3a770d17bb3d 100644
--- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
+++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
@@ -28,6 +28,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 0
/* Port 0 */
{
+ 0, //Segment
PCI_HB0RB0_ECAM_BASE, //ecam
0, //BusBase
31, //BusLimit
@@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 1, //Segment
PCI_HB0RB1_ECAM_BASE,//ecam
224, //BusBase
254, //BusLimit
@@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 2, //Segment
PCI_HB0RB2_ECAM_BASE,
128, //BusBase
159, //BusLimit
@@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 3, //Segment
PCI_HB0RB3_ECAM_BASE,
96, //BusBase
127, //BusLimit
@@ -92,6 +96,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 1
/* Port 0 */
{
+ 4, //Segment
PCI_HB1RB0_ECAM_BASE,
128, //BusBase
159, //BusLimit
@@ -107,6 +112,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 5, //Segment
PCI_HB1RB1_ECAM_BASE,
160, //BusBase
191, //BusLimit
@@ -122,6 +128,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 6, //Segment
PCI_HB1RB2_ECAM_BASE,
192, //BusBase
223, //BusLimit
@@ -138,6 +145,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 7, //Segment
PCI_HB1RB3_ECAM_BASE,
224, //BusBase
255, //BusLimit
diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
index c8e20356f818..c511a0ecbb52 100644
--- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
+++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
@@ -29,6 +29,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 0
/* Port 0 */
{
+ 0, //Segment
PCI_HB0RB0_ECAM_BASE, //ecam
0x80, //BusBase
0x87, //BusLimit
@@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 1, //Segment
PCI_HB0RB1_ECAM_BASE,//ecam
0x90, //BusBase
0x97, //BusLimit
@@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 2, //Segment
PCI_HB0RB2_ECAM_BASE,
0x80, //BusBase
0x87, //BusLimit
@@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 3, //Segment
PCI_HB0RB3_ECAM_BASE,
0xb0, //BusBase
0xb7, //BusLimit
@@ -90,6 +94,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 4 */
{
+ 4, //Segment
PCI_HB0RB4_ECAM_BASE, //ecam
0x88, //BusBase
0x8f, //BusLimit
@@ -105,6 +110,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 5 */
{
+ 5, //Segment
PCI_HB0RB5_ECAM_BASE,//ecam
0x0, //BusBase
0x7, //BusLimit
@@ -120,6 +126,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 6 */
{
+ 6, //Segment
PCI_HB0RB6_ECAM_BASE,
0xC0, //BusBase
0xC7, //BusLimit
@@ -136,6 +143,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 7 */
{
+ 7, //Segment
PCI_HB0RB7_ECAM_BASE,
0x90, //BusBase
0x97, //BusLimit
@@ -153,6 +161,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 1
/* Port 0 */
{
+ 8, //Segment
PCI_HB1RB0_ECAM_BASE,
0x80, //BusBase
0x87, //BusLimit
@@ -168,6 +177,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 9, //Segment
PCI_HB1RB1_ECAM_BASE,
0x90, //BusBase
0x97, //BusLimit
@@ -183,6 +193,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 0xa, //Segment
PCI_HB1RB2_ECAM_BASE,
0x10, //BusBase
0x1f, //BusLimit
@@ -199,6 +210,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 0xb, //Segment
PCI_HB1RB3_ECAM_BASE,
0xb0, //BusBase
0xb7, //BusLimit
@@ -214,6 +226,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 4 */
{
+ 0xc, //Segment
PCI_HB1RB4_ECAM_BASE,
0x20, //BusBase
0x2f, //BusLimit
@@ -229,6 +242,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 5 */
{
+ 0xd, //Segment
PCI_HB1RB5_ECAM_BASE,
0x30, //BusBase
0x3f, //BusLimit
@@ -244,6 +258,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 6 */
{
+ 0xe, //Segment
PCI_HB1RB6_ECAM_BASE,
0xa8, //BusBase
0xaf, //BusLimit
@@ -260,6 +275,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE
mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 7 */
{
+ 0xf, //Segment
PCI_HB1RB7_ECAM_BASE,
0xb8, //BusBase
0xbf, //BusLimit
--
2.7.4
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