Re: [edk2] [PATCH edk2-platforms v1 5/6] Hisilicon/D05/Pcie: optimize two pcie ports space
On 27 June 2018 at 09:04, Ming Huang wrote: > Optimize pcie space for promoting usage rate.Change regions order > of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion > can satisfy the requirement of larger address alignment. > OK, so I suppose it is the ECAM shift mode that is forcing you to change the bus ranges if you move the config space around, no? > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > Signed-off-by: Heyi Guo > --- > Platform/Hisilicon/D05/D05.dsc | 12 > Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 8 ++--- > Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 8 ++--- > Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc| 8 ++--- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 > ++-- > 5 files changed, 34 insertions(+), 34 deletions(-) > > diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc > index 0e6d5912a0..ab7c5caf86 100644 > --- a/Platform/Hisilicon/D05/D05.dsc > +++ b/Platform/Hisilicon/D05/D05.dsc > @@ -305,13 +305,13 @@ >gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf >gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa940 >gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf > - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa880 > + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa800 >gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f >gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab40 >gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf >gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa900 >gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff > - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb080 > + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb000 >gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f >gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac90 >gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f > @@ -336,10 +336,10 @@ > >gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA840 >gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA940 > - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA880 > + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA800 >gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB40 >gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A900 > - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B080 > + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B000 >gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC90 >gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B980 >gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A840 > @@ -353,10 +353,10 @@ > >gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff >gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff > - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff > + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f >gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff >gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff > - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff > + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f >gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff >gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff >gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff > diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c > b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c > index 57283a1053..ed6c4ac321 100644 > --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c > +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c > @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE > mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO >/* Port 2 */ >{ >PCI_HB0RB2_ECAM_BASE, > - 0x80, //BusBase > - 0x87, //BusLimit > + 0xF8, //BusBase > + 0xFF, //BusLimit >PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase >PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit >(PCI_HB0RB2_IO_BASE), //IOBase > @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE > mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO >/* Port 5 */ >{ >PCI_HB0RB5_ECAM_BASE,//ecam > - 0x0, //BusBase > - 0x7, //BusLimit > + 0x78, //BusBase > + 0x7F, //BusLimit >PCI_HB0RB5_CPUMEMREGIONBASE, //Membase >PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit >(PCI_HB0RB5_IO_BASE), //IoBase > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl > b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl > index 50ccac1b06..9955f6dbeb 100644 > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl > +++
[edk2] [PATCH edk2-platforms v1 5/6] Hisilicon/D05/Pcie: optimize two pcie ports space
Optimize pcie space for promoting usage rate.Change regions order of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion can satisfy the requirement of larger address alignment. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 12 Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc| 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 ++-- 5 files changed, 34 insertions(+), 34 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 0e6d5912a0..ab7c5caf86 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -305,13 +305,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa940 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa880 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa800 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab40 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa900 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb080 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac90 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f @@ -336,10 +336,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA840 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA940 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA880 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA800 gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB40 gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A900 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B080 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC90 gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B980 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A840 @@ -353,10 +353,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 57283a1053..ed6c4ac321 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 2 */ { PCI_HB0RB2_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit + 0xF8, //BusBase + 0xFF, //BusLimit PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 5 */ { PCI_HB0RB5_ECAM_BASE,//ecam - 0x0, //BusBase - 0x7, //BusLimit + 0x78, //BusBase + 0x7F, //BusLimit PCI_HB0RB5_CPUMEMREGIONBASE, //Membase PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB5_IO_BASE), //IoBase diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 50ccac1b06..9955f6dbeb 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -412,9 +412,9 @@ [0004] ATS Attribute : [0004] PCI Segment Number : 0002 -[0004] Input base : 8000 +[0004] Input base : f800 [0004] ID Count : 0800 -[0004]Output Base : 8000 +[0004]