Re: [Emc-developers] serious PCIe parallel port problem

[Jon Elson]

Well, everything you know is wrong!

NetMos used to be the PCI parport chip that was known to not 
work in EPP mode.  (That really only applied to the NM9805 
and maybe 9815 chips.  But, it was a bad reputation.)

Now, we see that the Oxford OXPCIe952 chip doesn't work, or 
is at least different enough that the code we've been using 
for 15 years doesn't work with it.  And, the NetMos 9900 
chip works like a champ!

So, the Syba PCIe parallel port uses the NetMos 9900 chip, 
and is quite affordable from such outfits as NewEgg and Amazon.

The Oxford chip is used in such boards as Startech PEX1P, 
SIIG DP 1-Port ECP/EPP Parallel PCIe and the Rosewill 
RC-302E (I didn't even test this one, it uses the same chip.)

I'm not sure what they've done to break it, but I put 0x04 
in the DCR to write and 0x24 in the DCR to read, and have 
used this code since 2001.  When the DCR has 0x24 in it, it 
will not produce the DATASTB/ pulse when there
is an INB instruction executed to the EPP data port register.

I will have to update my documentation on what parport cards 
work.

Jon

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Re: [Emc-developers] serious PCIe parallel port problem

[Jon Elson]

On 04/09/2016 05:13 PM, bari wrote:
> Jon,
>
> I've been using these the past 2 years:
>
> http://www.ebay.com/itm/Parallel-Port-DB25-LPT-Printer-to-PCI-E-PCI-Express-Card-Adapter-Converter-/181127386371
>
>
Thanks, Bari!  As this one is going to take a long time to 
get here, I also ordered a Syba card from Amazon, so I can 
get this customer something that works.  But, if these also 
work, I think I'm going to stock them.  Geez, if I had EVER 
known how much trouble crummy, non-compliant EPP ports were 
going to be, I'd have NEVER developed this line of products 
using them.  It has been rather smooth sailing since 2006 or 
so, so I thought the makers of these things had it figured 
out!  Silly me!

Jon

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Re: [Emc-developers] serious PCIe parallel port problem

[Jon Elson]

On 04/09/2016 04:57 PM, Gene Heskett wrote:
> But its sure sounding like one of you two ought to find 
> 1000 or more chips that you know do work, buy them at 
> graveyard prices, and build us a board that DOES work. I 
> believe the parport may be a victim of the "everybody is 
> useing usb for that stuff now" mentality in the chip 
> makers board rooms.
I've been building stuff using EPP mode since 2001.  I have 
been using almost exactly the same code, and definitely the 
same sequences of operations on the I/O port registers since 
then.  We did find, along the way, a few parallel port cards 
and motherboard multi-I/O chips that just got it totally 
wrong.  The NetMos 9805 is pretty famous for advertising 
DEEP in their datasheet that EPP mode does NOT work.

Up to this point, I have never had a problem with SIIG, but 
that was all PCI (not express).  I have also never had a 
problem with Dell motherboard parallel ports, except they 
had a little BIOS quirk, so we have to force the port to EPP 
mode, even though the BIOS says it is not supported.

So, this was a great big surprise, that code that has been 
working for almost 15 years just doesn't work on these cards!

It is all MicroSoft's fault, of course.  They wrote the 
original EPP spec, and it is the loosest piece of electrical 
specification I've ever seen.  Lots of timing diagrams, but 
not a specification of timing anywhere on them.  And, some 
parport cards actually manage to violate that.  So, 
MicroSoft's document shows the data and WRITE/ lines 
stabilizing before the strobe, but some boards generate the 
strobe BEFORE the data lines and WRITE/ are sent!
Geez, why write a standard in the first place??

I've found a Syba parport card at NewEgg and Amazon, that is 
reasonably priced, and clearly does NOT use the Oxford chip.
So, I will get one of those to test.

Jon

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Re: [Emc-developers] serious PCIe parallel port problem

[bari]

Jon,

I've been using these the past 2 years:

http://www.ebay.com/itm/Parallel-Port-DB25-LPT-Printer-to-PCI-E-PCI-Express-Card-Adapter-Converter-/181127386371

chipset WCH CH382L.

On 04/09/2016 03:21 PM, Jon Elson wrote:
> On 04/09/2016 03:16 PM, Peter C. Wallace wrote:
>> You might see if the data sheet is available from
>> Avago
>>
>> (Oxsemi was bought out by PLXTech which was subsequently bought out by
>> Avago)
>>
>>
>>
> Thanks!  Do you know of a PCIe card that works in EPP mode
> with your hardware?  I'd always had good luck with SIIG
> until just now.  All the other PCIe boards are using the
> same chip.
>
> But, I'll look for that data sheet.
>
> Jon
>
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Re: [Emc-developers] serious PCIe parallel port problem

[Gene Heskett]

On Saturday 09 April 2016 16:35:04 Jon Elson wrote:

> On 04/09/2016 03:16 PM, Peter C. Wallace wrote:
> > You might see if the data sheet is available from
> > Avago
> >
> > (Oxsemi was bought out by PLXTech which was subsequently bought out
> > by Avago)
>
And according to a google search when avago.com turned up with a for sale 
sign on it just now, but a few links down that same google search page, 
it says avago has offered broadcom 37 Billion to buy broadcom.  All that 
is way above my pay grade.  And it smells like a market crash if it 
weren't for the bloomberg story.

But its sure sounding like one of you two ought to find 1000 or more 
chips that you know do work, buy them at graveyard prices, and build us 
a board that DOES work.

I believe the parport may be a victim of the "everybody is useing usb for 
that stuff now" mentality in the chip makers board rooms. We're such a 
small piece of that market that we don't count.



> The data sheet is easily available, and quite awful!  It
> says the EPP timeout is 10 ms (I measured it at 10 us).
> They describe the EPP register bits by name in a table, and
> really have NO TEXT describing what they do at ALL!  The
> entire EPP section is about one page, after about 30 pages
> of info on the UART function.
>
> Jon
>
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Cheers, Gene Heskett
-- 
"There are four boxes to be used in defense of liberty:
 soap, ballot, jury, and ammo. Please use in that order."
-Ed Howdershelt (Author)
Genes Web page 

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Re: [Emc-developers] serious PCIe parallel port problem

[Jon Elson]

On 04/09/2016 03:16 PM, Peter C. Wallace wrote:
>
> You might see if the data sheet is available from
> Avago
>
> (Oxsemi was bought out by PLXTech which was subsequently bought out by
> Avago)
>
>
The data sheet is easily available, and quite awful!  It 
says the EPP timeout is 10 ms (I measured it at 10 us).
They describe the EPP register bits by name in a table, and 
really have NO TEXT describing what they do at ALL!  The 
entire EPP section is about one page, after about 30 pages 
of info on the UART function.

Jon

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Re: [Emc-developers] serious PCIe parallel port problem

[Jon Elson]

On 04/09/2016 03:16 PM, Peter C. Wallace wrote:
> You might see if the data sheet is available from
> Avago
>
> (Oxsemi was bought out by PLXTech which was subsequently bought out by
> Avago)
>
>
>
Thanks!  Do you know of a PCIe card that works in EPP mode 
with your hardware?  I'd always had good luck with SIIG 
until just now.  All the other PCIe boards are using the 
same chip.

But, I'll look for that data sheet.

Jon

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Re: [Emc-developers] serious PCIe parallel port problem

[Peter C. Wallace]

On Sat, 9 Apr 2016, Jon Elson wrote:

> Date: Sat, 09 Apr 2016 14:27:24 -0500
> From: Jon Elson <el...@pico-systems.com>
> Reply-To: EMC developers <emc-developers@lists.sourceforge.net>
> To: EMC developers <emc-developers@lists.sourceforge.net>
> Subject: [Emc-developers] serious PCIe parallel port problem
> 
> Well, I'm in BIG trouble.
>
> I have 3 PCIe parallel port cards here that are all doing
> the same thing.  They are, however, all the exact SAME PC
> board with the Oxford OXPCIe952 chip.  They are branded
> SIIG, Startech and Rosewill.  I cannot get them to work with
> my PPMC-family boards.  I hooked up the logic analyzer, and
> my diagnostic program does a series of writes to the board
> that all look OK.  Then, it tries to enumerate the board,
> and this involves an address write and then a data read, and
> the read is not performed at ALL.  (The data writes
> performed previously all look fine, WRITE/ is asserted with
> the data lines, then DATASTB/ is pulsed and WAIT/
> acknowledges the cycle.) For the reads, WRITE/ goes low with
> the address to be read on the data lines, ADDRSTB/ is
> pulsed, WAIT/ acknowledges it.  THEN, WRITE/ is supposed to
> stay high, and DATASTB/ SHOULD be pulsed, but NOTHING happens!
>
> The only thing I can figure is that the reconfiguration I've
> been using for well over a DECADE to turn the bus from write
> mode to read mode has somehow disabled the EPP data cycle.
>
> As far as I know, the way I'm doing this is approved and
> recommended by all the experts who have written how to do
> EPP transfers at the PC register level.
>
> Setting the port to write mode :  write 0x04 to controlport
>
> Setting the port to read  mode :  OR 0x20 to controlport
>
> Anybody ever done EPP programming that might have some ideas?
>
> Jon
>
>

You might see if the data sheet is available from
Avago

(Oxsemi was bought out by PLXTech which was subsequently bought out by 
Avago)


Peter Wallace
Mesa Electronics

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[Emc-developers] serious PCIe parallel port problem

[Jon Elson]

Well, I'm in BIG trouble.

I have 3 PCIe parallel port cards here that are all doing 
the same thing.  They are, however, all the exact SAME PC 
board with the Oxford OXPCIe952 chip.  They are branded 
SIIG, Startech and Rosewill.  I cannot get them to work with 
my PPMC-family boards.  I hooked up the logic analyzer, and 
my diagnostic program does a series of writes to the board 
that all look OK.  Then, it tries to enumerate the board, 
and this involves an address write and then a data read, and 
the read is not performed at ALL.  (The data writes 
performed previously all look fine, WRITE/ is asserted with 
the data lines, then DATASTB/ is pulsed and WAIT/ 
acknowledges the cycle.) For the reads, WRITE/ goes low with 
the address to be read on the data lines, ADDRSTB/ is 
pulsed, WAIT/ acknowledges it.  THEN, WRITE/ is supposed to 
stay high, and DATASTB/ SHOULD be pulsed, but NOTHING happens!

The only thing I can figure is that the reconfiguration I've 
been using for well over a DECADE to turn the bus from write 
mode to read mode has somehow disabled the EPP data cycle.

As far as I know, the way I'm doing this is approved and 
recommended by all the experts who have written how to do 
EPP transfers at the PC register level.

Setting the port to write mode :  write 0x04 to controlport

Setting the port to read  mode :  OR 0x20 to controlport

Anybody ever done EPP programming that might have some ideas?

Jon



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