Re: PCB layout question for good EMC performance
Dear all, Are you working with a MLB, if so how many layers and what is your stack assignment? I think if you are looking for a rule of thumb on layout density, you can end up literally barking up the wrong tree. I believe the correct rule of thumb is not to let a critical trace/track cross any of the ground/power layer. This Swiss cheese phenomena (presence of holes and gaps in the ground/power plane) result in large loop areas for the return current ( inductance) because the ground (return current 'image') plane was full of obstructions and obstacles. I assume that you are working with a 4 layer board, you could try to place the 'signal layer' over the ' ground /power' planes and see if the critical tracks/traces does cross any ground gaps. First check if the ground and power plane are all gapped in the same places. :-) best regards Tim Foo Ken Javor ken.javor@emccomplian To: emc-p...@majordomo.ieee.org ce.comcc: (bcc: Wan Juang Foo/ece/staff/npnet) Sent by: Subject: PCB layout question for good EMC performance owner-emc-pstc@majordo mo.ieee.org 06/08/02 04:19 AM Please respond to Ken Javor I have a problem where a very large number of chips are mounted on a very small board. The ground plane looks like Swiss cheese and there is ground bounce accordingly. For future reference, is there a rule-of-thumb for how much PCB area should be allocated per number of IC chips/pins so as to be able to provide ground returns for all important signal/clock routing? snip --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
Re: PCB layout question for good EMC performance
Thanks to all who replied on this question. Ken Javor -- From: emccom...@aol.com To: dave.clem...@motorola.com, ken.ja...@emccompliance.com, emc-p...@majordomo.ieee.org Subject: Re: PCB layout question for good EMC performance Date: Fri, Jun 7, 2002, 6:00 PM Hi Ken, Rent's Rule (spelled as in Howard and Graham's book) with a worked example is on pages 216-217. Good Luck with your problem, Thurman J. (Bill) Ritenour EMC Compliance LLC 4575 Sioux Drive #303 Boulder, CO 80303 303-543-7404 emccom...@aol.com --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
Re: PCB layout question for good EMC performance
Hi Ken, Rent's Rule (spelled as in Howard and Graham's book) with a worked example is on pages 216-217. Good Luck with your problem, Thurman J. (Bill) Ritenour EMC Compliance LLC 4575 Sioux Drive #303 Boulder, CO 80303 303-543-7404 emccom...@aol.com --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
RE: PCB layout question for good EMC performance
Check out High-Speed Digital Design by Howard Hohnson and Martin Graham. Rhents rule deals with this topic. Dave Clement Motorola Inc. Global Homologation Engineering 20 Cabot Blvd. Mansfield, MA 02048 P:508-851-8259 F:508-851-8512 C:508-725-9689 mailto:dave.clem...@motorola.com http://www.motorola.com/globalcompliance/ -Original Message- From: Ken Javor [mailto:ken.ja...@emccompliance.com] Sent: Friday, June 07, 2002 4:20 PM To: emc-p...@majordomo.ieee.org Subject: PCB layout question for good EMC performance I have a problem where a very large number of chips are mounted on a very small board. The ground plane looks like Swiss cheese and there is ground bounce accordingly. For future reference, is there a rule-of-thumb for how much PCB area should be allocated per number of IC chips/pins so as to be able to provide ground returns for all important signal/clock routing? --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
PCB layout question for good EMC performance
I have a problem where a very large number of chips are mounted on a very small board. The ground plane looks like Swiss cheese and there is ground bounce accordingly. For future reference, is there a rule-of-thumb for how much PCB area should be allocated per number of IC chips/pins so as to be able to provide ground returns for all important signal/clock routing? --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
