[ewg] RE: Post receive WR to QP in error state

2007-08-15 Thread Tang, Changqing

Since implementor is more accurate that spec.  Thanks.

--CQ


> -Original Message-
> From: Roland Dreier [mailto:[EMAIL PROTECTED] 
> Sent: Wednesday, August 15, 2007 10:15 PM
> To: Tang, Changqing
> Cc: [EMAIL PROTECTED]; ewg@lists.openfabrics.org
> Subject: Re: Post receive WR to QP in error state
> 
>  >I read the IB specification, it does say posting send WR to QP
>  > in error state is OK, and the WR will be completed in 
> FLUSH error, but  > it does not say that for posting receive 
> WR. I want to check with you if  > "posting receive WR to QP 
> in error state returns SUCCESS, and the WR  > will be 
> completed with FLUSH error".  Thanks.
> 
> Not sure why I'm your spec interpreter, but I don't see 
> anything in the spec that distinguishes between how send and 
> receive requests are processed in the error state.  As far as 
> I know, all requests will be completed with a flush error.
> 
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[ewg] Re: Post receive WR to QP in error state

2007-08-15 Thread Roland Dreier
 >  I read the IB specification, it does say posting send WR to QP
 > in error state is OK, and the WR will be completed in FLUSH error, but
 > it does not say that for posting receive WR. I want to check with you if
 > "posting receive WR to QP in error state returns SUCCESS, and the WR
 > will be completed with FLUSH error".  Thanks.

Not sure why I'm your spec interpreter, but I don't see anything in
the spec that distinguishes between how send and receive requests are
processed in the error state.  As far as I know, all requests will be
completed with a flush error.
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[ewg] Re: OFED 1.2.5 issue with MSI ??

2007-08-15 Thread Roland Dreier
Please report OFED bugs to the appropriate list -- I have no idea what
mthca patches got stuck into OFED 1.2.5 to cause problems.  If you
want to test the latest 2.6.23-rc kernel to make sure things are OK
there then that might be useful.

 - R.
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[ewg] OFED 1.2.5 issue with MSI ??

2007-08-15 Thread Arlin Davis

I just noticed when setting up MSI support that ib_mthca fails with the 
following:

This is on 2 different Intel platforms that worked with OFED 1.2:

ib_mthca: Mellanox InfiniBand HCA driver v0.08 (February 14, 2006)
ib_mthca: Initializing :0a:00.0
ACPI: PCI interrupt :0a:00.0[A] -> GSI 16 (level, low) -> IRQ 169
PCI: Setting latency timer of device :0a:00.0 to 64
ib_mthca :0a:00.0: NOP command failed to generate interrupt (IRQ 233), 
aborting.
ib_mthca :0a:00.0: Try again with MSI/MSI-X disabled.
ib_mthca: probe of :0a:00.0 failed with error -16

lspci -v v
0a:00.0 InfiniBand: Mellanox Technologies MT25208 InfiniHost III Ex (Tavor 
compatibility mode) (rev
a0)
Subsystem: Mellanox Technologies MT25208 InfiniHost III Ex (Tavor 
compatibility mode)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-
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[ewg] Post receive WR to QP in error state

2007-08-15 Thread Tang, Changqing

Roland:

I read the IB specification, it does say posting send WR to QP
in error state is OK, and the WR will be completed in FLUSH error, but
it does not say that for posting receive WR. I want to check with you if
"posting receive WR to QP in error state returns SUCCESS, and the WR
will be completed with FLUSH error".  Thanks.


--CQ

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Re: [ewg] Re: OFED Aug 13 meeting summary

2007-08-15 Thread Stefan Roscher
On Tuesday 14 August 2007 18:12, Tziporet Koren wrote:

> >  
> > I pushed a fix for this out in my tree, so Vlad will take it in 1.2.c 
> > branch.
> >
> >   
> Vlad will take this patch, and we will do a new build with it.
> This will delay the 1.2.5 release for tomorrow :-(

Hi,
we tested the ofa_1_2_c_kernel-20070815-0200.tgz from today.
The changes are applied and we successfully built the package on SLES10 and 
rhel-4.5.

All works fine for us.

regards Stefan

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