Re: SMP P4 Xeons out there?
the # of cpus dos not change when enabling/disabling hyperthread, 4.6 only sees 2. mptable: === MPTable, version 2.0.15 --- MP Floating Pointer Structure: location: BIOS physical address: 0x000f6670 signature:'_MP_' length: 16 bytes version: 1.4 checksum: 0x68 mode: Virtual Wire --- MP Config Table Header: physical address: 0x0009bf70 signature:'PCMP' base table length:324 version: 1.4 checksum: 0xcb OEM ID: ' ' Product ID: 'SE7500CW2' OEM table pointer:0x OEM table size: 0 entry count: 32 local APIC address: 0xfee0 extended table length:144 extended table checksum: 98 --- MP Config Base Table Entries: -- Processors: APIC ID Version State Family Model StepFlags 0 0x14BSP, usable 15 2 4 0x3febfbff 6 0x14AP, usable 15 2 4 0x3febfbff -- Bus:Bus ID Type 0 PCI 1 PCI 2 PCI 3 PCI 4 PCI 5 ISA -- I/O APICs: APIC ID Version State Address 2 0x20usable 0xfec0 3 0x20usable 0xfec8 4 0x20usable 0xfec80400 -- I/O Ints: TypePolarityTrigger Bus ID IRQAPIC ID PIN# ExtINT active-hiedge5 0 20 INT active-hiedge5 1 21 INT active-hiedge5 0 22 INT active-lo level4 5:A 2 23 INT active-hiedge5 4 24 INT active-lo level0 29:B 2 19 INT active-hiedge5 6 26 INT active-hiedge5 7 27 INT active-hiedge5 8 28 INT active-hiedge5 9 29 INT active-lo level0 29:A 2 16 INT active-lo level0 31:B 2 17 INT active-hiedge512 2 12 INT active-hiedge513 2 13 INT active-hiedge514 2 14 INT active-hiedge515 2 15 INT active-lo level4 3:A 2 21 INT active-lo level4 4:A 2 20 INT active-lo level4 6:A 2 22 -- Local Ints: TypePolarityTrigger Bus ID IRQAPIC ID PIN# ExtINT active-hiedge5 02550 NMI active-hiedge5 02551 --- MP Config Extended Table Entries: -- System Address Space bus ID: 0 address type: I/O address address base: 0x0 address range: 0x1 -- System Address Space bus ID: 0 address type: memory address address base: 0x4000 address range: 0xbee0 -- System Address Space bus ID: 0 address type: memory address address base: 0xfee01000 address range: 0x11ff000 -- System Address Space bus ID: 4 address type: memory address address base: 0xa address range: 0x2 -- System Address Space bus ID: 4 address type: memory address address base: 0xcc000 address range: 0x18000 -- System Address Space bus ID: 0 address type: memory address address base: 0x3ff8 address range: 0x8 -- Bus Heirarchy bus ID: 5 bus info: 0x01 parent bus ID: 0 -- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x -- Compatibility Bus Address bus ID: 0 address modifier: add predefined range: 0x0001 === To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-hackers"
Re: SMP P4 Xeons out there?
Lars Eggert wrote: > Doug White wrote: >> >> Anyone other there with multiprocessor P4 Xeon systems with >> Hyperthreading enabled that are seeing 4 CPUs show up on boot? > > Not yet, but we're expecting some Dell Precision 530s later this week > - I'll let you know. Just got them, and no, 4.6-RELEASE only sees two CPUs with hyperthreading, not four. Lars -- Lars Eggert <[EMAIL PROTECTED]> USC Information Sciences Institute smime.p7s Description: S/MIME Cryptographic Signature
RE: SMP P4 Xeons out there?
On Wed, 21 Aug 2002, John Baldwin wrote: > Newer P4 Xeon's do enumerate all CPU's via the mptable. We use ACPI to > enumerate CPU's for ia64 SMP, so at some point it could be backported > if needed. What's a "newer" P4 Xeon? :-) The two I have downstairs don't, and linux requires overriding the SMP initialization to use ACPI to make it work. I think the ones I have are 1.8's. -- Doug White| FreeBSD: The Power to Serve [EMAIL PROTECTED] | www.FreeBSD.org To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-hackers" in the body of the message
RE: SMP P4 Xeons out there?
On 10-Aug-2002 Doug White wrote: > Hey folks, > > Anyone other there with multiprocessor P4 Xeon systems with Hyperthreading > enabled that are seeing 4 CPUs show up on boot? > > If you are, can you mail me the output of 'mptable'? > > It appears you need to enumerate CPUs out of ACPI if you want the logical > CPUs to show up. FreeBSD doesn't appear to support this (yet -- correct me > if I've misread the MP init code), but some people are seeing 4 CPUs > anyway. I'm curious if those systems are modifying the mptable for the > benefit of non-ACPI systems. Newer P4 Xeon's do enumerate all CPU's via the mptable. We use ACPI to enumerate CPU's for ia64 SMP, so at some point it could be backported if needed. -- John Baldwin <[EMAIL PROTECTED]> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-hackers" in the body of the message
Re: SMP P4 Xeons out there?
Doug White wrote: > Hey folks, > > Anyone other there with multiprocessor P4 Xeon systems with Hyperthreading > enabled that are seeing 4 CPUs show up on boot? Not yet, but we're expecting some Dell Precision 530s later this week - I'll let you know. Lars -- Lars Eggert <[EMAIL PROTECTED]> USC Information Sciences Institute smime.p7s Description: S/MIME Cryptographic Signature
SMP P4 Xeons out there?
Hey folks, Anyone other there with multiprocessor P4 Xeon systems with Hyperthreading enabled that are seeing 4 CPUs show up on boot? If you are, can you mail me the output of 'mptable'? It appears you need to enumerate CPUs out of ACPI if you want the logical CPUs to show up. FreeBSD doesn't appear to support this (yet -- correct me if I've misread the MP init code), but some people are seeing 4 CPUs anyway. I'm curious if those systems are modifying the mptable for the benefit of non-ACPI systems. Systems that don't modify the mptable (board/chipset): Intel SE7500WV2 (Intel E7500) Dell PE2650 (Serverworks GC-HE) If anyone understands the Proper(tm) way to support hyperthreaded CPUs and can explain it that would be neat too. Intels docs are a little lean on the matter. Thanks! -- Doug White| FreeBSD: The Power to Serve [EMAIL PROTECTED] | www.FreeBSD.org To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-hackers" in the body of the message
