On 2005-09-07 15:21, Nils Vogels <[EMAIL PROTECTED]> wrote:
> Hi there !
>
> I'm trying to write a Makefile and it's my first time writing a bit more
> complex one .. I seem to be stuck and examples currently are not very
> helpful, so I thought I'd try here:
>
> What I am trying to do is differ the way of building depending if a
> variable has been defined, my current Makefile looks like this:
>
> build_1:
> @cd /build/dir && make OPTION=set
>
> build_2:
> @cd /build/dir && make
>
> build:
> .if defined(WANT_OPTION)
> HAS_OPTION?=1
> ${MAKE} build_1
> .else
> HAS_OPTION?=0
> ${MAKE} build_2 <-- error in this line
> .endif
If the indentation shown above is what you are truly using and not what
your mailer thinks is a good way to format it, you are missing vital
whitespace before the build commands of the ``build'' target.
Please note that the above makefile will build the build_1 target by
default, as this is the first target that appears in the Makefile.
I'd probably write this a little differently, moving all the conditional
material out of the target build commands:
#
# Pick the default target, depending on WANT_OPTION.
#
.if defined(WANT_OPTION)
HAVE_OPTION?= 1
BUILD_TARGET= build_1
.else
HAVE_OPTION?= 0
BUILD_TARGET= build_2
.endif
build: $(BUILD_TARGET)
build_1:
@cd /build/dir && make OPTION=set
build_2:
@cd /build/dir && make
> Whenever I run "make build" I get:
>
> "Makefile", line xx: Need an operator
> make: fatal errors encountered -- cannot continue
This is usually an indication of whitespace/indentation errors.
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