Dan Langille wrote:
Hi folks,
It appears I am not the first to buy a K7S5A motherboard (an SiS 735
chipset) with integrated NIC. I can't get my NIC to work either.
Bill: I'm ready to help with this. If you so wish, I can give you a
login on the box.
I received these two patches from J. Lemon. They sort of do something.
I can see the first two blocks of the MAC address but it doesn't move
to the next two pairs and that is as far as they go towards working. I
converted what JLemon sent to patches to stable. I have attached them.
I have two systems using the K7S5A motherboard and one that uses an
Amptron 830LM, which is also based on the SiS 735 chipset.
Kent
cheers.
--
Kent Stewart
Richland, WA
mailto:[EMAIL PROTECTED]
http://users.owt.com/kstewart/index.html
FreeBSD News http://daily.daemonnews.org/
--- if_sis.c.orig Sat Dec 29 03:45:11 2001
+++ if_sis.cSat Dec 29 04:40:18 2001
@@ -439,6 +439,31 @@
pci_write_config(bridge, 0x48, reg ~0x40, 1);
return;
}
+
+static void sis635_mac_addr(sc, dest)
+ struct sis_softc*sc;
+ caddr_t dest;
+{
+ u_int32_t filtsave;
+
+ filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
+
+ SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RELOAD);
+ CSR_WRITE_4(sc, SIS_CSR, 0);
+
+ /* Disable the the receive filter. */
+ SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
+
+ /* Get MAC address */
+ CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
+ ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
+ CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
+ ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
+ CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
+ ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
+
+ CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
+}
#endif
static int sis_miibus_readreg(dev, phy, reg)
@@ -891,6 +916,8 @@
command == SIS_REV_630E ||
command == SIS_REV_630EA1)
sis_read_cmos(sc, dev, (caddr_t)eaddr, 0x9, 6);
+ else if (command == SIS_REV_635A)
+ sis635_mac_addr(sc, (caddr_t)eaddr);
else
#endif
sis_read_eeprom(sc, (caddr_t)eaddr,
--- if_sisreg.h.origSat Dec 29 03:45:36 2001
+++ if_sisreg.h Sat Dec 29 03:58:00 2001
@@ -105,6 +105,7 @@
#define SIS_CSR_RX_RESET 0x0020
#define SIS_CSR_SOFTINTR 0x0080
#define SIS_CSR_RESET 0x0100
+#define SIS_CSR_RELOAD 0x0400
#define SIS_CFG_BIGENDIAN 0x0001
#define SIS_CFG_PERR_DETECT0x0008
@@ -367,6 +368,7 @@
#define SIS_REV_630E 0x0081
#define SIS_REV_630S 0x0082
#define SIS_REV_630EA1 0x0083
+#define SIS_REV_635A 0x0090
/*
* NatSemi vendor ID
@@ -410,6 +412,8 @@
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc-sis_btag, sc-sis_bhandle, reg, val)
+#define CSR_READ_2(sc, reg)\
+ bus_space_read_2(sc-sis_btag, sc-sis_bhandle, reg)
#define CSR_READ_4(sc, reg)\
bus_space_read_4(sc-sis_btag, sc-sis_bhandle, reg)
