Re: AcerLabs/ULi SATA woes

[Bruce M. Simpson]

Just for reference:
Soren has gotten back to me about this and has a patch pending. In the 
meantime here is the style(9)-ified patch from Sven which I am currently 
using (in 6.2-STABLE, CURRENT , and p4 branches).


Regards,
BMS
--- ata-chipset.c.orig  Wed May 23 17:59:28 2007
+++ ata-chipset.c   Wed May 23 18:00:44 2007
@@ -952,7 +952,7 @@
 struct ata_chip_id *idx;
 static struct ata_chip_id ids[] =
 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
- { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
+ { ATA_ALI_5288, 0x00, 4, ALIAHCI, ATA_SA300, "M5288" },
  { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
  { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
  { ATA_ALI_5229, 0xc5, 0, ALINEW,  ATA_UDMA6, "M5229" },
@@ -984,16 +984,19 @@
 
 switch (ctlr->chip->cfg2) {
 case ALISATA:
+case ALIAHCI:
ctlr->channels = ctlr->chip->cfg1;
ctlr->allocate = ata_ali_sata_allocate;
ctlr->setmode = ata_sata_setmode;
 
/* if we have a memory resource we can likely do AHCI */
-   ctlr->r_type2 = SYS_RES_MEMORY;
-   ctlr->r_rid2 = PCIR_BAR(5);
-   if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
-  &ctlr->r_rid2, RF_ACTIVE)))
-   return ata_ahci_chipinit(dev);
+   if (ctlr->chip->cfg2 == ALIAHCI) {
+   ctlr->r_type2 = SYS_RES_MEMORY;
+   ctlr->r_rid2 = PCIR_BAR(5);
+   if ((ctlr->r_res2 = bus_alloc_resource_any(dev,
+   ctlr->r_type2, &ctlr->r_rid2, RF_ACTIVE)))
+   return ata_ahci_chipinit(dev);
+   }
 
/* enable PCI interrupt */
pci_write_config(dev, PCIR_COMMAND,
--- ata-pci.h.orig  Wed May 23 18:00:53 2007
+++ ata-pci.h   Wed May 23 18:01:02 2007
@@ -360,6 +360,7 @@
 #define ALIOLD  0x01
 #define ALINEW  0x02
 #define ALISATA 0x04
+#define ALIAHCI 0x08
 
 #define HPT366  0
 #define HPT370  1
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Re: AcerLabs/ULi SATA woes

[Bruce M. Simpson]

A workaround for this issue posted here works for me with 6.2-STABLE:
   http://www.mail-archive.com/freebsd-stable@freebsd.org/msg87083.html

I plan to commit it on HEAD and RELENG_6 as soon as possible, as it 
fixes the regression introduced last year. It seems acceptable that the 
AHCI controller be degraded to legacy mode until such time as AHCI mode 
may be reliably enabled on this hardware. I don't have time to implement 
a better fix.


It seems there has been some Linux activity from the vendor. The 
controller on my system is the one described in the patch set for Linux: 
http://www.ussg.iu.edu/hypermail/linux/kernel/0412.2/0825.html


Regards,
BMS
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