[Freedreno] [DPU PATCH 17/19] drm/msm: dpu: Remove dsi debug block name
Leftover from dsi-staging, it looks like.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dpu_dbg.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 2a9b8c732e33..51d46975cc27 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -130,7 +130,6 @@ struct dpu_dbg_vbif_debug_bus {
* @dump_work: work struct for deferring register dump work to separate thread
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
- * @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
struct list_head reg_base_list;
@@ -140,7 +139,6 @@ static struct dpu_dbg_base {
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
- bool dsi_dbg_bus;
} dpu_dbg_base;
static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base,
@@ -2270,9 +2268,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
if (!strcmp(blk_name, "vbif_dbg_bus"))
dump_dbgbus_vbif_rt = true;
-
- if (!strcmp(blk_name, "dsi_dbg_bus"))
- dpu_dbg_base.dsi_dbg_bus = true;
}
va_end(args);
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 19/19] drm/msm: dpu: Move dpu_dbg into dpu1 directory
Now that dpu_dbg is cleaned up, move it into dpu directory with the
rest of dpu things.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c | 0
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.h | 0
3 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c (100%)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.h (100%)
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 9c182a9dab2b..1745447922bf 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -49,6 +49,7 @@ msm-y := \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
+ disp/dpu1/dpu_dbg.o \
disp/dpu1/dpu_encoder.o \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
@@ -74,7 +75,6 @@ msm-y := \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_mdss.o \
disp/dpu1/dpu_power_handle.o \
- dpu_dbg.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
similarity index 100%
rename from drivers/gpu/drm/msm/dpu_dbg.c
rename to drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
similarity index 100%
rename from drivers/gpu/drm/msm/dpu_dbg.h
rename to drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 15/19] drm/msm: dpu: Remove arbitrary register dumps
This can be achieved via /dev/mem. Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c| 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 - .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 - drivers/gpu/drm/msm/dpu_dbg.c | 716 +- drivers/gpu/drm/msm/dpu_dbg.h | 59 -- 10 files changed, 7 insertions(+), 822 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c index 24b0dbc76f3a..da6f0609be5f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c @@ -301,9 +301,6 @@ struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - /* * Perform any default initialization for the chroma down module * @setup default csc coefficients diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index ad02316fafce..06be7cf7ce50 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -524,9 +524,6 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 7386d4643115..d280df5613c9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -332,9 +332,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 5b4d529a1a89..4ab72b0f07a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -245,9 +245,6 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 12e90b8e5466..cc3a623903f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -234,9 +234,6 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 6640906e4f03..2b3f5e88af98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -734,20 +734,6 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, goto blk_init_error; } - if (!is_virtual_pipe) - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, - hw_pipe->hw.blk_off, - hw_pipe->hw.blk_off + hw_pipe->hw.length, - hw_pipe->hw.xin_id); - - if (cfg->sblk->scaler_blk.len && !is_virtual_pipe) - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, - cfg->sblk->scaler_blk.name, - hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base, - hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base + - cfg->sblk->scaler_blk.len, - hw_pipe->hw.xin_id); - return hw_pipe; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 115eeedd90e8..42fc72cf48dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -379,9 +379,6 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
[Freedreno] [DPU PATCH 18/19] drm/msm: dpu_dbg: Remove string parsing from DBG_DUMP
Now that we don't have arbitrary register dumping, remove the macro and
just call dpu_dbg_dump directly.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 37 +--
drivers/gpu/drm/msm/dpu_dbg.h | 23
5 files changed, 21 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 3519f7e84f0f..ce4faee12adc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys
*phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 19f5b5064ed8..9519dbc24266 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 54f4e78cf1fd..110c463077ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
+ dpu_dbg_dump(false, __func__, true, true);
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 51d46975cc27..ae2aee7ed9e1 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -2248,39 +2248,22 @@ static void _dpu_dump_work(struct work_struct *work)
dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
}
-void dpu_dbg_dump(bool queue_work, const char *name, ...)
+void dpu_dbg_dump(bool queue_work, const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt)
{
- bool dump_dbgbus_dpu = false;
- bool dump_dbgbus_vbif_rt = false;
- va_list args;
- char *blk_name = NULL;
-
if (queue_work && work_pending(&dpu_dbg_base.dump_work))
return;
- va_start(args, name);
- while ((blk_name = va_arg(args, char*))) {
- if (IS_ERR_OR_NULL(blk_name))
- break;
-
- if (!strcmp(blk_name, "dbg_bus"))
- dump_dbgbus_dpu = true;
-
- if (!strcmp(blk_name, "vbif_dbg_bus"))
- dump_dbgbus_vbif_rt = true;
- }
- va_end(args);
-
- if (queue_work) {
- /* schedule work to dump later */
- dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work =
- dump_dbgbus_dpu;
- dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
- dump_dbgbus_vbif_rt;
- schedule_work(&dpu_dbg_base.dump_work);
- } else {
+ if (!queue_work) {
_dpu_dump_array(name, dump_dbgbus_dpu, dump_dbgbus_vbif_rt);
+ return;
}
+
+ /* schedule work to dump later */
+ dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work = dump_dbgbus_dpu;
+ dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work =
+ dump_dbgbus_vbif_rt;
+ schedule_work(&dpu_dbg_base.dump_work);
}
/*
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h b/drivers/gpu/drm/msm/dpu_dbg.h
index 6a247ce39997..05504e676f6a 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/dpu_dbg.h
@@ -22,14 +22,6 @@ enum dpu_dbg_dump_flag {
DPU_DBG_DUMP_IN_MEM = BIT(1),
};
-/**
- * DPU_DBG_DUMP - trigger dumping of all dpu_dbg facilities
- * @va_args: list of named register dump ranges and regions to dump, as
- * registered previously through dpu_dbg_reg_register_base and
- *
[Freedreno] [DPU PATCH 10/19] drm/msm: dpu_core_irq: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_core_irq with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 52
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 50 +++
2 files changed, 71 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 33ab2ac46833..530c24dec017 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -18,6 +18,7 @@
#include
#include "dpu_core_irq.h"
+#include "dpu_trace.h"
/**
* dpu_core_irq_callback_handler - dispatch core interrupts
@@ -34,10 +35,8 @@ static void dpu_core_irq_callback_handler(void *arg, int
irq_idx)
pr_debug("irq_idx=%d\n", irq_idx);
if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {
- DPU_ERROR("irq_idx=%d has no registered callback\n", irq_idx);
- DPU_EVT32_IRQ(irq_idx, atomic_read(
- &dpu_kms->irq_obj.enable_counts[irq_idx]),
- DPU_EVTLOG_ERROR);
+ DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,
+ atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
}
atomic_inc(&irq_obj->irq_counts[irq_idx]);
@@ -80,7 +79,7 @@ int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
{
unsigned long irq_flags;
- int ret = 0;
+ int ret = 0, enable_count;
if (!dpu_kms || !dpu_kms->hw_intr ||
!dpu_kms->irq_obj.enable_counts ||
@@ -94,11 +93,10 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms,
int irq_idx)
return -EINVAL;
}
- DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
+ enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
+ DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
+ trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
- DPU_EVT32(irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) {
ret = dpu_kms->hw_intr->ops.enable_irq(
dpu_kms->hw_intr,
@@ -130,11 +128,8 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int
*irq_idxs, u32 irq_count)
}
counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
- if (counts) {
- DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n",
- __builtin_return_address(0), irq_idxs[0], counts);
- DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR);
- }
+ if (counts)
+ DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
for (i = 0; (i < irq_count) && !ret; i++)
ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
@@ -149,7 +144,7 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int
*irq_idxs, u32 irq_count)
*/
static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
{
- int ret = 0;
+ int ret = 0, enable_count;
if (!dpu_kms || !dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
DPU_ERROR("invalid params\n");
@@ -161,11 +156,10 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms,
int irq_idx)
return -EINVAL;
}
- DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
+ enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
+ DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
+ trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
- DPU_EVT32(irq_idx,
- atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
ret = dpu_kms->hw_intr->ops.disable_irq(
dpu_kms->hw_intr,
@@ -189,11 +183,8 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int
*irq_idxs, u32 irq_count)
}
counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
- if (counts == 2) {
- DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n",
- __builtin_return_address(0), irq_idxs[0], counts);
- DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR);
- }
+ if (counts == 2)
+ DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
for (i = 0; (i < irq_count) && !ret; i++)
ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]);
@@ -209,7 +200,7 @@
[Freedreno] [DPU PATCH 00/19] drm/msm: dpu: Clean up dpu_dbg
Well hello,
This patchset attempts to clean up some of dpu_dbg that was duplicating
functionality already upstream. The majority of the set is replacing
all instances of DPU_EVT* functions with proper tracepoints instead of
the obfuscated ones that exist now. The second part of the set disects
dpu_dbg.[ch] a bit and removes the arbitrary register reads, and evtlog
duplication. Finally, the dpu_dbg files are moved into the dpu1
directory.
Sean
Sean Paul (19):
drm/msm: dpu_encoder: Replace DPU_EVT with tracepoints
drm/msm: dpu_crtc: Replace DPU_EVT with tracepoints
drm/msm: dpu_plane: Replace DPU_EVT with tracepoints
drm/msm: dpu_rm: Replace DPU_EVT with tracepoints
drm/msm: dpu_kms: Replace DPU_EVT with tracepoints
drm/msm: dpu_encoder_phys_cmd: Replace DPU_EVT with tracepoints
drm/msm: dpu_encoder_phys_vid: Replace DPU_EVT with tracepoints
drm/msm: dpu_vbif: Replace DPU_EVT with tracepoints
drm/msm: dpu_pingpong: Replace DPU_EVT with tracepoints
drm/msm: dpu_core_irq: Replace DPU_EVT with tracepoints
drm/msm: dpu_core_perf: Replace DPU_EVT with tracepoints
drm/msm: dpu_mdss: Replace DPU_EVT with DRM_ERROR
drm/msm: dpu: Remove dpu evtlog
drm/msm: dpu_dbg: Remove dump_all option for dumping registers
drm/msm: dpu: Remove arbitrary register dumps
drm/msm: dpu: Remove panic from dpu debug dump
drm/msm: dpu: Remove dsi debug block name
drm/msm: dpu_dbg: Remove string parsing from DBG_DUMP
drm/msm: dpu: Move dpu_dbg into dpu1 directory
drivers/gpu/drm/msm/Makefile | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 52 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 122 +--
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c | 944 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 116 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 292 +++---
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 81 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 38 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 -
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 46 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 5 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 19 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 65 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 836 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 7 +-
drivers/gpu/drm/msm/dpu_dbg.h | 406
drivers/gpu/drm/msm/dpu_dbg_evtlog.c | 306 --
24 files changed, 1251 insertions(+), 2124 deletions(-)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c (70%)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
delete mode 100644 drivers/gpu/drm/msm/dpu_dbg.h
delete mode 100644 drivers/gpu/drm/msm/dpu_dbg_evtlog.c
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 02/19] drm/msm: dpu_crtc: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_crtc with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 122 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 166 ++
2 files changed, 210 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9ca8325877a1..eefc1892ad47 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -431,18 +431,12 @@ static void *_dpu_crtc_rp_get(struct dpu_crtc_respool
*rp, u32 type, u64 tag)
list_for_each_entry(res, &old_rp->res_list, list) {
if (res->type != type)
continue;
- DPU_DEBUG(
- "crtc%d.%u found res:0x%x//%pK/ in
crtc%d.%d\n",
- crtc->base.id,
- rp->sequence_id,
- res->type, res->val,
- crtc->base.id,
- old_rp->sequence_id);
- DPU_EVT32_VERBOSE(crtc->base.id,
- rp->sequence_id,
- res->type, res->val,
- crtc->base.id,
- old_rp->sequence_id);
+ DRM_DEBUG_KMS("crtc%d.%u found res:0x%x//%pK/ "
+ "in crtc%d.%d\n",
+ crtc->base.id, rp->sequence_id,
+ res->type, res->val,
+ crtc->base.id,
+ old_rp->sequence_id);
if (res->ops.get)
res->ops.get(res->val, 0, -1);
val = res->val;
@@ -688,23 +682,17 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
- DPU_EVT32(DRMID(crtc), DRMID(plane),
- state->fb ? state->fb->base.id : -1,
- state->src_x >> 16, state->src_y >> 16,
- state->src_w >> 16, state->src_h >> 16,
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h);
-
stage_idx = zpos_cnt[pstate->stage]++;
stage_cfg->stage[pstate->stage][stage_idx] =
dpu_plane_pipe(plane);
stage_cfg->multirect_index[pstate->stage][stage_idx] =
pstate->multirect_index;
- DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
- dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- pstate->multirect_index, pstate->multirect_mode,
- format->base.pixel_format, fb ? fb->modifier : 0);
+ trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
+ state, pstate, stage_idx,
+ dpu_plane_pipe(plane) - SSPP_VIG0,
+ format->base.pixel_format,
+ fb ? fb->modifier : 0);
/* blend config update */
for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
@@ -821,7 +809,7 @@ static void _dpu_crtc_complete_flip(struct drm_crtc *crtc,
dpu_crtc->event = NULL;
DRM_DEBUG_VBL("%s: send event: %pK\n",
dpu_crtc->name, event);
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_crtc_complete_flip(DRMID(crtc));
drm_crtc_send_vblank_event(crtc, event);
}
}
@@ -856,8 +844,7 @@ static void dpu_crtc_vblank_cb(void *data)
dpu_crtc->vblank_cb_count++;
_dpu_crtc_complete_flip(crtc, NULL);
drm_crtc_handle_vblank(crtc);
- DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_crtc_vblank_cb(DRMID(crtc));
}
/* _dpu_crtc_idle_notify - signal idle timeout to client */
@@ -933,34 +920,28 @@ static void dpu_crtc_frame_event_work(struct kthread_work
*work)
priv = dpu_kms->dev->dev_private;
DPU_ATRACE_BEGIN("crtc_frame_event");
- DPU_DEBUG("crtc%d event:%u ts:%lld\n",
[Freedreno] [DPU PATCH 11/19] drm/msm: dpu_core_perf: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_core_perf with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 17 +
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 6c0f66cc177f..1019ce7594ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -474,7 +474,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
if (update_clk) {
clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
- DPU_EVT32(kms->dev, stop_req, clk_rate);
+ trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate);
ret = _dpu_core_perf_set_core_clk_rate(kms, clk_rate);
if (ret) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index ee41db86a2e9..d6f117bdad24 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -1016,6 +1016,23 @@ DEFINE_EVENT(dpu_core_irq_callback_template,
dpu_core_irq_unregister_callback,
TP_ARGS(irq_idx, callback)
);
+TRACE_EVENT(dpu_core_perf_update_clk,
+ TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
+ TP_ARGS(dev, stop_req, clk_rate),
+ TP_STRUCT__entry(
+ __field(struct drm_device *,dev )
+ __field(bool, stop_req)
+ __field(u64,clk_rate)
+ ),
+ TP_fast_assign(
+ __entry->dev = dev;
+ __entry->stop_req = stop_req;
+ __entry->clk_rate = clk_rate;
+ ),
+ TP_printk("dev:%s stop_req:%s clk_rate:%llu", __entry->dev->unique,
+ __entry->stop_req ? "true" : "false", __entry->clk_rate)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 08/19] drm/msm: dpu_vbif: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_vbif with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 15 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 7 +++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index c9041e2a7aa1..73f76387803f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -20,6 +20,7 @@
#include "dpu_crtc.h"
#include "dpu_encoder_phys.h"
#include "dpu_hw_mdss.h"
+#include "dpu_hw_vbif.h"
#include "dpu_plane.h"
#undef TRACE_SYSTEM
@@ -937,6 +938,20 @@ TRACE_EVENT(dpu_rm_reserve_lms,
__entry->type, __entry->enc_id, __entry->pp_id)
);
+TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
+ TP_PROTO(enum dpu_vbif index, u32 xin_id),
+ TP_ARGS(index, xin_id),
+ TP_STRUCT__entry(
+ __field(enum dpu_vbif, index )
+ __field(u32,xin_id )
+ ),
+ TP_fast_assign(
+ __entry->index = index;
+ __entry->xin_id = xin_id;
+ ),
+ TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
index 801155fe0989..295528292296 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
@@ -204,7 +204,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
ret = _dpu_vbif_wait_for_xin_halt(vbif, params->xin_id);
if (ret)
- DPU_EVT32(vbif->idx, params->xin_id);
+ trace_dpu_vbif_wait_xin_halt_fail(vbif->idx, params->xin_id);
vbif->ops.set_halt_ctrl(vbif, params->xin_id, false);
@@ -284,9 +284,8 @@ void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms)
if (vbif && vbif->ops.clear_errors) {
vbif->ops.clear_errors(vbif, &pnd, &src);
if (pnd || src) {
- DPU_EVT32(i, pnd, src);
- DPU_DEBUG("VBIF %d: pnd 0x%X, src 0x%X\n",
- vbif->idx - VBIF_0, pnd, src);
+ DRM_DEBUG_KMS("VBIF %d: pnd 0x%X, src 0x%X\n",
+ vbif->idx - VBIF_0, pnd, src);
}
}
}
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 12/19] drm/msm: dpu_mdss: Replace DPU_EVT with DRM_ERROR
The events are only issued in error cases, so use DRM_ERROR instead.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 04accdf483c0..5c69c2cc5d10 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -33,13 +33,14 @@ static irqreturn_t dpu_mdss_irq(int irq, void *arg)
mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
hwirq);
if (mapping == 0) {
- DPU_EVT32(hwirq, DPU_EVTLOG_ERROR);
+ DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
return IRQ_NONE;
}
rc = generic_handle_irq(mapping);
if (rc < 0) {
- DPU_EVT32(hwirq, mapping, rc, DPU_EVTLOG_ERROR);
+ DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
+ hwirq, mapping, rc);
return IRQ_NONE;
}
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 04/19] drm/msm: dpu_rm: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_rm with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 65 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 49 +
2 files changed, 78 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index eff316bb2134..13c0a36d4ef9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -20,6 +20,7 @@
#include "dpu_hw_pingpong.h"
#include "dpu_hw_intf.h"
#include "dpu_encoder.h"
+#include "dpu_trace.h"
#define RESERVED_BY_OTHER(h, r) \
((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
@@ -121,9 +122,8 @@ static void _dpu_rm_print_rsvps(
DPU_DEBUG("%d\n", stage);
list_for_each_entry(rsvp, &rm->rsvps, list) {
- DPU_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
- rsvp->enc_id, rsvp->topology);
- DPU_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
+ DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
+ rsvp->enc_id, rsvp->topology);
}
for (type = 0; type < DPU_HW_BLK_MAX; type++) {
@@ -131,14 +131,7 @@ static void _dpu_rm_print_rsvps(
if (!blk->rsvp && !blk->rsvp_nxt)
continue;
- DPU_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
- (blk->rsvp) ? blk->rsvp->seq : 0,
- (blk->rsvp) ? blk->rsvp->enc_id : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
- blk->type, blk->id);
-
- DPU_EVT32(stage,
+ DRM_DEBUG_KMS("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
(blk->rsvp) ? blk->rsvp->seq : 0,
(blk->rsvp) ? blk->rsvp->enc_id : 0,
(blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
@@ -597,7 +590,8 @@ static int _dpu_rm_reserve_lms(
lm[i]->rsvp_nxt = rsvp;
pp[i]->rsvp_nxt = rsvp;
- DPU_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id);
+ trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, rsvp->enc_id,
+pp[i]->id);
}
return rc;
@@ -642,7 +636,8 @@ static int _dpu_rm_reserve_ctls(
for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
ctls[i]->rsvp_nxt = rsvp;
- DPU_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
+ trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
+ rsvp->enc_id);
}
return 0;
@@ -656,6 +651,8 @@ static int _dpu_rm_reserve_cdm(
{
struct dpu_rm_hw_iter iter;
+ DRM_DEBUG_KMS("type %d id %d\n", type, id);
+
dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CDM);
while (_dpu_rm_get_hw_locked(rm, &iter)) {
const struct dpu_hw_cdm *cdm = to_dpu_hw_cdm(iter.blk->hw);
@@ -668,14 +665,16 @@ static int _dpu_rm_reserve_cdm(
if (type == DPU_HW_BLK_INTF && id != INTF_MAX)
match = test_bit(id, &caps->intf_connect);
- DPU_DEBUG("type %d id %d, cdm intfs %lu match %d\n",
- type, id, caps->intf_connect, match);
+ DRM_DEBUG_KMS("iter: type:%d id:%d enc:%d cdm:%lu match:%d\n",
+ iter.blk->type, iter.blk->id, rsvp->enc_id,
+ caps->intf_connect, match);
if (!match)
continue;
+ trace_dpu_rm_reserve_cdm(iter.blk->id, iter.blk->type,
+rsvp->enc_id);
iter.blk->rsvp_nxt = rsvp;
- DPU_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
break;
}
@@ -709,7 +708,8 @@ static int _dpu_rm_reserve_intf(
}
iter.blk->rsvp_nxt = rsvp;
- DPU_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
+ trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
+ rsvp->enc_id);
break;
}
@@ -801,7 +801,6 @@ static int _dpu_rm_populate_requirements(
struct dpu_rm_requirements *reqs,
struct msm_display_topology req_topology)
{
- const struct drm_display_mode *mode = &crtc_state->mode;
int i;
memset(reqs, 0, sizeof(*reqs));
@@ -830,15 +829,12 @@ static int _dpu_rm_populate_requirements(
conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI)
[Freedreno] [DPU PATCH 03/19] drm/msm: dpu_plane: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_plane with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 19 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 44 +++
2 files changed, 49 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 6090ace6012a..2c3dc00477b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -609,18 +609,9 @@ static inline void _dpu_plane_set_scanout(struct drm_plane
*plane,
else if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
- DPU_EVT32_VERBOSE(pdpu->pipe_hw->idx,
- pipe_cfg->layout.width,
- pipe_cfg->layout.height,
- pipe_cfg->layout.plane_addr[0],
- pipe_cfg->layout.plane_size[0],
- pipe_cfg->layout.plane_addr[1],
- pipe_cfg->layout.plane_size[1],
- pipe_cfg->layout.plane_addr[2],
- pipe_cfg->layout.plane_size[2],
- pipe_cfg->layout.plane_addr[3],
- pipe_cfg->layout.plane_size[3],
- pstate->multirect_index);
+ trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
+ &pipe_cfg->layout,
+ pstate->multirect_index);
pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
pstate->multirect_index);
}
@@ -1420,8 +1411,8 @@ static void _dpu_plane_atomic_disable(struct drm_plane
*plane,
state = plane->state;
pstate = to_dpu_plane_state(state);
- DPU_EVT32(DRMID(plane), is_dpu_plane_virtual(plane),
- pstate->multirect_mode);
+ trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
+ pstate->multirect_mode);
pstate->pending = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 877621184782..5d3aa5a994be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -725,6 +725,50 @@ TRACE_EVENT(dpu_crtc_disable_frame_pending,
__entry->frame_pending)
);
+TRACE_EVENT(dpu_plane_set_scanout,
+ TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
+enum dpu_sspp_multirect_index multirect_index),
+ TP_ARGS(index, layout, multirect_index),
+ TP_STRUCT__entry(
+ __field(enum dpu_sspp, index )
+ __field(struct dpu_hw_fmt_layout*, layout )
+ __field(enum dpu_sspp_multirect_index, multirect_index)
+ ),
+ TP_fast_assign(
+ __entry->index = index;
+ __entry->layout = layout;
+ __entry->multirect_index = multirect_index;
+ ),
+ TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
+ "multirect_index:%d", __entry->index, __entry->layout->width,
+ __entry->layout->height, __entry->layout->plane_addr[0],
+ __entry->layout->plane_size[0],
+ __entry->layout->plane_addr[1],
+ __entry->layout->plane_size[1],
+ __entry->layout->plane_addr[2],
+ __entry->layout->plane_size[2],
+ __entry->layout->plane_addr[3],
+ __entry->layout->plane_size[3], __entry->multirect_index)
+);
+
+TRACE_EVENT(dpu_plane_disable,
+ TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
+ TP_ARGS(drm_id, is_virtual, multirect_mode),
+ TP_STRUCT__entry(
+ __field(uint32_t, drm_id )
+ __field(bool, is_virtual )
+ __field(uint32_t, multirect_mode )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->is_virtual = is_virtual;
+ __entry->multirect_mode = multirect_mode;
+ ),
+ TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
+ __entry->is_virtual ? "true" : "false",
+ __entry->multirect_mode)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engi
[Freedreno] [DPU PATCH 07/19] drm/msm: dpu_encoder_phys_vid: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_encoder_phys_vid with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 36 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 35 ++
2 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 73e59382eeac..fc83745b48fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -458,12 +458,8 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
goto end;
}
- DPU_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n",
- __builtin_return_address(0),
- enable, atomic_read(&phys_enc->vblank_refcount));
-
- DPU_EVT32(DRMID(phys_enc->parent), enable,
- atomic_read(&phys_enc->vblank_refcount));
+ DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
+ atomic_read(&phys_enc->vblank_refcount));
if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
@@ -473,12 +469,10 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
end:
if (ret) {
- DPU_ERROR_VIDENC(vid_enc,
- "control vblank irq error %d, enable %d\n",
- ret, enable);
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0,
- enable, refcount, DPU_EVTLOG_ERROR);
+ DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
+ DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0, ret, enable,
+ refcount);
}
return ret;
}
@@ -697,11 +691,9 @@ static void dpu_encoder_phys_vid_disable(struct
dpu_encoder_phys *phys_enc)
ret = _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, false);
if (ret) {
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
- DPU_ERROR_VIDENC(vid_enc,
- "failure waiting for disable: %d\n",
- ret);
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0, ret);
+ DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
+ DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0, ret);
}
}
@@ -727,8 +719,8 @@ static void dpu_encoder_phys_vid_handle_post_kickoff(
* Video encoders need to turn on their interfaces now
*/
if (phys_enc->enable_state == DPU_ENC_ENABLING) {
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0);
+ trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0);
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 1);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
@@ -747,8 +739,10 @@ static void dpu_encoder_phys_vid_irq_control(struct
dpu_encoder_phys *phys_enc,
vid_enc = to_dpu_encoder_phys_vid(phys_enc);
- DPU_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0,
- enable, atomic_read(&phys_enc->vblank_refcount));
+ trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0,
+ enable,
+ atomic_read(&phys_enc->vblank_refcount));
if (enable) {
ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index a6313c4343c8..c9041e2a7aa1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -672,6 +672,41 @@ TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
__entry->kickoff_count, __entry->event)
);
+TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
+ TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
+ TP_ARGS(drm_id, intf_idx),
+ TP_STRUCT__entry(
+ __field(uint32_t, drm_id )
+ __field(enum dpu_intf, intf_idx)
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->intf_id
[Freedreno] [DPU PATCH 14/19] drm/msm: dpu_dbg: Remove dump_all option for dumping registers
This can be accomplished via /dev/mem
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 34 +++
4 files changed, 7 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6aad40dccb05..5ff627827be9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys
*phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index eb9314aaa85f..5589d1289da9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
}
atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index fc83745b48fa..8ac7f0537c05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 9495a0f17f1b..813f6f3ff773 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -174,7 +174,6 @@ struct dpu_dbg_vbif_debug_bus {
* @enable_reg_dump: whether to dump registers into memory, kernel log, or both
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
- * @dump_all: dump all entries in register dump
* @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
@@ -190,7 +189,6 @@ static struct dpu_dbg_base {
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
- bool dump_all;
bool dsi_dbg_bus;
} dpu_dbg_base;
@@ -2207,22 +2205,6 @@ static void _dpu_dump_reg_by_blk(const char *blk_name)
}
}
-/**
- * _dpu_dump_reg_all - dump all register regions
- */
-static void _dpu_dump_reg_all(void)
-{
- struct dpu_dbg_base *dbg_base = &dpu_dbg_base;
- struct dpu_dbg_reg_base *blk_base;
-
- if (!dbg_base)
- return;
-
- list_for_each_entry(blk_base, &dbg_base->reg_base_list, reg_base_head)
- if (strlen(blk_base->name))
- _dpu_dump_reg_by_blk(blk_base->name);
-}
-
/**
* _dpu_dump_get_blk_addr - retrieve register block address by name
* @blk_name: register blk name
@@ -2517,13 +2499,11 @@ static void _dpu_dbg_dump_vbif_dbg_bus(struct
dpu_dbg_vbif_debug_bus *bus)
*/
static void _dpu_dump_array(struct dpu_dbg_reg_base *blk_arr[],
u32 len, bool do_panic, const char *name, bool dump_dbgbus_dpu,
- bool dump_dbgbus_vbif_rt, bool dump_all)
+ bool dump_dbgbus_vbif_rt)
{
int i;
- if (dump_all || !blk_arr || !len) {
- _dpu_dump_reg_all();
- } else {
+ if (!blk_arr || !len) {
for (i = 0; i < len; i++) {
if (blk_arr[i] != NULL)
_dpu_dump_reg_by_ranges(blk_arr[i],
@@ -2551,8 +2531,7 @@ static void _dpu_dump_work(struct work_struct *work)
ARRAY_SIZE(dpu_dbg_base.req_dump_blks),
dpu_dbg_base.work_panic, "dpudump_workitem",
dpu_dbg_base.dbgbus_dpu.cmn.include_in_deferred_work,
- dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work,
- dpu_dbg_base.dump_all);
+ dpu_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
}
void dpu_dbg_dump(bool queue_work
[Freedreno] [DPU PATCH 05/19] drm/msm: dpu_kms: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_kms with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 16
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fe614c06bb7b..6ae5bba21074 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -362,7 +362,7 @@ static void dpu_kms_wait_for_frame_transfer_complete(struct
msm_kms *kms,
* Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
* complete
*/
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_kms_wait_for_frame_transfer(DRMID(crtc));
ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
if (ret && ret != -EWOULDBLOCK) {
DPU_ERROR(
@@ -410,7 +410,7 @@ void dpu_kms_encoder_enable(struct drm_encoder *encoder)
funcs->commit(encoder);
if (crtc && crtc->state->active) {
- DPU_EVT32(DRMID(crtc));
+ trace_dpu_kms_enc_enable(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
}
}
@@ -427,7 +427,7 @@ static void dpu_kms_commit(struct msm_kms *kms, struct
drm_atomic_state *state)
continue;
if (crtc->state->active) {
- DPU_EVT32(DRMID(crtc));
+ trace_dpu_kms_commit(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
}
}
@@ -450,12 +450,14 @@ static void dpu_kms_complete_commit(struct msm_kms *kms,
return;
priv = dpu_kms->dev->dev_private;
+ DPU_ATRACE_BEGIN("kms_complete_commit");
+
for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
dpu_crtc_complete_commit(crtc, old_crtc_state);
pm_runtime_put_sync(&dpu_kms->pdev->dev);
- DPU_EVT32_VERBOSE(DPU_EVTLOG_FUNC_EXIT);
+ DPU_ATRACE_END("kms_complete_commit");
}
static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
@@ -490,7 +492,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms
*kms,
* plane_cleanup. For example, wait for vsync in case of video
* mode panels. This may be a no-op for command mode panels.
*/
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
if (ret && ret != -EWOULDBLOCK) {
DPU_ERROR("wait for commit done returned %d\n", ret);
@@ -1137,7 +1139,6 @@ static int dpu_kms_pm_suspend(struct device *dev)
return -EINVAL;
dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev));
- DPU_EVT32(0);
/* disable hot-plug polling */
drm_kms_helper_poll_disable(ddev);
@@ -1146,6 +1147,8 @@ static int dpu_kms_pm_suspend(struct device *dev)
drm_modeset_acquire_init(&ctx, 0);
retry:
+ DPU_ATRACE_BEGIN("kms_pm_suspend");
+
ret = drm_modeset_lock_all_ctx(ddev, &ctx);
if (ret)
goto unlock;
@@ -1195,6 +1198,7 @@ static int dpu_kms_pm_suspend(struct device *dev)
drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
+ DPU_ATRACE_END("kms_pm_suspend");
return 0;
}
@@ -1213,7 +1217,7 @@ static int dpu_kms_pm_resume(struct device *dev)
dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev));
- DPU_EVT32(dpu_kms->suspend_state != NULL);
+ DPU_ATRACE_BEGIN("kms_pm_resume");
drm_mode_config_reset(ddev);
@@ -1236,6 +1240,7 @@ static int dpu_kms_pm_resume(struct device *dev)
/* enable hot-plug polling */
drm_kms_helper_poll_enable(ddev);
+ DPU_ATRACE_END("kms_pm_resume");
return 0;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 99c45b8d84c0..7169ff3a9805 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -338,6 +338,22 @@ DEFINE_EVENT(dpu_drm_obj_template,
dpu_crtc_complete_commit,
TP_PROTO(uint32_t drm_id),
TP_ARGS(drm_id)
);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_frame_transfer,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
TRACE_EVENT
[Freedreno] [DPU PATCH 16/19] drm/msm: dpu: Remove panic from dpu debug dump
Better not to allow arbitrary panics of the kernel when poking debugfs
files.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 31 +++
drivers/gpu/drm/msm/dpu_dbg.h | 4 ---
5 files changed, 8 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5ff627827be9..3519f7e84f0f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys
*phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 5589d1289da9..19f5b5064ed8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 8ac7f0537c05..54f4e78cf1fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 3572e3cbec6c..2a9b8c732e33 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -26,7 +26,6 @@
#include "disp/dpu1/dpu_hw_catalog.h"
-#define DEFAULT_PANIC 1
#define DEFAULT_DBGBUS_DPU DPU_DBG_DUMP_IN_MEM
#define DEFAULT_DBGBUS_VBIFRT DPU_DBG_DUMP_IN_MEM
#define REG_BASE_NAME_LEN 80
@@ -128,9 +127,7 @@ struct dpu_dbg_vbif_debug_bus {
* struct dpu_dbg_base - global dpu debug base structure
* @reg_base_list: list of register dumping regions
* @dev: device pointer
- * @panic_on_err: whether to kernel panic after triggering dump via debugfs
* @dump_work: work struct for deferring register dump work to separate thread
- * @work_panic: panic after dump if internal user passed "panic" special region
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
* @dsi_dbg_bus: dump dsi debug bus register
@@ -139,9 +136,7 @@ static struct dpu_dbg_base {
struct list_head reg_base_list;
struct device *dev;
- u32 panic_on_err;
struct work_struct dump_work;
- bool work_panic;
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
@@ -2230,22 +2225,18 @@ static void _dpu_dbg_dump_vbif_dbg_bus(struct
dpu_dbg_vbif_debug_bus *bus)
/**
* _dpu_dump_array - dump array of register bases
- * @do_panic: whether to trigger a panic after dumping
* @name: string indicating origin of dump
* @dump_dbgbus_dpu: whether to dump the dpu debug bus
* @dump_dbgbus_vbif_rt: whether to dump the vbif rt debug bus
*/
-static void _dpu_dump_array(bool do_panic, const char *name,
- bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt)
+static void _dpu_dump_array(const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt)
{
if (dump_dbgbus_dpu)
_dpu_dbg_dump_dpu_dbg_bus(&dpu_dbg_base.dbgbus_dpu);
if (dump_dbgbus_vbif_rt)
_dpu_dbg_dump_vbif_dbg_bus(&dpu_dbg_base.dbgbus_vbif_rt);
-
- if (do_panic && dpu_dbg_base.panic_on_err)
- panic(name);
}
/**
@@ -2254,14 +2245,13 @@ static void _dpu_dump_array(bool do_panic, const char
*name,
*/
static void _dpu_dump_work(struct work_struct *work)
{
- _dpu_dump_array(dpu_dbg_base.work_panic, "dpudump_workitem",
+ _dpu_dump_a
[Freedreno] [DPU PATCH 06/19] drm/msm: dpu_encoder_phys_cmd: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_encoder_phys_cmd with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 79 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 68
2 files changed, 104 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 388de384e2cf..eb9314aaa85f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -108,8 +108,9 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg,
int irq_idx)
new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
- DPU_EVT32_IRQ(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0, new_cnt, event);
+ trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ new_cnt, event);
/* Signal any waiting atomic commit thread */
wake_up_all(&phys_enc->pending_kickoff_wq);
@@ -245,21 +246,20 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
do_log = true;
}
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- cmd_enc->pp_timeout_report_cnt,
- atomic_read(&phys_enc->pending_kickoff_cnt),
- frame_event);
+ trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),
+phys_enc->hw_pp->idx - PINGPONG_0,
+cmd_enc->pp_timeout_report_cnt,
+atomic_read(&phys_enc->pending_kickoff_cnt),
+frame_event);
/* to avoid flooding, only log first time, and "dead" time */
if (do_log) {
- DPU_ERROR_CMDENC(cmd_enc,
- "pp:%d kickoff timed out ctl %d cnt %d koff_cnt
%d\n",
- phys_enc->hw_pp->idx - PINGPONG_0,
- phys_enc->hw_ctl->idx - CTL_0,
- cmd_enc->pp_timeout_report_cnt,
- atomic_read(&phys_enc->pending_kickoff_cnt));
-
- DPU_EVT32(DRMID(phys_enc->parent), DPU_EVTLOG_FATAL);
+ DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ phys_enc->hw_ctl->idx - CTL_0,
+ cmd_enc->pp_timeout_report_cnt,
+ atomic_read(&phys_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
@@ -308,8 +308,6 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
struct dpu_encoder_phys *phys_enc,
bool enable)
{
- struct dpu_encoder_phys_cmd *cmd_enc =
- to_dpu_encoder_phys_cmd(phys_enc);
int ret = 0;
int refcount;
@@ -330,10 +328,9 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
goto end;
}
- DPU_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
- __builtin_return_address(0), enable, refcount);
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- enable, refcount);
+ DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ enable ? "true" : "false", refcount);
if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR);
@@ -343,12 +340,10 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
end:
if (ret) {
- DPU_ERROR_CMDENC(cmd_enc,
- "control vblank irq error %d, enable %d,
refcount %d\n",
- ret, enable, refcount);
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0,
- enable, refcount, DPU_EVTLOG_ERROR);
+ DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0, ret,
+ enable ? "true" : "false", refcount);
}
return ret;
@@ -364,7 +359,8 @@ void dpu_encoder_phys_cmd_irq_control(struct
dpu_encoder_phys *phys_enc,
cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
- DPU_EVT32(DRMID(phys_enc->pa
[Freedreno] [DPU PATCH 01/19] drm/msm: dpu_encoder: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_encoder with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 290 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 329
2 files changed, 464 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 11a1045bf132..6aad40dccb05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -254,11 +254,9 @@ static inline int _dpu_encoder_power_enable(struct
dpu_encoder_virt *dpu_enc,
void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx)
{
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->intf_idx - INTF_0,
- phys_enc->hw_pp->idx - PINGPONG_0,
- intr_idx);
- DPU_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
+ DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
+ DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
+ phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
if (phys_enc->parent_ops.handle_frame_done)
phys_enc->parent_ops.handle_frame_done(
@@ -284,25 +282,23 @@ int dpu_encoder_helper_wait_for_irq(struct
dpu_encoder_phys *phys_enc,
/* return EWOULDBLOCK since we know the wait isn't necessary */
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
- DPU_ERROR_PHYS(phys_enc, "encoder is disabled\n");
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, intr_idx, DPU_EVTLOG_ERROR);
+ DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx);
return -EWOULDBLOCK;
}
if (irq->irq_idx < 0) {
- DPU_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
- irq->name, irq->hw_idx);
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx);
+ DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->name);
return 0;
}
- DPU_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
- atomic_read(wait_info->atomic_cnt));
- DPU_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt), DPU_EVTLOG_FUNC_ENTRY);
+ DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(wait_info->atomic_cnt));
ret = dpu_encoder_helper_wait_event_timeout(
DRMID(phys_enc->parent),
@@ -315,36 +311,33 @@ int dpu_encoder_helper_wait_for_irq(struct
dpu_encoder_phys *phys_enc,
if (irq_status) {
unsigned long flags;
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx,
- irq->hw_idx, irq->irq_idx,
- phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt));
- DPU_DEBUG_PHYS(phys_enc,
- "done but irq %d not triggered\n",
- irq->irq_idx);
+ DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
+ "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+ DRMID(phys_enc->parent), intr_idx,
+ irq->hw_idx, irq->irq_idx,
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(wait_info->atomic_cnt));
local_irq_save(flags);
irq->cb.func(phys_enc, irq->irq_idx);
local_irq_restore(flags);
ret = 0;
} else {
ret = -ETIMEDOUT;
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx,
- irq->hw_idx, irq->irq_idx,
- phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt), irq_status,
- DPU_EVTLOG_ERROR);
+ DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
+
[Freedreno] [DPU PATCH 09/19] drm/msm: dpu_pingpong: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_pingpong with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 14 ++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 84d2176ecafb..12e90b8e5466 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -18,6 +18,7 @@
#include "dpu_hw_pingpong.h"
#include "dpu_dbg.h"
#include "dpu_kms.h"
+#include "dpu_trace.h"
#define PP_TEAR_CHECK_EN0x000
#define PP_SYNC_CONFIG_VSYNC0x004
@@ -134,7 +135,7 @@ static int dpu_hw_pp_connect_external_te(struct
dpu_hw_pingpong *pp,
else
cfg &= ~BIT(20);
DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
- DPU_EVT32(pp->idx - PINGPONG_0, cfg);
+ trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
return orig;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 73f76387803f..9d044f5ce26e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -952,6 +952,20 @@ TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
);
+TRACE_EVENT(dpu_pp_connect_ext_te,
+ TP_PROTO(enum dpu_pingpong pp, u32 cfg),
+ TP_ARGS(pp, cfg),
+ TP_STRUCT__entry(
+ __field(enum dpu_pingpong, pp )
+ __field(u32,cfg )
+ ),
+ TP_fast_assign(
+ __entry->pp = pp;
+ __entry->cfg = cfg;
+ ),
+ TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 13/19] drm/msm: dpu: Remove dpu evtlog
Now that everything has been converted to tracepoints, remove the dpu
evtlog.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 33 ---
drivers/gpu/drm/msm/dpu_dbg.c | 147 +--
drivers/gpu/drm/msm/dpu_dbg.h | 224 +---
drivers/gpu/drm/msm/dpu_dbg_evtlog.c | 306 --
6 files changed, 11 insertions(+), 705 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dpu_dbg_evtlog.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index dc56904367d8..9c182a9dab2b 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -75,7 +75,6 @@ msm-y := \
disp/dpu1/dpu_mdss.o \
disp/dpu1/dpu_power_handle.o \
dpu_dbg.o \
- dpu_dbg_evtlog.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 6ae5bba21074..4fd5e1d7261e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -43,11 +43,6 @@ static const char * const iommu_ports[] = {
"mdp_0",
};
-/**
- * Controls size of event log buffer. Specified as a power of 2.
- */
-#define DPU_EVTLOG_SIZE1024
-
/*
* To enable overall DRM driver logging
* # echo 0x2 > /sys/module/drm/parameters/debug
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index d6f117bdad24..41fd6a227d8b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -165,39 +165,6 @@ TRACE_EVENT(dpu_trace_counter,
__get_str(counter_name), __entry->value)
)
-#define DPU_TRACE_EVTLOG_SIZE 15
-TRACE_EVENT(dpu_evtlog,
- TP_PROTO(const char *tag, u32 tag_id, u32 cnt, u32 data[]),
- TP_ARGS(tag, tag_id, cnt, data),
- TP_STRUCT__entry(
- __field(int, pid)
- __string(evtlog_tag, tag)
- __field(u32, tag_id)
- __array(u32, data, DPU_TRACE_EVTLOG_SIZE)
- ),
- TP_fast_assign(
- __entry->pid = current->tgid;
- __assign_str(evtlog_tag, tag);
- __entry->tag_id = tag_id;
- if (cnt > DPU_TRACE_EVTLOG_SIZE)
- cnt = DPU_TRACE_EVTLOG_SIZE;
- memcpy(__entry->data, data, cnt * sizeof(u32));
- memset(&__entry->data[cnt], 0,
- (DPU_TRACE_EVTLOG_SIZE - cnt) * sizeof(u32));
- ),
- TP_printk("%d|%s:%d|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x",
- __entry->pid, __get_str(evtlog_tag),
- __entry->tag_id,
- __entry->data[0], __entry->data[1],
- __entry->data[2], __entry->data[3],
- __entry->data[4], __entry->data[5],
- __entry->data[6], __entry->data[7],
- __entry->data[8], __entry->data[9],
- __entry->data[10], __entry->data[11],
- __entry->data[12], __entry->data[13],
- __entry->data[14])
-)
-
TRACE_EVENT(dpu_perf_crtc_update,
TP_PROTO(u32 crtc, u64 bw_ctl_mnoc, u64 bw_ctl_llcc,
u64 bw_ctl_ebi, u32 core_clk_rate,
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 27538bc6c290..9495a0f17f1b 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -165,7 +165,6 @@ struct dpu_dbg_vbif_debug_bus {
/**
* struct dpu_dbg_base - global dpu debug base structure
- * @evtlog: event log instance
* @reg_base_list: list of register dumping regions
* @dev: device pointer
* @req_dump_blks: list of blocks requested for dumping
@@ -179,7 +178,6 @@ struct dpu_dbg_vbif_debug_bus {
* @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
- struct dpu_dbg_evtlog *evtlog;
struct list_head reg_base_list;
struct device *dev;
@@ -196,9 +194,6 @@ static struct dpu_dbg_base {
bool dsi_dbg_bus;
} dpu_dbg_base;
-/* dpu_dbg_base_evtlog - global pointer to main dpu event log for macro use */
-struct dpu_dbg_evtlog *dpu_dbg_base_evtlog;
-
static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base,
struct dpu_debug_bus_entry *entry, u32 val)
{
@@ -2526,8 +2521,6 @@ static void _dpu_dump_array(struct dpu_dbg_reg_base
*blk_arr[],
{
int i;
- dpu_evtlog_dump_all(dpu_dbg_base.evtlog);
-
if (dump_all || !blk_arr || !len) {
_dpu_dump_reg_all();
} else {
@@ -2556,7 +2549,7 @@ static void _dpu_dump_work(struct work_struct *work)
{
_dpu_d
Re: [Freedreno] [DPU PATCH 2/5] drm/msm/dpu: enable cursor plane for primary crtc
On Wed, Jun 20, 2018 at 12:29 PM, wrote:
> On 2018-06-20 19:18, Rob Clark wrote:
>>
>> On Wed, Jun 20, 2018 at 8:50 AM, Sravanthi Kollukuduru
>> wrote:
>>>
>>> Reserve one DMA pipe as cursor plane and also, update crtc
>>> support of cursor in crtc_init.
>>
>>
>> hmm, mdp5 in 820 had real cursor planes in hw, did these go away? If
>> so I guess DMA plane is best candidate for cursor..
>
> Hi Rob,
> Yes, the hw cursor support is not present on sdm845.
> The ozone compositor expects cursor planes to be present otherwise cursor is
> not rendered on screen.
> So, we are planning to use one of the DMA pipe for cursor plane.
ok, makes sense
BR,
-R
> Thanks,
> Rajesh
>
>>
>> BR,
>> -R
>>
>>>
>>> Signed-off-by: Sravanthi Kollukuduru
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 ++--
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53
>>> +++---
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 7 +++-
>>> 4 files changed, 34 insertions(+), 36 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> index f0aafec..56f6576 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> @@ -2027,7 +2027,8 @@ static int _dpu_crtc_init_events(struct dpu_crtc
>>> *dpu_crtc)
>>> }
>>>
>>> /* initialize crtc */
>>> -struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane)
>>> +struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane,
>>> + struct drm_plane
>>> *cursor_plane)
>>> {
>>> struct drm_crtc *crtc = NULL;
>>> struct dpu_crtc *dpu_crtc = NULL;
>>> @@ -2061,8 +2062,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
>>> *dev, struct drm_plane *plane)
>>> dpu_crtc_frame_event_work);
>>> }
>>>
>>> - drm_crtc_init_with_planes(dev, crtc, plane, NULL,
>>> &dpu_crtc_funcs,
>>> - NULL);
>>> + drm_crtc_init_with_planes(dev, crtc, plane,
>>> + cursor_plane, &dpu_crtc_funcs, NULL);
>>>
>>> drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>> plane->crtc = crtc;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> index 50c3d4b..b44750d 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> @@ -366,7 +366,8 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
>>> * @plane: base plane
>>> * @Return: new crtc object or error
>>> */
>>> -struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane);
>>> +struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>>> *plane,
>>> + struct drm_plane *cursor_plane);
>>>
>>> /**
>>> * dpu_crtc_cancel_pending_flip - complete flip for clients on lastclose
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> index f0c2881..c0b8116 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> @@ -29,6 +29,9 @@
>>> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
>>> BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
>>>
>>> +#define DMA_CURSOR_SDM845_MASK \
>>> + (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
>>> +
>>> #define MIXER_SDM845_MASK \
>>> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>>>
>>> @@ -169,45 +172,35 @@
>>> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 =
>>> _DMA_SBLK("10");
>>> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 =
>>> _DMA_SBLK("11");
>>>
>>> -#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
>>> - { \
>>> - .name = _name, .id = _id, \
>>> - .base = _base, .len = 0x1c8, \
>>> - .features = VIG_SDM845_MASK, \
>>> - .sblk = &_sblk, \
>>> - .xin_id = _xinid, \
>>> - .type = SSPP_TYPE_VIG, \
>>> - .clk_ctrl = _clkctrl \
>>> - }
>>> -
>>> -#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
>>> +#define SSPP_BLK(_name, _id, _base, _features, \
>>> + _sblk, _xinid, _type, _clkctrl) \
>>> { \
>>> .name = _name, .id = _id, \
>>> .base = _base, .len = 0x1c8, \
>>> - .features = DMA_SDM845_MASK, \
>>> + .features = _features, \
>>> .sblk = &_sblk, \
>>> .xin_id = _xinid, \
>>> - .type = SSPP_TYPE_DMA, \
>>> + .type = _type, \
>>> .clk_ctrl = _clkctrl \
>>> }
>>>
>>> static struct dpu_sspp_cfg sdm845_sspp[] = {
>>> - SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
>>> - sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
>>> - SSPP_VIG_BLK
Re: [Freedreno] [DPU PATCH 2/5] drm/msm/dpu: enable cursor plane for primary crtc
On 2018-06-20 19:18, Rob Clark wrote:
On Wed, Jun 20, 2018 at 8:50 AM, Sravanthi Kollukuduru
wrote:
Reserve one DMA pipe as cursor plane and also, update crtc
support of cursor in crtc_init.
hmm, mdp5 in 820 had real cursor planes in hw, did these go away? If
so I guess DMA plane is best candidate for cursor..
Hi Rob,
Yes, the hw cursor support is not present on sdm845.
The ozone compositor expects cursor planes to be present otherwise
cursor is not rendered on screen.
So, we are planning to use one of the DMA pipe for cursor plane.
Thanks,
Rajesh
BR,
-R
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53
+++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 7 +++-
4 files changed, 34 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f0aafec..56f6576 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2027,7 +2027,8 @@ static int _dpu_crtc_init_events(struct dpu_crtc
*dpu_crtc)
}
/* initialize crtc */
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
drm_plane *plane)
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
drm_plane *plane,
+ struct drm_plane
*cursor_plane)
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -2061,8 +2062,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
*dev, struct drm_plane *plane)
dpu_crtc_frame_event_work);
}
- drm_crtc_init_with_planes(dev, crtc, plane, NULL,
&dpu_crtc_funcs,
- NULL);
+ drm_crtc_init_with_planes(dev, crtc, plane,
+ cursor_plane, &dpu_crtc_funcs, NULL);
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
plane->crtc = crtc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 50c3d4b..b44750d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -366,7 +366,8 @@ void dpu_crtc_complete_commit(struct drm_crtc
*crtc,
* @plane: base plane
* @Return: new crtc object or error
*/
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
drm_plane *plane);
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
drm_plane *plane,
+ struct drm_plane *cursor_plane);
/**
* dpu_crtc_cancel_pending_flip - complete flip for clients on
lastclose
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index f0c2881..c0b8116 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -29,6 +29,9 @@
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
+#define DMA_CURSOR_SDM845_MASK \
+ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
+
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -169,45 +172,35 @@
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 =
_DMA_SBLK("10");
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 =
_DMA_SBLK("11");
-#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x1c8, \
- .features = VIG_SDM845_MASK, \
- .sblk = &_sblk, \
- .xin_id = _xinid, \
- .type = SSPP_TYPE_VIG, \
- .clk_ctrl = _clkctrl \
- }
-
-#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
+#define SSPP_BLK(_name, _id, _base, _features, \
+ _sblk, _xinid, _type, _clkctrl) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x1c8, \
- .features = DMA_SDM845_MASK, \
+ .features = _features, \
.sblk = &_sblk, \
.xin_id = _xinid, \
- .type = SSPP_TYPE_DMA, \
+ .type = _type, \
.clk_ctrl = _clkctrl \
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
- sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
- sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
- sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
- sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
- sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
- sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
-
Re: [Freedreno] [PATCH v11 1/5] dt-bindings: media: extend interface documentation for DSI and DP
On Fri, Jun 15, 2018 at 12:13:39PM +0530, Sandeep Panda wrote: > Properties like data-lanes, clock-noncontinuous and lane-polarities > are applicable to DSI and DisplayPort interface also. So update the > documentation to mention the same. > > Signed-off-by: Sandeep Panda > --- > Documentation/devicetree/bindings/media/video-interfaces.txt | 10 ++ > 1 file changed, 6 insertions(+), 4 deletions(-) Reviewed-by: Rob Herring ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v11 3/5] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
On Fri, Jun 15, 2018 at 12:13:41PM +0530, Sandeep Panda wrote: > Document the bindings used for the sn65dsi86 DSI to eDP bridge. > > Changes in v1: > - Rephrase the dt-binding descriptions to be more inline with existing >bindings (Andrzej Hajda). > - Add missing dt-binding that are parsed by corresponding driver >(Andrzej Hajda). > > Changes in v2: > - Remove edp panel specific dt-binding entries. Only keep bridge >specific entries (Sean Paul). > - Remove custom-modes dt entry since its usage is removed from driver also > (Sean Paul). > - Remove is-pluggable dt entry since this will not be needed anymore (Sean > Paul). > > Changes in v3: > - Remove irq-gpio dt entry and instead populate is an interrupt >property (Rob Herring). > > Changes in v4: > - Add link to bridge chip datasheet (Stephen Boyd) > - Add vpll and vcc regulator supply bindings (Stephen Boyd) > - Add ref clk optional dt binding (Stephen Boyd) > - Add gpio-controller optional dt binding (Stephen Boyd) > > Changes in v5: > - Use clock property to specify the input refclk (Stephen Boyd). > - Update gpio cell and pwm cell numbers (Stephen Boyd). > > Changes in v6: > - Add property to mention the lane mapping scheme and polarity inversion >(Stephen Boyd). > > Changes in v7: > - Detail description of lane mapping scheme dt property (Andrzej >Hajda/ Rob Herring). > - Removed HDP gpio binding, since the bridge uses IRQ signal to >determine HPD, and IRQ property is already documented in binding. > > Changes in v8: > - Removed unnecessary explanation of lane mapping and polarity dt >property, since these are already explained in media/video-interface >dt binidng (Rob Herring). > > Changes in v9: > - Avoid putting re-definition of lane mapping and polarity dt binding >(Rob Herring). > > Signed-off-by: Sandeep Panda > --- > .../bindings/display/bridge/ti,sn65dsi86.txt | 87 > ++ > 1 file changed, 87 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt Reviewed-by: Rob Herring ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [DPU PATCH 2/5] drm/msm/dpu: enable cursor plane for primary crtc
On Wed, Jun 20, 2018 at 8:50 AM, Sravanthi Kollukuduru
wrote:
> Reserve one DMA pipe as cursor plane and also, update crtc
> support of cursor in crtc_init.
hmm, mdp5 in 820 had real cursor planes in hw, did these go away? If
so I guess DMA plane is best candidate for cursor..
BR,
-R
>
> Signed-off-by: Sravanthi Kollukuduru
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53
> +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 7 +++-
> 4 files changed, 34 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index f0aafec..56f6576 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -2027,7 +2027,8 @@ static int _dpu_crtc_init_events(struct dpu_crtc
> *dpu_crtc)
> }
>
> /* initialize crtc */
> -struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
> *plane)
> +struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
> *plane,
> + struct drm_plane
> *cursor_plane)
> {
> struct drm_crtc *crtc = NULL;
> struct dpu_crtc *dpu_crtc = NULL;
> @@ -2061,8 +2062,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
> struct drm_plane *plane)
> dpu_crtc_frame_event_work);
> }
>
> - drm_crtc_init_with_planes(dev, crtc, plane, NULL, &dpu_crtc_funcs,
> - NULL);
> + drm_crtc_init_with_planes(dev, crtc, plane,
> + cursor_plane, &dpu_crtc_funcs, NULL);
>
> drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
> plane->crtc = crtc;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 50c3d4b..b44750d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -366,7 +366,8 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
> * @plane: base plane
> * @Return: new crtc object or error
> */
> -struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
> *plane);
> +struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
> *plane,
> + struct drm_plane *cursor_plane);
>
> /**
> * dpu_crtc_cancel_pending_flip - complete flip for clients on lastclose
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index f0c2881..c0b8116 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -29,6 +29,9 @@
> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
> BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
>
> +#define DMA_CURSOR_SDM845_MASK \
> + (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
> +
> #define MIXER_SDM845_MASK \
> (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>
> @@ -169,45 +172,35 @@
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10");
> static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11");
>
> -#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
> - { \
> - .name = _name, .id = _id, \
> - .base = _base, .len = 0x1c8, \
> - .features = VIG_SDM845_MASK, \
> - .sblk = &_sblk, \
> - .xin_id = _xinid, \
> - .type = SSPP_TYPE_VIG, \
> - .clk_ctrl = _clkctrl \
> - }
> -
> -#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
> +#define SSPP_BLK(_name, _id, _base, _features, \
> + _sblk, _xinid, _type, _clkctrl) \
> { \
> .name = _name, .id = _id, \
> .base = _base, .len = 0x1c8, \
> - .features = DMA_SDM845_MASK, \
> + .features = _features, \
> .sblk = &_sblk, \
> .xin_id = _xinid, \
> - .type = SSPP_TYPE_DMA, \
> + .type = _type, \
> .clk_ctrl = _clkctrl \
> }
>
> static struct dpu_sspp_cfg sdm845_sspp[] = {
> - SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
> - sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
> - SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
> - sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
> - SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
> - sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
> - SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
> - sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
> - SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
> - sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
> - SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
> - sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
> - SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
> - sdm845_dm
[Freedreno] [DPU PATCH 2/5] drm/msm/dpu: enable cursor plane for primary crtc
Reserve one DMA pipe as cursor plane and also, update crtc
support of cursor in crtc_init.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 7 +++-
4 files changed, 34 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f0aafec..56f6576 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2027,7 +2027,8 @@ static int _dpu_crtc_init_events(struct dpu_crtc
*dpu_crtc)
}
/* initialize crtc */
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor_plane)
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -2061,8 +2062,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
struct drm_plane *plane)
dpu_crtc_frame_event_work);
}
- drm_crtc_init_with_planes(dev, crtc, plane, NULL, &dpu_crtc_funcs,
- NULL);
+ drm_crtc_init_with_planes(dev, crtc, plane,
+ cursor_plane, &dpu_crtc_funcs, NULL);
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
plane->crtc = crtc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 50c3d4b..b44750d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -366,7 +366,8 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
* @plane: base plane
* @Return: new crtc object or error
*/
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
*plane);
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor_plane);
/**
* dpu_crtc_cancel_pending_flip - complete flip for clients on lastclose
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index f0c2881..c0b8116 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -29,6 +29,9 @@
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
+#define DMA_CURSOR_SDM845_MASK \
+ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
+
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -169,45 +172,35 @@
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10");
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11");
-#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x1c8, \
- .features = VIG_SDM845_MASK, \
- .sblk = &_sblk, \
- .xin_id = _xinid, \
- .type = SSPP_TYPE_VIG, \
- .clk_ctrl = _clkctrl \
- }
-
-#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
+#define SSPP_BLK(_name, _id, _base, _features, \
+ _sblk, _xinid, _type, _clkctrl) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x1c8, \
- .features = DMA_SDM845_MASK, \
+ .features = _features, \
.sblk = &_sblk, \
.xin_id = _xinid, \
- .type = SSPP_TYPE_DMA, \
+ .type = _type, \
.clk_ctrl = _clkctrl \
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
- sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
- sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
- sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
- sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
- sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
- sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
- sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
- SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
- sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
+ sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
+ sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
[Freedreno] [DPU PATCH 5/5] drm/msm/dpu: dynamic assignment of hw pipe to plane
Currently, there exists a static binding of hw pipe to
plane. This restricts wide plane support where plane width
exceeds the pipe's maximum width.
To enable such use cases, the hw pipes are dynamically
(re)allocated to a plane during atomic check based on the
plane capabilities.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 45 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 670 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
3 files changed, 414 insertions(+), 305 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 56f6576..afb8c79 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -175,7 +175,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
struct dpu_rect plane_crtc_roi;
u32 flush_mask;
- uint32_t stage_idx, lm_idx;
+ uint32_t stage_idx = 0, lm_idx;
+ int i;
int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
bool bg_alpha_enable = false;
@@ -204,11 +205,11 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
- DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
- crtc->base.id,
- pstate->stage,
- plane->base.id,
- dpu_plane_pipe(plane) - SSPP_VIG0,
+ DPU_DEBUG("crtc %d stage%d: plane%d ssppmode%d[%d %d] fb%d\n",
+ crtc->base.id, pstate->stage,
+ plane->base.id, pstate->num_pipes,
+ dpu_plane_pipe(pstate->pipe_hw[0]) - SSPP_VIG0,
+ dpu_plane_pipe(pstate->pipe_hw[1]) - SSPP_VIG0,
state->fb ? state->fb->base.id : -1);
format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
@@ -221,19 +222,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
bg_alpha_enable = true;
DPU_EVT32(DRMID(crtc), DRMID(plane),
- state->fb ? state->fb->base.id : -1,
- state->src_x >> 16, state->src_y >> 16,
- state->src_w >> 16, state->src_h >> 16,
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h);
-
- stage_idx = zpos_cnt[pstate->stage]++;
- stage_cfg->stage[pstate->stage][stage_idx] =
- dpu_plane_pipe(plane);
-
- DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
- dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- format->base.pixel_format, fb ? fb->modifier : 0);
+ state->fb ? state->fb->base.id : -1,
+ state->src_x >> 16, state->src_y >> 16,
+ state->src_w >> 16, state->src_h >> 16,
+ state->crtc_x, state->crtc_y,
+ state->crtc_w, state->crtc_h);
+
+ for (i = 0; i < pstate->num_pipes; i++) {
+ stage_idx = zpos_cnt[pstate->stage]++;
+ if (stage_idx >= PIPES_PER_STAGE)
+ break;
+
+ stage_cfg->stage[pstate->stage][stage_idx] =
+ dpu_plane_pipe(pstate->pipe_hw[i]);
+
+ DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
+ dpu_plane_pipe(pstate->pipe_hw[i]) - SSPP_VIG0,
+ pstate->stage, format->base.pixel_format,
+ fb ? fb->modifier : 0);
+ }
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index be40a2c..2c6960e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -81,40 +81,26 @@ enum dpu_plane_qos {
/*
* struct dpu_plane - local dpu plane structure
- * @aspace: address space pointer
* @csc_ptr: Points to dpu_csc_cfg structure to use for current
- * @catalog: Points to dpu catalog structure
- * @revalidate: force revalidation of all the plane properties
*/
struct dpu_plane {
struct drm_plane base;
struct mutex lock;
- enum dpu_sspp pipe;
- uint32_t features; /* capabilities from catalog */
uint32_t nformats;
uint32_t formats[64];
- struct dpu_hw_pipe *pipe_hw;
- struct dpu_hw_pipe_cfg pipe_cfg;
- struct dpu_hw_pipe_qos_cfg pipe_qos_cfg;
uint32_t color_fill;
[Freedreno] [DPU PATCH 3/5] drm/msm/dpu: remove static binding of hw pipe to plane
Expose all planes with superset of formats and with no
hw pipe static binding. Accordingly, remove checks from
atomic_check reflecting the decoupling.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 26 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 50 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 17 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 158 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 5 +-
5 files changed, 56 insertions(+), 200 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c0b8116..c2a7c64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -44,13 +44,6 @@
#define DEFAULT_DPU_LINE_WIDTH 2048
#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
-#define MAX_HORZ_DECIMATION4
-#define MAX_VERT_DECIMATION4
-
-#define MAX_UPSCALE_RATIO 20
-#define MAX_DOWNSCALE_RATIO4
-#define SSPP_UNITY_SCALE 1
-
#define STRCAT(X, Y) (X Y)
/*
@@ -58,9 +51,12 @@
*/
/* DPU top level caps */
static const struct dpu_caps sdm845_dpu_caps = {
+ .max_sspp_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_sspp_pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .csc_type = DPU_SSPP_CSC_10BIT,
.ubwc_version = DPU_HW_UBWC_VER_20,
.has_src_split = true,
.has_dim_layer = true,
@@ -128,19 +124,8 @@
* SSPP sub blocks config
*/
-/* SSPP common configuration */
-static const struct dpu_sspp_blks_common sdm845_sspp_common = {
- .maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
- .maxhdeciexp = MAX_HORZ_DECIMATION,
- .maxvdeciexp = MAX_VERT_DECIMATION,
-};
-
#define _VIG_SBLK(num) \
{ \
- .common = &sdm845_sspp_common, \
- .maxdwnscale = MAX_DOWNSCALE_RATIO, \
- .maxupscale = MAX_UPSCALE_RATIO, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
@@ -149,17 +134,12 @@
.csc_blk = {.name = STRCAT("sspp_csc", num), \
.id = DPU_SSPP_CSC_10BIT, \
.base = 0x1a00, .len = 0x100,}, \
- .format_list = plane_formats_yuv, \
}
#define _DMA_SBLK(num) \
{ \
- .common = &sdm845_sspp_common, \
- .maxdwnscale = SSPP_UNITY_SCALE, \
- .maxupscale = SSPP_UNITY_SCALE, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
- .format_list = plane_formats, \
}
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 1b04448..68644db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -63,6 +63,10 @@
#define CRTC_DUAL_MIXERS 2
+#define MAX_UPSCALE_RATIO 20
+#define MAX_DOWNSCALE_RATIO4
+#define SSPP_UNITY_SCALE 1
+
#define MAX_XIN_COUNT 16
/**
@@ -290,19 +294,26 @@ struct dpu_qos_lut_tbl {
/**
* struct dpu_caps - define DPU capabilities
- * @max_mixer_widthmax layer mixer line width support.
- * @max_mixer_blendstages max layer mixer blend stages or
+ * @max_sspp_width max: pixelwidth supported by this pipe
+ * @max_sspp_pixel_ram_size: size of latency hiding and
+ * de-tiling buffer in bytes
+ * @max_mixer_width: max layer mixer line width support
+ * @max_mixer_blendstages: max layer mixer blend stages or
* supported z order
- * @qseed_type qseed2 or qseed3 support.
- * @ubwc_version UBWC feature version (0x0 for not supported)
- * @has_src_split source split feature status
- * @has_dim_layer dim layer feature status
- * @has_idle_pcindicate if idle power collapse feature is supported
+ * @qseed_type: qseed2 or qseed3 support
+ * @csc_type: csc or csc_10bit support
+ * @ubwc_version: UBWC feature version (0x0 for not supported)
+ * @has_src_split: source split feature status
+ * @has_dim_layer: dim layer feature status
+ * @has_idle_pc:indicate if idle power collapse feature is supported
*/
struct dpu_caps {
+ u32 max_sspp_width;
+ u32 max_sspp_pixel_ram_size;
u32 max_mixer_width;
u32 max_mixer_blendstages;
u32 qseed_type;
+ u32 csc_type;
[Freedreno] [DPU PATCH 4/5] drm/msm/dpu: introduce state based plane resource management
A plane can be attached to a maximum of two hw pipes
in case of wide resolution greater than pipe's max width limit.
This mapping of hw pipe(s) to plane and number of pipes will be
maintained in the plane state.
Resource manager (RM) will handle the SSPP blocks reservation
for a given plane.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 11 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 156 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h| 20
3 files changed, 172 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index e0688895..4eb929b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -25,6 +25,8 @@
#include "dpu_hw_mdss.h"
#include "dpu_hw_sspp.h"
+#define PLANE_DUAL_PIPES 2
+
/**
* struct dpu_plane_state: Define dpu extension of drm plane state object
* @base: base drm plane state object
@@ -36,6 +38,8 @@
* @multirect_index: index of the rectangle of SSPP
* @multirect_mode: parallel or time multiplex multirect mode
* @pending: whether the current update is still pending
+ * @num_pipes: number of pipes attached to plane
+ * @pipe_hw: array of pointers to hardware pipes reserved for plane
* @scaler3_cfg: configuration data for scaler3
* @pixel_ext: configuration data for pixel extensions
* @scaler_check_state: indicates status of user provided pixel extension data
@@ -48,6 +52,10 @@ struct dpu_plane_state {
enum dpu_stage stage;
bool pending;
+ /* HW pipe config */
+ u32 num_pipes;
+ struct dpu_hw_pipe *pipe_hw[PLANE_DUAL_PIPES];
+
/* scaler configuration */
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
@@ -58,6 +66,9 @@ struct dpu_plane_state {
#define to_dpu_plane_state(x) \
container_of(x, struct dpu_plane_state, base)
+/* get plane id from dpu plane state */
+#define get_plane_id(x) ((x->base.plane)->base.id)
+
/**
* dpu_plane_pipe - return sspp identifier for the given plane
* @plane: Pointer to DRM plane object
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 018d01a..5387600 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -14,6 +14,7 @@
#define pr_fmt(fmt)"[drm:%s] " fmt, __func__
#include "dpu_kms.h"
+#include "dpu_hw_sspp.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_cdm.h"
@@ -22,10 +23,13 @@
#include "dpu_encoder.h"
#include "dpu_rm.h"
+#define RESERVED_BY_OTHER(drm_map_id, drm_id) \
+ (drm_map_id && (drm_map_id != drm_id))
+
/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @type: Type of hardware block this structure tracks
- * @drm_id:DRM component ID associated with the HW block
+ * @rm_id: DRM component ID associated with the HW block
* @id:Hardware ID number, within it's own space, ie. LM_X
* @hw:Pointer to the hardware register access object for this
block
*/
@@ -157,7 +161,8 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type,
void *hw)
dpu_hw_intf_destroy(hw);
break;
case DPU_HW_BLK_SSPP:
- /* SSPPs are not managed by the resource manager */
+ dpu_hw_sspp_destroy(hw);
+ break;
case DPU_HW_BLK_TOP:
/* Top is a singleton, not managed in hw_blks list */
case DPU_HW_BLK_MAX:
@@ -229,7 +234,8 @@ static int _dpu_rm_hw_blk_create(
hw = dpu_hw_intf_init(id, mmio, cat);
break;
case DPU_HW_BLK_SSPP:
- /* SSPPs are not managed by the resource manager */
+ hw = dpu_hw_sspp_init(id, mmio, cat);
+ break;
case DPU_HW_BLK_TOP:
/* Top is a singleton, not managed in hw_blks list */
case DPU_HW_BLK_MAX:
@@ -281,6 +287,15 @@ int dpu_rm_init(struct dpu_rm *rm,
}
/* Interrogate HW catalog and create tracking items for hw blocks */
+ for (i = 0; i < cat->sspp_count; i++) {
+ rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_SSPP,
+ cat->sspp[i].id, &cat->sspp[i]);
+ if (rc) {
+ DPU_ERROR("failed: sspp hw not available\n");
+ goto fail;
+ }
+ }
+
for (i = 0; i < cat->mixer_count; i++) {
struct dpu_lm_cfg *lm = &cat->mixer[i];
@@ -570,12 +585,10 @@ static int _dpu_rm_reserve_intf_related_hw(
}
static int _dpu_rm_release_hw_blk(
- struct dpu_rm *rm,
- struct dpu_crtc_state *state,
+ struct dpu_rm *rm, int drm_id,
enum dpu_hw_blk_type type)
{
struct dpu_rm_hw_iter iter;
-
[Freedreno] [DPU PATCH 0/5] Introduce plane virtualization in DPU driver
Currently, each drm plane controls a single HW pipe. For all use cases where plane width exceeds the maximum pipe width, the DPU driver will require more than one HW pipe. This patchset enables virtualization of planes through the following changes: (1) Expose all the planes with the superset of formats and without any static binding of HW pipe during the initialization. (2) Introduce the state based plane resource management. (3) Dynamically assign a maximum of two pipes per plane based on plane capabilities in atomic check. This patchset is based on https://patchwork.kernel.org/patch/10471479/ Sravanthi Kollukuduru (5): drm/msm/dpu: remove smart dma support drm/msm/dpu: enable cursor plane for primary crtc drm/msm/dpu: remove static binding of hw pipe to plane drm/msm/dpu: introduce state based plane resource management drm/msm/dpu: dynamic assignment of hw pipe to plane drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 103 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 104 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 69 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 76 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |4 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 159 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h| 56 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 48 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1063 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 58 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 156 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 20 + drivers/gpu/drm/msm/msm_drv.h |2 +- 14 files changed, 744 insertions(+), 1177 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 1/5] drm/msm/dpu: remove smart dma support
Removing the smart dma feature implementation as it is
currently not enabled on dpu driver.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 51 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 25 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 19 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 76 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 159 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h| 56 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 26 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 265 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 38 +---
drivers/gpu/drm/msm/msm_drv.h | 2 +-
11 files changed, 84 insertions(+), 637 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 6c78c11c3..f0aafec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -230,12 +230,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
stage_idx = zpos_cnt[pstate->stage]++;
stage_cfg->stage[pstate->stage][stage_idx] =
dpu_plane_pipe(plane);
- stage_cfg->multirect_index[pstate->stage][stage_idx] =
- pstate->multirect_index;
DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- pstate->multirect_index, pstate->multirect_mode,
format->base.pixel_format, fb ? fb->modifier : 0);
/* blend config update */
@@ -1334,14 +1331,13 @@ struct plane_state {
struct dpu_plane_state *dpu_pstate;
const struct drm_plane_state *drm_pstate;
int stage;
- u32 pipe_id;
};
static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct dpu_crtc *dpu_crtc;
- struct plane_state pstates[DPU_STAGE_MAX * 4];
+ struct plane_state pstates[DPU_STAGE_MAX * 2];
struct dpu_crtc_state *cstate;
const struct drm_plane_state *pstate;
@@ -1351,10 +1347,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct dpu_private_state *dpu_priv_state;
int cnt = 0, rc = 0, mixer_width, i, z_pos;
-
- struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
- int multirect_count = 0;
- const struct drm_plane_state *pipe_staged[SSPP_MAX];
int left_zpos_cnt = 0, right_zpos_cnt = 0;
if (!crtc) {
@@ -1378,8 +1370,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (state->active_changed)
state->mode_changed = true;
- memset(pipe_staged, 0, sizeof(pipe_staged));
-
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
_dpu_crtc_setup_lm_bounds(crtc, state);
@@ -1398,18 +1388,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
pstates[cnt].drm_pstate = pstate;
pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = dpu_plane_pipe(plane);
-
- if (pipe_staged[pstates[cnt].pipe_id]) {
- multirect_plane[multirect_count].r0 =
- pipe_staged[pstates[cnt].pipe_id];
- multirect_plane[multirect_count].r1 = pstate;
- multirect_count++;
-
- pipe_staged[pstates[cnt].pipe_id] = NULL;
- } else {
- pipe_staged[pstates[cnt].pipe_id] = pstate;
- }
cnt++;
@@ -1426,20 +1404,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
}
}
- for (i = 1; i < SSPP_MAX; i++) {
- if (pipe_staged[i]) {
- dpu_plane_clear_multirect(pipe_staged[i]);
-
- if (is_dpu_plane_virtual(pipe_staged[i]->plane)) {
- DPU_ERROR(
- "r1 only virt plane:%d not supported\n",
- pipe_staged[i]->plane->base.id);
- rc = -EINVAL;
- goto end;
- }
- }
- }
-
z_pos = -1;
for (i = 0; i < cnt; i++) {
/* reset counts at every new blend stage */
@@ -1478,17 +1442,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos);
}
- for (i = 0; i < multirect_count; i++) {
- if (dpu_plane_validate_multirect_v2(&multirec
Re: [Freedreno] [PATCH 9/9] drm/msm: Always obey implicit fencing
On Thu, Apr 05, 2018 at 05:44:49PM +0200, Daniel Vetter wrote:
> Again same justification as for drm_gem_fb_prepare_fb().
>
> Definitely needs some testing because Rob doesn't remember why he did
> this, and Google/git.fd.o or anything also doesn't shed some light on
> it.
>
> Signed-off-by: Daniel Vetter
> Cc: Rob Clark
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedreno@lists.freedesktop.org
Just rebased this and noticed it's supreseeded by Sean Paul's work. I'd
appreciate some more official msm group maintainership so I have more
people to nag, since this not going anywhere has held up the entire patch
series.
-Daniel
> ---
> drivers/gpu/drm/msm/msm_atomic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> b/drivers/gpu/drm/msm/msm_atomic.c
> index bf5f8c39f34d..0dcdc922fc61 100644
> --- a/drivers/gpu/drm/msm/msm_atomic.c
> +++ b/drivers/gpu/drm/msm/msm_atomic.c
> @@ -201,7 +201,7 @@ int msm_atomic_commit(struct drm_device *dev,
>* Figure out what fence to wait for:
>*/
> for_each_oldnew_plane_in_state(state, plane, old_plane_state,
> new_plane_state, i) {
> - if ((new_plane_state->fb != old_plane_state->fb) &&
> new_plane_state->fb) {
> + if (new_plane_state->fb) {
> struct drm_gem_object *obj =
> msm_framebuffer_bo(new_plane_state->fb, 0);
> struct msm_gem_object *msm_obj = to_msm_bo(obj);
> struct dma_fence *fence =
> reservation_object_get_excl_rcu(msm_obj->resv);
> --
> 2.16.2
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
