[Freedreno] [PATCH 1/2] drm/msm/gpu: fix msm_gpu_crashstate_capture stub prototype
The function prototype recently changed, but the patch missed the
second prototype that is used when CONFIG_DEV_COREDUMP is disabled:
drivers/gpu/drm/msm/msm_gpu.c: In function 'recover_worker':
drivers/gpu/drm/msm/msm_gpu.c:461:34: error: passing argument 2 of
'msm_gpu_crashstate_capture' from incompatible pointer type
[-Werror=incompatible-pointer-types]
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
^~
drivers/gpu/drm/msm/msm_gpu.c:370:67: note: expected 'char *' but argument is
of type 'struct msm_gem_submit *'
static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
~~^~~~
drivers/gpu/drm/msm/msm_gpu.c:461:2: error: too many arguments to function
'msm_gpu_crashstate_capture'
msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
^~
drivers/gpu/drm/msm/msm_gpu.c:370:13: note: declared here
static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
Change the stub to match the normal function.
Fixes: cdb95931dea3 ("drm/msm/gpu: Add the buffer objects from the submit to
the crash dump")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/msm/msm_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 5e808cfec345..46e6b82f7b66 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -367,8 +367,8 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
}
#else
-static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, char *comm,
- char *cmd)
+static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
+ struct msm_gem_submit *submit, char *comm, char *cmd)
{
}
#endif
--
2.18.0
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Re: [Freedreno] [PATCH v3 01/13] drm/msm/dpu: remove scalar config definitions
On Tue, Aug 07, 2018 at 08:12:28PM -0700, Jeykumar Sankaran wrote:
> cleans up left out scalar config definitions from headers
>
> changes in v2:
> - none
> changes in v3:
> - none
>
> Change-Id: Id824dd5075c666f97b964573c97215bb786eac75
Please strip Change-Id before sending patches.
Reviewed-by: Sean Paul
> Signed-off-by: Jeykumar Sankaran
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 10 --
> 2 files changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index e87109e..0e9aafa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -164,7 +164,6 @@ struct dpu_crtc_frame_event {
> * @cur_perf : current performance committed to clock/bandwidth driver
> * @rp_lock : serialization lock for resource pool
> * @rp_head : list of active resource pool
> - * @scl3_cfg_lut : qseed3 lut config
> */
> struct dpu_crtc {
> struct drm_crtc base;
> @@ -175,7 +174,6 @@ struct dpu_crtc {
> u32 num_mixers;
> bool mixers_swapped;
> struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> - struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
>
> struct drm_pending_vblank_event *event;
> u32 vsync_count;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> index 1240f50..c5c8f60 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> @@ -148,16 +148,6 @@ struct dpu_hw_scaler3_cfg {
> struct dpu_hw_scaler3_de_cfg de;
> };
>
> -struct dpu_hw_scaler3_lut_cfg {
> - bool is_configured;
> - u32 *dir_lut;
> - size_t dir_len;
> - u32 *cir_lut;
> - size_t cir_len;
> - u32 *sep_lut;
> - size_t sep_len;
> -};
> -
> /**
> * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
> * @num_ext_pxls_lr: Number of total horizontal pixels
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] db820c: Input signal Out of range
Hello again > On Mon, Aug 13, 2018 at 2:16 PM Archit Taneja wrote: > > > > Are you seeing issues only for this mode in particular(1680x1050)? I'm > > wondering if the issue is specific to a frequency range. > > > > I have only tried with the native resolution of the panel, which on > both screens in 1680x1050 Result of the tests Screen 1 (Lenovo) FAILS: xrandr --output HDMI-1 --mode 1600x1000 --rate 60.01 OK: xrandr --output HDMI-1 --mode 1280x1024 --rate 75.02 FAILS: xrandr --output HDMI-1 --mode 1280x1024 --rate 72.05 FAILS: xrandr --output HDMI-1 --mode 1280x1024 --rate 60.02 OK: xrandr --output HDMI-1 --mode 1440x900 --rate 74.98 OK: xrandr --output HDMI-1 --mode 1440x900 --rate 59.90 FAILS: xrandr --output HDMI-1 --mode 1152x864 --rate 75.00 OK: xrandr --output HDMI-1 --mode 1024x768 --rate 75.03 OK: xrandr --output HDMI-1 --mode 1024x768 --rate 70.07 FAILS: xrandr --output HDMI-1 --mode 1024x768 --rate 60.00 FAILS: xrandr --output HDMI-1 --mode 800x600 --rate 72.19 FAILS: xrandr --output HDMI-1 --mode 800x600 --rate 75.00 OK: xrandr --output HDMI-1 --mode 800x600 --rate 60.32 OK: xrandr --output HDMI-1 --mode 640x480 --rate 75.00 OK: xrandr --output HDMI-1 --mode 640x480 --rate 72.81 FAILS: xrandr --output HDMI-1 --mode 640x480 --rate 66.67 FAILS: xrandr --output HDMI-1 --mode 640x480 --rate 59.94 FAILS:xrandr --output HDMI-1 --mode 720x400 --rate 70.08 [16.216] (II) modeset(0): EDID (in hex): [16.216] (II) modeset(0): 000030ae0c0a01010101 [16.216] (II) modeset(0): 1e140103802f1e78eedc55a359489e24 [16.216] (II) modeset(0): 115054bdcf00714f8180818c9500950f [16.216] (II) modeset(0): a900b300010126399030621a274068b0 [16.216] (II) modeset(0): 3600da28111a00fd00324b1e [16.216] (II) modeset(0): 5311000a20202020202000fc004c [16.216] (II) modeset(0): 32323530702057696465202000ff [16.217] (II) modeset(0): 003656365637350a2020202000a8 [16.217] (II) modeset(0): Printing probed modes for output HDMI-1 [16.217] (II) modeset(0): Modeline "1680x1050"x60.0 146.30 1680 1784 1960 2240 1050 1053 1059 1089 +hsync -vsync (65.3 kHz eP) [16.217] (II) modeset(0): Modeline "1600x1000"x60.0 133.16 1600 1704 1872 2144 1000 1001 1004 1035 -hsync +vsync (62.1 kHz) [16.217] (II) modeset(0): Modeline "1280x1024"x75.0 135.00 1280 1296 1440 1688 1024 1025 1028 1066 +hsync +vsync (80.0 kHz e) [16.217] (II) modeset(0): Modeline "1280x1024"x72.0 132.84 1280 1368 1504 1728 1024 1025 1028 1067 -hsync +vsync (76.9 kHz) [16.217] (II) modeset(0): Modeline "1280x1024"x60.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz e) [16.217] (II) modeset(0): Modeline "1440x900"x75.0 136.75 1440 1536 1688 1936 900 903 909 942 -hsync +vsync (70.6 kHz e) [16.217] (II) modeset(0): Modeline "1440x900"x59.9 88.75 1440 1488 1520 1600 900 903 909 926 +hsync -vsync (55.5 kHz e) [16.217] (II) modeset(0): Modeline "1152x864"x75.0 108.00 1152 1216 1344 1600 864 865 868 900 +hsync +vsync (67.5 kHz e) [16.217] (II) modeset(0): Modeline "1024x768"x75.0 78.75 1024 1040 1136 1312 768 769 772 800 +hsync +vsync (60.0 kHz e) [16.217] (II) modeset(0): Modeline "1024x768"x70.1 75.00 1024 1048 1184 1328 768 771 777 806 -hsync -vsync (56.5 kHz e) [16.217] (II) modeset(0): Modeline "1024x768"x60.0 65.00 1024 1048 1184 1344 768 771 777 806 -hsync -vsync (48.4 kHz e) [16.217] (II) modeset(0): Modeline "800x600"x72.2 50.00 800 856 976 1040 600 637 643 666 +hsync +vsync (48.1 kHz e) [16.217] (II) modeset(0): Modeline "800x600"x75.0 49.50 800 816 896 1056 600 601 604 625 +hsync +vsync (46.9 kHz e) [16.217] (II) modeset(0): Modeline "800x600"x60.3 40.00 800 840 968 1056 600 601 605 628 +hsync +vsync (37.9 kHz e) [16.217] (II) modeset(0): Modeline "640x480"x75.0 31.50 640 656 720 840 480 481 484 500 -hsync -vsync (37.5 kHz e) [16.217] (II) modeset(0): Modeline "640x480"x72.8 31.50 640 664 704 832 480 489 492 520 -hsync -vsync (37.9 kHz e) [16.217] (II) modeset(0): Modeline "640x480"x66.7 30.24 640 704 768 864 480 483 486 525 -hsync -vsync (35.0 kHz e) [16.217] (II) modeset(0): Modeline "640x480"x59.9 25.18 640 656 752 800 480 490 492 525 -hsync -vsync (31.5 kHz e) [16.217] (II) modeset(0): Modeline "720x400"x70.1 28.32 720 738 846 900 400 412 414 449 -hsync +vsync (31.5 kHz e) Screen 2 (Samsung) OK: xrandr --output HDMI-1 --mode 1280x1024 --rate 75.02 FAILS: xrandr --output HDMI-1 --mode 1280x1024 --rate 60.02 FAILS: xrandr --output HDMI-1 --mode 1280x960 --rate 60.00 FAILS: xrandr --output HDMI-1 --mode 1152x864 --rate 75.00 OK: xrandr --output HDMI-1 --mode 1024x768 --rate 75.03 OK: xrandr --output HDMI-1 --mode 1024x768 --rate 70.07 FAILS: xrandr --output HDMI-1 --mode 1024x768 --rate 60.00 OK: xrandr --output HDMI-1 --mode 832x624 --rate 74.55 FAILS: xrandr --output HDMI-1 --mode 800x600 --rate 72.19 FAILS: xrandr --output HDMI-1
Re: [Freedreno] db820c: Input signal Out of range
Hi Archit, On Mon, Aug 13, 2018 at 2:16 PM Archit Taneja wrote: > > Hi, > > > > On Monday 13 August 2018 02:24 PM, Ricardo Ribalda Delgado wrote: > > Hi Archit > > On Sun, Aug 12, 2018 at 9:47 AM Archit Taneja > > wrote: > >> > >> Hi, > >> > >> On Friday 10 August 2018 12:08 PM, Ricardo Ribalda Delgado wrote: > >>> Hello > >>> > >>> I have a screen that via edid expects the following modeline by > >>> default via detailed mode: > >>> > >>> Modeline "1680x1050"x60.0 146.30 1680 1784 1960 2240 1050 1053 1059 > >>> 1089 +hsync -vsync > >>> > >>> When the card is configured to that modeline the screen cannot output > >>> the image and shows the following error message: Input signal out of > >>> range. > >>> > >>> I have tried with a different card and that exact modeline: > >>> > >>> xrandr --newmode fast 146.30 1680 1784 1960 2240 1050 1053 1059 1089 > >>> +hsync -vsync > >>> xrandr --addmode HDMI-1 slow > >>> xrandr --output HDMI-1 --mode fast > >>> > >>> and the screen works just fine. > >>> > >>> > >>> If I just tweak down a bit the clock: > >>> xrandr --newmode slow 146.25 1680 1784 1960 2240 1050 1053 1059 1089 > >>> +hsync -vsync > >>> the screen shows an image as expected. > >>> > >>> I believe that there might be a misscalculation on the pll code. And I > >>> am printing the debug info from: > >>> drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c > >>> > >>> The configuration that fails shows: > >>> > >>> [ 138.553168] VCO freq: 877800 > >>> [ 138.553172] fdata: 146300 > >>> [ 138.553187] pix_clk: 14630 > >>> [ 138.555447] tmds clk: 14630 > >>> [ 138.558336] HSCLK_SEL: 1 > >>> [ 138.561277] DEC_START: 114 > >>> [ 138.564316] DIV_FRAC_START: 311296 > >>> [ 138.567080] PLL_CPCTRL: 11 > >>> [ 138.569614] PLL_RCTRL: 22 > >>> [ 138.572996] PLL_CCTRL: 40 > >>> [ 138.575698] INTEGLOOP_GAIN: 256 > >>> [ 138.578366] TX_BAND: 0 > >>> [ 138.580986] PLL_CMP: 7802 > >>> [ 138.583936] com_svs_mode_clk_sel = 0x2 > >>> [ 138.586351] com_hsclk_sel = 0x21 > >>> [ 138.589067] com_lock_cmp_en = 0x0 > >>> [ 138.592704] com_pll_cctrl_mode0 = 0x28 > >>> [ 138.596089] com_pll_rctrl_mode0 = 0x16 > >>> [ 138.599286] com_cp_ctrl_mode0 = 0xb > >>> [ 138.602955] com_dec_start_mode0 = 0x72 > >>> [ 138.606678] com_div_frac_start1_mode0 = 0x0 > >>> [ 138.610064] com_div_frac_start2_mode0 = 0xc0 > >>> [ 138.613894] com_div_frac_start3_mode0 = 0x4 > >>> [ 138.617964] com_integloop_gain0_mode0 = 0x0 > >>> [ 138.622478] com_integloop_gain1_mode0 = 0x1 > >>> [ 138.626393] com_lock_cmp1_mode0 = 0x7a > >>> [ 138.630550] com_lock_cmp2_mode0 = 0x1e > >>> [ 138.634719] com_lock_cmp3_mode0 = 0x0 > >>> [ 138.638545] com_core_clk_en = 0x2c > >>> [ 138.642271] com_coreclk_div = 0x5 > >>> [ 138.646001] phy_mode = 0x0 > >>> [ 138.649308] tx_l0_lane_mode = 0x43 > >>> [ 138.652684] tx_l2_lane_mode = 0x43 > >>> [ 138.655275] tx_l0_tx_band = 0x4 > >>> [ 138.658679] tx_l0_tx_drv_lvl = 0x25 > >>> [ 138.662070] tx_l0_tx_emp_post1_lvl = 0x23 > >>> [ 138.665101] tx_l0_vmode_ctrl1 = 0x0 > >>> [ 138.668571] tx_l0_vmode_ctrl2 = 0xd > >>> [ 138.672747] tx_l1_tx_band = 0x4 > >>> [ 138.676037] tx_l1_tx_drv_lvl = 0x25 > >>> [ 138.679493] tx_l1_tx_emp_post1_lvl = 0x23 > >>> [ 138.682633] tx_l1_vmode_ctrl1 = 0x0 > >>> [ 138.686117] tx_l1_vmode_ctrl2 = 0xd > >>> [ 138.690272] tx_l2_tx_band = 0x4 > >>> [ 138.693571] tx_l2_tx_drv_lvl = 0x25 > >>> [ 138.697050] tx_l2_tx_emp_post1_lvl = 0x23 > >>> [ 138.700168] tx_l2_vmode_ctrl1 = 0x0 > >>> [ 138.703641] tx_l2_vmode_ctrl2 = 0xd > >>> [ 138.707816] tx_l3_tx_band = 0x4 > >>> [ 138.711092] tx_l3_tx_drv_lvl = 0x25 > >>> [ 138.714577] tx_l3_tx_emp_post1_lvl = 0x23 > >>> [ 138.717705] tx_l3_vmode_ctrl1 = 0x0 > >>> [ 138.721182] tx_l3_vmode_ctrl2 = 0x0 > >>> > >>> and the configuration that works: > >>> > >>> [ 62.936970] VCO freq: 877500 > >>> [ 62.936976] fdata: 146250 > >>> [ 62.936990] pix_clk: 14625 > >>> [ 62.939250] tmds clk: 14625 > >>> [ 62.942175] HSCLK_SEL: 1 > >>> [ 62.945095] DEC_START: 114 > >>> [ 62.948117] DIV_FRAC_START: 270336 > >>> [ 62.950881] PLL_CPCTRL: 11 > >>> [ 62.953421] PLL_RCTRL: 22 > >>> [ 62.956798] PLL_CCTRL: 40 > >>> [ 62.959475] INTEGLOOP_GAIN: 256 > >>> [ 62.962179] TX_BAND: 0 > >>> [ 62.964785] PLL_CMP: 7799 > >>> [ 62.967738] com_svs_mode_clk_sel = 0x2 > >>> [ 62.970153] com_hsclk_sel = 0x21 > >>> [ 62.972862] com_lock_cmp_en = 0x0 > >>> [ 62.976506] com_pll_cctrl_mode0 = 0x28 > >>> [ 62.979893] com_pll_rctrl_mode0 = 0x16 > >>> [ 62.983088] com_cp_ctrl_mode0 = 0xb > >>> [ 62.986749] com_dec_start_mode0 = 0x72 > >>> [ 62.990480] com_div_frac_start1_mode0 = 0x0 > >>> [ 62.993868] com_div_frac_start2_mode0 = 0x20 > >>> [ 62.997688] com_div_frac_start3_mode0 = 0x4 > >>> [ 63.001769] com_integloop_gain0_mode0 = 0x0 > >>> [ 63.006281] com_integloop_gain1_mode0 = 0x1 > >>> [ 63.010189] com_lock_cmp1_mode0 = 0x77 > >>> [ 63.014354] com_lock_cmp2_mode0 = 0x1e >
Re: [Freedreno] db820c: Input signal Out of range
Hi, On Monday 13 August 2018 02:24 PM, Ricardo Ribalda Delgado wrote: Hi Archit On Sun, Aug 12, 2018 at 9:47 AM Archit Taneja wrote: Hi, On Friday 10 August 2018 12:08 PM, Ricardo Ribalda Delgado wrote: Hello I have a screen that via edid expects the following modeline by default via detailed mode: Modeline "1680x1050"x60.0 146.30 1680 1784 1960 2240 1050 1053 1059 1089 +hsync -vsync When the card is configured to that modeline the screen cannot output the image and shows the following error message: Input signal out of range. I have tried with a different card and that exact modeline: xrandr --newmode fast 146.30 1680 1784 1960 2240 1050 1053 1059 1089 +hsync -vsync xrandr --addmode HDMI-1 slow xrandr --output HDMI-1 --mode fast and the screen works just fine. If I just tweak down a bit the clock: xrandr --newmode slow 146.25 1680 1784 1960 2240 1050 1053 1059 1089 +hsync -vsync the screen shows an image as expected. I believe that there might be a misscalculation on the pll code. And I am printing the debug info from: drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c The configuration that fails shows: [ 138.553168] VCO freq: 877800 [ 138.553172] fdata: 146300 [ 138.553187] pix_clk: 14630 [ 138.555447] tmds clk: 14630 [ 138.558336] HSCLK_SEL: 1 [ 138.561277] DEC_START: 114 [ 138.564316] DIV_FRAC_START: 311296 [ 138.567080] PLL_CPCTRL: 11 [ 138.569614] PLL_RCTRL: 22 [ 138.572996] PLL_CCTRL: 40 [ 138.575698] INTEGLOOP_GAIN: 256 [ 138.578366] TX_BAND: 0 [ 138.580986] PLL_CMP: 7802 [ 138.583936] com_svs_mode_clk_sel = 0x2 [ 138.586351] com_hsclk_sel = 0x21 [ 138.589067] com_lock_cmp_en = 0x0 [ 138.592704] com_pll_cctrl_mode0 = 0x28 [ 138.596089] com_pll_rctrl_mode0 = 0x16 [ 138.599286] com_cp_ctrl_mode0 = 0xb [ 138.602955] com_dec_start_mode0 = 0x72 [ 138.606678] com_div_frac_start1_mode0 = 0x0 [ 138.610064] com_div_frac_start2_mode0 = 0xc0 [ 138.613894] com_div_frac_start3_mode0 = 0x4 [ 138.617964] com_integloop_gain0_mode0 = 0x0 [ 138.622478] com_integloop_gain1_mode0 = 0x1 [ 138.626393] com_lock_cmp1_mode0 = 0x7a [ 138.630550] com_lock_cmp2_mode0 = 0x1e [ 138.634719] com_lock_cmp3_mode0 = 0x0 [ 138.638545] com_core_clk_en = 0x2c [ 138.642271] com_coreclk_div = 0x5 [ 138.646001] phy_mode = 0x0 [ 138.649308] tx_l0_lane_mode = 0x43 [ 138.652684] tx_l2_lane_mode = 0x43 [ 138.655275] tx_l0_tx_band = 0x4 [ 138.658679] tx_l0_tx_drv_lvl = 0x25 [ 138.662070] tx_l0_tx_emp_post1_lvl = 0x23 [ 138.665101] tx_l0_vmode_ctrl1 = 0x0 [ 138.668571] tx_l0_vmode_ctrl2 = 0xd [ 138.672747] tx_l1_tx_band = 0x4 [ 138.676037] tx_l1_tx_drv_lvl = 0x25 [ 138.679493] tx_l1_tx_emp_post1_lvl = 0x23 [ 138.682633] tx_l1_vmode_ctrl1 = 0x0 [ 138.686117] tx_l1_vmode_ctrl2 = 0xd [ 138.690272] tx_l2_tx_band = 0x4 [ 138.693571] tx_l2_tx_drv_lvl = 0x25 [ 138.697050] tx_l2_tx_emp_post1_lvl = 0x23 [ 138.700168] tx_l2_vmode_ctrl1 = 0x0 [ 138.703641] tx_l2_vmode_ctrl2 = 0xd [ 138.707816] tx_l3_tx_band = 0x4 [ 138.711092] tx_l3_tx_drv_lvl = 0x25 [ 138.714577] tx_l3_tx_emp_post1_lvl = 0x23 [ 138.717705] tx_l3_vmode_ctrl1 = 0x0 [ 138.721182] tx_l3_vmode_ctrl2 = 0x0 and the configuration that works: [ 62.936970] VCO freq: 877500 [ 62.936976] fdata: 146250 [ 62.936990] pix_clk: 14625 [ 62.939250] tmds clk: 14625 [ 62.942175] HSCLK_SEL: 1 [ 62.945095] DEC_START: 114 [ 62.948117] DIV_FRAC_START: 270336 [ 62.950881] PLL_CPCTRL: 11 [ 62.953421] PLL_RCTRL: 22 [ 62.956798] PLL_CCTRL: 40 [ 62.959475] INTEGLOOP_GAIN: 256 [ 62.962179] TX_BAND: 0 [ 62.964785] PLL_CMP: 7799 [ 62.967738] com_svs_mode_clk_sel = 0x2 [ 62.970153] com_hsclk_sel = 0x21 [ 62.972862] com_lock_cmp_en = 0x0 [ 62.976506] com_pll_cctrl_mode0 = 0x28 [ 62.979893] com_pll_rctrl_mode0 = 0x16 [ 62.983088] com_cp_ctrl_mode0 = 0xb [ 62.986749] com_dec_start_mode0 = 0x72 [ 62.990480] com_div_frac_start1_mode0 = 0x0 [ 62.993868] com_div_frac_start2_mode0 = 0x20 [ 62.997688] com_div_frac_start3_mode0 = 0x4 [ 63.001769] com_integloop_gain0_mode0 = 0x0 [ 63.006281] com_integloop_gain1_mode0 = 0x1 [ 63.010189] com_lock_cmp1_mode0 = 0x77 [ 63.014354] com_lock_cmp2_mode0 = 0x1e [ 63.018521] com_lock_cmp3_mode0 = 0x0 [ 63.022338] com_core_clk_en = 0x2c [ 63.026072] com_coreclk_div = 0x5 [ 63.029804] phy_mode = 0x0 [ 63.033103] tx_l0_lane_mode = 0x43 [ 63.036488] tx_l2_lane_mode = 0x43 [ 63.039078] tx_l0_tx_band = 0x4 [ 63.042479] tx_l0_tx_drv_lvl = 0x25 [ 63.045864] tx_l0_tx_emp_post1_lvl = 0x23 [ 63.048901] tx_l0_vmode_ctrl1 = 0x0 [ 63.052375] tx_l0_vmode_ctrl2 = 0xd [ 63.056541] tx_l1_tx_band = 0x4 [ 63.059840] tx_l1_tx_drv_lvl = 0x25 [ 63.063295] tx_l1_tx_emp_post1_lvl = 0x23 [ 63.066437] tx_l1_vmode_ctrl1 = 0x0 [ 63.069908] tx_l1_vmode_ctrl2 = 0xd [ 63.074075] tx_l2_tx_band = 0x4 [ 63.077373] tx_l2_tx_drv_lvl = 0x25 [ 63.080844] tx_l2_tx_emp_post1_lvl = 0x23 [ 63.083971] tx_l2_vmode_ctrl1 = 0x0 [
Re: [Freedreno] db820c: Input signal Out of range
Hi Archit On Sun, Aug 12, 2018 at 9:47 AM Archit Taneja wrote: > > Hi, > > On Friday 10 August 2018 12:08 PM, Ricardo Ribalda Delgado wrote: > > Hello > > > > I have a screen that via edid expects the following modeline by > > default via detailed mode: > > > > Modeline "1680x1050"x60.0 146.30 1680 1784 1960 2240 1050 1053 1059 > > 1089 +hsync -vsync > > > > When the card is configured to that modeline the screen cannot output > > the image and shows the following error message: Input signal out of > > range. > > > > I have tried with a different card and that exact modeline: > > > > xrandr --newmode fast 146.30 1680 1784 1960 2240 1050 1053 1059 1089 > > +hsync -vsync > > xrandr --addmode HDMI-1 slow > > xrandr --output HDMI-1 --mode fast > > > > and the screen works just fine. > > > > > > If I just tweak down a bit the clock: > > xrandr --newmode slow 146.25 1680 1784 1960 2240 1050 1053 1059 1089 > > +hsync -vsync > > the screen shows an image as expected. > > > > I believe that there might be a misscalculation on the pll code. And I > > am printing the debug info from: > > drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c > > > > The configuration that fails shows: > > > > [ 138.553168] VCO freq: 877800 > > [ 138.553172] fdata: 146300 > > [ 138.553187] pix_clk: 14630 > > [ 138.555447] tmds clk: 14630 > > [ 138.558336] HSCLK_SEL: 1 > > [ 138.561277] DEC_START: 114 > > [ 138.564316] DIV_FRAC_START: 311296 > > [ 138.567080] PLL_CPCTRL: 11 > > [ 138.569614] PLL_RCTRL: 22 > > [ 138.572996] PLL_CCTRL: 40 > > [ 138.575698] INTEGLOOP_GAIN: 256 > > [ 138.578366] TX_BAND: 0 > > [ 138.580986] PLL_CMP: 7802 > > [ 138.583936] com_svs_mode_clk_sel = 0x2 > > [ 138.586351] com_hsclk_sel = 0x21 > > [ 138.589067] com_lock_cmp_en = 0x0 > > [ 138.592704] com_pll_cctrl_mode0 = 0x28 > > [ 138.596089] com_pll_rctrl_mode0 = 0x16 > > [ 138.599286] com_cp_ctrl_mode0 = 0xb > > [ 138.602955] com_dec_start_mode0 = 0x72 > > [ 138.606678] com_div_frac_start1_mode0 = 0x0 > > [ 138.610064] com_div_frac_start2_mode0 = 0xc0 > > [ 138.613894] com_div_frac_start3_mode0 = 0x4 > > [ 138.617964] com_integloop_gain0_mode0 = 0x0 > > [ 138.622478] com_integloop_gain1_mode0 = 0x1 > > [ 138.626393] com_lock_cmp1_mode0 = 0x7a > > [ 138.630550] com_lock_cmp2_mode0 = 0x1e > > [ 138.634719] com_lock_cmp3_mode0 = 0x0 > > [ 138.638545] com_core_clk_en = 0x2c > > [ 138.642271] com_coreclk_div = 0x5 > > [ 138.646001] phy_mode = 0x0 > > [ 138.649308] tx_l0_lane_mode = 0x43 > > [ 138.652684] tx_l2_lane_mode = 0x43 > > [ 138.655275] tx_l0_tx_band = 0x4 > > [ 138.658679] tx_l0_tx_drv_lvl = 0x25 > > [ 138.662070] tx_l0_tx_emp_post1_lvl = 0x23 > > [ 138.665101] tx_l0_vmode_ctrl1 = 0x0 > > [ 138.668571] tx_l0_vmode_ctrl2 = 0xd > > [ 138.672747] tx_l1_tx_band = 0x4 > > [ 138.676037] tx_l1_tx_drv_lvl = 0x25 > > [ 138.679493] tx_l1_tx_emp_post1_lvl = 0x23 > > [ 138.682633] tx_l1_vmode_ctrl1 = 0x0 > > [ 138.686117] tx_l1_vmode_ctrl2 = 0xd > > [ 138.690272] tx_l2_tx_band = 0x4 > > [ 138.693571] tx_l2_tx_drv_lvl = 0x25 > > [ 138.697050] tx_l2_tx_emp_post1_lvl = 0x23 > > [ 138.700168] tx_l2_vmode_ctrl1 = 0x0 > > [ 138.703641] tx_l2_vmode_ctrl2 = 0xd > > [ 138.707816] tx_l3_tx_band = 0x4 > > [ 138.711092] tx_l3_tx_drv_lvl = 0x25 > > [ 138.714577] tx_l3_tx_emp_post1_lvl = 0x23 > > [ 138.717705] tx_l3_vmode_ctrl1 = 0x0 > > [ 138.721182] tx_l3_vmode_ctrl2 = 0x0 > > > > and the configuration that works: > > > > [ 62.936970] VCO freq: 877500 > > [ 62.936976] fdata: 146250 > > [ 62.936990] pix_clk: 14625 > > [ 62.939250] tmds clk: 14625 > > [ 62.942175] HSCLK_SEL: 1 > > [ 62.945095] DEC_START: 114 > > [ 62.948117] DIV_FRAC_START: 270336 > > [ 62.950881] PLL_CPCTRL: 11 > > [ 62.953421] PLL_RCTRL: 22 > > [ 62.956798] PLL_CCTRL: 40 > > [ 62.959475] INTEGLOOP_GAIN: 256 > > [ 62.962179] TX_BAND: 0 > > [ 62.964785] PLL_CMP: 7799 > > [ 62.967738] com_svs_mode_clk_sel = 0x2 > > [ 62.970153] com_hsclk_sel = 0x21 > > [ 62.972862] com_lock_cmp_en = 0x0 > > [ 62.976506] com_pll_cctrl_mode0 = 0x28 > > [ 62.979893] com_pll_rctrl_mode0 = 0x16 > > [ 62.983088] com_cp_ctrl_mode0 = 0xb > > [ 62.986749] com_dec_start_mode0 = 0x72 > > [ 62.990480] com_div_frac_start1_mode0 = 0x0 > > [ 62.993868] com_div_frac_start2_mode0 = 0x20 > > [ 62.997688] com_div_frac_start3_mode0 = 0x4 > > [ 63.001769] com_integloop_gain0_mode0 = 0x0 > > [ 63.006281] com_integloop_gain1_mode0 = 0x1 > > [ 63.010189] com_lock_cmp1_mode0 = 0x77 > > [ 63.014354] com_lock_cmp2_mode0 = 0x1e > > [ 63.018521] com_lock_cmp3_mode0 = 0x0 > > [ 63.022338] com_core_clk_en = 0x2c > > [ 63.026072] com_coreclk_div = 0x5 > > [ 63.029804] phy_mode = 0x0 > > [ 63.033103] tx_l0_lane_mode = 0x43 > > [ 63.036488] tx_l2_lane_mode = 0x43 > > [ 63.039078] tx_l0_tx_band = 0x4 > > [ 63.042479] tx_l0_tx_drv_lvl = 0x25 > > [ 63.045864] tx_l0_tx_emp_post1_lvl = 0x23 > > [ 63.048901]
