Re: [Freedreno] [PATCH v16 4/5] dt-bindings: arm-smmu: Add bindings for qcom, smmu-v2
Hi Rob,
On Thu, Aug 30, 2018 at 8:16 PM Vivek Gautam
wrote:
>
> Add bindings doc for Qcom's smmu-v2 implementation.
>
> Signed-off-by: Vivek Gautam
> Reviewed-by: Tomasz Figa
> Tested-by: Srinivas Kandagatla
> ---
I removed your reviewed-by for this particular patch.
Can you please consider giving your review if you find the changes okay now.
Thanks.
Best regards
Vivek
> .../devicetree/bindings/iommu/arm,smmu.txt | 39
> ++
> 1 file changed, 39 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 8a6ffce12af5..a6504b37cc21 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -17,10 +17,16 @@ conditions.
> "arm,mmu-401"
> "arm,mmu-500"
> "cavium,smmu-v2"
> +"qcom,smmu-v2"
>
>depending on the particular implementation and/or the
>version of the architecture implemented.
>
> + Qcom SoCs must contain, as below, SoC-specific compatibles
> + along with "qcom,smmu-v2":
> + "qcom,msm8996-smmu-v2", "qcom,smmu-v2",
> + "qcom,sdm845-smmu-v2", "qcom,smmu-v2".
> +
> - reg : Base address and size of the SMMU.
>
> - #global-interrupts : The number of global interrupts exposed by the
> @@ -71,6 +77,22 @@ conditions.
>or using stream matching with #iommu-cells = <2>, and
>may be ignored if present in such cases.
>
> +- clock-names:List of the names of clocks input to the device. The
> + required list depends on particular implementation and
> + is as follows:
> + - for "qcom,smmu-v2":
> +- "bus": clock required for downstream bus access and
> + for the smmu ptw,
> +- "iface": clock required to access smmu's registers
> + through the TCU's programming interface.
> + - unspecified for other implementations.
> +
> +- clocks: Specifiers for all clocks listed in the clock-names
> property,
> + as per generic clock bindings.
> +
> +- power-domains: Specifiers for power domains required to be powered on for
> + the SMMU to operate, as per generic power domain bindings.
> +
> ** Deprecated properties:
>
> - mmu-masters (deprecated in favour of the generic "iommus" binding) :
> @@ -137,3 +159,20 @@ conditions.
> iommu-map = <0 0 0x400>;
> ...
> };
> +
> + /* Qcom's arm,smmu-v2 implementation */
> + smmu4: iommu@d0 {
> + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> + reg = <0xd0 0x1>;
> +
> + #global-interrupts = <1>;
> + interrupts = ,
> +,
> +;
> + #iommu-cells = <1>;
> + power-domains = < MDSS_GDSC>;
> +
> + clocks = < SMMU_MDP_AXI_CLK>,
> +< SMMU_MDP_AHB_CLK>;
> + clock-names = "bus", "iface";
> + };
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
> ___
> iommu mailing list
> io...@lists.linux-foundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/iommu
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 15/19] drm/msm/dpu: remove LOCK/CLEAR support in RM
DPU had the support to LOCK the hw resources in
atomic check and CLEAR the locked resources explicitly
through custom property values. Now that DPU is
stripped off of all the custom properties, the RM
handlers for this feature will be no-op's. This change
gets rid of all its references.
changes in v5:
- Introduced in the series.
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 25 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 16
2 files changed, 2 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index e2e64fe..42751ba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -24,8 +24,6 @@
#define RESERVED_BY_OTHER(h, r) \
((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
-#define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_LOCK))
-#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(DPU_RM_TOPCTL_RESERVE_CLEAR))
#define RM_IS_TOPOLOGY_MATCH(t, r) ((t).num_lm == (r).num_lm && \
(t).num_comp_enc == (r).num_enc && \
(t).num_intf == (r).num_intf)
@@ -48,12 +46,10 @@ struct dpu_rm_topology_def {
/**
* struct dpu_rm_requirements - Reservation requirements parameter bundle
- * @top_ctrl: topology control preference from kernel client
* @top: selected topology for the display
* @hw_res: Hardware resources required as reported by the encoders
*/
struct dpu_rm_requirements {
- uint64_t top_ctrl;
const struct dpu_rm_topology_def *topology;
struct dpu_encoder_hw_resources hw_res;
};
@@ -755,8 +751,7 @@ static int _dpu_rm_populate_requirements(
return -EINVAL;
}
- DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
- reqs->hw_res.display_num_of_h_tiles);
+ DRM_DEBUG_KMS("num_h_tiles: %d\n", reqs->hw_res.display_num_of_h_tiles);
DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
reqs->topology->num_lm, reqs->topology->num_ctl,
reqs->topology->top_name,
@@ -956,18 +951,6 @@ int dpu_rm_reserve(
rsvp_cur = _dpu_rm_get_rsvp(rm, enc);
- /*
-* User can request that we clear out any reservation during the
-* atomic_check phase by using this CLEAR bit
-*/
- if (rsvp_cur && test_only && RM_RQ_CLEAR()) {
- DPU_DEBUG("test_only & CLEAR: clear rsvp[s%de%d]\n",
- rsvp_cur->seq, rsvp_cur->enc_id);
- _dpu_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
- rsvp_cur = NULL;
- _dpu_rm_print_rsvps(rm, DPU_RM_STAGE_AFTER_CLEAR);
- }
-
/* Check the proposed reservation, store it in hw's "next" field */
ret = _dpu_rm_make_next_rsvp(rm, enc, crtc_state, conn_state,
rsvp_nxt, );
@@ -977,7 +960,7 @@ int dpu_rm_reserve(
if (ret) {
DPU_ERROR("failed to reserve hw resources: %d\n", ret);
_dpu_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
- } else if (test_only && !RM_RQ_LOCK()) {
+ } else if (test_only) {
/*
* Normally, if test_only, test the reservation and then undo
* However, if the user requests LOCK, then keep the reservation
@@ -987,10 +970,6 @@ int dpu_rm_reserve(
rsvp_nxt->seq, rsvp_nxt->enc_id);
_dpu_rm_release_rsvp(rm, rsvp_nxt, conn_state->connector);
} else {
- if (test_only && RM_RQ_LOCK())
- DPU_DEBUG("test_only & LOCK: lock rsvp[s%de%d]\n",
- rsvp_nxt->seq, rsvp_nxt->enc_id);
-
_dpu_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
ret = _dpu_rm_commit_rsvp(rm, rsvp_nxt, conn_state);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 89355d0..3a6a5546 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -36,22 +36,6 @@ enum dpu_rm_topology_name {
};
/**
- * enum dpu_rm_topology_control - HW resource use case in use by connector
- * @DPU_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a successful
- * test, reserve the resources for this display.
- * Normal behavior would not impact the
reservation
- * list during the AtomicTest phase.
- * @DPU_RM_TOPCTL_RESERVE_CLEAR: If set, in AtomicTest phase, before testing,
- * release any reservation held by this display.
- * Normal behavior would not impact the
- * reservation list
[Freedreno] [PATCH v5 17/19] drm/msm/dpu: remove RM dependency on connector state
Connector states were passed around RM to update the custom
topology connector property with chosen topology data. Now that
we got rid of both custom properties and topology names, this
change cleans up the mechanism to pass connector states across
RM helpers and encoder functions.
changes in v5:
- Introduced in the series
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 15 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 60 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 -
7 files changed, 27 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0d43525..18f5d1d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -436,15 +436,14 @@ int dpu_encoder_helper_unregister_irq(struct
dpu_encoder_phys *phys_enc,
}
void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
- struct dpu_encoder_hw_resources *hw_res,
- struct drm_connector_state *conn_state)
+ struct dpu_encoder_hw_resources *hw_res)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int i = 0;
- if (!hw_res || !drm_enc || !conn_state) {
- DPU_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
- drm_enc != 0, hw_res != 0, conn_state != 0);
+ if (!hw_res || !drm_enc) {
+ DPU_ERROR("invalid argument(s), drm_enc %d, res %d\n",
+ drm_enc != 0, hw_res != 0);
return;
}
@@ -458,7 +457,7 @@ void dpu_encoder_get_hw_resources(struct drm_encoder
*drm_enc,
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
if (phys && phys->ops.get_hw_resources)
- phys->ops.get_hw_resources(phys, hw_res, conn_state);
+ phys->ops.get_hw_resources(phys, hw_res);
}
}
@@ -652,7 +651,7 @@ static int dpu_encoder_virt_atomic_check(
if (drm_atomic_crtc_needs_modeset(crtc_state)
&& dpu_enc->mode_set_complete) {
ret = dpu_rm_reserve(_kms->rm, drm_enc, crtc_state,
- conn_state, topology, true);
+topology, true);
dpu_enc->mode_set_complete = false;
}
}
@@ -1044,7 +1043,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
/* Reserve dynamic resources now. Indicating non-AtomicTest phase */
ret = dpu_rm_reserve(_kms->rm, drm_enc, drm_enc->crtc->state,
- conn->state, topology, false);
+topology, false);
if (ret) {
DPU_ERROR_ENC(dpu_enc,
"failed to reserve hw resources, %d\n", ret);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index f109b4d..34ac5b6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -51,11 +51,9 @@ struct dpu_encoder_kickoff_params {
* dpu_encoder_get_hw_resources - Populate table of required hardware resources
* @encoder: encoder pointer
* @hw_res:resource table to populate with encoder required resources
- * @conn_state:report hw reqs based on this proposed connector state
*/
void dpu_encoder_get_hw_resources(struct drm_encoder *encoder,
- struct dpu_encoder_hw_resources *hw_res,
- struct drm_connector_state *conn_state);
+ struct dpu_encoder_hw_resources *hw_res);
/**
* dpu_encoder_register_vblank_callback - provide callback to encoder that
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index a00b222..3fe4ed9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -140,8 +140,7 @@ struct dpu_encoder_phys_ops {
struct drm_connector_state *conn_state);
void (*destroy)(struct dpu_encoder_phys *encoder);
void (*get_hw_resources)(struct dpu_encoder_phys *encoder,
- struct dpu_encoder_hw_resources *hw_res,
- struct drm_connector_state *conn_state);
+struct dpu_encoder_hw_resources *hw_res);
int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
int (*wait_for_commit_done)(struct dpu_encoder_phys
[Freedreno] [PATCH v5 14/19] drm/msm/dpu: remove cdm block support from resource manager
Support for CDM block is not present in DPU. Remove CDM
handlers from resource manager.
changes in v4:
- Introduced in the series
changes in v5:
- Remove catalog references to CDM (Sean)
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 323 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 139 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 26 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 18 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 17 --
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 68 +
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 4 -
14 files changed, 11 insertions(+), 640 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 261fa79..19ab521 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -58,7 +58,6 @@ msm-y := \
disp/dpu1/dpu_formats.o \
disp/dpu1/dpu_hw_blk.o \
disp/dpu1/dpu_hw_catalog.o \
- disp/dpu1/dpu_hw_cdm.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 60f809f..ff064e3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -32,14 +32,12 @@
/**
* Encoder functions and data types
* @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused
- * @needs_cdm: Encoder requests a CDM based on pixel format conversion needs
* @display_num_of_h_tiles: Number of horizontal tiles in case of split
* interface
* @topology: Topology of the display
*/
struct dpu_encoder_hw_resources {
enum dpu_intf_mode intfs[INTF_MAX];
- bool needs_cdm;
u32 display_num_of_h_tiles;
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index b3917e0..a00b222 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -22,7 +22,6 @@
#include "dpu_hw_pingpong.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_top.h"
-#include "dpu_hw_cdm.h"
#include "dpu_encoder.h"
#define DPU_ENCODER_NAME_MAX 16
@@ -204,8 +203,6 @@ struct dpu_encoder_irq {
* @parent_ops:Callbacks exposed by the parent to the phys_enc
* @hw_mdptop: Hardware interface to the top registers
* @hw_ctl:Hardware interface to the ctl registers
- * @hw_cdm:Hardware interface to the cdm registers
- * @cdm_cfg: Chroma-down hardware configuration
* @hw_pp: Hardware interface to the ping pong registers
* @dpu_kms: Pointer to the dpu_kms top level
* @cached_mode: DRM mode cached at mode_set time, acted on in enable
@@ -235,8 +232,6 @@ struct dpu_encoder_phys {
const struct dpu_encoder_virt_ops *parent_ops;
struct dpu_hw_mdp *hw_mdptop;
struct dpu_hw_ctl *hw_ctl;
- struct dpu_hw_cdm *hw_cdm;
- struct dpu_hw_cdm_cfg cdm_cfg;
struct dpu_hw_pingpong *hw_pp;
struct dpu_kms *dpu_kms;
struct drm_display_mode cached_mode;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 9f71861..512ac08 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -295,18 +295,6 @@
};
/*
- * CDM sub blocks config
- */
-static struct dpu_cdm_cfg sdm845_cdm[] = {
- {
- .name = "cdm_0", .id = CDM_0,
- .base = 0x79200, .len = 0x224,
- .features = 0,
- .intf_connect = BIT(INTF_3),
- },
-};
-
-/*
* VBIF sub blocks config
*/
/* VBIF QOS remap */
@@ -430,8 +418,6 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.mixer = sdm845_lm,
.pingpong_count = ARRAY_SIZE(sdm845_pp),
.pingpong = sdm845_pp,
- .cdm_count = ARRAY_SIZE(sdm845_cdm),
- .cdm = sdm845_cdm,
.intf_count
[Freedreno] [PATCH v5 13/19] drm/msm/dpu: clean up destination scaler residue
Destination scaling(DS) is a Snapdragon hardware feature to
scale up the display ROI after layer blending. DPU driver doesn't
support programming of DS blocks yet. This change cleans up the
residual code present in catalog and RM for DS block handling.
Support for the same can be added back when the feature is
formally implemented.
changes in v5:
- introduced in the series
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 42 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 40
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 7 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 10 --
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 --
5 files changed, 7 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c04f3f3..9f71861 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -74,7 +74,6 @@
.base = 0x0, .len = 0x45C,
.features = 0,
.highest_bank_bit = 0x2,
- .has_dest_scaler = true,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2AC, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
@@ -220,48 +219,23 @@
},
};
-#define LM_BLK(_name, _id, _base, _ds, _pp, _lmpair) \
+#define LM_BLK(_name, _id, _base, _pp, _lmpair) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x320, \
.features = MIXER_SDM845_MASK, \
.sblk = _lm_sblk, \
- .ds = _ds, \
.pingpong = _pp, \
.lm_pair_mask = (1 << _lmpair) \
}
static struct dpu_lm_cfg sdm845_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, DS_0, PINGPONG_0, LM_1),
- LM_BLK("lm_1", LM_1, 0x45000, DS_1, PINGPONG_1, LM_0),
- LM_BLK("lm_2", LM_2, 0x46000, DS_MAX, PINGPONG_2, LM_5),
- LM_BLK("lm_3", LM_3, 0x0, DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_4", LM_4, 0x0, DS_MAX, PINGPONG_MAX, 0),
- LM_BLK("lm_5", LM_5, 0x49000, DS_MAX, PINGPONG_3, LM_2),
-};
-
-/*
- * DS sub blocks config
- */
-static const struct dpu_ds_top_cfg sdm845_ds_top = {
- .name = "ds_top_0", .id = DS_TOP,
- .base = 0x6, .len = 0xc,
- .maxinputwidth = DEFAULT_DPU_LINE_WIDTH,
- .maxoutputwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .maxupscale = MAX_UPSCALE_RATIO,
-};
-
-#define DS_BLK(_name, _id, _base) \
- {\
- .name = _name, .id = _id, \
- .base = _base, .len = 0x800, \
- .features = DPU_SSPP_SCALER_QSEED3, \
- .top = _ds_top \
- }
-
-static struct dpu_ds_cfg sdm845_ds[] = {
- DS_BLK("ds_0", DS_0, 0x800),
- DS_BLK("ds_1", DS_1, 0x1000),
+ LM_BLK("lm_0", LM_0, 0x44000, PINGPONG_0, LM_1),
+ LM_BLK("lm_1", LM_1, 0x45000, PINGPONG_1, LM_0),
+ LM_BLK("lm_2", LM_2, 0x46000, PINGPONG_2, LM_5),
+ LM_BLK("lm_3", LM_3, 0x0, PINGPONG_MAX, 0),
+ LM_BLK("lm_4", LM_4, 0x0, PINGPONG_MAX, 0),
+ LM_BLK("lm_5", LM_5, 0x49000, PINGPONG_3, LM_2),
};
/*
@@ -454,8 +428,6 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.sspp = sdm845_sspp,
.mixer_count = ARRAY_SIZE(sdm845_lm),
.mixer = sdm845_lm,
- .ds_count = ARRAY_SIZE(sdm845_ds),
- .ds = sdm845_ds,
.pingpong_count = ARRAY_SIZE(sdm845_pp),
.pingpong = sdm845_pp,
.cdm_count = ARRAY_SIZE(sdm845_cdm),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f0cb0d4..2da803c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -428,7 +428,6 @@ struct dpu_clk_ctrl_reg {
* @highest_bank_bit: UBWC parameter
* @ubwc_static: ubwc static configuration
* @ubwc_swizzle: ubwc default swizzle setting
- * @has_dest_scaler: indicates support of destination scaler
* @clk_ctrls clock control register definition
*/
struct dpu_mdp_cfg {
@@ -436,7 +435,6 @@ struct dpu_mdp_cfg {
u32 highest_bank_bit;
u32 ubwc_static;
u32 ubwc_swizzle;
- bool has_dest_scaler;
struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
};
@@ -474,50 +472,16 @@ struct dpu_sspp_cfg {
* @features bit mask identifying sub-blocks/features
* @sblk: LM Sub-blocks information
* @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
- * @ds:ID of connected DS, DS_MAX if unsupported
* @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
*/
struct dpu_lm_cfg {
DPU_HW_BLK_INFO;
[Freedreno] [PATCH v5 18/19] drm/msm/dpu: relax parameter validation in encoders
DPU, being over protective, validates every parameter of a
module. This change traces the call stack for some of encoder
functions affected by previous set of clean up patches and
cleans up unwanted validations.
changes in v5:
- Introduced in the series
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 --
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 14 --
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 6 --
3 files changed, 26 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 18f5d1d..e15d09f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -441,12 +441,6 @@ void dpu_encoder_get_hw_resources(struct drm_encoder
*drm_enc,
struct dpu_encoder_virt *dpu_enc = NULL;
int i = 0;
- if (!hw_res || !drm_enc) {
- DPU_ERROR("invalid argument(s), drm_enc %d, res %d\n",
- drm_enc != 0, hw_res != 0);
- return;
- }
-
dpu_enc = to_dpu_encoder_virt(drm_enc);
DPU_DEBUG_ENC(dpu_enc, "\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index f277a69..b2d7f0d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -601,20 +601,6 @@ static void dpu_encoder_phys_cmd_get_hw_resources(
struct dpu_encoder_phys *phys_enc,
struct dpu_encoder_hw_resources *hw_res)
{
- struct dpu_encoder_phys_cmd *cmd_enc =
- to_dpu_encoder_phys_cmd(phys_enc);
-
- if (!phys_enc) {
- DPU_ERROR("invalid encoder\n");
- return;
- }
-
- if ((phys_enc->intf_idx - INTF_0) >= INTF_MAX) {
- DPU_ERROR("invalid intf idx:%d\n", phys_enc->intf_idx);
- return;
- }
-
- DPU_DEBUG_CMDENC(cmd_enc, "\n");
hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index fd51fe6..6fc7060 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -539,12 +539,6 @@ static void dpu_encoder_phys_vid_get_hw_resources(
struct dpu_encoder_phys *phys_enc,
struct dpu_encoder_hw_resources *hw_res)
{
- if (!phys_enc || !hw_res) {
- DPU_ERROR("invalid arg(s), enc %d hw_res %d\n",
- phys_enc != 0, hw_res != 0);
- return;
- }
-
hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 16/19] drm/msm/dpu: remove display H_TILE from encoder
Encoder H_TILE values are not used for allocating the hw blocks.
no. of hw_intf blocks provides the info.
changes in v4:
- remove irrelevant changes (Sean)
- retain log macros (Sean)
changes in v5:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 1 -
3 files changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0454e94..0d43525 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -175,8 +175,6 @@ struct dpu_encoder_virt {
spinlock_t enc_spinlock;
uint32_t bus_scaling_client;
- uint32_t display_num_of_h_tiles;
-
unsigned int num_phys_encs;
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
@@ -455,7 +453,6 @@ void dpu_encoder_get_hw_resources(struct drm_encoder
*drm_enc,
/* Query resources used by phys encs, expected to be without overlap */
memset(hw_res, 0, sizeof(*hw_res));
- hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles;
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -2104,8 +2101,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
WARN_ON(disp_info->num_of_h_tiles < 1);
- dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
-
DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index ff064e3..f109b4d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -32,13 +32,10 @@
/**
* Encoder functions and data types
* @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused
- * @display_num_of_h_tiles: Number of horizontal tiles in case of split
- * interface
* @topology: Topology of the display
*/
struct dpu_encoder_hw_resources {
enum dpu_intf_mode intfs[INTF_MAX];
- u32 display_num_of_h_tiles;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 42751ba..86466f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -751,7 +751,6 @@ static int _dpu_rm_populate_requirements(
return -EINVAL;
}
- DRM_DEBUG_KMS("num_h_tiles: %d\n", reqs->hw_res.display_num_of_h_tiles);
DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
reqs->topology->num_lm, reqs->topology->num_ctl,
reqs->topology->top_name,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 08/19] drm/msm/dpu: iterate for assigned hw ctl in virtual encoder
In virtual encoder modeset, DPU makes RM request to assign hw blocks
for the display. It is also expected in modeset to iterate and
associate the physical encoders with their relevant hw blocks.
Ping pong blocks are already handled here but hw ctl blocks are not.
This change moves the hw_ctl iteration and mapping from physical
encoder to virtual encoder.
changes in v4:
- Fix hw_ctl initialization (Sean)
changes in v5:
- Update commit text with details on why the change is
needed (Sean)
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 23 +++---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 19 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 19 --
3 files changed, 20 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index a8bbe81..0454e94 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1011,9 +1011,10 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
struct dpu_kms *dpu_kms;
struct list_head *connector_list;
struct drm_connector *conn = NULL, *conn_iter;
- struct dpu_rm_hw_iter pp_iter;
+ struct dpu_rm_hw_iter pp_iter, ctl_iter;
struct msm_display_topology topology;
enum dpu_rm_topology_name topology_name;
+ struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
int i = 0, ret;
if (!drm_enc) {
@@ -1061,17 +1062,33 @@ static void dpu_encoder_virt_mode_set(struct
drm_encoder *drm_enc,
dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
}
+ dpu_rm_init_hw_iter(_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+ if (!dpu_rm_get_hw(_kms->rm, _iter))
+ break;
+ hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
+ }
+
topology_name = dpu_rm_get_topology_name(topology);
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
if (phys) {
if (!dpu_enc->hw_pp[i]) {
- DPU_ERROR_ENC(dpu_enc,
- "invalid pingpong block for the encoder\n");
+ DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
+"at idx: %d\n", i);
return;
}
+
+ if (!hw_ctl[i]) {
+ DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
+"at idx: %d\n", i);
+ return;
+ }
+
phys->hw_pp = dpu_enc->hw_pp[i];
+ phys->hw_ctl = hw_ctl[i];
+
phys->connector = conn->state->connector;
phys->topology_name = topology_name;
if (phys->ops.mode_set)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index c8c4612..5c89868 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -196,9 +196,6 @@ static void dpu_encoder_phys_cmd_mode_set(
{
struct dpu_encoder_phys_cmd *cmd_enc =
to_dpu_encoder_phys_cmd(phys_enc);
- struct dpu_rm *rm = _enc->dpu_kms->rm;
- struct dpu_rm_hw_iter iter;
- int i, instance;
if (!phys_enc || !mode || !adj_mode) {
DPU_ERROR("invalid args\n");
@@ -208,22 +205,6 @@ static void dpu_encoder_phys_cmd_mode_set(
DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
drm_mode_debug_printmodeline(adj_mode);
- instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
-
- /* Retrieve previously allocated HW Resources. Shouldn't fail */
- dpu_rm_init_hw_iter(, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
- for (i = 0; i <= instance; i++) {
- if (dpu_rm_get_hw(rm, ))
- phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
- }
-
- if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
- DPU_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
- PTR_ERR(phys_enc->hw_ctl));
- phys_enc->hw_ctl = NULL;
- return;
- }
-
_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ecb8c65..ca0963c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -395,9
[Freedreno] [PATCH v5 10/19] drm/msm/dpu: make crtc get_mixer_width helper static
Mark CRTC get_mixer_width helper API static as it is
not used outside the file.
changes in v4:
- Patch introduced in the series
changes in v5:
- Simplify the inline function (Sean)
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 18 --
2 files changed, 9 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index c6db877..448994f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,6 +47,12 @@
#define LEFT_MIXER 0
#define RIGHT_MIXER 1
+static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate,
+ struct drm_display_mode *mode)
+{
+ return mode->hdisplay / cstate->num_mixers;
+}
+
static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
{
struct msm_drm_private *priv;
@@ -601,7 +607,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
cstate = to_dpu_crtc_state(state);
adj_mode = >adjusted_mode;
- crtc_split_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, adj_mode);
+ crtc_split_width = _dpu_crtc_get_mixer_width(cstate, adj_mode);
for (i = 0; i < dpu_crtc->num_mixers; i++) {
struct drm_rect *r = >lm_bounds[i];
@@ -1283,7 +1289,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
memset(pipe_staged, 0, sizeof(pipe_staged));
- mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
+ mixer_width = _dpu_crtc_get_mixer_width(cstate, mode);
_dpu_crtc_setup_lm_bounds(crtc, state);
@@ -1519,7 +1525,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s,
void *data)
mutex_lock(_crtc->crtc_lock);
mode = >state->adjusted_mode;
- out_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
+ out_width = _dpu_crtc_get_mixer_width(cstate, mode);
seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
mode->hdisplay, mode->vdisplay);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index ec9c538..5e4dc5c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -238,24 +238,6 @@ struct dpu_crtc_state {
container_of(x, struct dpu_crtc_state, base)
/**
- * dpu_crtc_get_mixer_width - get the mixer width
- * Mixer width will be same as panel width(/2 for split)
- */
-static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
- struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
-{
- u32 mixer_width;
-
- if (!dpu_crtc || !cstate || !mode)
- return 0;
-
- mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
- mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
-
- return mixer_width;
-}
-
-/**
* dpu_crtc_get_mixer_height - get the mixer height
* Mixer height will be same as panel height
*/
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 19/19] drm/msm/dpu: remove RM topology definition
RM maintained a redundant definition for display topology
to identify the no. of hw blocks needed for a display
and their hardware dependencies. This information can be
implicitly deduced from the msm_display_topology structure
available in RM reserve request. In addition to getting
rid of the redundant topology, this change also removes
the topology name enums and their usages.
changes in v4:
- remove the topology name enum entirely (Sean)
changes in v5:
- remove RM topology definition and their
references (Sean)
- Implement helper for dual mixer CRTC (Sean)
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 10 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 9 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 118 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 24 -
7 files changed, 53 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 9b1056c..3723b48 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -238,6 +238,16 @@ struct dpu_crtc_state {
container_of(x, struct dpu_crtc_state, base)
/**
+ * dpu_crtc_state_is_stereo - Is crtc virtualized with two mixers?
+ * @cstate: Pointer to dpu crtc state
+ * @Return: true - has two mixers, false - has one mixer
+ */
+static inline bool dpu_crtc_state_is_stereo(struct dpu_crtc_state *cstate)
+{
+ return cstate->num_mixers == CRTC_DUAL_MIXERS;
+}
+
+/**
* dpu_crtc_get_mixer_height - get the mixer height
* Mixer height will be same as panel height
*/
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index e15d09f..c2e8985 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1003,7 +1003,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
struct drm_connector *conn = NULL, *conn_iter;
struct dpu_rm_hw_iter pp_iter, ctl_iter;
struct msm_display_topology topology;
- enum dpu_rm_topology_name topology_name;
struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
int i = 0, ret;
@@ -1059,7 +1058,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
}
- topology_name = dpu_rm_get_topology_name(topology);
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -1080,7 +1078,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
phys->hw_ctl = hw_ctl[i];
phys->connector = conn->state->connector;
- phys->topology_name = topology_name;
if (phys->ops.mode_set)
phys->ops.mode_set(phys, mode, adj_mode);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 34ac5b6..9dbf38f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -32,7 +32,6 @@
/**
* Encoder functions and data types
* @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused
- * @topology: Topology of the display
*/
struct dpu_encoder_hw_resources {
enum dpu_intf_mode intfs[INTF_MAX];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 3fe4ed9..964efcc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -23,6 +23,7 @@
#include "dpu_hw_ctl.h"
#include "dpu_hw_top.h"
#include "dpu_encoder.h"
+#include "dpu_crtc.h"
#define DPU_ENCODER_NAME_MAX 16
@@ -209,7 +210,6 @@ struct dpu_encoder_irq {
* @split_role:Role to play in a split-panel configuration
* @intf_mode: Interface mode
* @intf_idx: Interface index on dpu hardware
- * @topology_name: topology selected for the display
* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
* @enable_state: Enable state tracking
* @vblank_refcount: Reference count of vblank request
@@ -237,7 +237,6 @@ struct dpu_encoder_phys {
enum dpu_enc_split_role split_role;
enum dpu_intf_mode intf_mode;
enum dpu_intf intf_idx;
- enum dpu_rm_topology_name topology_name;
spinlock_t *enc_spinlock;
enum dpu_enc_enable_state enable_state;
atomic_t vblank_refcount;
@@ -355,11 +354,15 @@ struct dpu_encoder_phys
[Freedreno] [PATCH v5 05/19] drm/msm/dpu: remove ping pong split topology variables
removes left out variables of previous ping pong
split topology cleanup.
changes in v4:
- none
changes in v5:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 5498c00..ec9c538 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -213,7 +213,6 @@ struct dpu_crtc {
/**
* struct dpu_crtc_state - dpu container for atomic crtc state
* @base: Base drm crtc state structure
- * @is_ppsplit: Whether current topology requires PPSplit special handling
* @bw_control: true if bw/clk controlled by core bw/clk properties
* @bw_split_vote : true if bw controlled by llcc/dram bw properties
* @lm_bounds : LM boundaries based on current mode full resolution, no
ROI.
@@ -228,8 +227,6 @@ struct dpu_crtc_state {
bool bw_control;
bool bw_split_vote;
-
- bool is_ppsplit;
struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
uint64_t input_fence_timeout_ns;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 11/19] drm/msm/dpu: move hw resource tracking to crtc state
Prep changes for state based resource management.
Moves all the hw block tracking for the crtc to the state
object.
changes in v4:
- Serialize crtc state access in debugfs handlers (Sean)
- Split the crtc width query as a separate change (Sean)
changes in v5:
- mode set lock all before crtc state access (Sean)
- remove unwanted memset for hw mixer cache (Sean)
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 59 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 22 ++--
2 files changed, 39 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 448994f..4ab1355 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -155,9 +155,9 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc
*crtc)
crtc_state = to_dpu_crtc_state(crtc->state);
lm_horiz_position = 0;
- for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+ for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
const struct drm_rect *lm_roi = _state->lm_bounds[lm_idx];
- struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm;
+ struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
struct dpu_hw_mixer_cfg cfg;
if (!lm_roi || !drm_rect_visible(lm_roi))
@@ -238,7 +238,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
fb ? fb->modifier : 0);
/* blend config update */
- for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
pstate, format);
@@ -262,7 +262,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
{
struct dpu_crtc *dpu_crtc;
- struct dpu_crtc_state *dpu_crtc_state;
+ struct dpu_crtc_state *cstate;
struct dpu_crtc_mixer *mixer;
struct dpu_hw_ctl *ctl;
struct dpu_hw_mixer *lm;
@@ -273,17 +273,12 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
return;
dpu_crtc = to_dpu_crtc(crtc);
- dpu_crtc_state = to_dpu_crtc_state(crtc->state);
- mixer = dpu_crtc->mixers;
+ cstate = to_dpu_crtc_state(crtc->state);
+ mixer = cstate->mixers;
DPU_DEBUG("%s\n", dpu_crtc->name);
- if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
- DPU_ERROR("invalid number mixers: %d\n", dpu_crtc->num_mixers);
- return;
- }
-
- for (i = 0; i < dpu_crtc->num_mixers; i++) {
+ for (i = 0; i < cstate->num_mixers; i++) {
if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
DPU_ERROR("invalid lm or ctl assigned to mixer\n");
return;
@@ -300,7 +295,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
- for (i = 0; i < dpu_crtc->num_mixers; i++) {
+ for (i = 0; i < cstate->num_mixers; i++) {
ctl = mixer[i].hw_ctl;
lm = mixer[i].hw_lm;
@@ -522,7 +517,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
struct drm_crtc *crtc,
struct drm_encoder *enc)
{
- struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
+ struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
struct dpu_rm *rm = _kms->rm;
struct dpu_crtc_mixer *mixer;
@@ -534,8 +529,8 @@ static void _dpu_crtc_setup_mixer_for_encoder(
dpu_rm_init_hw_iter(_iter, enc->base.id, DPU_HW_BLK_CTL);
/* Set up all the mixers and ctls reserved by this encoder */
- for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers); i++) {
- mixer = _crtc->mixers[i];
+ for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
+ mixer = >mixers[i];
if (!dpu_rm_get_hw(rm, _iter))
break;
@@ -560,7 +555,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
mixer->encoder = enc;
- dpu_crtc->num_mixers++;
+ cstate->num_mixers++;
DPU_DEBUG("setup mixer %d: lm %d\n",
i, mixer->hw_lm->idx - LM_0);
DPU_DEBUG("setup mixer %d: ctl %d\n",
@@ -573,10 +568,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct drm_encoder *enc;
- dpu_crtc->num_mixers = 0;
- dpu_crtc->mixers_swapped =
[Freedreno] [PATCH v5 04/19] drm/msm/dpu: remove resource pool manager
resource pool manager utility was introduced to manage
rotator sessions. Removing the support as the rotator
feature doesn't exist.
changes in v4:
- none
changes in v5:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 205 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 56 -
2 files changed, 261 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 6cc5ba7..c6db877 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -97,187 +97,6 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc
*dpu_crtc, bool enable)
return 0;
}
-/**
- * _dpu_crtc_rp_to_crtc - get crtc from resource pool object
- * @rp: Pointer to resource pool
- * return: Pointer to drm crtc if success; null otherwise
- */
-static struct drm_crtc *_dpu_crtc_rp_to_crtc(struct dpu_crtc_respool *rp)
-{
- if (!rp)
- return NULL;
-
- return container_of(rp, struct dpu_crtc_state, rp)->base.crtc;
-}
-
-/**
- * _dpu_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool
- * @rp: Pointer to resource pool
- * @force: True to reclaim all resources; otherwise, reclaim only unused ones
- * return: None
- */
-static void _dpu_crtc_rp_reclaim(struct dpu_crtc_respool *rp, bool force)
-{
- struct dpu_crtc_res *res, *next;
- struct drm_crtc *crtc;
-
- crtc = _dpu_crtc_rp_to_crtc(rp);
- if (!crtc) {
- DPU_ERROR("invalid crtc\n");
- return;
- }
-
- DPU_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id,
- force ? "destroy" : "free_unused");
-
- list_for_each_entry_safe(res, next, >res_list, list) {
- if (!force && !(res->flags & DPU_CRTC_RES_FLAG_FREE))
- continue;
- DPU_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n",
- crtc->base.id, rp->sequence_id,
- res->type, res->tag, res->val,
- atomic_read(>refcount));
- list_del(>list);
- if (res->ops.put)
- res->ops.put(res->val);
- kfree(res);
- }
-}
-
-/**
- * _dpu_crtc_rp_free_unused - free unused resource in pool
- * @rp: Pointer to resource pool
- * return: none
- */
-static void _dpu_crtc_rp_free_unused(struct dpu_crtc_respool *rp)
-{
- mutex_lock(rp->rp_lock);
- _dpu_crtc_rp_reclaim(rp, false);
- mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_rp_destroy - destroy resource pool
- * @rp: Pointer to resource pool
- * return: None
- */
-static void _dpu_crtc_rp_destroy(struct dpu_crtc_respool *rp)
-{
- mutex_lock(rp->rp_lock);
- list_del_init(>rp_list);
- _dpu_crtc_rp_reclaim(rp, true);
- mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_hw_blk_get - get callback for hardware block
- * @val: Resource handle
- * @type: Resource type
- * @tag: Search tag for given resource
- * return: Resource handle
- */
-static void *_dpu_crtc_hw_blk_get(void *val, u32 type, u64 tag)
-{
- DPU_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val);
- return dpu_hw_blk_get(val, type, tag);
-}
-
-/**
- * _dpu_crtc_hw_blk_put - put callback for hardware block
- * @val: Resource handle
- * return: None
- */
-static void _dpu_crtc_hw_blk_put(void *val)
-{
- DPU_DEBUG("res://%pK\n", val);
- dpu_hw_blk_put(val);
-}
-
-/**
- * _dpu_crtc_rp_duplicate - duplicate resource pool and reset reference count
- * @rp: Pointer to original resource pool
- * @dup_rp: Pointer to duplicated resource pool
- * return: None
- */
-static void _dpu_crtc_rp_duplicate(struct dpu_crtc_respool *rp,
- struct dpu_crtc_respool *dup_rp)
-{
- struct dpu_crtc_res *res, *dup_res;
- struct drm_crtc *crtc;
-
- if (!rp || !dup_rp || !rp->rp_head) {
- DPU_ERROR("invalid resource pool\n");
- return;
- }
-
- crtc = _dpu_crtc_rp_to_crtc(rp);
- if (!crtc) {
- DPU_ERROR("invalid crtc\n");
- return;
- }
-
- DPU_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id);
-
- mutex_lock(rp->rp_lock);
- dup_rp->sequence_id = rp->sequence_id + 1;
- INIT_LIST_HEAD(_rp->res_list);
- dup_rp->ops = rp->ops;
- list_for_each_entry(res, >res_list, list) {
- dup_res = kzalloc(sizeof(struct dpu_crtc_res), GFP_KERNEL);
- if (!dup_res) {
- mutex_unlock(rp->rp_lock);
- return;
- }
- INIT_LIST_HEAD(_res->list);
- atomic_set(_res->refcount, 0);
- dup_res->type = res->type;
- dup_res->tag = res->tag;
- dup_res->val = res->val;
-
[Freedreno] [PATCH v5 01/19] drm/msm/dpu: remove debugfs support for misr
MISR support is the debug feature present in Snapdragon chipsets.
At the layer mixer and interfaces, MISR algorithm can generate CRC
signatures of the pixel data which can be used for validating
the frames generated. Since there are no clients for this feature,
strip down the support from the driver.
changes in v4:
- changed introduced in the series
changes in v5:
- update commit text with the need for the change(Sean)
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 139 -
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 127 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 6 -
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 28 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 29 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 7 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 29 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 7 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h| 6 -
11 files changed, 387 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f0a5e77..1e0382f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,8 +47,6 @@
#define LEFT_MIXER 0
#define RIGHT_MIXER 1
-#define MISR_BUFF_SIZE 256
-
static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
{
struct msm_drm_private *priv;
@@ -1272,8 +1270,6 @@ static void dpu_crtc_handle_power_event(u32 event_type,
void *arg)
struct drm_crtc *crtc = arg;
struct dpu_crtc *dpu_crtc;
struct drm_encoder *encoder;
- struct dpu_crtc_mixer *m;
- u32 i, misr_status;
if (!crtc) {
DPU_ERROR("invalid crtc\n");
@@ -1294,29 +1290,8 @@ static void dpu_crtc_handle_power_event(u32 event_type,
void *arg)
dpu_encoder_virt_restore(encoder);
}
-
- for (i = 0; i < dpu_crtc->num_mixers; ++i) {
- m = _crtc->mixers[i];
- if (!m->hw_lm || !m->hw_lm->ops.setup_misr ||
- !dpu_crtc->misr_enable)
- continue;
-
- m->hw_lm->ops.setup_misr(m->hw_lm, true,
- dpu_crtc->misr_frame_count);
- }
break;
case DPU_POWER_EVENT_PRE_DISABLE:
- for (i = 0; i < dpu_crtc->num_mixers; ++i) {
- m = _crtc->mixers[i];
- if (!m->hw_lm || !m->hw_lm->ops.collect_misr ||
- !dpu_crtc->misr_enable)
- continue;
-
- misr_status = m->hw_lm->ops.collect_misr(m->hw_lm);
- dpu_crtc->misr_data[i] = misr_status ? misr_status :
- dpu_crtc->misr_data[i];
- }
- break;
case DPU_POWER_EVENT_POST_DISABLE:
/**
* Nothing to do. All the planes on the CRTC will be
@@ -1846,113 +1821,6 @@ static int _dpu_debugfs_status_open(struct inode
*inode, struct file *file)
return single_open(file, _dpu_debugfs_status_show, inode->i_private);
}
-static ssize_t _dpu_crtc_misr_setup(struct file *file,
- const char __user *user_buf, size_t count, loff_t *ppos)
-{
- struct dpu_crtc *dpu_crtc;
- struct dpu_crtc_mixer *m;
- int i = 0, rc;
- char buf[MISR_BUFF_SIZE + 1];
- u32 frame_count, enable;
- size_t buff_copy;
-
- if (!file || !file->private_data)
- return -EINVAL;
-
- dpu_crtc = file->private_data;
- buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
- if (copy_from_user(buf, user_buf, buff_copy)) {
- DPU_ERROR("buffer copy failed\n");
- return -EINVAL;
- }
-
- buf[buff_copy] = 0; /* end of string */
-
- if (sscanf(buf, "%u %u", , _count) != 2)
- return -EINVAL;
-
- rc = _dpu_crtc_power_enable(dpu_crtc, true);
- if (rc)
- return rc;
-
- mutex_lock(_crtc->crtc_lock);
- dpu_crtc->misr_enable = enable;
- dpu_crtc->misr_frame_count = frame_count;
- for (i = 0; i < dpu_crtc->num_mixers; ++i) {
- dpu_crtc->misr_data[i] = 0;
- m = _crtc->mixers[i];
- if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
- continue;
-
- m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
- }
- mutex_unlock(_crtc->crtc_lock);
- _dpu_crtc_power_enable(dpu_crtc, false);
-
- return count;
-}
-
[Freedreno] [PATCH v5 09/19] drm/msm/dpu: avoid querying for hw intf before assignment
Resource manager assigns hw_intf blocks for the encoder only on
modeset. If queried for hw_intf objects during init, it will be
NULL. Since hw_intf objects are needed only after encoder enable,
defer the query to encoder enable which will be triggered after
modeset.
changes in v4:
- Add details on commit text on why the change is needed (Sean)
changes in v5:
- Reword commit text on the usage of hw_intf objects (Sean)
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 53 +++---
1 file changed, 16 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ca0963c..6de13f4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -462,7 +462,7 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
{
struct msm_drm_private *priv;
struct dpu_encoder_phys_vid *vid_enc;
- struct dpu_hw_intf *intf;
+ struct dpu_rm_hw_iter iter;
struct dpu_hw_ctl *ctl;
u32 flush_mask = 0;
@@ -474,11 +474,20 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
priv = phys_enc->parent->dev->dev_private;
vid_enc = to_dpu_encoder_phys_vid(phys_enc);
- intf = vid_enc->hw_intf;
ctl = phys_enc->hw_ctl;
- if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
- DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
- vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
+
+ dpu_rm_init_hw_iter(, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
+ while (dpu_rm_get_hw(_enc->dpu_kms->rm, )) {
+ struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
+
+ if (hw_intf->idx == phys_enc->intf_idx) {
+ vid_enc->hw_intf = hw_intf;
+ break;
+ }
+ }
+
+ if (!vid_enc->hw_intf) {
+ DPU_ERROR("hw_intf not assigned\n");
return;
}
@@ -500,7 +509,7 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
!dpu_encoder_phys_vid_is_master(phys_enc))
goto skip_flush;
- ctl->ops.get_bitmask_intf(ctl, _mask, intf->idx);
+ ctl->ops.get_bitmask_intf(ctl, _mask, vid_enc->hw_intf->idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
skip_flush:
@@ -531,22 +540,13 @@ static void dpu_encoder_phys_vid_get_hw_resources(
struct dpu_encoder_hw_resources *hw_res,
struct drm_connector_state *conn_state)
{
- struct dpu_encoder_phys_vid *vid_enc;
-
if (!phys_enc || !hw_res) {
DPU_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
phys_enc != 0, hw_res != 0, conn_state != 0);
return;
}
- vid_enc = to_dpu_encoder_phys_vid(phys_enc);
- if (!vid_enc->hw_intf) {
- DPU_ERROR("invalid arg(s), hw_intf\n");
- return;
- }
-
- DPU_DEBUG_VIDENC(vid_enc, "\n");
- hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO;
+ hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
}
static int _dpu_encoder_phys_vid_wait_for_vblank(
@@ -781,7 +781,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
{
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_vid *vid_enc = NULL;
- struct dpu_rm_hw_iter iter;
struct dpu_encoder_irq *irq;
int i, ret = 0;
@@ -801,26 +800,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
- /**
-* hw_intf resource permanently assigned to this encoder
-* Other resources allocated at atomic commit time by use case
-*/
- dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_INTF);
- while (dpu_rm_get_hw(>dpu_kms->rm, )) {
- struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
-
- if (hw_intf->idx == p->intf_idx) {
- vid_enc->hw_intf = hw_intf;
- break;
- }
- }
-
- if (!vid_enc->hw_intf) {
- ret = -EINVAL;
- DPU_ERROR("failed to get hw_intf\n");
- goto fail;
- }
-
DPU_DEBUG_VIDENC(vid_enc, "\n");
dpu_encoder_phys_vid_init_ops(_enc->ops);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 02/19] drm/msm/dpu: squash power handle event types
DPU power handler maintained PRE/POST versions of power
ENABLE/DISABLE events to accommodate tasks which need be
handled before/after data bus voting. But since the bus voting
API's are deprecated and removed from the driver, squash
the events and their clients respective event handlers
to handle only ENABLE/DISABLE events.
changes in v5:
- introduced in the series
Signed-off-by: Jeykumar Sankaran
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 28 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 15 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 14
4 files changed, 16 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 1e0382f..6cc5ba7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1281,26 +1281,12 @@ static void dpu_crtc_handle_power_event(u32 event_type,
void *arg)
trace_dpu_crtc_handle_power_event(DRMID(crtc), event_type);
- switch (event_type) {
- case DPU_POWER_EVENT_POST_ENABLE:
- /* restore encoder; crtc will be programmed during commit */
- drm_for_each_encoder(encoder, crtc->dev) {
- if (encoder->crtc != crtc)
- continue;
+ /* restore encoder; crtc will be programmed during commit */
+ drm_for_each_encoder(encoder, crtc->dev) {
+ if (encoder->crtc != crtc)
+ continue;
- dpu_encoder_virt_restore(encoder);
- }
- break;
- case DPU_POWER_EVENT_PRE_DISABLE:
- case DPU_POWER_EVENT_POST_DISABLE:
- /**
-* Nothing to do. All the planes on the CRTC will be
-* programmed for every frame
-*/
- break;
- default:
- DPU_DEBUG("event:%d not handled\n", event_type);
- break;
+ dpu_encoder_virt_restore(encoder);
}
mutex_unlock(_crtc->crtc_lock);
@@ -1429,9 +1415,7 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
drm_crtc_vblank_on(crtc);
dpu_crtc->power_event = dpu_power_handle_register_event(
- dpu_crtc->phandle,
- DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE |
- DPU_POWER_EVENT_PRE_DISABLE,
+ dpu_crtc->phandle, DPU_POWER_EVENT_ENABLE,
dpu_crtc_handle_power_event, crtc, dpu_crtc->name);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5fd2f7f..0a683e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -967,8 +967,7 @@ static void dpu_kms_handle_power_event(u32 event_type, void
*usr)
if (!dpu_kms)
return;
- if (event_type == DPU_POWER_EVENT_POST_ENABLE)
- dpu_vbif_init_memtypes(dpu_kms);
+ dpu_vbif_init_memtypes(dpu_kms);
}
static int dpu_kms_hw_init(struct msm_kms *kms)
@@ -1155,10 +1154,9 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
/*
* Handle (re)initializations during power enable
*/
- dpu_kms_handle_power_event(DPU_POWER_EVENT_POST_ENABLE, dpu_kms);
+ dpu_kms_handle_power_event(DPU_POWER_EVENT_ENABLE, dpu_kms);
dpu_kms->power_event = dpu_power_handle_register_event(
- _kms->phandle,
- DPU_POWER_EVENT_POST_ENABLE,
+ _kms->phandle, DPU_POWER_EVENT_ENABLE,
dpu_kms_handle_power_event, dpu_kms, "kms");
pm_runtime_put_sync(_kms->pdev->dev);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
index a75eebc..fc14116 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
@@ -145,6 +145,7 @@ int dpu_power_resource_enable(struct dpu_power_handle
*phandle,
bool changed = false;
u32 max_usecase_ndx = VOTE_INDEX_DISABLE, prev_usecase_ndx;
struct dpu_power_client *client;
+ u32 event_type;
if (!phandle || !pclient) {
pr_err("invalid input argument\n");
@@ -181,19 +182,9 @@ int dpu_power_resource_enable(struct dpu_power_handle
*phandle,
if (!changed)
goto end;
- if (enable) {
- dpu_power_event_trigger_locked(phandle,
- DPU_POWER_EVENT_PRE_ENABLE);
- dpu_power_event_trigger_locked(phandle,
- DPU_POWER_EVENT_POST_ENABLE);
-
- } else {
- dpu_power_event_trigger_locked(phandle,
- DPU_POWER_EVENT_PRE_DISABLE);
-
[Freedreno] [PATCH v5 00/19] clean up DPU for RM refactor
Based on the comments received for the patch series[1] and to make the review process a bit more easy, spliting up the patches for cleanup and resource manager refactor. This series cleans up and prepares the DPU for upcoming RM changes. [1] https://patchwork.freedesktop.org/series/44669/ Thanks and Regards, Jeykumar S. Jeykumar Sankaran (19): drm/msm/dpu: remove debugfs support for misr drm/msm/dpu: squash power handle event types drm/msm/dpu: remove scalar config definitions drm/msm/dpu: remove resource pool manager drm/msm/dpu: remove ping pong split topology variables drm/msm/dpu: enable master-slave encoders explicitly drm/msm/dpu: use kms stored hw mdp block drm/msm/dpu: iterate for assigned hw ctl in virtual encoder drm/msm/dpu: avoid querying for hw intf before assignment drm/msm/dpu: make crtc get_mixer_width helper static drm/msm/dpu: move hw resource tracking to crtc state drm/msm/dpu: rename hw_ctl to lm_ctl drm/msm/dpu: clean up destination scaler residue drm/msm/dpu: remove cdm block support from resource manager drm/msm/dpu: remove LOCK/CLEAR support in RM drm/msm/dpu: remove display H_TILE from encoder drm/msm/dpu: remove RM dependency on connector state drm/msm/dpu: relax parameter validation in encoders drm/msm/dpu: remove RM topology definition drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 467 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 111 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 216 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 23 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 48 +-- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 125 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 56 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 56 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 323 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 139 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 29 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 29 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 33 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 18 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 17 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c| 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h| 16 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 15 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 278 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 44 -- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 4 - 29 files changed, 216 insertions(+), 1899 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 07/19] drm/msm/dpu: use kms stored hw mdp block
Avoid querying RM for hw mdp block. Use the one
stored in KMS during initialization.
changes in v4:
- none
changes in v5:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +
2 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 3084675..c8c4612 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -823,7 +823,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
{
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_cmd *cmd_enc = NULL;
- struct dpu_hw_mdp *hw_mdp;
struct dpu_encoder_irq *irq;
int i, ret = 0;
@@ -836,14 +835,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
goto fail;
}
phys_enc = _enc->base;
-
- hw_mdp = dpu_rm_get_mdp(>dpu_kms->rm);
- if (IS_ERR_OR_NULL(hw_mdp)) {
- ret = PTR_ERR(hw_mdp);
- DPU_ERROR("failed to get mdptop\n");
- goto fail_mdp_init;
- }
- phys_enc->hw_mdptop = hw_mdp;
+ phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
dpu_encoder_phys_cmd_init_ops(_enc->ops);
@@ -898,8 +890,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
return phys_enc;
-fail_mdp_init:
- kfree(cmd_enc);
fail:
return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 6fc3d3f..ecb8c65 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -801,7 +801,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_vid *vid_enc = NULL;
struct dpu_rm_hw_iter iter;
- struct dpu_hw_mdp *hw_mdp;
struct dpu_encoder_irq *irq;
int i, ret = 0;
@@ -818,13 +817,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
phys_enc = _enc->base;
- hw_mdp = dpu_rm_get_mdp(>dpu_kms->rm);
- if (IS_ERR_OR_NULL(hw_mdp)) {
- ret = PTR_ERR(hw_mdp);
- DPU_ERROR("failed to get mdptop\n");
- goto fail;
- }
- phys_enc->hw_mdptop = hw_mdp;
+ phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
/**
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 06/19] drm/msm/dpu: enable master-slave encoders explicitly
Identify slave-master encoders during initialization and enable
the encoders explicitly as the current logic has redundant and
ambiguous loops.
changes in v4:
- identify master/slave encoder while adding
adding physical encoders(Sean)
changes in v5:
- get rid of temporary variable for phys enc(Sean)
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 43 -
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 991b22c..a8bbe81 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -180,6 +180,7 @@ struct dpu_encoder_virt {
unsigned int num_phys_encs;
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
+ struct dpu_encoder_phys *cur_slave;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
bool intfs_swapped;
@@ -1141,7 +1142,7 @@ void dpu_encoder_virt_restore(struct drm_encoder *drm_enc)
static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc = NULL;
- int i, ret = 0;
+ int ret = 0;
struct drm_display_mode *cur_mode = NULL;
if (!drm_enc) {
@@ -1154,21 +1155,12 @@ static void dpu_encoder_virt_enable(struct drm_encoder
*drm_enc)
trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
cur_mode->vdisplay);
- dpu_enc->cur_master = NULL;
- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
- if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
- DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n", i);
- dpu_enc->cur_master = phys;
- break;
- }
- }
+ /* always enable slave encoder before master */
+ if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
+ dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
- if (!dpu_enc->cur_master) {
- DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
- return;
- }
+ if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
+ dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
if (ret) {
@@ -1177,21 +1169,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder
*drm_enc)
return;
}
- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
- if (!phys)
- continue;
-
- if (phys != dpu_enc->cur_master) {
- if (phys->ops.enable)
- phys->ops.enable(phys);
- }
- }
-
- if (dpu_enc->cur_master->ops.enable)
- dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
-
_dpu_encoder_virt_enable_helper(drm_enc);
}
@@ -2062,6 +2039,11 @@ static int dpu_encoder_virt_add_phys_encs(
++dpu_enc->num_phys_encs;
}
+ if (params->split_role == ENC_ROLE_SLAVE)
+ dpu_enc->cur_slave = enc;
+ else
+ dpu_enc->cur_master = enc;
+
return 0;
}
@@ -2228,7 +2210,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct
drm_encoder *enc,
if (ret)
goto fail;
- dpu_enc->cur_master = NULL;
spin_lock_init(_enc->enc_spinlock);
atomic_set(_enc->frame_done_timeout, 0);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 12/19] drm/msm/dpu: rename hw_ctl to lm_ctl
Rename hw_ctl to lm_ctl to mean the ctl associated
with the hw layer mixer block.
sed -i 's/\([*@.>]\)hw_ctl\([^s]\)/\1lm_ctl\2/g' dpu_crtc.c dpu_crtc.h
changes in v4:
- Specifiy shell command used for renaming (Sean)
changes in v5:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 ++--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4ab1355..a8f2dd7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -194,7 +194,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
return;
}
- ctl = mixer->hw_ctl;
+ ctl = mixer->lm_ctl;
lm = mixer->hw_lm;
stage_cfg = _crtc->stage_cfg;
cstate = to_dpu_crtc_state(crtc->state);
@@ -279,15 +279,15 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
DPU_DEBUG("%s\n", dpu_crtc->name);
for (i = 0; i < cstate->num_mixers; i++) {
- if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
+ if (!mixer[i].hw_lm || !mixer[i].lm_ctl) {
DPU_ERROR("invalid lm or ctl assigned to mixer\n");
return;
}
mixer[i].mixer_op_mode = 0;
mixer[i].flush_mask = 0;
- if (mixer[i].hw_ctl->ops.clear_all_blendstages)
- mixer[i].hw_ctl->ops.clear_all_blendstages(
- mixer[i].hw_ctl);
+ if (mixer[i].lm_ctl->ops.clear_all_blendstages)
+ mixer[i].lm_ctl->ops.clear_all_blendstages(
+ mixer[i].lm_ctl);
}
/* initialize stage cfg */
@@ -296,7 +296,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
for (i = 0; i < cstate->num_mixers; i++) {
- ctl = mixer[i].hw_ctl;
+ ctl = mixer[i].lm_ctl;
lm = mixer[i].hw_lm;
lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
@@ -540,14 +540,14 @@ static void _dpu_crtc_setup_mixer_for_encoder(
if (!dpu_rm_get_hw(rm, _iter)) {
DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
mixer->hw_lm->idx - LM_0);
- mixer->hw_ctl = last_valid_ctl;
+ mixer->lm_ctl = last_valid_ctl;
} else {
- mixer->hw_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
- last_valid_ctl = mixer->hw_ctl;
+ mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
+ last_valid_ctl = mixer->lm_ctl;
}
/* Shouldn't happen, mixers are always >= ctls */
- if (!mixer->hw_ctl) {
+ if (!mixer->lm_ctl) {
DPU_ERROR("no valid ctls found for lm %d\n",
mixer->hw_lm->idx - LM_0);
return;
@@ -559,7 +559,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
DPU_DEBUG("setup mixer %d: lm %d\n",
i, mixer->hw_lm->idx - LM_0);
DPU_DEBUG("setup mixer %d: ctl %d\n",
- i, mixer->hw_ctl->idx - CTL_0);
+ i, mixer->lm_ctl->idx - CTL_0);
}
}
@@ -1532,11 +1532,11 @@ static int _dpu_debugfs_status_show(struct seq_file *s,
void *data)
m = >mixers[i];
if (!m->hw_lm)
seq_printf(s, "\tmixer[%d] has no lm\n", i);
- else if (!m->hw_ctl)
+ else if (!m->lm_ctl)
seq_printf(s, "\tmixer[%d] has no ctl\n", i);
else
seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
- m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
+ m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
out_width, mode->vdisplay);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 7aa772f..9b1056c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -83,14 +83,14 @@ struct dpu_crtc_smmu_state_data {
/**
* struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
* @hw_lm: LM HW Driver context
- * @hw_ctl:CTL Path HW driver context
+ * @lm_ctl:CTL Path HW driver context
* @encoder: Encoder attached to this lm & ctl
* @mixer_op_mode: mixer blending operation mode
* @flush_mask:
[Freedreno] [PATCH v5 03/19] drm/msm/dpu: remove scalar config definitions
cleans up left out scalar config definitions from headers
changes in v4:
- none
changes in v5:
- none
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 10 --
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 53484b1..34ce724 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -161,7 +161,6 @@ struct dpu_crtc_frame_event {
* @cur_perf : current performance committed to clock/bandwidth driver
* @rp_lock : serialization lock for resource pool
* @rp_head : list of active resource pool
- * @scl3_cfg_lut : qseed3 lut config
*/
struct dpu_crtc {
struct drm_crtc base;
@@ -172,7 +171,6 @@ struct dpu_crtc {
u32 num_mixers;
bool mixers_swapped;
struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
- struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
struct drm_pending_vblank_event *event;
u32 vsync_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index cb02041..321fc64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -148,16 +148,6 @@ struct dpu_hw_scaler3_cfg {
struct dpu_hw_scaler3_de_cfg de;
};
-struct dpu_hw_scaler3_lut_cfg {
- bool is_configured;
- u32 *dir_lut;
- size_t dir_len;
- u32 *cir_lut;
- size_t cir_len;
- u32 *sep_lut;
- size_t sep_len;
-};
-
/**
* struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
* @num_ext_pxls_lr: Number of total horizontal pixels
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [RFC] UAPI: Check headers by compiling all together as C++
On Wednesday 2018-09-05 18:55, Greg KH wrote: >On Wed, Sep 05, 2018 at 04:54:27PM +0100, David Howells wrote: >> >> Here's a set of patches that inserts a step into the build process to make >> sure that the UAPI headers can all be built together with C++ (if the >> compiler being used supports C++). All but the final patch perform fixups, >> including: > >Wait, why do we care? What has recently changed to start to directly >import kernel uapi files into C++ code? With C++11, C++ has become a much nicer language to use (for userspace, anyway). >And if userspace wants to do this, can't they do the C namespace trick >themselves when they do the import? The only trick is to use an extra C source file and extensively wrap things. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [RFC] UAPI: Check headers by compiling all together as C++
Hi,
Le mercredi 05 septembre 2018 à 18:55 +0200, Greg KH a écrit :
> On Wed, Sep 05, 2018 at 04:54:27PM +0100, David Howells wrote:
> >
> > Here's a set of patches that inserts a step into the build process to make
> > sure that the UAPI headers can all be built together with C++ (if the
> > compiler being used supports C++). All but the final patch perform fixups,
> > including:
>
> Wait, why do we care? What has recently changed to start to directly
> import kernel uapi files into C++ code?
>
> And if userspace wants to do this, can't they do the C namespace trick
> themselves when they do the import? That must be how they are doing it
> today, right?
>
They can't.
Adding extern "C" { } doesn't magically make "class" a non keyword.
Even if it was the case, writing C++ code using whatever->class would
probably broke because class is a keyword in C++.
--
Yann Droneaud
OPTEYA
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [RFC] UAPI: Check headers by compiling all together as C++
On Wed, Sep 05, 2018 at 07:33:38PM +0200, Yann Droneaud wrote:
> Hi,
>
> Le mercredi 05 septembre 2018 à 18:55 +0200, Greg KH a écrit :
> > On Wed, Sep 05, 2018 at 04:54:27PM +0100, David Howells wrote:
> > >
> > > Here's a set of patches that inserts a step into the build process to make
> > > sure that the UAPI headers can all be built together with C++ (if the
> > > compiler being used supports C++). All but the final patch perform
> > > fixups,
> > > including:
> >
> > Wait, why do we care? What has recently changed to start to directly
> > import kernel uapi files into C++ code?
> >
> > And if userspace wants to do this, can't they do the C namespace trick
> > themselves when they do the import? That must be how they are doing it
> > today, right?
> >
>
> They can't.
>
>
> Adding extern "C" { } doesn't magically make "class" a non keyword.
> Even if it was the case, writing C++ code using whatever->class would
> probably broke because class is a keyword in C++.
I think it's a bug in the language TBH.
> --
> Yann Droneaud
> OPTEYA
>
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [RFC] UAPI: Check headers by compiling all together as C++
Greg KH wrote: > > Here's a set of patches that inserts a step into the build process to make > > sure that the UAPI headers can all be built together with C++ (if the > > compiler being used supports C++). All but the final patch perform fixups, > > including: > > Wait, why do we care? What has recently changed to start to directly > import kernel uapi files into C++ code? There's at least one outstanding bug due to a C++ identifier in the kernel UAPI headers. Are you saying you explicitly don't want people to be able to use the kernel UAPI headers in C++? > And if userspace wants to do this, can't they do the C namespace trick > themselves when they do the import? That must be how they are doing it > today, right? No, because there's no such trick (except with the preprocessor). David ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [RFC] UAPI: Check headers by compiling all together as C++
On Wed, Sep 05, 2018 at 04:54:27PM +0100, David Howells wrote: > > Here's a set of patches that inserts a step into the build process to make > sure that the UAPI headers can all be built together with C++ (if the > compiler being used supports C++). All but the final patch perform fixups, > including: Wait, why do we care? What has recently changed to start to directly import kernel uapi files into C++ code? And if userspace wants to do this, can't they do the C namespace trick themselves when they do the import? That must be how they are doing it today, right? thanks, greg k-h ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [RFC] UAPI: Check headers by compiling all together as C++
Here's a set of patches that inserts a step into the build process to make sure that the UAPI headers can all be built together with C++ (if the compiler being used supports C++). All but the final patch perform fixups, including: (1) Fix member names that conflict with C++ reserved words by providing alternates that can be used anywhere. An anonymous union is used so that that the conflicting name is still available outside of C++. (2) Fix the use of flexible arrays in structs that get embedded (which is illegal in C++). (3) Remove the use of internal kernel structs in UAPI structures. (4) Fix symbol collisions. (5) Replace usage of u32 and co. with __u32 and co. (6) Fix use of sparsely initialised arrays (which g++ doesn't implement). (7) Remove some use of PAGE_SIZE since this isn't valid outside of the kernel. And lastly: (8) Compile all of the UAPI headers (with a few exceptions) together as C++ to catch new errors occurring as part of the regular build process. The patches can also be found here: http://git.kernel.org/cgit/linux/kernel/git/dhowells/linux-fs.git/log/?h=uapi-check Thanks, David --- David Howells (11): UAPI: drm: Fix use of C++ keywords as structural members UAPI: keys: Fix use of C++ keywords as structural members UAPI: virtio_net: Fix use of C++ keywords as structural members UAPI: bcache: Fix use of embedded flexible array UAPI: coda: Don't use internal kernel structs in UAPI UAPI: netfilter: Fix symbol collision issues UAPI: nilfs2: Fix use of undefined byteswapping functions UAPI: sound: Fix use of u32 and co. in UAPI headers UAPI: ndctl: Fix g++-unsupported initialisation in headers UAPI: ndctl: Remove use of PAGE_SIZE UAPI: Check headers build for C++ Makefile |1 include/linux/ndctl.h | 22 include/uapi/drm/i810_drm.h |7 + include/uapi/drm/msm_drm.h|7 + include/uapi/linux/bcache.h |2 include/uapi/linux/coda_psdev.h |4 + include/uapi/linux/keyctl.h |7 + include/uapi/linux/ndctl.h| 20 ++- include/uapi/linux/netfilter/nfnetlink_cthelper.h |2 include/uapi/linux/netfilter_ipv4/ipt_ECN.h |9 -- include/uapi/linux/nilfs2_ondisk.h| 21 ++-- include/uapi/linux/virtio_net.h |7 + include/uapi/sound/skl-tplg-interface.h | 106 +- scripts/headers-c++.sh| 124 + 14 files changed, 255 insertions(+), 84 deletions(-) create mode 100644 include/linux/ndctl.h create mode 100755 scripts/headers-c++.sh ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 1/2] drm/msm: Fix leak in submitqueue create
On Mon, Sep 03, 2018 at 12:54:44PM +0530, Sharat Masetty wrote:
> This patch fixes a trivial leak when trying to create a submitqueue.
>
> Signed-off-by: Sharat Masetty
Doh. Thanks.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/msm_submitqueue.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c
> b/drivers/gpu/drm/msm/msm_submitqueue.c
> index 5115f75..325da44 100644
> --- a/drivers/gpu/drm/msm/msm_submitqueue.c
> +++ b/drivers/gpu/drm/msm/msm_submitqueue.c
> @@ -78,8 +78,10 @@ int msm_submitqueue_create(struct drm_device *drm, struct
> msm_file_private *ctx,
> queue->flags = flags;
>
> if (priv->gpu) {
> - if (prio >= priv->gpu->nr_rings)
> + if (prio >= priv->gpu->nr_rings) {
> + kfree(queue);
> return -EINVAL;
> + }
>
> queue->prio = prio;
> }
> --
> 1.9.1
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 12/14] drm/msm/dpu: remove topology name
On Tue, Sep 04, 2018 at 04:03:25PM -0700, Jeykumar Sankaran wrote:
> On 2018-08-31 09:08, Sean Paul wrote:
> > On Tue, Aug 28, 2018 at 05:40:01PM -0700, Jeykumar Sankaran wrote:
> > > Strip down the support for topology enums. It
> > > can be replaced with simple hw count checks.
> > >
> >
> > Changes in v4:
> > ...
> >
> > > Signed-off-by: Jeykumar Sankaran
> > > ---
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 3 --
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 1 -
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 9 --
> > > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +++--
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 36
> > ++
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 24
> > > ---
> > > 6 files changed, 19 insertions(+), 61 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > index dbf669e..56ef349 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > @@ -1013,7 +1013,6 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > > struct drm_connector *conn = NULL, *conn_iter;
> > > struct dpu_rm_hw_iter pp_iter, ctl_iter;
> > > struct msm_display_topology topology;
> > > - enum dpu_rm_topology_name topology_name;
> > > struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
> > > int i = 0, ret;
> > >
> > > @@ -1069,7 +1068,6 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > > hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
> > > }
> > >
> > > - topology_name = dpu_rm_get_topology_name(topology);
> > > for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> > > struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> > >
> > > @@ -1089,7 +1087,6 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > > phys->hw_ctl = hw_ctl[i];
> > >
> > > phys->connector = conn->state->connector;
> > > - phys->topology_name = topology_name;
> > > if (phys->ops.mode_set)
> > > phys->ops.mode_set(phys, mode, adj_mode);
> > > }
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > > index 60f809f..c5600e6 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > > @@ -35,7 +35,6 @@
> > > * @needs_cdm: Encoder requests a CDM based on pixel format
> > conversion needs
> > > * @display_num_of_h_tiles: Number of horizontal tiles in case of
> > > split
> > > * interface
> > > - * @topology: Topology of the display
> > > */
> > > struct dpu_encoder_hw_resources {
> > > enum dpu_intf_mode intfs[INTF_MAX];
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > > index b3917e0..b5fc65c 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > > @@ -24,6 +24,7 @@
> > > #include "dpu_hw_top.h"
> > > #include "dpu_hw_cdm.h"
> > > #include "dpu_encoder.h"
> > > +#include "dpu_crtc.h"
> > >
> > > #define DPU_ENCODER_NAME_MAX 16
> > >
> > > @@ -213,7 +214,6 @@ struct dpu_encoder_irq {
> > > * @split_role: Role to play in a split-panel
> > configuration
> > > * @intf_mode: Interface mode
> > > * @intf_idx:Interface index on dpu hardware
> > > - * @topology_name: topology selected for the display
> > > * @enc_spinlock:Virtual-Encoder-Wide Spin Lock for IRQ purposes
> > > * @enable_state:Enable state tracking
> > > * @vblank_refcount: Reference count of vblank request
> > > @@ -243,7 +243,6 @@ struct dpu_encoder_phys {
> > > enum dpu_enc_split_role split_role;
> > > enum dpu_intf_mode intf_mode;
> > > enum dpu_intf intf_idx;
> > > - enum dpu_rm_topology_name topology_name;
> > > spinlock_t *enc_spinlock;
> > > enum dpu_enc_enable_state enable_state;
> > > atomic_t vblank_refcount;
> > > @@ -361,11 +360,15 @@ struct dpu_encoder_phys
> > *dpu_encoder_phys_cmd_init(
> > > static inline enum dpu_3d_blend_mode
> > dpu_encoder_helper_get_3d_blend_mode(
> > > struct dpu_encoder_phys *phys_enc)
> > > {
> > > + struct dpu_crtc_state *dpu_cstate;
> > > +
> > > if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
> > > return BLEND_3D_NONE;
> > >
> > > + dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
> > > +
> > > if (phys_enc->split_role == ENC_ROLE_SOLO &&
> > > - phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
> > > + (dpu_cstate->num_mixers == 2))
> >
> > I guess this should be
Re: [Freedreno] [PATCH v3] drm/msm: dpu: Allow planes to extend past active display
On Tue, Sep 04, 2018 at 05:14:01PM -0700, Jeykumar Sankaran wrote:
> On 2018-08-29 10:49, Sean Paul wrote:
> > From: Sean Paul
> >
> > The atomic_check is a bit too aggressive with respect to planes which
> > leave the active area. This caused a bunch of log spew when the cursor
> > got to the edge of the screen and stopped it from going all the way.
> >
> > This patch removes the conservative bounds checks from atomic and clips
> > the dst rect such that we properly display planes which go off the
> > screen.
> >
> > Changes in v2:
> > - Apply the clip to src as well (taking into account scaling)
> > Changes in v3:
> > - Use drm_atomic_helper_check_plane_state() to clip src/dst
> >
> > Cc: Sravanthi Kollukuduru
> > Cc: Jeykumar Sankaran
> > Cc: Ville Syrjälä
> > Signed-off-by: Sean Paul
> > ---
>
> Reviewed-by: Jeykumar Sankaran
Thanks for your review, I've pushed to dpu-staging/for-next.
Sean
>
> > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 34 +-
> > drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 1 -
> > drivers/gpu/drm/msm/msm_drv.h | 2 ++
> > 4 files changed, 24 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > index 07c2d15b45f2..f0a5e776ba32 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -1551,8 +1551,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc
> > *crtc,
> > cnt++;
> >
> > dst = drm_plane_state_dest(pstate);
> > - if (!drm_rect_intersect(, ) ||
> > - !drm_rect_equals(, )) {
> > + if (!drm_rect_intersect(, )) {
> > DPU_ERROR("invalid vertical/horizontal destination\n");
> > DPU_ERROR("display: " DRM_RECT_FMT " plane: "
> > DRM_RECT_FMT "\n", DRM_RECT_ARG(_rect),
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index efdf9b200dd9..46de0de466ff 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -1254,7 +1254,7 @@ static int dpu_plane_sspp_atomic_update(struct
> > drm_plane *plane,
> > const struct dpu_format *fmt;
> > struct drm_crtc *crtc;
> > struct drm_framebuffer *fb;
> > - struct drm_rect src, dst;
> > + int ret, min_scale;
> >
> > if (!plane) {
> > DPU_ERROR("invalid plane\n");
> > @@ -1293,21 +1293,29 @@ static int dpu_plane_sspp_atomic_update(struct
> > drm_plane *plane,
> > pdpu->is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
> > _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL);
> >
> > - src.x1 = state->src_x >> 16;
> > - src.y1 = state->src_y >> 16;
> > - src.x2 = src.x1 + (state->src_w >> 16);
> > - src.y2 = src.y1 + (state->src_h >> 16);
> > + min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);
> > + ret = drm_atomic_helper_check_plane_state(state, crtc->state,
> > min_scale,
> > + pdpu->pipe_sblk->maxupscale << 16,
> > + true, false);
> > + if (ret) {
> > + DPU_ERROR_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
> > + return ret;
> > + }
> >
> > - dst = drm_plane_state_dest(state);
> > + DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u "
> > DRM_RECT_FMT
> > + ", %4.4s ubwc %d\n", fb->base.id,
> > DRM_RECT_FP_ARG(>src),
> > + crtc->base.id, DRM_RECT_ARG(>dst),
> > + (char *)>base.pixel_format,
> > DPU_FORMAT_IS_UBWC(fmt));
> >
> > - DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FMT "->crtc%u " DRM_RECT_FMT
> > - ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_ARG(),
> > - crtc->base.id, DRM_RECT_ARG(),
> > - (char *)>base.pixel_format,
> > - DPU_FORMAT_IS_UBWC(fmt));
> > + pdpu->pipe_cfg.src_rect = state->src;
> > +
> > + /* state->src is 16.16, src_rect is not */
> > + pdpu->pipe_cfg.src_rect.x1 >>= 16;
> > + pdpu->pipe_cfg.src_rect.x2 >>= 16;
> > + pdpu->pipe_cfg.src_rect.y1 >>= 16;
> > + pdpu->pipe_cfg.src_rect.y2 >>= 16;
> >
> > - pdpu->pipe_cfg.src_rect = src;
> > - pdpu->pipe_cfg.dst_rect = dst;
> > + pdpu->pipe_cfg.dst_rect = state->dst;
> >
> > _dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
> >
> > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> > index 7d306c5acd09..273cbbe27c2e 100644
> > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
> > @@ -259,7 +259,6 @@ static void mdp5_plane_cleanup_fb(struct drm_plane
> > *plane,
> > msm_framebuffer_cleanup(fb, kms->aspace);
> > }
> >
> >
Re: [Freedreno] [PATCH 06/14] drm: extract drm_atomic_uapi.c
On Tue, Sep 04, 2018 at 01:41:33PM -0700, Rodrigo Vivi wrote:
> Maybe start a new file with SPDX identifier?
>
> I like the idea of this split...
I just checked, none of the other drm files have them. I'm not sure I want
to start this specific bikeshed, so I think I'll leave it as-is.
> Acked-by: Rodrigo Vivi
Thanks, Daniel
>
> > + *
> > + * Authors:
> > + * Rob Clark
> > + * Daniel Vetter
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "drm_crtc_internal.h"
> > +
> > +/**
> > + * DOC: overview
> > + *
> > + * This file contains the marshalling and demarshalling glue for the
> > atomic UAPI
> > + * in all it's form: The monster ATOMIC IOCTL itself, code for
> > GET_PROPERTY and
> > + * SET_PROPERTY IOCTls. Plus interface functions for compatibility helpers
> > and
> > + * drivers which have special needs to construct their own atomic updates,
> > e.g.
> > + * for load detect or similiar.
> > + */
> > +
> > +/**
> > + * drm_atomic_set_mode_for_crtc - set mode for CRTC
> > + * @state: the CRTC whose incoming state to update
> > + * @mode: kernel-internal mode to use for the CRTC, or NULL to disable
> > + *
> > + * Set a mode (originating from the kernel) on the desired CRTC state and
> > update
> > + * the enable property.
> > + *
> > + * RETURNS:
> > + * Zero on success, error code on failure. Cannot return -EDEADLK.
> > + */
> > +int drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state,
> > +const struct drm_display_mode *mode)
> > +{
> > + struct drm_crtc *crtc = state->crtc;
> > + struct drm_mode_modeinfo umode;
> > +
> > + /* Early return for no change. */
> > + if (mode && memcmp(>mode, mode, sizeof(*mode)) == 0)
> > + return 0;
> > +
> > + drm_property_blob_put(state->mode_blob);
> > + state->mode_blob = NULL;
> > +
> > + if (mode) {
> > + drm_mode_convert_to_umode(, mode);
> > + state->mode_blob =
> > + drm_property_create_blob(state->crtc->dev,
> > +sizeof(umode),
> > +);
> > + if (IS_ERR(state->mode_blob))
> > + return PTR_ERR(state->mode_blob);
> > +
> > + drm_mode_copy(>mode, mode);
> > + state->enable = true;
> > + DRM_DEBUG_ATOMIC("Set [MODE:%s] for [CRTC:%d:%s] state %p\n",
> > +mode->name, crtc->base.id, crtc->name, state);
> > + } else {
> > + memset(>mode, 0, sizeof(state->mode));
> > + state->enable = false;
> > + DRM_DEBUG_ATOMIC("Set [NOMODE] for [CRTC:%d:%s] state %p\n",
> > +crtc->base.id, crtc->name, state);
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL(drm_atomic_set_mode_for_crtc);
> > +
> > +/**
> > + * drm_atomic_set_mode_prop_for_crtc - set mode for CRTC
> > + * @state: the CRTC whose incoming state to update
> > + * @blob: pointer to blob property to use for mode
> > + *
> > + * Set a mode (originating from a blob property) on the desired CRTC state.
> > + * This function will take a reference on the blob property for the CRTC
> > state,
> > + * and release the reference held on the state's existing mode property,
> > if any
> > + * was set.
> > + *
> > + * RETURNS:
> > + * Zero on success, error code on failure. Cannot return -EDEADLK.
> > + */
> > +int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
> > + struct drm_property_blob *blob)
> > +{
> > + struct drm_crtc *crtc = state->crtc;
> > +
> > + if (blob == state->mode_blob)
> > + return 0;
> > +
> > + drm_property_blob_put(state->mode_blob);
> > + state->mode_blob = NULL;
> > +
> > + memset(>mode, 0, sizeof(state->mode));
> > +
> > + if (blob) {
> > + int ret;
> > +
> > + if (blob->length != sizeof(struct drm_mode_modeinfo)) {
> > + DRM_DEBUG_ATOMIC("[CRTC:%d:%s] bad mode blob length:
> > %zu\n",
> > +crtc->base.id, crtc->name,
> > +blob->length);
> > + return -EINVAL;
> > + }
> > +
> > + ret = drm_mode_convert_umode(crtc->dev,
> > +>mode, blob->data);
> > + if (ret) {
> > + DRM_DEBUG_ATOMIC("[CRTC:%d:%s] invalid mode (ret=%d,
> > status=%s):\n",
> > +crtc->base.id, crtc->name,
> > +ret,
> > drm_get_mode_status_name(state->mode.status));
> > + drm_mode_debug_printmodeline(>mode);
> > + return -EINVAL;
> > + }
> > +
> > + state->mode_blob = drm_property_blob_get(blob);
> > + state->enable = true;
> > +
