date:20181212

[Freedreno] [pull] drm/msm: msm-next for 4.21

2018-12-12 Thread Rob Clark

Hi Dave,

A little bigger this time, but still negative diffstat.

This time around, seeing some love for some older hw:

 - a2xx gpu support for apq8060 (hp touchpad) and imx5 (headless
   gpu-only mode)
 - a2xx gpummu support (a2xx was pre-iommu)
 - mdp4 display support for apq8060/touchpad

For display/dpu:

 - a big pile of continuing dpu fixes and cleanups

On the gpu side of things:

 - per-submit statistics and traceevents for better profiling
 - a6xx crashdump support
 - decouple get_iova() and page pinning.. so we can unpin from
   physical memory inactive bo's while using softpin to lower
   cpu overhead
 - new interface to set debug names on GEM BOs and debugfs
   output improvements
 - additional submit flag to indicate buffers that are usef
   to dump (so $debugfs/rd cmdstream dumping is useful with
   softpin + state-objects)



The following changes since commit e69aa5f9b97f7f871643336deb281db5cb14878b:

  Merge tag 'drm-misc-next-2018-12-06' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2018-12-07
11:23:05 +1000)

are available in the Git repository at:

  git://people.freedesktop.org/~robclark/linux drm-msm-next-2018-12-12

for you to fetch changes up to ba0ede185ef4c74bfecfe1c992be5dbcc5c5ac04:

  drm/msm/dpu: Fix clock issue after bind failure (2018-12-11 13:10:19 -0500)


Abhinav Kumar (1):
  drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver

Bruce Wang (4):
  drm/msm/dpu: Remove dpu_kms_pm_suspend/resume
  drm/msm: Cut dpu_kms hooks from msm_pm_suspend/resume
  drm/msm/dpu: Remove suspend state tracking from crtc
  drm/msm/dpu: Replace dpu_crtc_reset by atomic helper

Douglas Anderson (1):
  drm/msm: Only add available components

Jayant Shekhar (2):
  drm/msm/dpu: Correct dpu destroy and disable order
  drm/msm/dpu: Fix clock issue after bind failure

Jeykumar Sankaran (1):
  drm/msm/dpu: set geometry for iommu domain

Jonathan Marek (10):
  drm/msm/mdp4: only use lut_clk on mdp4.2+
  drm/msm/mdp4: allocate blank_cursor_no with MSM_BO_SCANOUT flag
  drm/msm: use contiguous vram for MSM_BO_SCANOUT when possible
  drm/msm/adreno: add a2xx
  drm/msm/mdp5: add config for msm8917
  drm/msm: set priv->kms to NULL before uninit
  drm/msm: implement a2xx mmu
  drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment
  dt-bindings: display: msm/gpu: document amd,imageon compatible
  drm/msm: add headless gpu device for imx5

Jordan Crouse (29):
  drm/msm/gpu: Allocate the correct size for the GPU memptrs
  drm/msm: Gracefully handle failure in _msm_gem_kernel_new
  drm/msm/gpu: Add per-submission statistics
  drm/msm/gpu: Add trace events for tracking GPU submissions
  drm/msm/gpu: Only store local command buffers in the GPU state
  drm/msm/gpu: Move gpu_poll_timeout() to adreno_gpu.h
  drm/msm/adreno: Don't capture register values if target doesn't
define them
  drm/msm/a6xx: Add a6xx gpu state
  drm/msm/a6xx: Track and manage a6xx state memory
  drm/msm: Add a common function to free kernel buffer objects
  drm/msm: Remove sgt from the mmu unmap function
  drm/msm: Split msm_gem_get_iova into two steps
  drm/msm: Clean up and enhance the output of the 'gem' debugfs node
  drm/msm: Add msm_gem_get_and_pin_iova()
  drm/msm: Count how many times iova memory is pinned
  drm/msm: Add a name field for gem objects
  drm/msm/gpu: Map the ringbuffer in the iova at create time
  drm/msm/a6xx: Use new kernel API free function for gpu state
  drm/msm/a6xx: Add a name for the crashdumper buffer
  drm/msm/dpu: Remove dpu_dbg
  drm/msm/dpu: Remove dpu_crtc_get_mixer_height
  drm/msm/dpu: Remove dpu_crtc_is_enabled()
  drm/msm/dpu: Remove unused functions
  drm/msm/dpu: Cleanup callers of dpu_hw_blk_init
  drm/msm: Make irq_postinstall optional
  drm/msm/dpu: Remove dpu_irq and unused functions
  drm/msm/dpu: Cleanup the debugfs functions
  drm/msm/dpu: Further cleanups for static inline functions
  drm/msm/dpu: Clean up dpu_media_info.h static inline functions

Mamta Shukla (1):
  drm: msm: Use DRM_DEV_* instead of dev_*

Matthias Kaehlcke (1):
  dt-bindings: msm/dsi: Add ref clock for PHYs

Rob Clark (5):
  drm/msm: update generated headers
  drm/msm/gpu: add submit flag to hint which buffers should be dumped
  drm/msm: rework GEM_INFO ioctl
  drm/msm: add uapi to get/set debug name
  drm/msm: bump UAPI version

Sean Paul (35):
  drm/msm: dpu: Add tracing around CTL_FLUSH
  drm/msm: Remove dpu_encoder_phys_ops->hw_reset()
  drm/msm: dpu: Remove unused functions from msm_media_info.h
  drm/msm: dpu: Remove _dpu_encoder_power_enable()
  drm/msm: dpu: Remove 'inline' from several functions
  drm/msm: dpu: Remove empty/useless labels
  drm/msm: dpu: Clean up

Re: [Freedreno] [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

2018-12-12 Thread Niklas Cassel

On Tue, Dec 04, 2018 at 02:42:29PM -0800, Matthias Kaehlcke wrote:
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
> 
> Signed-off-by: Matthias Kaehlcke 
> ---
> Changes in v4:
> - always use parent rate in dsi_pll_28nm_clk_set_rate() and
>dsi_pll_28nm_clk_recalc_rate()
> - pass name of VCO ref clock to pll_28nm_register() instead of
>   storing it in a struct field
> - updated commit message
> 
> Changes in v3:
> - use default name and rate if the ref clock is not specified
>   in the DT
> - store vco_ref_clk_name instead of vco_ref_clk
> - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
>   unsigned long
> - fixed check for EPROBE_DEFER
> - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
> 
> Changes in v2:
> - patch added to the series
> ---
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++---
>  1 file changed, 25 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 
> b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> index 26e3a01a99c2b..340b03e8d 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> @@ -40,7 +40,6 @@
>  
>  #define NUM_PROVIDED_CLKS2
>  
> -#define VCO_REF_CLK_RATE 1920
>  #define VCO_MIN_RATE 35000
>  #define VCO_MAX_RATE 75000
>  
> @@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, 
> unsigned long rate,
>   pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
>   pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
>  
> - rem = rate % VCO_REF_CLK_RATE;
> + rem = rate % parent_rate;
>   if (rem) {
>   refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
>   frac_n_mode = 1;
> - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
> - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
> + div_fbx1000 = rate / (parent_rate / 500);
> + gen_vco_clk = div_fbx1000 * (parent_rate / 500);
>   } else {
>   refclk_cfg = 0x0;
>   frac_n_mode = 0;
> - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
> - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
> + div_fbx1000 = rate / (parent_rate / 1000);
> + gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
>   }
>  
>   DBG("refclk_cfg = %d", refclk_cfg);
> @@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct 
> clk_hw *hw,
>   void __iomem *base = pll_28nm->mmio;
>   u32 sdm0, doubler, sdm_byp_div;
>   u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> - u32 ref_clk = VCO_REF_CLK_RATE;
> + u32 ref_clk = parent_rate;
>   unsigned long vco_rate;
>  
>   VERB("parent_rate=%lu", parent_rate);
> @@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct 
> clk_hw *hw,
>   /* Check to see if the ref clk doubler is enabled */
>   doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
>   DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> - ref_clk += (doubler * VCO_REF_CLK_RATE);
> + ref_clk += (doubler * ref_clk);
>  
>   /* see if it is integer mode or sdm mode */
>   sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
> @@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll 
> *pll)
>   pll_28nm->clk_data.clk_num = 0;
>  }
>  
> -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
> +  const char *ref_clk_name)
>  {
>   char clk_name[32], parent1[32], parent2[32], vco_name[32];
>   struct clk_init_data vco_init = {
> - .parent_names = (const char *[]){ "xo" },
> + .parent_names = _clk_name,
>   .num_parents = 1,
>   .name = vco_name,
>   .flags = CLK_IGNORE_UNUSED,
> @@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct 
> platform_device *pdev,
>  {
>   struct dsi_pll_28nm *pll_28nm;
>   struct msm_dsi_pll *pll;
> + struct clk *vco_ref_clk;
> + const char *vco_ref_clk_name;
>   int ret;
>  
>   if (!pdev)
> @@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct 
> platform_device *pdev,
>   pll_28nm->pdev = pdev;
>   pll_28nm->id = id;
>  
> + vco_ref_clk = devm_clk_get(>dev, "ref");
> + if (!IS_ERR(vco_ref_clk)) {
> + vco_ref_clk_name = __clk_get_name(vco_ref_clk);
> + } else {
> + ret = PTR_ERR(vco_ref_clk);
> + if (ret == -EPROBE_DEFER)
> + ERR_PTR(ret);

It looks like you are missing the return keyword here.

> +
> + dev_warn(>dev, "'ref' clock is not specified, using 
> default name\n");
> + vco_ref_clk_name = "xo";
> + }
> +
>   pll_28nm->mmio =

[Freedreno] [PATCH v6 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU

2018-12-12 Thread Jordan Crouse

Now that more of the sdm845 bindings are headed upstream this a refresh of
of https://patchwork.freedesktop.org/series/39308/ to add bindings and nodes
for the GPU/GMU and GPU SMMU for sdm845.

This is based on :
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next

with:
https://lore.kernel.org/patchwork/patch/1018365/

This change requires the following dependencies:

include/dt-bindings/power/qcom-rpmpd.h:
https://patchwork.kernel.org/patch/1079/

qcom,smmu-v2 binding:
https://patchwork.kernel.org/patch/10581911/

v6: Update GPU bindings for a6xx and make the examples match the nodes and vice
 versa.  Clean up types and rebase on
 https://lore.kernel.org/patchwork/patch/1018365/ to help facilitate merging.
v5: Use symbolic names for the RPMH power levels defined in OPP table,
 move the opp tables as children of their respective nodes and rename
 the iommu device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
  really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
  change gmu phandle to qcom,gmu per Rob

*** BLURB HERE ***

Jordan Crouse (2):
  dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
  arm64: dts: sdm845: Add gpu and gmu device nodes

 .../devicetree/bindings/display/msm/gmu.txt   |  56 
 .../devicetree/bindings/display/msm/gpu.txt   |  41 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi  | 123 ++
 3 files changed, 217 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

-- 
2.18.0

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[Freedreno] [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

2018-12-12 Thread Jordan Crouse

Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.

Signed-off-by: Jordan Crouse 
---
 .../devicetree/bindings/display/msm/gmu.txt   | 56 +++
 .../devicetree/bindings/display/msm/gpu.txt   | 41 +-
 2 files changed, 94 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt 
b/Documentation/devicetree/bindings/display/msm/gmu.txt
new file mode 100644
index ..6152cb551d29
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
@@ -0,0 +1,56 @@
+Qualcomm adreno/snapdragon GMU (Graphics management unit)
+
+The GMU is a programmable power controller for the GPU. the CPU controls the
+GMU which in turn handles power controls for the GPU.
+
+Required properties:
+- compatible:
+  * "qcom,adreno-gmu"
+- reg: Physical base address and length of the GMU registers.
+- reg-names: Matching names for the register regions
+  * "gmu"
+  * "gmu_pdc"
+  * "gmu_pdc_seg"
+- interrupts: The interrupt signals from the GMU.
+- interrupt-names: Matching names for the interrupts
+  * "hfi"
+  * "gmu"
+- clocks: phandles to the device clocks
+- clock-names: Matching names for the clocks
+   * "gmu"
+   * "cxo"
+   * "axi"
+   * "mnoc"
+- power-domains: should be <_gpucc GPU_CX_GDSC>
+- iommus: phandle to the adreno iommu
+- operating-points-v2: phandle to the OPP operating points
+
+Example:
+
+/ {
+   ...
+
+   gmu: gmu@506a000 {
+   compatible="qcom,adreno-gmu";
+
+   reg = <0x506a000 0x3>,
+   <0xb28 0x1>,
+   <0xb48 0x1>;
+   reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+   interrupts = ,
+;
+   interrupt-names = "hfi", "gmu";
+
+   clocks = < GPU_CC_CX_GMU_CLK>,
+   < GPU_CC_CXO_CLK>,
+   < GCC_DDRSS_GPU_AXI_CLK>,
+   < GCC_GPU_MEMNOC_GFX_CLK>;
+   clock-names = "gmu", "cxo", "axi", "memnoc";
+
+   power-domains = < GPU_CX_GDSC>;
+   iommus = <_smmu 5>;
+
+   operating-points-v2 = <_opp_table>;
+   };
+};
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt 
b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 43fac0fe09bb..8d9415180c22 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -8,14 +8,21 @@ Required properties:
   with the chip-id.
 - reg: Physical base address and length of the controller's registers.
 - interrupts: The interrupt signal from the gpu.
-- clocks: device clocks
+- interrupt-names: List of names for the interrupt signals. The following can 
be
+  provided:
+  * "kgsl_3d0_irq"
+- clocks: device clocks (if applicable)
   See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required:
+- clock-names: the following clocks can be provided:
   * "core"
   * "iface"
   * "mem_iface"
+- iommus: optional phandle to an adreno iommu instance
+- operating-points-v2: optional phandle to the OPP operating points
+- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will
+  control the power for the GPU
 
-Example:
+Example 3xx/4xx/a5xx:
 
 / {
...
@@ -36,3 +43,31 @@ Example:
< MMSS_IMEM_AHB_CLK>;
};
 };
+
+Example a6xx (with GMU):
+
+/ {
+   ...
+
+   gpu@500 {
+   compatible = "qcom,adreno-630.2", "qcom,adreno";
+   #stream-id-cells = <16>;
+
+   reg = <0x500 0x4>, <0x509e000 0x10>;
+   reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+   /*
+* Look ma, no clocks! The GPU clocks and power are
+* controlled entirely by the GMU
+*/
+
+   interrupts = ;
+   interrupt-names = "kgsl_3d0_irq";
+
+   iommus = <_smmu 0>;
+
+   operating-points-v2 = <_opp_table>;
+
+   qcom,gmu = <>;
+   };
+};
-- 
2.18.0

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[Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

2018-12-12 Thread Jordan Crouse

Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by: Jordan Crouse 
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++
 1 file changed, 123 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 233a5898ebc2..a608afed502e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1349,6 +1350,128 @@
};
};
 
+
+   gpu@500 {
+   compatible = "qcom,adreno-630.2", "qcom,adreno";
+   #stream-id-cells = <16>;
+
+   reg = <0x500 0x4>, <0x509e000 0x10>;
+   reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+   /*
+* Look ma, no clocks! The GPU clocks and power are
+* controlled entirely by the GMU
+*/
+
+   interrupts = ;
+   interrupt-names = "kgsl_3d0_irq";
+
+   iommus = <_smmu 0>;
+
+   operating-points-v2 = <_opp_table>;
+
+   qcom,gmu = <>;
+
+   gpu_opp_table: opp-table {
+   compatible = "operating-points-v2-qcom-level";
+
+   opp-71000 {
+   opp-hz = /bits/ 64 <71000>;
+   qcom,level = 
;
+   };
+
+   opp-67500 {
+   opp-hz = /bits/ 64 <67500>;
+   qcom,level = 
;
+   };
+
+   opp-59600 {
+   opp-hz = /bits/ 64 <59600>;
+   qcom,level = 
;
+   };
+
+   opp-52000 {
+   opp-hz = /bits/ 64 <52000>;
+   qcom,level = ;
+   };
+
+   opp-41400 {
+   opp-hz = /bits/ 64 <41400>;
+   qcom,level = 
;
+   };
+
+   opp-34200 {
+   opp-hz = /bits/ 64 <34200>;
+   qcom,level = ;
+   };
+
+   opp-25700 {
+   opp-hz = /bits/ 64 <25700>;
+   qcom,level = 
;
+   };
+   };
+   };
+
+   adreno_smmu: iommu@504 {
+   compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+   reg = <0x504 0x1>;
+   #iommu-cells = <1>;
+   #global-interrupts = <2>;
+   interrupts = ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ,
+   ;
+   clocks = < GCC_GPU_MEMNOC_GFX_CLK>,
+   < GCC_GPU_CFG_AHB_CLK>;
+   clock-names = "bus", "iface";
+
+   power-domains = < GPU_CX_GDSC>;
+   };
+
+   gmu: gmu@506a000 {
+   compatible="qcom,adreno-gmu";
+
+   reg = <0x506a000 0x3>,
+   <0xb28 0x1>,
+   <0xb48 0x1>;
+   reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+   interrupts = ,
+;
+   interrupt-names = "hfi", "gmu";
+
+   clocks = < GPU_CC_CX_GMU_CLK>,
+   < GPU_CC_CXO_CLK>,
+   < GCC_DDRSS_GPU_AXI_CLK>,
+   < GCC_GPU_MEMNOC_GFX_CLK>;
+   clock-names = "gmu", "cxo", "axi", "memnoc";
+
+   power-domains = < GPU_CX_GDSC>;
+   iommus = <_smmu 5>;
+
+   operating-points-v2 = <_opp_table>;
+
+   gmu_opp_table: opp-table {
+   compatible = "operating-points-v2-qcom-level";
+
+

Re: [Freedreno] [PATCH v5 1/2] dt-bindings: Document, qcom, adreno-gmu

2018-12-12 Thread Jordan Crouse

On Wed, Dec 12, 2018 at 11:26:46AM -0800, Doug Anderson wrote:
> Hi,
> 
> On Wed, Dec 12, 2018 at 9:31 AM Jordan Crouse  wrote:
> >
> > Document the device tree bindings for the Adreno GMU device
> > available on Adreno a6xx targets.
> >
> > Reviewed-by: Rob Herring 
> > Signed-off-by: Jordan Crouse 
> > ---
> >  .../devicetree/bindings/display/msm/gmu.txt   | 54 +++
> >  .../devicetree/bindings/display/msm/gpu.txt   |  2 +
> >  2 files changed, 56 insertions(+)
> 
> nit: Why does subject have a "," after "Document"?

Typo.

> nit: Should subject start "dt-bindings: drm/msm/a6xx" or something
> like that?  I thought you wanted not just "dt-bindings" but also a
> subsystem prefix?

I was trying to reuse the subject from the previous versions, but I would be
happy to change it.

> 
> >  create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt 
> > b/Documentation/devicetree/bindings/display/msm/gmu.txt
> > new file mode 100644
> > index ..f65bb49fff36
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
> > @@ -0,0 +1,54 @@
> > +Qualcomm adreno/snapdragon GMU (Graphics management unit)
> > +
> > +The GMU is a programmable power controller for the GPU. the CPU controls 
> > the
> > +GMU which in turn handles power controls for the GPU.
> > +
> > +Required properties:
> > +- compatible:
> > +  * "qcom,adreno-gmu"
> > +- reg: Physical base address and length of the GMU registers.
> > +- reg-names: Matching names for the register regions
> > +  * "gmu"
> > +  * "gmu_pdc"
> > +- interrupts: The interrupt signals from the GMU.
> > +- interrupt-names: Matching names for the interrupts
> > +  * "hfi"
> > +  * "gmu"
> > +- clocks: phandles to the device clocks
> > +- clock-names: Matching names for the clocks
> > +   * "gmu"
> > +   * "cxo"
> > +   * "axi"
> > +   * "mnoc"
> > +- power-domains: should be <_gpucc GPU_CX_GDSC>
> > +- iommus: phandle to the adreno iommu
> > +- operating-points-v2: phandle to the OPP operating points
> > +
> > +Example:
> > +
> > +/ {
> > +   ...
> > +
> > +   gmu: gmu@506a000 {
> > +   compatible="qcom,adreno-gmu";
> > +
> > +   reg = <0x506a000 0x3>,
> > +   <0xb20 0x30>;
> > +   reg-names = "gmu", "gmu_pdc";
> 
> Your implementation has 3 register ranges but your bindings have 2.
> You also have a different address for "gmu_pdc" even though it looks
> like your examples are supposed to be based on sdm845.
>
> (you'd want to not only change the example but also the bindings above)

I'll update the settings - a new region has indeed been added since the last
time we were here.

> 
> > +
> > +   interrupts = ,
> > +   ;
> > +   interrupt-names = "hfi", "gmu";
> > +
> > +   clocks = <_gpucc GPU_CC_CX_GMU_CLK>,
> > +   <_gpucc GPU_CC_CXO_CLK>,
> > +   <_gcc GCC_DDRSS_GPU_AXI_CLK>,
> > +   <_gcc GCC_GPU_MEMNOC_GFX_CLK>;
> 
> nit: might as well update to "" to match the style of clock
> controller labels used in sdm845.dts.
> 
> 
> > +   clock-names = "gmu", "cxo", "axi", "memnoc";
> > +
> > +   power-domains = <_gpucc GPU_CX_GDSC>;
> > +   iommus = <_smmu 5>;
> > +
> > +   i   operating-points-v2 = <_opp_table>;
> 
> Why "i"?

Also a typo.

> ...also: worth actually including the operating table here in the example?

I say no.  It might good practice to have the opp tables in the child node but I
don't think it is mandatory from a bindings perspective.

The bindings are documented elsewhere and to me that seems enough for our
purposes - at least thats our story for smmu and gpucc and other phandles.

> 
> > +   };
> > +};
> > diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt 
> > b/Documentation/devicetree/bindings/display/msm/gpu.txt
> > index 43fac0fe09bb..754f6c6f34e5 100644
> > --- a/Documentation/devicetree/bindings/display/msm/gpu.txt
> > +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
> > @@ -14,6 +14,8 @@ Required properties:
> >* "core"
> >* "iface"
> >* "mem_iface"
> > +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that 
> > will
> > +  control the power for the GPU
> 
> You seem to have lost something between the previous version of this
> and the latest.  In the last version (and the version Rob gave his
> review to) you added some extra text.  Diffing your old patch to your
> new one:
> 
> -Optional properties.
> -- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and
> -  newer with a GMU attached do not have direct clock control from the CPU and
> -  do not need to provide clock properties.
> +- clocks: device clocks
>See ../clocks/clock-bindings.txt for details.
> -- clock-names: the following clocks can be

Re: [Freedreno] [PATCH v5 1/2] dt-bindings: Document, qcom, adreno-gmu

2018-12-12 Thread Doug Anderson

Hi,

On Wed, Dec 12, 2018 at 9:31 AM Jordan Crouse  wrote:
>
> Document the device tree bindings for the Adreno GMU device
> available on Adreno a6xx targets.
>
> Reviewed-by: Rob Herring 
> Signed-off-by: Jordan Crouse 
> ---
>  .../devicetree/bindings/display/msm/gmu.txt   | 54 +++
>  .../devicetree/bindings/display/msm/gpu.txt   |  2 +
>  2 files changed, 56 insertions(+)

nit: Why does subject have a "," after "Document"?

nit: Should subject start "dt-bindings: drm/msm/a6xx" or something
like that?  I thought you wanted not just "dt-bindings" but also a
subsystem prefix?


>  create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
>
> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt 
> b/Documentation/devicetree/bindings/display/msm/gmu.txt
> new file mode 100644
> index ..f65bb49fff36
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
> @@ -0,0 +1,54 @@
> +Qualcomm adreno/snapdragon GMU (Graphics management unit)
> +
> +The GMU is a programmable power controller for the GPU. the CPU controls the
> +GMU which in turn handles power controls for the GPU.
> +
> +Required properties:
> +- compatible:
> +  * "qcom,adreno-gmu"
> +- reg: Physical base address and length of the GMU registers.
> +- reg-names: Matching names for the register regions
> +  * "gmu"
> +  * "gmu_pdc"
> +- interrupts: The interrupt signals from the GMU.
> +- interrupt-names: Matching names for the interrupts
> +  * "hfi"
> +  * "gmu"
> +- clocks: phandles to the device clocks
> +- clock-names: Matching names for the clocks
> +   * "gmu"
> +   * "cxo"
> +   * "axi"
> +   * "mnoc"
> +- power-domains: should be <_gpucc GPU_CX_GDSC>
> +- iommus: phandle to the adreno iommu
> +- operating-points-v2: phandle to the OPP operating points
> +
> +Example:
> +
> +/ {
> +   ...
> +
> +   gmu: gmu@506a000 {
> +   compatible="qcom,adreno-gmu";
> +
> +   reg = <0x506a000 0x3>,
> +   <0xb20 0x30>;
> +   reg-names = "gmu", "gmu_pdc";

Your implementation has 3 register ranges but your bindings have 2.
You also have a different address for "gmu_pdc" even though it looks
like your examples are supposed to be based on sdm845.

(you'd want to not only change the example but also the bindings above)


> +
> +   interrupts = ,
> +   ;
> +   interrupt-names = "hfi", "gmu";
> +
> +   clocks = <_gpucc GPU_CC_CX_GMU_CLK>,
> +   <_gpucc GPU_CC_CXO_CLK>,
> +   <_gcc GCC_DDRSS_GPU_AXI_CLK>,
> +   <_gcc GCC_GPU_MEMNOC_GFX_CLK>;

nit: might as well update to "" to match the style of clock
controller labels used in sdm845.dts.


> +   clock-names = "gmu", "cxo", "axi", "memnoc";
> +
> +   power-domains = <_gpucc GPU_CX_GDSC>;
> +   iommus = <_smmu 5>;
> +
> +   i   operating-points-v2 = <_opp_table>;

Why "i"?

...also: worth actually including the operating table here in the example?


> +   };
> +};
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt 
> b/Documentation/devicetree/bindings/display/msm/gpu.txt
> index 43fac0fe09bb..754f6c6f34e5 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.txt
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
> @@ -14,6 +14,8 @@ Required properties:
>* "core"
>* "iface"
>* "mem_iface"
> +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will
> +  control the power for the GPU

You seem to have lost something between the previous version of this
and the latest.  In the last version (and the version Rob gave his
review to) you added some extra text.  Diffing your old patch to your
new one:

-Optional properties.
-- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and
-  newer with a GMU attached do not have direct clock control from the CPU and
-  do not need to provide clock properties.
+- clocks: device clocks
   See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks can be provided:
+- clock-names: the following clocks are required:

Did you mean to remove that?  Your current bindings now say that the
clocks are required but then your device tree patch for sdm845 says
they're not.

>  Example:

While you're touching this file, maybe update the "Example" so instead
of saying "qcom,kgsl-3d0@" it says "gpu@"


-Doug
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Re: [Freedreno] [PATCH v5 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

2018-12-12 Thread Doug Anderson

Hi,

On Wed, Dec 12, 2018 at 9:31 AM Jordan Crouse  wrote:
>
> Add the nodes to describe the Adreno GPU and GMU devices.
>
> Signed-off-by: Jordan Crouse 
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++
>  1 file changed, 123 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index c27cbd3bcb0a..daa404b05a70 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -7,9 +7,11 @@
>
>  #include 
>  #include 
> +#include 

Probably don't need to add this in your patch since (presumably) your
patch needs to be based atop
 and that already
adds the #include (and also the node that you depend on).


>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1348,6 +1350,127 @@
> };
> };
>
> +   gpu@500 {
> +   compatible = "qcom,adreno-630.2", "qcom,adreno";
> +   #stream-id-cells = <16>;
> +
> +   reg = <0x500 0x4>, <0x509e000 0x10>;
> +   reg-names = "kgsl_3d0_reg_memory", "cx_mem";

The second register range isn't in your bindings patch.  Can you add it?


> +   /*
> +* Look ma, no clocks! The GPU clocks and power are
> +* controlled entirely by the GMU
> +*/
> +
> +   interrupts = ;
> +   interrupt-names = "kgsl_3d0_irq";
> +
> +   iommus = <_smmu 0>;

It it worth mentioning the iommus and #stream-id-cells in the bindings?


> +   operating-points-v2 = <_opp_table>;

Is it worth mentioning the operating-points-v2 in the bindings patch?


> +
> +   qcom,gmu = <>;
> +
> +   gpu_opp_table: adreno-opp-table {

nit: since this is no longer at the top level you can just call it
"opp-table" now.  That matches what the latest RPMh PD node looks
like.


> +   compatible = "operating-points-v2-qcom-level";
> +
> +   opp-71000 {
> +   opp-hz = /bits/ 64 <71000>;
> +   qcom,level = 
> ;
> +   };
> +
> +   opp-67500 {
> +   opp-hz = /bits/ 64 <67500>;
> +   qcom,level = 
> ;
> +   };
> +
> +   opp-59600 {
> +   opp-hz = /bits/ 64 <59600>;
> +   qcom,level = 
> ;
> +   };
> +
> +   opp-52000 {
> +   opp-hz = /bits/ 64 <52000>;
> +   qcom,level = 
> ;
> +   };
> +
> +   opp-41400 {
> +   opp-hz = /bits/ 64 <41400>;
> +   qcom,level = 
> ;
> +   };
> +
> +   opp-34200 {
> +   opp-hz = /bits/ 64 <34200>;
> +   qcom,level = 
> ;
> +   };
> +
> +   opp-25700 {
> +   opp-hz = /bits/ 64 <25700>;
> +   qcom,level = 
> ;
> +   };
> +   };
> +   };
> +
> +   adreno_smmu: iommu@504 {
> +   compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
> +   reg = <0x504 0x1>;
> +   #iommu-cells = <1>;
> +   #global-interrupts = <2>;
> +   interrupts = ,
> +   ,
> +   ,
> +   ,
> +   ,
> +   ,
> +   ,
> +   ,
> +   ,
> +   ;
> +   clocks = < GCC_GPU_MEMNOC_GFX_CLK>,
> +   < GCC_GPU_CFG_AHB_CLK>;
> +   clock-names = "bus", "iface";
> +
> +   power-domains = < GPU_CX_GDSC>;
> +   };
> +
> +   gmu: gmu@506a000 {
> +   compatible="qcom,adreno-gmu";
> +
> +   reg = <0x506a000 0x3>,
> +

Re: [Freedreno] [PATCH 7/7] drm: Split out drm_probe_helper.h

2018-12-12 Thread Daniel Vetter

On Mon, Dec 10, 2018 at 02:40:25PM +0100, Benjamin Gaignard wrote:
> Le lun. 10 déc. 2018 à 12:10, Benjamin Gaignard
>  a écrit :
> >
> > Le lun. 10 déc. 2018 à 11:24, Thierry Reding
> >  a écrit :
> > >
> > > On Mon, Dec 10, 2018 at 11:11:33AM +0100, Daniel Vetter wrote:
> > > > Having the probe helper stuff (which pretty much everyone needs) in
> > > > the drm_crtc_helper.h file (which atomic drivers should never need) is
> > > > confusing. Split them out.
> > > >
> > > > To make sure I actually achieved the goal here I went through all
> > > > drivers. And indeed, all atomic drivers are now free of
> > > > drm_crtc_helper.h includes.
> > > >
> >
> > I have difficulties to apply this with git on top of drm-misc-next.
> > It is because of that I got errors (encoder and connector types not
> > found) while compiling adv7511_audio.c and exynos_dp.c ?
> >
> 
> Nack on this patch because it break compiling at least on sti driver.
> drm_probe_helper.h doesn't bring the same includes than drm_crtc_helper.h:
> #include 
> #include 
> #include 
> so some types, structures and functions proptotypes are missing while 
> compiling.

Hm, I thought I've compile-tested all the arm stuff, I guess I've failed.
Will respin, sorry for the confusion.
-Daniel

> 
> 
> > Benjamin
> > > > Signed-off-by: Daniel Vetter 
> > > > Cc: linux-arm-ker...@lists.infradead.org
> > > > Cc: virtualizat...@lists.linux-foundation.org
> > > > Cc: etna...@lists.freedesktop.org
> > > > Cc: linux-samsung-...@vger.kernel.org
> > > > Cc: intel-...@lists.freedesktop.org
> > > > Cc: linux-media...@lists.infradead.org
> > > > Cc: linux-amlo...@lists.infradead.org
> > > > Cc: linux-arm-...@vger.kernel.org
> > > > Cc: freedreno@lists.freedesktop.org
> > > > Cc: nouv...@lists.freedesktop.org
> > > > Cc: spice-de...@lists.freedesktop.org
> > > > Cc: amd-...@lists.freedesktop.org
> > > > Cc: linux-renesas-...@vger.kernel.org
> > > > Cc: linux-rockc...@lists.infradead.org
> > > > Cc: linux-st...@st-md-mailman.stormreply.com
> > > > Cc: linux-te...@vger.kernel.org
> > > > Cc: xen-de...@lists.xen.org
> > > > ---
> > > >  .../gpu/drm/amd/amdgpu/amdgpu_connectors.c|  2 +-
> > > >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  2 +-
> > > >  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  2 +-
> > > >  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h  |  1 +
> > > >  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  2 +-
> > > >  .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  |  2 +-
> > > >  .../display/amdgpu_dm/amdgpu_dm_services.c|  2 +-
> > > >  drivers/gpu/drm/arc/arcpgu_crtc.c |  2 +-
> > > >  drivers/gpu/drm/arc/arcpgu_drv.c  |  2 +-
> > > >  drivers/gpu/drm/arc/arcpgu_sim.c  |  2 +-
> > > >  drivers/gpu/drm/arm/hdlcd_crtc.c  |  2 +-
> > > >  drivers/gpu/drm/arm/hdlcd_drv.c   |  2 +-
> > > >  drivers/gpu/drm/arm/malidp_crtc.c |  2 +-
> > > >  drivers/gpu/drm/arm/malidp_drv.c  |  2 +-
> > > >  drivers/gpu/drm/arm/malidp_mw.c   |  2 +-
> > > >  drivers/gpu/drm/armada/armada_510.c   |  2 +-
> > > >  drivers/gpu/drm/armada/armada_crtc.c  |  2 +-
> > > >  drivers/gpu/drm/armada/armada_drv.c   |  2 +-
> > > >  drivers/gpu/drm/armada/armada_fb.c|  2 +-
> > > >  drivers/gpu/drm/ast/ast_drv.c |  1 +
> > > >  drivers/gpu/drm/ast/ast_mode.c|  1 +
> > > >  .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c|  2 +-
> > > >  drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h  |  2 +-
> > > >  drivers/gpu/drm/bochs/bochs_drv.c |  1 +
> > > >  drivers/gpu/drm/bochs/bochs_kms.c |  1 +
> > > >  drivers/gpu/drm/bridge/adv7511/adv7511.h  |  2 +-
> > > >  drivers/gpu/drm/bridge/analogix-anx78xx.c |  3 +-
> > > >  .../drm/bridge/analogix/analogix_dp_core.c|  2 +-
> > > >  drivers/gpu/drm/bridge/cdns-dsi.c |  2 +-
> > > >  drivers/gpu/drm/bridge/dumb-vga-dac.c |  2 +-
> > > >  .../bridge/megachips-stdp-ge-b850v3-fw.c  |  2 +-
> > > >  drivers/gpu/drm/bridge/nxp-ptn3460.c  |  2 +-
> > > >  drivers/gpu/drm/bridge/panel.c|  2 +-
> > > >  drivers/gpu/drm/bridge/parade-ps8622.c|  2 +-
> > > >  drivers/gpu/drm/bridge/sii902x.c  |  2 +-
> > > >  drivers/gpu/drm/bridge/synopsys/dw-hdmi.c |  2 +-
> > > >  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c |  2 +-
> > > >  drivers/gpu/drm/bridge/tc358764.c |  2 +-
> > > >  drivers/gpu/drm/bridge/tc358767.c |  2 +-
> > > >  drivers/gpu/drm/bridge/ti-sn65dsi86.c |  2 +-
> > > >  drivers/gpu/drm/bridge/ti-tfp410.c|  2 +-
> > > >  drivers/gpu/drm/cirrus/cirrus_drv.c   |  1 +
> > > >  drivers/gpu/drm/cirrus/cirrus_mode.c  |  1 +
> > > >  drivers/gpu/drm/drm_atomic_helper.c   |  1 -
> > > >  drivers/gpu/drm/drm_dp_mst_topology.c |  2 +-
> > > >  drivers/gpu/drm/drm_modeset_helper.c  |  2 +-
> > > >

[Freedreno] [pull] drm/msm: msm-next for 4.21

Re: [Freedreno] [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

[Freedreno] [PATCH v6 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU

[Freedreno] [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

[Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

Re: [Freedreno] [PATCH v5 1/2] dt-bindings: Document, qcom, adreno-gmu

Re: [Freedreno] [PATCH v5 1/2] dt-bindings: Document, qcom, adreno-gmu

Re: [Freedreno] [PATCH v5 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes

Re: [Freedreno] [PATCH 7/7] drm: Split out drm_probe_helper.h

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