[Freedreno] [PATCH v5 2/8] drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd
---
Changes in v5:
- added "Reviewed-by: Stephen Boyd " tag
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
- updated commit message
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
.../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 +++
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 49008451085b8..76e5188169b91 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -47,7 +47,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 2700
#define VCO_MIN_RATE 6
#define VCO_MAX_RATE 12
@@ -125,7 +124,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10;
- val = VCO_REF_CLK_RATE / 10;
+ val = parent_rate / 10;
fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
fb_divider = fb_divider / 2 - 1;
pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1,
@@ -406,11 +405,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
pll_28nm->clks, pll_28nm->num_clks);
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+const char *ref_clk_name)
{
char *clk_name, *parent_name, *vco_name;
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "pxo" },
+ .parent_names = &ref_clk_name,
.num_parents = 1,
.flags = CLK_IGNORE_UNUSED,
.ops = &clk_ops_dsi_pll_28nm_vco,
@@ -494,6 +494,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -506,6 +508,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id + 1;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ return ERR_PTR(ret);
+
+ dev_warn(&pdev->dev, "'ref' clock is not specified, using
default name\n");
+ vco_ref_clk_name = "pxo";
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
@@ -524,7 +538,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct
platform_device *pdev,
pll->en_seq_cnt = 1;
pll->enable_seqs[0] = dsi_pll_28nm_enable_seq;
- ret = pll_28nm_register(pll_28nm);
+ ret = pll_28nm_register(pll_28nm, vco_ref_clk_name);
if (ret) {
dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
2.20.1.415.g653613c723-goog
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[Freedreno] [PATCH v5 1/8] dt-bindings: msm/dsi: Add ref clock for PHYs
Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring --- Changes in v5: - added "Reviewed-by: Rob Herring " tag Changes in v4: - added "Reviewed-by" tags from Stephen and Doug Changes in v3: - added note that the ref clock is only required for new DTS files/entries Changes in v2: - add the ref clock for all PHYs, not only the 10nm one - updated commit message --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd88..9ae9469427207 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Stephen Boyd tag
---
Changes in v5:
- added missing return keyword in msm_dsi_pll_28nm_init()
- added "Reviewed-by: Stephen Boyd " tag
Changes in v4:
- always use parent rate in dsi_pll_28nm_clk_set_rate() and
dsi_pll_28nm_clk_recalc_rate()
- pass name of VCO ref clock to pll_28nm_register() instead of
storing it in a struct field
- updated commit message
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
unsigned long
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 26e3a01a99c2b..c839464741927 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 35000
#define VCO_MAX_RATE 75000
@@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
- rem = rate % VCO_REF_CLK_RATE;
+ rem = rate % parent_rate;
if (rem) {
refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
frac_n_mode = 1;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
+ div_fbx1000 = rate / (parent_rate / 500);
+ gen_vco_clk = div_fbx1000 * (parent_rate / 500);
} else {
refclk_cfg = 0x0;
frac_n_mode = 0;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
+ div_fbx1000 = rate / (parent_rate / 1000);
+ gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
}
DBG("refclk_cfg = %d", refclk_cfg);
@@ -265,7 +264,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
void __iomem *base = pll_28nm->mmio;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
- u32 ref_clk = VCO_REF_CLK_RATE;
+ u32 ref_clk = parent_rate;
unsigned long vco_rate;
VERB("parent_rate=%lu", parent_rate);
@@ -273,7 +272,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct
clk_hw *hw,
/* Check to see if the ref clk doubler is enabled */
doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
- ref_clk += (doubler * VCO_REF_CLK_RATE);
+ ref_clk += (doubler * ref_clk);
/* see if it is integer mode or sdm mode */
sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
@@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
pll_28nm->clk_data.clk_num = 0;
}
-static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
+static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
+const char *ref_clk_name)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = &ref_clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ return ERR_PTR(ret);
+
+ dev_warn(&pdev->dev, "'ref' clock is not specified, using
default name\n");
+ vco_ref_clk_name = "xo";
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio))
[Freedreno] [PATCH v5 6/8] arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- Changes in v5: - none Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a12..89f30f34ff896 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -959,8 +959,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&gcc GCC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&gcc GCC_MDSS_AHB_CLK>, +<&xo_board>; + clock-names = "iface", "ref"; }; }; -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 8/8] ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHY, it was previously hardcoded in the PLL 'driver' for the 28nm 8960 PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- Changes in v5: - none Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - patch added to the series --- arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 48c3cf4276101..d337ae9326cd8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1338,8 +1338,9 @@ <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk"; - clocks = <&mmcc DSI_M_AHB_CLK>; + clock-names = "iface_clk", "ref"; + clocks = <&mmcc DSI_M_AHB_CLK>, +<&xo_board>; }; -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 7/8] arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 10nm PHY. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd --- based on "[v6] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file" (https://patchwork.kernel.org/patch/10712827/) Changes in v5: - rebased on v6 of DPU DT patch Changes in v4: - added 'Reviewed-by: Stephen Boyd ' tag Changes in v3: - added 'Reviewed-by: Douglas Anderson ' tag Changes in v2: - patch added to the series --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 3e3ffe096f18a..f278f08906d21 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1378,8 +1378,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +<&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; status = "disabled"; }; @@ -1444,8 +1445,9 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, +<&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; status = "disabled"; }; -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v5 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register() instead of storing a point
to the clk object in the PLL data structure
Changes in v4:
- none
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 23 +-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index 71fe60e5f01f1..9a647d93a7e0b 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -40,7 +40,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 1920
#define VCO_MIN_RATE 13UL
#define VCO_MAX_RATE 26UL
@@ -591,7 +590,7 @@ static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw,
unsigned long rate,
parent_rate);
pll_14nm->vco_current_rate = rate;
- pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
+ pll_14nm->vco_ref_clk_rate = parent_rate;
dsi_pll_14nm_input_init(pll_14nm);
@@ -947,11 +946,12 @@ static struct clk_hw *pll_14nm_postdiv_register(struct
dsi_pll_14nm *pll_14nm,
return &pll_postdiv->hw;
}
-static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
+static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm,
+const char *ref_clk_name)
{
char clk_name[32], parent[32], vco_name[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = &ref_clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -1050,6 +1050,8 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
{
struct dsi_pll_14nm *pll_14nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -1065,6 +1067,17 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
pll_14nm->id = id;
pll_14nm_list[id] = pll_14nm;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+ if (IS_ERR(vco_ref_clk)) {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+
pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
dev_err(&pdev->dev, "failed to map CMN PHY base\n");
@@ -1094,7 +1107,7 @@ struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct
platform_device *pdev, int id)
pll->en_seq_cnt = 1;
pll->enable_seqs[0] = dsi_pll_14nm_enable_seq;
- ret = pll_14nm_register(pll_14nm);
+ ret = pll_14nm_register(pll_14nm, vco_ref_clk_name);
if (ret) {
dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
2.20.1.415.g653613c723-goog
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[Freedreno] [PATCH v5 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v5:
- pass the ref clock name to _register() instead of storing a point
to the clk object in the PLL data structure
Changes in v4:
- none
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
- updated commit message
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..adbe5395f4f38 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -625,12 +625,14 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
* state to follow the master PLL's divider/mux state. Therefore, we don't
* require special clock ops that also configure the slave PLL registers
*/
-static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
+static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm,
+const char *ref_clk_name)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
+
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = &ref_clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -771,6 +773,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
{
struct dsi_pll_10nm *pll_10nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -786,6 +790,16 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+ if (IS_ERR(vco_ref_clk)) {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
dev_err(&pdev->dev, "failed to map CMN PHY base\n");
@@ -811,7 +825,7 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct
platform_device *pdev, int id)
pll_10nm->vco_delay = 1;
- ret = pll_10nm_register(pll_10nm);
+ ret = pll_10nm_register(pll_10nm, vco_ref_clk_name);
if (ret) {
dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
2.20.1.415.g653613c723-goog
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[Freedreno] [PATCH v5 0/8] drm/msm/dsi: Get PHY ref clocks from the DT
The MSM DSI PHY drivers currently hardcode the name and the rate of the PHY ref clock. Get the ref clock from the device tree instead. Note: testing of this series was limited to SDM845 and the 10nm PHY Major changes in v5: - none (see per-patch change log for minor changes) Major changes in v4: - always use parent rate for 28nm and 28nm 8960 PHYs Major changes in v3: - keep supporting DTs without ref clock for the 28nm and the 28nm 8960 PHYs - added patch to add ref clock to qcom-apq8064.dtsi Major changes in v2: - apply to all MSM DSI PHY drivers, not only 10nm Matthias Kaehlcke (8): dt-bindings: msm/dsi: Add ref clock for PHYs drm/msm/dsi: 28nm 8960 PHY: Get ref clock from the DT drm/msm/dsi: 28nm PHY: Get ref clock from the DT drm/msm/dsi: 14nm PHY: Get ref clock from the DT drm/msm/dsi: 10nm PHY: Get ref clock from the DT arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs ARM: dts: qcom-apq8064: Set 'xo_board' as ref clock of the DSI PHY .../devicetree/bindings/display/msm/dsi.txt | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 +++--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c| 20 +-- drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c| 23 +--- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c| 36 +-- .../gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 24 ++--- 8 files changed, 92 insertions(+), 32 deletions(-) -- 2.20.1.415.g653613c723-goog ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
On Wed, Dec 19, 2018 at 4:40 PM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Dec 19, 2018 at 12:40 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Wed, Dec 19, 2018 at 12:09 PM Rob Herring wrote:
> > >
> > > On Tue, Dec 18, 2018 at 10:49 PM Viresh Kumar
> > > wrote:
> > > >
> > > > On 18-12-18, 11:05, Doug Anderson wrote:
> > > > > OK, it's fine with me to have the fallback, but if we do we should be
> > > > > consistent about it and make sure it's in all the bindings and device
> > > > > tree files...
> > > >
> > > > Sure.
> > > >
> > > > I am not sure what's the right way to do it is, i.e. should we keep the
> > > > "operating-points-v2" string or not.
> > >
> > > Does having it buy you anything? Given the QCom one doesn't have any
> > > frequency or voltage, I don't see how it would be useful to have it.
> >
> > ...but it does have a frequency, doesn't it?
> >
> > + compatible = "operating-points-v2-qcom-level";
> > +
> > + opp-71000 {
> > + opp-hz = /bits/ 64 <71000>;
> > + qcom,level = ;
> > + };
>
> Ah, I perhaps see the confusion. So Rajendra's usage of
> "operating-points-v2-qcom-level" [1] doesn't have a frequency but
> Jordan's do. So I guess it makes sense that Jordan's have the
> fallback compatible but Rajendra's don't?
Is having it useful to s/w that doesn't understand
"operating-points-v2-qcom-level"? If so, then add
"operating-points-v2". If not, then don't.
I don't really care either way. Just don't do both ways and document
which way is correct.
Rob
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Re: [Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
Hi,
On Wed, Dec 19, 2018 at 12:40 PM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Dec 19, 2018 at 12:09 PM Rob Herring wrote:
> >
> > On Tue, Dec 18, 2018 at 10:49 PM Viresh Kumar
> > wrote:
> > >
> > > On 18-12-18, 11:05, Doug Anderson wrote:
> > > > OK, it's fine with me to have the fallback, but if we do we should be
> > > > consistent about it and make sure it's in all the bindings and device
> > > > tree files...
> > >
> > > Sure.
> > >
> > > I am not sure what's the right way to do it is, i.e. should we keep the
> > > "operating-points-v2" string or not.
> >
> > Does having it buy you anything? Given the QCom one doesn't have any
> > frequency or voltage, I don't see how it would be useful to have it.
>
> ...but it does have a frequency, doesn't it?
>
> + compatible = "operating-points-v2-qcom-level";
> +
> + opp-71000 {
> + opp-hz = /bits/ 64 <71000>;
> + qcom,level = ;
> + };
Ah, I perhaps see the confusion. So Rajendra's usage of
"operating-points-v2-qcom-level" [1] doesn't have a frequency but
Jordan's do. So I guess it makes sense that Jordan's have the
fallback compatible but Rajendra's don't?
[1] https://patchwork.kernel.org/patch/10725793/
-Doug
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Re: [Freedreno] [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
Quoting Matthias Kaehlcke (2018-12-19 14:22:22)
> On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote:
> > Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > > index 71fe60e5f01f1..032bf3e8614bd 100644
> > > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > > @@ -40,7 +40,6 @@
> > >
> > > #define NUM_PROVIDED_CLKS 2
> > >
> > > -#define VCO_REF_CLK_RATE 1920
> > > #define VCO_MIN_RATE 13UL
> > > #define VCO_MAX_RATE 26UL
> > >
> > > @@ -139,6 +138,7 @@ struct dsi_pll_14nm {
> > > /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
> > > spinlock_t postdiv_lock;
> > >
> > > + struct clk *vco_ref_clk;
> >
> > Is there any need to keep it in the struct? Or just get the clk, find
> > the rate, and then put the clk and call pll_14nm_postdiv_register()?
>
> I suppose you mean passing the clock name to pll_14nm_register()?
Yes, whatever makes it possible to avoid storing the pointer in the
struct.
>
> Is putting the clock really needed or preferable, or is it just fine
> to auto-put it when the device is deleted?
Up to you. If you don't have a need for the clk anymore it seems fine to
just put the clk and be done.
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Re: [Freedreno] [PATCH v4 4/8] drm/msm/dsi: 14nm PHY: Get ref clock from the DT
On Mon, Dec 10, 2018 at 07:51:19AM -0800, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2018-12-04 14:42:30)
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > index 71fe60e5f01f1..032bf3e8614bd 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> > @@ -40,7 +40,6 @@
> >
> > #define NUM_PROVIDED_CLKS 2
> >
> > -#define VCO_REF_CLK_RATE 1920
> > #define VCO_MIN_RATE 13UL
> > #define VCO_MAX_RATE 26UL
> >
> > @@ -139,6 +138,7 @@ struct dsi_pll_14nm {
> > /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
> > spinlock_t postdiv_lock;
> >
> > + struct clk *vco_ref_clk;
>
> Is there any need to keep it in the struct? Or just get the clk, find
> the rate, and then put the clk and call pll_14nm_postdiv_register()?
I suppose you mean passing the clock name to pll_14nm_register()?
Is putting the clock really needed or preferable, or is it just fine
to auto-put it when the device is deleted?
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Re: [Freedreno] [PATCH v4 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Hi Niklas,
On Wed, Dec 12, 2018 at 11:07:17PM +0100, Niklas Cassel wrote:
> On Tue, Dec 04, 2018 at 02:42:29PM -0800, Matthias Kaehlcke wrote:
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > Changes in v4:
> > - always use parent rate in dsi_pll_28nm_clk_set_rate() and
> >dsi_pll_28nm_clk_recalc_rate()
> > - pass name of VCO ref clock to pll_28nm_register() instead of
> > storing it in a struct field
> > - updated commit message
> >
> > Changes in v3:
> > - use default name and rate if the ref clock is not specified
> > in the DT
> > - store vco_ref_clk_name instead of vco_ref_clk
> > - dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
> > unsigned long
> > - fixed check for EPROBE_DEFER
> > - renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
> >
> > Changes in v2:
> > - patch added to the series
> > ---
> > drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 36 +++---
> > 1 file changed, 25 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > index 26e3a01a99c2b..340b03e8d 100644
> > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
> > @@ -40,7 +40,6 @@
> >
> > #define NUM_PROVIDED_CLKS 2
> >
> > -#define VCO_REF_CLK_RATE 1920
> > #define VCO_MIN_RATE 35000
> > #define VCO_MAX_RATE 75000
> >
> > @@ -166,17 +165,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw
> > *hw, unsigned long rate,
> > pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
> > pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
> >
> > - rem = rate % VCO_REF_CLK_RATE;
> > + rem = rate % parent_rate;
> > if (rem) {
> > refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> > frac_n_mode = 1;
> > - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
> > - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
> > + div_fbx1000 = rate / (parent_rate / 500);
> > + gen_vco_clk = div_fbx1000 * (parent_rate / 500);
> > } else {
> > refclk_cfg = 0x0;
> > frac_n_mode = 0;
> > - div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
> > - gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
> > + div_fbx1000 = rate / (parent_rate / 1000);
> > + gen_vco_clk = div_fbx1000 * (parent_rate / 1000);
> > }
> >
> > DBG("refclk_cfg = %d", refclk_cfg);
> > @@ -265,7 +264,7 @@ static unsigned long
> > dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> > void __iomem *base = pll_28nm->mmio;
> > u32 sdm0, doubler, sdm_byp_div;
> > u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
> > - u32 ref_clk = VCO_REF_CLK_RATE;
> > + u32 ref_clk = parent_rate;
> > unsigned long vco_rate;
> >
> > VERB("parent_rate=%lu", parent_rate);
> > @@ -273,7 +272,7 @@ static unsigned long
> > dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
> > /* Check to see if the ref clk doubler is enabled */
> > doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
> > DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
> > - ref_clk += (doubler * VCO_REF_CLK_RATE);
> > + ref_clk += (doubler * ref_clk);
> >
> > /* see if it is integer mode or sdm mode */
> > sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
> > @@ -514,11 +513,12 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll
> > *pll)
> > pll_28nm->clk_data.clk_num = 0;
> > }
> >
> > -static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> > +static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm,
> > +const char *ref_clk_name)
> > {
> > char clk_name[32], parent1[32], parent2[32], vco_name[32];
> > struct clk_init_data vco_init = {
> > - .parent_names = (const char *[]){ "xo" },
> > + .parent_names = &ref_clk_name,
> > .num_parents = 1,
> > .name = vco_name,
> > .flags = CLK_IGNORE_UNUSED,
> > @@ -593,6 +593,8 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
> > platform_device *pdev,
> > {
> > struct dsi_pll_28nm *pll_28nm;
> > struct msm_dsi_pll *pll;
> > + struct clk *vco_ref_clk;
> > + const char *vco_ref_clk_name;
> > int ret;
> >
> > if (!pdev)
> > @@ -605,6 +607,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct
> > platform_device *pdev,
> > pll_28nm->pdev = pdev;
> > pll_28nm->id = id;
> >
> > + vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
> > + if (!IS_ERR(vco_ref_clk)) {
> > + vco_ref_clk_name = __clk_get_name(vco_ref_clk);
> > + } else {
> > + ret = PTR_ERR(vco_ref_clk);
> > + if (ret == -EPROBE_DEFER)
> > + ERR_PTR(ret);
>
> It l
Re: [Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
Hi,
On Wed, Dec 19, 2018 at 12:09 PM Rob Herring wrote:
>
> On Tue, Dec 18, 2018 at 10:49 PM Viresh Kumar wrote:
> >
> > On 18-12-18, 11:05, Doug Anderson wrote:
> > > OK, it's fine with me to have the fallback, but if we do we should be
> > > consistent about it and make sure it's in all the bindings and device
> > > tree files...
> >
> > Sure.
> >
> > I am not sure what's the right way to do it is, i.e. should we keep the
> > "operating-points-v2" string or not.
>
> Does having it buy you anything? Given the QCom one doesn't have any
> frequency or voltage, I don't see how it would be useful to have it.
...but it does have a frequency, doesn't it?
+ compatible = "operating-points-v2-qcom-level";
+
+ opp-71000 {
+ opp-hz = /bits/ 64 <71000>;
+ qcom,level = ;
+ };
-Doug
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[Freedreno] [PATCH] drm/msm/gpu: fix bo size for msm_rbmemptrs
memptrs_bo is used to store msm_rbmemptrs. Size it correctly. Signed-off-by: Chia-I Wu --- drivers/gpu/drm/msm/msm_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 11aac8337066..d23049eb29c4 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -917,7 +917,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, goto fail; } - memptrs = msm_gem_kernel_new(drm, sizeof(*gpu->memptrs_bo), + memptrs = msm_gem_kernel_new(drm, sizeof(struct msm_rbmemptrs) * nr_rings, MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo, &memptrs_iova); -- 2.18.1 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
On Tue, Dec 18, 2018 at 10:49 PM Viresh Kumar wrote: > > On 18-12-18, 11:05, Doug Anderson wrote: > > OK, it's fine with me to have the fallback, but if we do we should be > > consistent about it and make sure it's in all the bindings and device > > tree files... > > Sure. > > I am not sure what's the right way to do it is, i.e. should we keep the > "operating-points-v2" string or not. Does having it buy you anything? Given the QCom one doesn't have any frequency or voltage, I don't see how it would be useful to have it. Rob ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] drm/msm: Unblock writer if reader closes file
Prevents deadlock when fifo is full and reader closes file.
Signed-off-by: Kristian H. Kristensen
---
drivers/gpu/drm/msm/msm_rd.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c
index b5672061ae085..d990b5f5154cf 100644
--- a/drivers/gpu/drm/msm/msm_rd.c
+++ b/drivers/gpu/drm/msm/msm_rd.c
@@ -115,7 +115,9 @@ static void rd_write(struct msm_rd_state *rd, const void
*buf, int sz)
char *fptr = &fifo->buf[fifo->head];
int n;
- wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0);
+ wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 ||
!rd->open);
+ if (!rd->open)
+ return;
/* Note that smp_load_acquire() is not strictly required
* as CIRC_SPACE_TO_END() does not access the tail more
@@ -213,7 +215,10 @@ static int rd_open(struct inode *inode, struct file *file)
static int rd_release(struct inode *inode, struct file *file)
{
struct msm_rd_state *rd = inode->i_private;
+
rd->open = false;
+ wake_up_all(&rd->fifo_event);
+
return 0;
}
--
2.20.0.405.gbc1bbc6f85-goog
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Re: [Freedreno] [PATCH v3 3/3] dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845
Hi Sravanthi, Thanks for the patch! On 11/22/18 11:06, Sravanthi Kollukuduru wrote: > Add interconnect properties such as interconnect provider specifier > , the edge source and destination ports which are required by the > interconnect API to configure interconnect path for MDSS. > > Changes in v2: > - none > > Changes in v3: > - Remove common property definitions (Rob Herring) > > Signed-off-by: Sravanthi Kollukuduru > --- > Documentation/devicetree/bindings/display/msm/dpu.txt | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt > b/Documentation/devicetree/bindings/display/msm/dpu.txt > index ad2e8830324e..d75b4360a4be 100644 > --- a/Documentation/devicetree/bindings/display/msm/dpu.txt > +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt > @@ -28,6 +28,11 @@ Required properties: > - #address-cells: number of address cells for the MDSS children. Should be 1. > - #size-cells: Should be 1. > - ranges: parent bus address space is the same as the child bus address > space. > +- interconnects : interconnect path specifier for MDSS according to > + Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be > + 2 paths corresponding to 2 AXI ports. > +- interconnect-names : MDSS will have 2 port names to differentiate between > the > + 2 interconnect paths defined with interconnect specifier. > > Optional properties: > - assigned-clocks: list of clock specifiers for clocks needing rate > assignment > @@ -86,6 +91,10 @@ Example: > interrupt-controller; > #interrupt-cells = <1>; > > + interconnects = <&qnoc 38 &qnoc 512>, > + <&qnoc 39 &qnoc 512>; Please use string names instead of hard-coded integers. interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>, <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>; > + interconnect-names = "port0", "port1"; We are trying to be more descriptive and include both the source and the destination like: "mdp0-mem", "mdp1-mem" > + > iommus = <&apps_iommu 0>; > > #address-cells = <2>; Otherwise looks good. Thanks, Georgi ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v3 2/3] drm/msm/dpu: Integrate interconnect API in MDSS
Hi Sravanthi,
Thanks for the patch!
On 11/22/18 11:06, Sravanthi Kollukuduru wrote:
> The interconnect framework is designed to provide a
> standard kernel interface to control the settings of
> the interconnects on a SoC.
>
> The interconnect API uses a consumer/provider-based model,
> where the providers are the interconnect buses and the
> consumers could be various drivers.
>
> MDSS is one of the interconnect consumers which uses the
> interconnect APIs to get the path between endpoints and
> set its bandwidth/latency/QoS requirements for the given
> interconnected path.
>
> Changes in v2:
> - Remove error log and unnecessary check (Jordan Crouse)
>
> Changes in v3:
> - Code clean involving variable name change, removal
> of extra paranthesis and variables (Matthias Kaehlcke)
>
> Signed-off-by: Sravanthi Kollukuduru
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49
>
> 1 file changed, 44 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> index 38576f8b90b6..1387a6b1b39e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> @@ -4,10 +4,12 @@
> */
>
> #include "dpu_kms.h"
> +#include
>
> #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
>
> -#define HW_INTR_STATUS 0x0010
> +#define HW_INTR_STATUS 0x0010
Unrelated change?
> +#define MAX_BW 680
In what units? Maybe add a comment.
>
> struct dpu_mdss {
> struct msm_mdss base;
> @@ -16,8 +18,30 @@ struct dpu_mdss {
> u32 hwversion;
> struct dss_module_power mp;
> struct dpu_irq_controller irq_controller;
> + struct icc_path *path[2];
> + u32 num_paths;
> };
>
> +static int dpu_mdss_parse_data_bus_icc_path(
> + struct drm_device *dev, struct dpu_mdss *dpu_mdss)
Nit: Lines should not end with a '('. Please move the first argument up:
static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
struct dpu_mdss *dpu_mdss)
> +{
> + struct icc_path *path0 = of_icc_get(dev->dev, "port0");
> + struct icc_path *path1 = of_icc_get(dev->dev, "port1");
In DT it's preferred that the name contains both the source and
destination, so maybe of_icc_get(dev->dev, "mdp0-mem") etc.
> +
> + if (IS_ERR(path0))
> + return PTR_ERR(path0);
> +
> + dpu_mdss->path[0] = path0;
> + dpu_mdss->num_paths = 1;
> +
> + if (!IS_ERR(path1)) {
> + dpu_mdss->path[1] = path1;
> + dpu_mdss->num_paths++;
> + }
> +
> + return 0;
> +}
> +
> static irqreturn_t dpu_mdss_irq(int irq, void *arg)
> {
> struct dpu_mdss *dpu_mdss = arg;
> @@ -127,7 +151,11 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
> {
> struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
> struct dss_module_power *mp = &dpu_mdss->mp;
> - int ret;
> + int ret, i;
> + u64 avg_bw = dpu_mdss->num_paths ? MAX_BW/dpu_mdss->num_paths : 0;
Nit: Please add spaces around "/"
> +
> + for (i = 0; i < dpu_mdss->num_paths; i++)
> + icc_set(dpu_mdss->path[i], avg_bw, MAX_BW);
Now we have macros in the header, that can be used to specify the
bandwidth units. So please use kBps_to_icc or MBps_to_icc etc. If we
decide in the future to change the internal units, we will be able to do
it without touching the users.
Thanks,
Georgi
>
> ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
> if (ret)
> @@ -140,12 +168,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss)
> {
> struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
> struct dss_module_power *mp = &dpu_mdss->mp;
> - int ret;
> + int ret, i;
>
> ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
> if (ret)
> DPU_ERROR("clock disable failed, ret:%d\n", ret);
>
> + for (i = 0; i < dpu_mdss->num_paths; i++)
> + icc_set(dpu_mdss->path[i], 0, 0);
> +
> return ret;
> }
>
> @@ -155,6 +186,7 @@ static void dpu_mdss_destroy(struct drm_device *dev)
> struct msm_drm_private *priv = dev->dev_private;
> struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
> struct dss_module_power *mp = &dpu_mdss->mp;
> + int i;
>
> pm_runtime_disable(dev->dev);
> _dpu_mdss_irq_domain_fini(dpu_mdss);
> @@ -162,6 +194,9 @@ static void dpu_mdss_destroy(struct drm_device *dev)
> msm_dss_put_clk(mp->clk_config, mp->num_clk);
> devm_kfree(&pdev->dev, mp->clk_config);
>
> + for (i = 0; i < dpu_mdss->num_paths; i++)
> + icc_put(dpu_mdss->path[i]);
> +
> if (dpu_mdss->mmio)
> devm_iounmap(&pdev->dev, dpu_mdss->mmio);
> dpu_mdss->mmio = NULL;
> @@ -200,6 +235,10 @@ int dpu_mdss_init(struct drm_device *dev)
> }
> dpu_mdss->mmio_len
