Re: [Freedreno] [PATCH v6 19/24] drm/bridge: dumb-vga-dac: Provide ddc symlink in connector sysfs directory
On Fri, Jul 26, 2019 at 07:23:13PM +0200, Andrzej Pietrasiewicz wrote: > Use the ddc pointer provided by the generic connector. > > Signed-off-by: Andrzej Pietrasiewicz > Reviewed-by: Neil Armstrong This patch results in a crash when running qemu:versatilepb. Unable to handle kernel NULL pointer dereference at virtual address 00c5 pgd = (ptrval) [00c5] *pgd= Internal error: Oops: 5 [#1] ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper Not tainted 5.3.0-rc1+ #1 Hardware name: ARM-Versatile (Device Tree Support) PC is at sysfs_do_create_link_sd+0x38/0xd8 LR is at sysfs_do_create_link_sd+0x38/0xd8 pc : []lr : []psr: a153 sp : c783bd18 ip : fp : c783bde8 r10: c7ef5ea8 r9 : 0001 r8 : c0955dc0 r7 : c73cb5b0 r6 : c73cd800 r5 : 00ad r4 : r3 : c7838ae0 r2 : r1 : 0008 r0 : c0aa2898 Flags: NzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment none Control: 00093177 Table: 4000 DAC: 0053 Process swapper (pid: 1, stack limit = 0x(ptrval)) Stack: (0xc783bd18 to 0xc783c000) bd00: c73ccc48 c73ccc74 bd20: c73cd800 c0ac7c88 c729cc80 c7ef5ea8 c04c7fc0 c73ccc48 c0a73068 bd40: c73cd800 c0ac7c88 c04c87e0 0001 c04cefcc c04dc3f8 bd60: c73a9030 c73cd800 c73ccc48 7fc2ce37 c73cd800 c04cefcc bd80: c73cd800 c04b4ebc c0a73068 c7ef5ea8 c783bde8 c049ffcc bda0: c73a9020 c73cd800 c78e6000 c73a9020 c73a9020 c0a73068 c04df2f8 bdc0: c783bde8 c095a76c c73a9020 c0065744 c73ccc20 c73a9020 0001 bde0: c7838ae0 c73ccc20 7fc2ce37 c78e6000 c0ac7c34 be00: c07dc1f8 c0a6b384 c0a59858 c045e8d8 c78e6000 c1173a78 be20: c0ac7c34 c04e77c4 c78e6000 c0ac7c34 c0ac7c34 c0a73068 be40: e000 c0a6b384 c04e7a34 c0ac7c34 c0ac7c34 c0a73068 c78e6000 be60: c0ac7c34 c0a73068 e000 c0a6b384 c0a59858 c04e7cf0 be80: c0ac7c34 c78e6000 c04e7d7c c0ac7c34 c04e7cf8 c04e5928 bea0: c73b2800 c78d88a0 c78dd110 7fc2ce37 e000 c0ac7c34 c73b2800 c0ac16e0 bec0: c04e6b28 c095a73c c0af0a60 c0a73068 c0ac7c34 c0af0a60 c0a73068 bee0: c0a401c4 c04e8968 e000 c0af0a60 c0a73068 c000b3bc 0115 bf00: c7ffce6c c7ffce00 c09e15b0 0115 0115 c0048844 c09e000c c097cfd4 bf20: 0006 0006 c7ffce6c e000 c006954c bf40: e000 7fc2ce37 c0afb000 c0af0a60 0115 c0afb000 0007 c0a59850 bf60: e000 c0a111e8 0006 0006 c0a10678 7fc2ce37 bf80: c07824cc bfa0: c07824d4 c00090b0 bfc0: bfe0: 0013 [] (sysfs_do_create_link_sd) from [] (drm_connector_register.part.1+0x40/0xa0) [] (drm_connector_register.part.1) from [] (drm_connector_register_all+0x90/0xb8) [] (drm_connector_register_all) from [] (drm_modeset_register_all+0x44/0x6c) [] (drm_modeset_register_all) from [] (drm_dev_register+0x15c/0x1c0) [] (drm_dev_register) from [] (pl111_amba_probe+0x2e0/0x4ac) [] (pl111_amba_probe) from [] (amba_probe+0x9c/0x118) [] (amba_probe) from [] (really_probe+0x1c0/0x2bc) [] (really_probe) from [] (driver_probe_device+0x5c/0x170) [] (driver_probe_device) from [] (device_driver_attach+0x58/0x60) [] (device_driver_attach) from [] (__driver_attach+0x84/0xc0) [] (__driver_attach) from [] (bus_for_each_dev+0x70/0xb4) [] (bus_for_each_dev) from [] (bus_add_driver+0x154/0x1e0) [] (bus_add_driver) from [] (driver_register+0x74/0x108) [] (driver_register) from [] (do_one_initcall+0x84/0x2e4) [] (do_one_initcall) from [] (kernel_init_freeable+0x2bc/0x394) [] (kernel_init_freeable) from [] (kernel_init+0x8/0xf0) [] (kernel_init) from [] (ret_from_fork+0x14/0x24) Exception stack(0xc783bfb0 to 0xc783bff8) bfa0: bfc0: bfe0: 0013 Code: e59f00a0 e1a09003 e1a08002 eb176e54 (e5955018) ---[ end trace f503b374936886c5 ]--- Bisect log attached. Guenter --- # bad: [3880be629e26f6c407593602398c6651860d5fae] Add linux-next specific files for 20190807 # good: [e21a712a9685488f5ce80495b37b9fdbe96c230d] Linux 5.3-rc3 git bisect start 'HEAD' 'v5.3-rc3' # good: [83d74da9e6d2ca78b32e9e794c6bcbd433d5efaa] Merge remote-tracking branch 'crypto/master' git bisect good 83d74da9e6d2ca78b32e9e794c6bcbd433d5efaa # bad: [3add021bff629f1792a5e4268afe13b3047b5523] Merge remote-tracking branch 'sound/for-next' git bisect bad 3add021bff629f1792a5e4268afe13b3047b5523 # good: [4ef58ee18a654b1992d00281501d6eff051a
Re: [PATCH v2] drivers: qcom: Add BCM vote macro to header
Quoting Jordan Crouse (2019-08-05 13:33:46) > The macro to generate a Bus Controller Manager (BCM) TCS command is used > by the interconnect driver but might also be interesting to other > drivers that need to construct TCS commands for sub processors so move > it out of the sdm845 specific file and into the header. > > Signed-off-by: Jordan Crouse > --- Acked-by: Stephen Boyd Unless this is supposed to be applied by me? BTW, I wonder why we need an rpm clk driver much at all nowadays, except maybe for the XO clk state. The big user, from what I can tell, is the interconnect driver and we don't use any of the features of the clk framework besides the API to set a frequency. Maybe it would be better to just push push the bus frequency logic into interconnect code, then XO clk is the only thing we need to keep, and it can be a simple on/off thing.
[Freedreno] [PATCH v3 1/2] iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable format
Add a new sub-format ARM_ADRENO_GPU_LPAE to set up TTBR0 and TTBR1 for
use by the Adreno GPU. This will allow The GPU driver to map global
buffers in the TTBR1 and leave the TTBR0 configured but unset and
free to be changed dynamically by the GPU.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 214 ++---
drivers/iommu/io-pgtable.c | 1 +
include/linux/io-pgtable.h | 2 +
3 files changed, 202 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 161a7d5..8eb0dbb 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -112,13 +112,19 @@
#define ARM_32_LPAE_TCR_EAE(1 << 31)
#define ARM_64_LPAE_S2_TCR_RES1(1 << 31)
+#define ARM_LPAE_TCR_EPD0 (1 << 7)
#define ARM_LPAE_TCR_EPD1 (1 << 23)
#define ARM_LPAE_TCR_TG0_4K(0 << 14)
#define ARM_LPAE_TCR_TG0_64K (1 << 14)
#define ARM_LPAE_TCR_TG0_16K (2 << 14)
+#define ARM_LPAE_TCR_TG1_4K(0 << 30)
+#define ARM_LPAE_TCR_TG1_64K (1 << 30)
+#define ARM_LPAE_TCR_TG1_16K (2 << 30)
+
#define ARM_LPAE_TCR_SH0_SHIFT 12
+#define ARM_LPAE_TCR_SH1_SHIFT 28
#define ARM_LPAE_TCR_SH0_MASK 0x3
#define ARM_LPAE_TCR_SH_NS 0
#define ARM_LPAE_TCR_SH_OS 2
@@ -126,6 +132,8 @@
#define ARM_LPAE_TCR_ORGN0_SHIFT 10
#define ARM_LPAE_TCR_IRGN0_SHIFT 8
+#define ARM_LPAE_TCR_ORGN1_SHIFT 26
+#define ARM_LPAE_TCR_IRGN1_SHIFT 24
#define ARM_LPAE_TCR_RGN_MASK 0x3
#define ARM_LPAE_TCR_RGN_NC0
#define ARM_LPAE_TCR_RGN_WBWA 1
@@ -136,6 +144,7 @@
#define ARM_LPAE_TCR_SL0_MASK 0x3
#define ARM_LPAE_TCR_T0SZ_SHIFT0
+#define ARM_LPAE_TCR_T1SZ_SHIFT16
#define ARM_LPAE_TCR_SZ_MASK 0xf
#define ARM_LPAE_TCR_PS_SHIFT 16
@@ -152,6 +161,14 @@
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
+#define ARM_LPAE_TCR_SEP_SHIFT 47
+#define ARM_LPAE_TCR_SEP_31(0x0ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_35(0x1ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_39(0x2ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_41(0x3ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_43(0x4ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_UPSTREAM (0x7ULL << ARM_LPAE_TCR_SEP_SHIFT)
+
#define ARM_LPAE_MAIR_ATTR_SHIFT(n)((n) << 3)
#define ARM_LPAE_MAIR_ATTR_MASK0xff
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
@@ -426,7 +443,8 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct
arm_lpae_io_pgtable *data,
arm_lpae_iopte pte;
if (data->iop.fmt == ARM_64_LPAE_S1 ||
- data->iop.fmt == ARM_32_LPAE_S1) {
+ data->iop.fmt == ARM_32_LPAE_S1 ||
+ data->iop.fmt == ARM_ADRENO_GPU_LPAE) {
pte = ARM_LPAE_PTE_nG;
if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
pte |= ARM_LPAE_PTE_AP_RDONLY;
@@ -497,6 +515,21 @@ static int arm_lpae_map(struct io_pgtable_ops *ops,
unsigned long iova,
return ret;
}
+static int arm_adreno_gpu_lpae_map(struct io_pgtable_ops *ops,
+ unsigned long iova, phys_addr_t paddr, size_t size,
+ int iommu_prot)
+{
+ struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ unsigned long mask = 1UL << data->iop.cfg.ias;
+
+ /* This configuration expects all iova addresses to be in TTBR1 */
+ if (WARN_ON(iova & mask))
+ return -ERANGE;
+
+ /* Mask off the sign extended bits and map as usual */
+ return arm_lpae_map(ops, iova & (mask - 1), paddr, size, iommu_prot);
+}
+
static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
arm_lpae_iopte *ptep)
{
@@ -643,6 +676,22 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable
*data,
return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
}
+static size_t arm_adreno_gpu_lpae_unmap(struct io_pgtable_ops *ops,
+ unsigned long iova, size_t size)
+{
+ struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ arm_lpae_iopte *ptep = data->pgd;
+ int lvl = ARM_LPAE_START_LVL(data);
+ unsigned long mask = 1UL << data->iop.cfg.ias;
+
+ /* Make sure the sign extend bit is set in the iova */
+ if (WARN_ON(!(iova & mask)))
+ return 0;
+
+ /* Mask off the sign extended bits before unmapping */
+ return __arm_lpae_unmap(data, iova & (mask - 1), size, lvl, ptep);
+}
+
static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
size_t size)
[Freedreno] [PATCH v3 2/2] iommu/arm-smmu: Add support for Adreno GPU pagetable formats
Add support for an Adreno GPU variant of the arm-smmu device to enable
a special pagetable format that enables TTBR1 and leaves TTBR0 free
to be switched by the GPU hardware.
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index aa06498..129ac83 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -124,6 +124,7 @@ enum arm_smmu_implementation {
ARM_MMU500,
CAVIUM_SMMUV2,
QCOM_SMMUV2,
+ ADRENO_SMMUV2,
};
struct arm_smmu_s2cr {
@@ -832,7 +833,10 @@ static int arm_smmu_init_domain_context(struct
iommu_domain *domain,
ias = smmu->va_size;
oas = smmu->ipa_size;
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
- fmt = ARM_64_LPAE_S1;
+ if (smmu->model == ADRENO_SMMUV2)
+ fmt = ARM_ADRENO_GPU_LPAE;
+ else
+ fmt = ARM_64_LPAE_S1;
} else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) {
fmt = ARM_32_LPAE_S1;
ias = min(ias, 32UL);
@@ -2030,6 +2034,7 @@ ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K,
GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2);
+ARM_SMMU_MATCH_DATA(adreno_smmuv2, ARM_SMMU_V2, ADRENO_SMMUV2);
static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
@@ -2039,6 +2044,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
{ .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
+ { .compatible = "qcom,adreno-smmu-v2", .data = &adreno_smmuv2 },
{ },
};
--
2.7.4
___
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Freedreno@lists.freedesktop.org
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[Freedreno] [PATCH v3 0/2] iommu/arm-smmu: Split pagetable support
(Sigh, resend. I freaked out my SMTP server) This is part of an ongoing evolution for enabling split pagetable support for arm-smmu. Previous versions can be found [1]. In the discussion for v2 Robin pointed out that this is a very Adreno specific use case and that is exactly true. Not only do we want to configure and use a pagetable in the TTBR1 space, we also want to configure the TTBR0 region but not allocate a pagetable for it or touch it until the GPU hardware does so. As much as I want it to be a generic concept it really isn't. This revision leans into that idea. Most of the same io-pgtable code is there but now it is wrapped as an Adreno GPU specific format that is selected by the compatible string in the arm-smmu device. Additionally, per Robin's suggestion we are skipping creating a TTBR0 pagetable to save on wasted memory. This isn't as clean as I would like it to be but I think that this is a better direction than trying to pretend that the generic format would work. I'm tempting fate by posting this and then taking some time off, but I wanted to try to kick off a conversation or at least get some flames so I can try to refine this again next week. Please take a look and give some advice on the direction. [1] https://patchwork.freedesktop.org/series/63403/ Jordan Jordan Crouse (2): iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable format iommu/arm-smmu: Add support for Adreno GPU pagetable formats drivers/iommu/arm-smmu.c | 8 +- drivers/iommu/io-pgtable-arm.c | 214 ++--- drivers/iommu/io-pgtable.c | 1 + include/linux/io-pgtable.h | 2 + 4 files changed, 209 insertions(+), 16 deletions(-) -- 2.7.4 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[PATCH v3 0/2] iommu/arm-smmu: Split pagetable support
This is part of an ongoing evolution for enabling split pagetable support for arm-smmu. Previous versions can be found [1]. In the discussion for v2 Robin pointed out that this is a very Adreno specific use case and that is exactly true. Not only do we want to configure and use a pagetable in the TTBR1 space, we also want to configure the TTBR0 region but not allocate a pagetable for it or touch it until the GPU hardware does so. As much as I want it to be a generic concept it really isn't. This revision leans into that idea. Most of the same io-pgtable code is there but now it is wrapped as an Adreno GPU specific format that is selected by the compatible string in the arm-smmu device. Additionally, per Robin's suggestion we are skipping creating a TTBR0 pagetable to save on wasted memory. This isn't as clean as I would like it to be but I think that this is a better direction than trying to pretend that the generic format would work. I'm tempting fate by posting this and then taking some time off, but I wanted to try to kick off a conversation or at least get some flames so I can try to refine this again next week. Please take a look and give some advice on the direction. [1] https://patchwork.freedesktop.org/series/63403/ Jordan Jordan Crouse (2): iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable format iommu/arm-smmu: Add support for Adreno GPU pagetable formats drivers/iommu/arm-smmu.c | 8 +- drivers/iommu/io-pgtable-arm.c | 214 ++--- drivers/iommu/io-pgtable.c | 1 + include/linux/io-pgtable.h | 2 + 4 files changed, 209 insertions(+), 16 deletions(-) -- 2.7.4
[PATCH v3 1/2] iommu/io-pgtable-arm: Add support for ARM_ADRENO_GPU_LPAE io-pgtable format
Add a new sub-format ARM_ADRENO_GPU_LPAE to set up TTBR0 and TTBR1 for
use by the Adreno GPU. This will allow The GPU driver to map global
buffers in the TTBR1 and leave the TTBR0 configured but unset and
free to be changed dynamically by the GPU.
Signed-off-by: Jordan Crouse
---
drivers/iommu/io-pgtable-arm.c | 214 ++---
drivers/iommu/io-pgtable.c | 1 +
include/linux/io-pgtable.h | 2 +
3 files changed, 202 insertions(+), 15 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 161a7d5..8eb0dbb 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -112,13 +112,19 @@
#define ARM_32_LPAE_TCR_EAE(1 << 31)
#define ARM_64_LPAE_S2_TCR_RES1(1 << 31)
+#define ARM_LPAE_TCR_EPD0 (1 << 7)
#define ARM_LPAE_TCR_EPD1 (1 << 23)
#define ARM_LPAE_TCR_TG0_4K(0 << 14)
#define ARM_LPAE_TCR_TG0_64K (1 << 14)
#define ARM_LPAE_TCR_TG0_16K (2 << 14)
+#define ARM_LPAE_TCR_TG1_4K(0 << 30)
+#define ARM_LPAE_TCR_TG1_64K (1 << 30)
+#define ARM_LPAE_TCR_TG1_16K (2 << 30)
+
#define ARM_LPAE_TCR_SH0_SHIFT 12
+#define ARM_LPAE_TCR_SH1_SHIFT 28
#define ARM_LPAE_TCR_SH0_MASK 0x3
#define ARM_LPAE_TCR_SH_NS 0
#define ARM_LPAE_TCR_SH_OS 2
@@ -126,6 +132,8 @@
#define ARM_LPAE_TCR_ORGN0_SHIFT 10
#define ARM_LPAE_TCR_IRGN0_SHIFT 8
+#define ARM_LPAE_TCR_ORGN1_SHIFT 26
+#define ARM_LPAE_TCR_IRGN1_SHIFT 24
#define ARM_LPAE_TCR_RGN_MASK 0x3
#define ARM_LPAE_TCR_RGN_NC0
#define ARM_LPAE_TCR_RGN_WBWA 1
@@ -136,6 +144,7 @@
#define ARM_LPAE_TCR_SL0_MASK 0x3
#define ARM_LPAE_TCR_T0SZ_SHIFT0
+#define ARM_LPAE_TCR_T1SZ_SHIFT16
#define ARM_LPAE_TCR_SZ_MASK 0xf
#define ARM_LPAE_TCR_PS_SHIFT 16
@@ -152,6 +161,14 @@
#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL
+#define ARM_LPAE_TCR_SEP_SHIFT 47
+#define ARM_LPAE_TCR_SEP_31(0x0ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_35(0x1ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_39(0x2ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_41(0x3ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_43(0x4ULL << ARM_LPAE_TCR_SEP_SHIFT)
+#define ARM_LPAE_TCR_SEP_UPSTREAM (0x7ULL << ARM_LPAE_TCR_SEP_SHIFT)
+
#define ARM_LPAE_MAIR_ATTR_SHIFT(n)((n) << 3)
#define ARM_LPAE_MAIR_ATTR_MASK0xff
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
@@ -426,7 +443,8 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct
arm_lpae_io_pgtable *data,
arm_lpae_iopte pte;
if (data->iop.fmt == ARM_64_LPAE_S1 ||
- data->iop.fmt == ARM_32_LPAE_S1) {
+ data->iop.fmt == ARM_32_LPAE_S1 ||
+ data->iop.fmt == ARM_ADRENO_GPU_LPAE) {
pte = ARM_LPAE_PTE_nG;
if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
pte |= ARM_LPAE_PTE_AP_RDONLY;
@@ -497,6 +515,21 @@ static int arm_lpae_map(struct io_pgtable_ops *ops,
unsigned long iova,
return ret;
}
+static int arm_adreno_gpu_lpae_map(struct io_pgtable_ops *ops,
+ unsigned long iova, phys_addr_t paddr, size_t size,
+ int iommu_prot)
+{
+ struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ unsigned long mask = 1UL << data->iop.cfg.ias;
+
+ /* This configuration expects all iova addresses to be in TTBR1 */
+ if (WARN_ON(iova & mask))
+ return -ERANGE;
+
+ /* Mask off the sign extended bits and map as usual */
+ return arm_lpae_map(ops, iova & (mask - 1), paddr, size, iommu_prot);
+}
+
static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
arm_lpae_iopte *ptep)
{
@@ -643,6 +676,22 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable
*data,
return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
}
+static size_t arm_adreno_gpu_lpae_unmap(struct io_pgtable_ops *ops,
+ unsigned long iova, size_t size)
+{
+ struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ arm_lpae_iopte *ptep = data->pgd;
+ int lvl = ARM_LPAE_START_LVL(data);
+ unsigned long mask = 1UL << data->iop.cfg.ias;
+
+ /* Make sure the sign extend bit is set in the iova */
+ if (WARN_ON(!(iova & mask)))
+ return 0;
+
+ /* Mask off the sign extended bits before unmapping */
+ return __arm_lpae_unmap(data, iova & (mask - 1), size, lvl, ptep);
+}
+
static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
size_t size)
Re: [Freedreno] [PATCH] drm/msm: Make DRM_MSM default to 'm'
Hi Jordan/Rob. On Wed, Aug 07, 2019 at 12:46:49PM -0600, Jordan Crouse wrote: > On Wed, Aug 07, 2019 at 11:08:53AM -0700, Rob Clark wrote: > > On Wed, Aug 7, 2019 at 10:38 AM Sam Ravnborg wrote: > > > > > > Hi Jordan. > > > On Wed, Aug 07, 2019 at 11:24:27AM -0600, Jordan Crouse wrote: > > > > Most use cases for DRM_MSM will prefer to build both DRM and MSM_DRM as > > > > modules but there are some cases where DRM might be built in for > > > > whatever > > > > reason and in those situations it is preferable to still keep MSM as a > > > > module by default and let the user decide if they _really_ want to build > > > > it in. > > > > > > > > Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure > > > > it doesn't get missed when we need it for a6xx tarets. > > > > > > > > Signed-off-by: Jordan Crouse > > > > --- > > > > > > > > drivers/gpu/drm/msm/Kconfig | 3 ++- > > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > > > > index 9c37e4d..3b2334b 100644 > > > > --- a/drivers/gpu/drm/msm/Kconfig > > > > +++ b/drivers/gpu/drm/msm/Kconfig > > > > @@ -14,11 +14,12 @@ config DRM_MSM > > > > select SHMEM > > > > select TMPFS > > > > select QCOM_SCM if ARCH_QCOM > > > > + select QCOM_COMMAND_DB if ARCH_QCOM > > > > select WANT_DEV_COREDUMP > > > > select SND_SOC_HDMI_CODEC if SND_SOC > > > > select SYNC_FILE > > > > select PM_OPP > > > > - default y > > > > + default m > > > > > > As a general comment the right thing would be to drop this default. > > > As it is now the Kconfig says that when DRM is selected then all of the > > > world would then also get DRM_MSM, which only a small part of this world > > > you see any benefit in. > > > So they now have to de-select MSM. > > > > If the default is dropped, it should probably be accompanied by adding > > CONFIG_DRM_MSM=m to defconfig's, I think That would be best. So the defconfigs end up with the same config as before. > > In general I prefer to not use a default but this is the only GPU driver for > ARCH_QCOM and I think its safe to stay that 99% of ARCH_QCOM users would > select > this module and those that wouldn't will omit DRM entirely. > > I feel it is net negative if we dropped the default but then had to turn > around > and enable it in every defconfig. "in every" equals three defconfigs: $ git grep ARCH_QCOM | grep defconfig arch/arm/configs/multi_v7_defconfig:CONFIG_ARCH_QCOM=y arch/arm/configs/qcom_defconfig:CONFIG_ARCH_QCOM=y arch/arm64/configs/defconfig:CONFIG_ARCH_QCOM=y Sam ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] drm/msm/dsi: Fix return value check for clk_get_parent
From: Sean Paul
clk_get_parent returns an error pointer upon failure, not NULL. So the
checks as they exist won't catch a failure. This patch changes the
checks and the return values to properly handle an error pointer.
Fixes: c4d8cfe516dc ("drm/msm/dsi: add implementation for helper functions")
Cc: Sibi Sankar
Cc: Sean Paul
Cc: Rob Clark
Cc: # v4.19+
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index aa35d18ab43c9..02acb4338721a 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -421,15 +421,15 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host)
}
msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
- if (!msm_host->byte_clk_src) {
- ret = -ENODEV;
+ if (IS_ERR(msm_host->byte_clk_src)) {
+ ret = PTR_ERR(msm_host->byte_clk_src);
pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__,
ret);
goto exit;
}
msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
- if (!msm_host->pixel_clk_src) {
- ret = -ENODEV;
+ if (IS_ERR(msm_host->pixel_clk_src)) {
+ ret = PTR_ERR(msm_host->pixel_clk_src);
pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__,
ret);
goto exit;
}
--
Sean Paul, Software Engineer, Google / Chromium OS
___
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Re: [Freedreno] [PATCH] drm/msm: Make DRM_MSM default to 'm'
On Wed, Aug 07, 2019 at 11:08:53AM -0700, Rob Clark wrote: > On Wed, Aug 7, 2019 at 10:38 AM Sam Ravnborg wrote: > > > > Hi Jordan. > > On Wed, Aug 07, 2019 at 11:24:27AM -0600, Jordan Crouse wrote: > > > Most use cases for DRM_MSM will prefer to build both DRM and MSM_DRM as > > > modules but there are some cases where DRM might be built in for whatever > > > reason and in those situations it is preferable to still keep MSM as a > > > module by default and let the user decide if they _really_ want to build > > > it in. > > > > > > Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure > > > it doesn't get missed when we need it for a6xx tarets. > > > > > > Signed-off-by: Jordan Crouse > > > --- > > > > > > drivers/gpu/drm/msm/Kconfig | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > > > index 9c37e4d..3b2334b 100644 > > > --- a/drivers/gpu/drm/msm/Kconfig > > > +++ b/drivers/gpu/drm/msm/Kconfig > > > @@ -14,11 +14,12 @@ config DRM_MSM > > > select SHMEM > > > select TMPFS > > > select QCOM_SCM if ARCH_QCOM > > > + select QCOM_COMMAND_DB if ARCH_QCOM > > > select WANT_DEV_COREDUMP > > > select SND_SOC_HDMI_CODEC if SND_SOC > > > select SYNC_FILE > > > select PM_OPP > > > - default y > > > + default m > > > > As a general comment the right thing would be to drop this default. > > As it is now the Kconfig says that when DRM is selected then all of the > > world would then also get DRM_MSM, which only a small part of this world > > you see any benefit in. > > So they now have to de-select MSM. > > If the default is dropped, it should probably be accompanied by adding > CONFIG_DRM_MSM=m to defconfig's, I think In general I prefer to not use a default but this is the only GPU driver for ARCH_QCOM and I think its safe to stay that 99% of ARCH_QCOM users would select this module and those that wouldn't will omit DRM entirely. I feel it is net negative if we dropped the default but then had to turn around and enable it in every defconfig. Jordan > BR, > -R > > > Kconfig has: > > depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST) > > > > So maybe not all of the world but all QCOM or IMX5 users. Maybe they are all > > interested in MSM. Otherwise the default should rather be dropped. > > If there is any good hints then the help text could anyway use some > > love, and then add the info there. > > > > The other change with QCOM_COMMAND_DB seems on the other hand to make > > sense but then this is another patch. > > > > Sam > > ___ > > Freedreno mailing list > > Freedreno@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH] drm/msm: Make DRM_MSM default to 'm'
On Wed, Aug 7, 2019 at 10:38 AM Sam Ravnborg wrote: > > Hi Jordan. > On Wed, Aug 07, 2019 at 11:24:27AM -0600, Jordan Crouse wrote: > > Most use cases for DRM_MSM will prefer to build both DRM and MSM_DRM as > > modules but there are some cases where DRM might be built in for whatever > > reason and in those situations it is preferable to still keep MSM as a > > module by default and let the user decide if they _really_ want to build > > it in. > > > > Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure > > it doesn't get missed when we need it for a6xx tarets. > > > > Signed-off-by: Jordan Crouse > > --- > > > > drivers/gpu/drm/msm/Kconfig | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > > index 9c37e4d..3b2334b 100644 > > --- a/drivers/gpu/drm/msm/Kconfig > > +++ b/drivers/gpu/drm/msm/Kconfig > > @@ -14,11 +14,12 @@ config DRM_MSM > > select SHMEM > > select TMPFS > > select QCOM_SCM if ARCH_QCOM > > + select QCOM_COMMAND_DB if ARCH_QCOM > > select WANT_DEV_COREDUMP > > select SND_SOC_HDMI_CODEC if SND_SOC > > select SYNC_FILE > > select PM_OPP > > - default y > > + default m > > As a general comment the right thing would be to drop this default. > As it is now the Kconfig says that when DRM is selected then all of the > world would then also get DRM_MSM, which only a small part of this world > you see any benefit in. > So they now have to de-select MSM. If the default is dropped, it should probably be accompanied by adding CONFIG_DRM_MSM=m to defconfig's, I think BR, -R > Kconfig has: > depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST) > > So maybe not all of the world but all QCOM or IMX5 users. Maybe they are all > interested in MSM. Otherwise the default should rather be dropped. > If there is any good hints then the help text could anyway use some > love, and then add the info there. > > The other change with QCOM_COMMAND_DB seems on the other hand to make > sense but then this is another patch. > > Sam > ___ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] next/master boot: 263 boots: 11 failed, 186 passed with 64 offline, 1 untried/unknown, 1 conflict (next-20190802)
On Fri, Aug 02, 2019 at 05:13:30AM -0700, kernelci.org bot wrote: Today's -next still fails to boot on CM-QS600 with qcom_defconfig: > qcom_defconfig: > gcc-8: > qcom-apq8064-cm-qs600: 1 failed lab This has been going on since June. It crashes initializing the GPU: [4.261135] adreno 430.adreno-3xx: 430.adreno-3xx supply vddcx not found, using dummy regulator [4.270254] msm 510.mdp: [drm:msm_gpu_init] A320: using IOMMU [4.280025] 8<--- cut here --- [4.285557] Unable to handle kernel paging request at virtual address 4000 [4.288430] pgd = (ptrval) [4.295714] [4000] *pgd= [4.298329] Internal error: Oops: 805 [#1] PREEMPT SMP ARM [4.302054] Modules linked in: [4.307352] CPU: 2 PID: 88 Comm: kworker/2:1 Tainted: GW 5.3.0-rc3-next-20190807 #1 [4.310391] Hardware name: Generic DT based system [4.319353] Workqueue: events deferred_probe_work_func [4.319930] usb 1-1: New USB device found, idVendor=04b4, idProduct=6570, bcdDevice=32.99 [4.324201] PC is at v7_dma_clean_range+0x1c/0x34 [4.324214] LR is at __dma_page_cpu_to_dev+0x28/0x8c ... [4.753642] [] (v7_dma_clean_range) from [] (__dma_page_cpu_to_dev+0x28/0x8c) [4.761795] [] (__dma_page_cpu_to_dev) from [] (arm_dma_sync_sg_for_device+0x4c/0x64) [4.770654] [] (arm_dma_sync_sg_for_device) from [] (get_pages+0x1bc/0x218) [4.780199] [] (get_pages) from [] (msm_gem_get_and_pin_iova+0xb4/0x13c) [4.788704] [] (msm_gem_get_and_pin_iova) from [] (_msm_gem_kernel_new+0x38/0xa8) [4.797386] [] (_msm_gem_kernel_new) from [] (msm_gem_kernel_new+0x24/0x2c) [4.806501] [] (msm_gem_kernel_new) from [] (msm_gpu_init+0x4a4/0x614) [4.815021] [] (msm_gpu_init) from [] (adreno_gpu_init+0x17c/0x288) [4.823342] [] (adreno_gpu_init) from [] (a3xx_gpu_init+0x84/0x108) [4.831239] [] (a3xx_gpu_init) from [] (adreno_bind+0x1c4/0x268) [4.839224] [] (adreno_bind) from [] (component_bind_all+0x11c/0x258) [4.847213] [] (component_bind_all) from [] (msm_drm_bind+0xf8/0x638) [4.855282] [] (msm_drm_bind) from [] (try_to_bring_up_master+0x1fc/0x2b8) More details including full logs and the image file at: https://kernelci.org/boot/id/5d4ac1e659b514754b31b293/ signature.asc Description: PGP signature ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH] drm/msm: Make DRM_MSM default to 'm'
Hi Jordan. On Wed, Aug 07, 2019 at 11:24:27AM -0600, Jordan Crouse wrote: > Most use cases for DRM_MSM will prefer to build both DRM and MSM_DRM as > modules but there are some cases where DRM might be built in for whatever > reason and in those situations it is preferable to still keep MSM as a > module by default and let the user decide if they _really_ want to build > it in. > > Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure > it doesn't get missed when we need it for a6xx tarets. > > Signed-off-by: Jordan Crouse > --- > > drivers/gpu/drm/msm/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > index 9c37e4d..3b2334b 100644 > --- a/drivers/gpu/drm/msm/Kconfig > +++ b/drivers/gpu/drm/msm/Kconfig > @@ -14,11 +14,12 @@ config DRM_MSM > select SHMEM > select TMPFS > select QCOM_SCM if ARCH_QCOM > + select QCOM_COMMAND_DB if ARCH_QCOM > select WANT_DEV_COREDUMP > select SND_SOC_HDMI_CODEC if SND_SOC > select SYNC_FILE > select PM_OPP > - default y > + default m As a general comment the right thing would be to drop this default. As it is now the Kconfig says that when DRM is selected then all of the world would then also get DRM_MSM, which only a small part of this world you see any benefit in. So they now have to de-select MSM. Kconfig has: depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST) So maybe not all of the world but all QCOM or IMX5 users. Maybe they are all interested in MSM. Otherwise the default should rather be dropped. If there is any good hints then the help text could anyway use some love, and then add the info there. The other change with QCOM_COMMAND_DB seems on the other hand to make sense but then this is another patch. Sam ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] drm/msm: Make DRM_MSM default to 'm'
Most use cases for DRM_MSM will prefer to build both DRM and MSM_DRM as modules but there are some cases where DRM might be built in for whatever reason and in those situations it is preferable to still keep MSM as a module by default and let the user decide if they _really_ want to build it in. Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure it doesn't get missed when we need it for a6xx tarets. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 9c37e4d..3b2334b 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -14,11 +14,12 @@ config DRM_MSM select SHMEM select TMPFS select QCOM_SCM if ARCH_QCOM + select QCOM_COMMAND_DB if ARCH_QCOM select WANT_DEV_COREDUMP select SND_SOC_HDMI_CODEC if SND_SOC select SYNC_FILE select PM_OPP - default y + default m help DRM/KMS driver for MSM/snapdragon. -- 2.7.4 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
