[Freedreno] [PATCH AUTOSEL 4.9 05/13] drm: msm: Fix return type of dsi_mgr_connector_mode_valid for kCFI

2020-03-02 Thread Sasha Levin 
From: John Stultz 

[ Upstream commit 7fd2dfc3694922eb7ace4801b7208cf9f62ebc7d ]

I was hitting kCFI crashes when building with clang, and after
some digging finally narrowed it down to the
dsi_mgr_connector_mode_valid() function being implemented as
returning an int, instead of an enum drm_mode_status.

This patch fixes it, and appeases the opaque word of the kCFI
gods (seriously, clang inlining everything makes the kCFI
backtraces only really rough estimates of where things went
wrong).

Thanks as always to Sami for his help narrowing this down.

Cc: Rob Clark 
Cc: Sean Paul 
Cc: Sami Tolvanen 
Cc: Todd Kjos 
Cc: Alistair Delva 
Cc: Amit Pundir 
Cc: Sumit Semwal 
Cc: freedreno@lists.freedesktop.org
Cc: clang-built-li...@googlegroups.com
Signed-off-by: John Stultz 
Reviewed-by: Nick Desaulniers 
Tested-by: Amit Pundir 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index c8d1f19c9a6d9..10d49d43c17eb 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -306,7 +306,7 @@ static int dsi_mgr_connector_get_modes(struct drm_connector 
*connector)
return num;
 }
 
-static int dsi_mgr_connector_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector 
*connector,
struct drm_display_mode *mode)
 {
int id = dsi_mgr_connector_get_id(connector);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.9 06/13] drm/msm/dsi: save pll state before dsi host is powered off

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit a1028dcfd0dd97884072288d0c8ed7f30399b528 ]

Save pll state before dsi host is powered off. Without this change
some register values gets resetted.

Signed-off-by: Harigovindan P 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 10d49d43c17eb..d46b9e75a8473 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -438,6 +438,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
struct mipi_dsi_host *host = msm_dsi->host;
struct drm_panel *panel = msm_dsi->panel;
+   struct msm_dsi_pll *src_pll;
bool is_dual_dsi = IS_DUAL_DSI();
int ret;
 
@@ -471,6 +472,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
id, ret);
}
 
+   /* Save PLL status if it is a clock source */
+   src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
+   msm_dsi_pll_save_state(src_pll);
+
ret = msm_dsi_host_power_off(host);
if (ret)
pr_err("%s: host %d power off failed,%d\n", __func__, id, ret);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.4 05/11] drm/msm/dsi: save pll state before dsi host is powered off

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit a1028dcfd0dd97884072288d0c8ed7f30399b528 ]

Save pll state before dsi host is powered off. Without this change
some register values gets resetted.

Signed-off-by: Harigovindan P 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 439dfb69e2ef8..34220df1265f5 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -434,6 +434,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
struct mipi_dsi_host *host = msm_dsi->host;
struct drm_panel *panel = msm_dsi->panel;
+   struct msm_dsi_pll *src_pll;
bool is_dual_dsi = IS_DUAL_DSI();
int ret;
 
@@ -467,6 +468,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
id, ret);
}
 
+   /* Save PLL status if it is a clock source */
+   src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
+   msm_dsi_pll_save_state(src_pll);
+
ret = msm_dsi_host_power_off(host);
if (ret)
pr_err("%s: host %d power off failed,%d\n", __func__, id, ret);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.4 04/11] drm: msm: Fix return type of dsi_mgr_connector_mode_valid for kCFI

2020-03-02 Thread Sasha Levin 
From: John Stultz 

[ Upstream commit 7fd2dfc3694922eb7ace4801b7208cf9f62ebc7d ]

I was hitting kCFI crashes when building with clang, and after
some digging finally narrowed it down to the
dsi_mgr_connector_mode_valid() function being implemented as
returning an int, instead of an enum drm_mode_status.

This patch fixes it, and appeases the opaque word of the kCFI
gods (seriously, clang inlining everything makes the kCFI
backtraces only really rough estimates of where things went
wrong).

Thanks as always to Sami for his help narrowing this down.

Cc: Rob Clark 
Cc: Sean Paul 
Cc: Sami Tolvanen 
Cc: Todd Kjos 
Cc: Alistair Delva 
Cc: Amit Pundir 
Cc: Sumit Semwal 
Cc: freedreno@lists.freedesktop.org
Cc: clang-built-li...@googlegroups.com
Signed-off-by: John Stultz 
Reviewed-by: Nick Desaulniers 
Tested-by: Amit Pundir 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 0455ff75074ad..439dfb69e2ef8 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -302,7 +302,7 @@ static int dsi_mgr_connector_get_modes(struct drm_connector 
*connector)
return num;
 }
 
-static int dsi_mgr_connector_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector 
*connector,
struct drm_display_mode *mode)
 {
int id = dsi_mgr_connector_get_id(connector);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.19 11/32] drm/msm/dsi: save pll state before dsi host is powered off

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit a1028dcfd0dd97884072288d0c8ed7f30399b528 ]

Save pll state before dsi host is powered off. Without this change
some register values gets resetted.

Signed-off-by: Harigovindan P 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index bd66d2aac41f7..b01762a7778ae 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -471,6 +471,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
struct mipi_dsi_host *host = msm_dsi->host;
struct drm_panel *panel = msm_dsi->panel;
+   struct msm_dsi_pll *src_pll;
bool is_dual_dsi = IS_DUAL_DSI();
int ret;
 
@@ -511,6 +512,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
id, ret);
}
 
+   /* Save PLL status if it is a clock source */
+   src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
+   msm_dsi_pll_save_state(src_pll);
+
ret = msm_dsi_host_power_off(host);
if (ret)
pr_err("%s: host %d power off failed,%d\n", __func__, id, ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 9a9fa0c75a131..c630871de7c5b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -726,10 +726,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
if (!phy || !phy->cfg->ops.disable)
return;
 
-   /* Save PLL status if it is a clock source */
-   if (phy->usecase != MSM_DSI_PHY_SLAVE)
-   msm_dsi_pll_save_state(phy->pll);
-
phy->cfg->ops.disable(phy);
 
dsi_phy_regulator_disable(phy);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.14 08/22] drm: msm: Fix return type of dsi_mgr_connector_mode_valid for kCFI

2020-03-02 Thread Sasha Levin 
From: John Stultz 

[ Upstream commit 7fd2dfc3694922eb7ace4801b7208cf9f62ebc7d ]

I was hitting kCFI crashes when building with clang, and after
some digging finally narrowed it down to the
dsi_mgr_connector_mode_valid() function being implemented as
returning an int, instead of an enum drm_mode_status.

This patch fixes it, and appeases the opaque word of the kCFI
gods (seriously, clang inlining everything makes the kCFI
backtraces only really rough estimates of where things went
wrong).

Thanks as always to Sami for his help narrowing this down.

Cc: Rob Clark 
Cc: Sean Paul 
Cc: Sami Tolvanen 
Cc: Todd Kjos 
Cc: Alistair Delva 
Cc: Amit Pundir 
Cc: Sumit Semwal 
Cc: freedreno@lists.freedesktop.org
Cc: clang-built-li...@googlegroups.com
Signed-off-by: John Stultz 
Reviewed-by: Nick Desaulniers 
Tested-by: Amit Pundir 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 855248132b2bd..7d46399a39b4d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -400,7 +400,7 @@ static int dsi_mgr_connector_get_modes(struct drm_connector 
*connector)
return num;
 }
 
-static int dsi_mgr_connector_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector 
*connector,
struct drm_display_mode *mode)
 {
int id = dsi_mgr_connector_get_id(connector);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.14 09/22] drm/msm/dsi: save pll state before dsi host is powered off

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit a1028dcfd0dd97884072288d0c8ed7f30399b528 ]

Save pll state before dsi host is powered off. Without this change
some register values gets resetted.

Signed-off-by: Harigovindan P 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 7d46399a39b4d..9fbfa9f94e6ce 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -543,6 +543,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
struct mipi_dsi_host *host = msm_dsi->host;
struct drm_panel *panel = msm_dsi->panel;
+   struct msm_dsi_pll *src_pll;
bool is_dual_dsi = IS_DUAL_DSI();
int ret;
 
@@ -583,6 +584,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
id, ret);
}
 
+   /* Save PLL status if it is a clock source */
+   src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
+   msm_dsi_pll_save_state(src_pll);
+
ret = msm_dsi_host_power_off(host);
if (ret)
pr_err("%s: host %d power off failed,%d\n", __func__, id, ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 7c9bf91bc22b6..c0a7fa56d9a74 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -613,10 +613,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
if (!phy || !phy->cfg->ops.disable)
return;
 
-   /* Save PLL status if it is a clock source */
-   if (phy->usecase != MSM_DSI_PHY_SLAVE)
-   msm_dsi_pll_save_state(phy->pll);
-
phy->cfg->ops.disable(phy);
 
dsi_phy_regulator_disable(phy);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.14 07/22] drm/msm/mdp5: rate limit pp done timeout warnings

2020-03-02 Thread Sasha Levin 
From: Brian Masney 

[ Upstream commit ef8c9809acb0805c991bba8bdd4749fc46d44a98 ]

Add rate limiting of the 'pp done time out' warnings since these
warnings can quickly fill the dmesg buffer.

Signed-off-by: Brian Masney 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 4409776770012..99d356b6e9151 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -1004,8 +1004,8 @@ static void mdp5_crtc_wait_for_pp_done(struct drm_crtc 
*crtc)
ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
msecs_to_jiffies(50));
if (ret == 0)
-   dev_warn(dev->dev, "pp done time out, lm=%d\n",
-mdp5_cstate->pipeline.mixer->lm);
+   dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
+mdp5_cstate->pipeline.mixer->lm);
 }
 
 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.19 12/32] drm/msm/dsi/pll: call vco set rate explicitly

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit c6659785dfb3f8d75f1fe637e4222ff8178f5280 ]

For a given byte clock, if VCO recalc value is exactly same as
vco set rate value, vco_set_rate does not get called assuming
VCO is already set to required value. But Due to GDSC toggle,
VCO values are erased in the HW. To make sure VCO is programmed
correctly, we forcefully call set_rate from vco_prepare.

Signed-off-by: Harigovindan P 
Reviewed-by: Jeffrey Hugo 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 31205625c7346..21a69b046625a 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -406,6 +406,12 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
if (pll_10nm->slave)
dsi_pll_enable_pll_bias(pll_10nm->slave);
 
+   rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
+   if (rc) {
+   pr_err("vco_set_rate failed, rc=%d\n", rc);
+   return rc;
+   }
+
/* Start PLL */
pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
  0x01);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.19 09/32] drm: msm: Fix return type of dsi_mgr_connector_mode_valid for kCFI

2020-03-02 Thread Sasha Levin 
From: John Stultz 

[ Upstream commit 7fd2dfc3694922eb7ace4801b7208cf9f62ebc7d ]

I was hitting kCFI crashes when building with clang, and after
some digging finally narrowed it down to the
dsi_mgr_connector_mode_valid() function being implemented as
returning an int, instead of an enum drm_mode_status.

This patch fixes it, and appeases the opaque word of the kCFI
gods (seriously, clang inlining everything makes the kCFI
backtraces only really rough estimates of where things went
wrong).

Thanks as always to Sami for his help narrowing this down.

Cc: Rob Clark 
Cc: Sean Paul 
Cc: Sami Tolvanen 
Cc: Todd Kjos 
Cc: Alistair Delva 
Cc: Amit Pundir 
Cc: Sumit Semwal 
Cc: freedreno@lists.freedesktop.org
Cc: clang-built-li...@googlegroups.com
Signed-off-by: John Stultz 
Reviewed-by: Nick Desaulniers 
Tested-by: Amit Pundir 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 5224010d90e4a..bd66d2aac41f7 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -328,7 +328,7 @@ static int dsi_mgr_connector_get_modes(struct drm_connector 
*connector)
return num;
 }
 
-static int dsi_mgr_connector_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector 
*connector,
struct drm_display_mode *mode)
 {
int id = dsi_mgr_connector_get_id(connector);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 4.19 08/32] drm/msm/mdp5: rate limit pp done timeout warnings

2020-03-02 Thread Sasha Levin 
From: Brian Masney 

[ Upstream commit ef8c9809acb0805c991bba8bdd4749fc46d44a98 ]

Add rate limiting of the 'pp done time out' warnings since these
warnings can quickly fill the dmesg buffer.

Signed-off-by: Brian Masney 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index b1da9ce543790..aa28a43ff842c 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1118,8 +1118,8 @@ static void mdp5_crtc_wait_for_pp_done(struct drm_crtc 
*crtc)
ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
msecs_to_jiffies(50));
if (ret == 0)
-   dev_warn(dev->dev, "pp done time out, lm=%d\n",
-mdp5_cstate->pipeline.mixer->lm);
+   dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
+mdp5_cstate->pipeline.mixer->lm);
 }
 
 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.4 12/58] drm: msm: Fix return type of dsi_mgr_connector_mode_valid for kCFI

2020-03-02 Thread Sasha Levin 
From: John Stultz 

[ Upstream commit 7fd2dfc3694922eb7ace4801b7208cf9f62ebc7d ]

I was hitting kCFI crashes when building with clang, and after
some digging finally narrowed it down to the
dsi_mgr_connector_mode_valid() function being implemented as
returning an int, instead of an enum drm_mode_status.

This patch fixes it, and appeases the opaque word of the kCFI
gods (seriously, clang inlining everything makes the kCFI
backtraces only really rough estimates of where things went
wrong).

Thanks as always to Sami for his help narrowing this down.

Cc: Rob Clark 
Cc: Sean Paul 
Cc: Sami Tolvanen 
Cc: Todd Kjos 
Cc: Alistair Delva 
Cc: Amit Pundir 
Cc: Sumit Semwal 
Cc: freedreno@lists.freedesktop.org
Cc: clang-built-li...@googlegroups.com
Signed-off-by: John Stultz 
Reviewed-by: Nick Desaulniers 
Tested-by: Amit Pundir 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 271aa7bbca925..355a60b4a536f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -336,7 +336,7 @@ static int dsi_mgr_connector_get_modes(struct drm_connector 
*connector)
return num;
 }
 
-static int dsi_mgr_connector_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector 
*connector,
struct drm_display_mode *mode)
 {
int id = dsi_mgr_connector_get_id(connector);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.4 16/58] drm/msm/dsi: save pll state before dsi host is powered off

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit a1028dcfd0dd97884072288d0c8ed7f30399b528 ]

Save pll state before dsi host is powered off. Without this change
some register values gets resetted.

Signed-off-by: Harigovindan P 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 355a60b4a536f..73127948f54d9 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -479,6 +479,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
struct mipi_dsi_host *host = msm_dsi->host;
struct drm_panel *panel = msm_dsi->panel;
+   struct msm_dsi_pll *src_pll;
bool is_dual_dsi = IS_DUAL_DSI();
int ret;
 
@@ -519,6 +520,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
id, ret);
}
 
+   /* Save PLL status if it is a clock source */
+   src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
+   msm_dsi_pll_save_state(src_pll);
+
ret = msm_dsi_host_power_off(host);
if (ret)
pr_err("%s: host %d power off failed,%d\n", __func__, id, ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 3522863a4984f..21519229fe73a 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -724,10 +724,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
if (!phy || !phy->cfg->ops.disable)
return;
 
-   /* Save PLL status if it is a clock source */
-   if (phy->usecase != MSM_DSI_PHY_SLAVE)
-   msm_dsi_pll_save_state(phy->pll);
-
phy->cfg->ops.disable(phy);
 
dsi_phy_regulator_disable(phy);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.4 11/58] drm/msm/mdp5: rate limit pp done timeout warnings

2020-03-02 Thread Sasha Levin 
From: Brian Masney 

[ Upstream commit ef8c9809acb0805c991bba8bdd4749fc46d44a98 ]

Add rate limiting of the 'pp done time out' warnings since these
warnings can quickly fill the dmesg buffer.

Signed-off-by: Brian Masney 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index eb0b4b7dc7cc7..03c6d6157e4d0 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1112,8 +1112,8 @@ static void mdp5_crtc_wait_for_pp_done(struct drm_crtc 
*crtc)
ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
msecs_to_jiffies(50));
if (ret == 0)
-   dev_warn(dev->dev, "pp done time out, lm=%d\n",
-mdp5_cstate->pipeline.mixer->lm);
+   dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
+mdp5_cstate->pipeline.mixer->lm);
 }
 
 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.4 17/58] drm/msm/dsi/pll: call vco set rate explicitly

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit c6659785dfb3f8d75f1fe637e4222ff8178f5280 ]

For a given byte clock, if VCO recalc value is exactly same as
vco set rate value, vco_set_rate does not get called assuming
VCO is already set to required value. But Due to GDSC toggle,
VCO values are erased in the HW. To make sure VCO is programmed
correctly, we forcefully call set_rate from vco_prepare.

Signed-off-by: Harigovindan P 
Reviewed-by: Jeffrey Hugo 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 8f6100db90ed4..aa9385d5bfff9 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -411,6 +411,12 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
if (pll_10nm->slave)
dsi_pll_enable_pll_bias(pll_10nm->slave);
 
+   rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
+   if (rc) {
+   pr_err("vco_set_rate failed, rc=%d\n", rc);
+   return rc;
+   }
+
/* Start PLL */
pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
  0x01);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.5 12/66] drm/msm/mdp5: rate limit pp done timeout warnings

2020-03-02 Thread Sasha Levin 
From: Brian Masney 

[ Upstream commit ef8c9809acb0805c991bba8bdd4749fc46d44a98 ]

Add rate limiting of the 'pp done time out' warnings since these
warnings can quickly fill the dmesg buffer.

Signed-off-by: Brian Masney 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 05cc04f729d63..e1cc541e0ef2e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1109,8 +1109,8 @@ static void mdp5_crtc_wait_for_pp_done(struct drm_crtc 
*crtc)
ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
msecs_to_jiffies(50));
if (ret == 0)
-   dev_warn(dev->dev, "pp done time out, lm=%d\n",
-mdp5_cstate->pipeline.mixer->lm);
+   dev_warn_ratelimited(dev->dev, "pp done time out, lm=%d\n",
+mdp5_cstate->pipeline.mixer->lm);
 }
 
 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.5 13/66] drm: msm: Fix return type of dsi_mgr_connector_mode_valid for kCFI

2020-03-02 Thread Sasha Levin 
From: John Stultz 

[ Upstream commit 7fd2dfc3694922eb7ace4801b7208cf9f62ebc7d ]

I was hitting kCFI crashes when building with clang, and after
some digging finally narrowed it down to the
dsi_mgr_connector_mode_valid() function being implemented as
returning an int, instead of an enum drm_mode_status.

This patch fixes it, and appeases the opaque word of the kCFI
gods (seriously, clang inlining everything makes the kCFI
backtraces only really rough estimates of where things went
wrong).

Thanks as always to Sami for his help narrowing this down.

Cc: Rob Clark 
Cc: Sean Paul 
Cc: Sami Tolvanen 
Cc: Todd Kjos 
Cc: Alistair Delva 
Cc: Amit Pundir 
Cc: Sumit Semwal 
Cc: freedreno@lists.freedesktop.org
Cc: clang-built-li...@googlegroups.com
Signed-off-by: John Stultz 
Reviewed-by: Nick Desaulniers 
Tested-by: Amit Pundir 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 271aa7bbca925..355a60b4a536f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -336,7 +336,7 @@ static int dsi_mgr_connector_get_modes(struct drm_connector 
*connector)
return num;
 }
 
-static int dsi_mgr_connector_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector 
*connector,
struct drm_display_mode *mode)
 {
int id = dsi_mgr_connector_get_id(connector);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.5 18/66] drm/msm/dsi/pll: call vco set rate explicitly

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit c6659785dfb3f8d75f1fe637e4222ff8178f5280 ]

For a given byte clock, if VCO recalc value is exactly same as
vco set rate value, vco_set_rate does not get called assuming
VCO is already set to required value. But Due to GDSC toggle,
VCO values are erased in the HW. To make sure VCO is programmed
correctly, we forcefully call set_rate from vco_prepare.

Signed-off-by: Harigovindan P 
Reviewed-by: Jeffrey Hugo 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 8f6100db90ed4..aa9385d5bfff9 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -411,6 +411,12 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
if (pll_10nm->slave)
dsi_pll_enable_pll_bias(pll_10nm->slave);
 
+   rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
+   if (rc) {
+   pr_err("vco_set_rate failed, rc=%d\n", rc);
+   return rc;
+   }
+
/* Start PLL */
pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
  0x01);
-- 
2.20.1

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[Freedreno] [PATCH AUTOSEL 5.5 17/66] drm/msm/dsi: save pll state before dsi host is powered off

2020-03-02 Thread Sasha Levin 
From: Harigovindan P 

[ Upstream commit a1028dcfd0dd97884072288d0c8ed7f30399b528 ]

Save pll state before dsi host is powered off. Without this change
some register values gets resetted.

Signed-off-by: Harigovindan P 
Signed-off-by: Rob Clark 
Signed-off-by: Sasha Levin 
---
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 355a60b4a536f..73127948f54d9 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -479,6 +479,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
struct mipi_dsi_host *host = msm_dsi->host;
struct drm_panel *panel = msm_dsi->panel;
+   struct msm_dsi_pll *src_pll;
bool is_dual_dsi = IS_DUAL_DSI();
int ret;
 
@@ -519,6 +520,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge 
*bridge)
id, ret);
}
 
+   /* Save PLL status if it is a clock source */
+   src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
+   msm_dsi_pll_save_state(src_pll);
+
ret = msm_dsi_host_power_off(host);
if (ret)
pr_err("%s: host %d power off failed,%d\n", __func__, id, ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index b0cfa67d2a578..f509ebd77500f 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -724,10 +724,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
if (!phy || !phy->cfg->ops.disable)
return;
 
-   /* Save PLL status if it is a clock source */
-   if (phy->usecase != MSM_DSI_PHY_SLAVE)
-   msm_dsi_pll_save_state(phy->pll);
-
phy->cfg->ops.disable(phy);
 
dsi_phy_regulator_disable(phy);
-- 
2.20.1

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Re: [Freedreno] [PATCH v4 1/2] dt-bindings: display: msm: Convert GMU bindings to YAML

2020-03-02 Thread Rob Herring 
On Mon,  2 Mar 2020 13:47:46 -0700, Jordan Crouse wrote:
> Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
> text bindings.
> 
> Signed-off-by: Jordan Crouse 
> ---
> 
>  .../devicetree/bindings/display/msm/gmu.txt| 116 ---
>  .../devicetree/bindings/display/msm/gmu.yaml   | 123 
> +
>  2 files changed, 123 insertions(+), 116 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
>  create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml
> 

Reviewed-by: Rob Herring 
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Re: [Freedreno] [PATCH v3 2/2] drm/msm/a6xx: Use the DMA API for GMU memory objects

2020-03-02 Thread Ruhl, Michael J 
>-Original Message-
>From: dri-devel  On Behalf Of
>Jordan Crouse
>Sent: Monday, March 2, 2020 1:24 PM
>To: linux-arm-...@vger.kernel.org
>Cc: David Airlie ; freedreno@lists.freedesktop.org;
>smase...@codeaurora.org; linux-ker...@vger.kernel.org; dri-
>de...@lists.freedesktop.org; Douglas Anderson ;
>Sean Paul 
>Subject: [PATCH v3 2/2] drm/msm/a6xx: Use the DMA API for GMU memory
>objects
>
>The GMU has very few memory allocations and uses a flat memory space so
>there is no good reason to go out of our way to bypass the DMA APIs which
>were basically designed for this exact scenario.
>
>v3: Set the dma mask correctly and use dma_addr_t for the iova type
>
>v2: Pass force_dma false to of_dma_configure to require that the DMA
>region be set up and return error from of_dma_configure to fail probe.
>
>Signed-off-by: Jordan Crouse 
>---
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 ---
>---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h |   7 +--
> 2 files changed, 15 insertions(+), 107 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>index 748cd37..854ba30 100644
>--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>@@ -2,6 +2,7 @@
> /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
>
> #include 
>+#include 
> #include 
> #include 
> #include 
>@@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
>
> static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct
>a6xx_gmu_bo *bo)
> {
>-  int count, i;
>-  u64 iova;
>-
>   if (IS_ERR_OR_NULL(bo))
>   return;
>
>-  count = bo->size >> PAGE_SHIFT;
>-  iova = bo->iova;
>-
>-  for (i = 0; i < count; i++, iova += PAGE_SIZE) {
>-  iommu_unmap(gmu->domain, iova, PAGE_SIZE);
>-  __free_pages(bo->pages[i], 0);
>-  }
>-
>-  kfree(bo->pages);
>+  dma_free_attrs(gmu->dev, bo->size, bo->virt, bo->iova, bo->attrs);
>   kfree(bo);
> }
>
>@@ -942,94 +932,23 @@ static struct a6xx_gmu_bo
>*a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
>   size_t size)
> {
>   struct a6xx_gmu_bo *bo;
>-  int ret, count, i;
>
>   bo = kzalloc(sizeof(*bo), GFP_KERNEL);
>   if (!bo)
>   return ERR_PTR(-ENOMEM);
>
>   bo->size = PAGE_ALIGN(size);
>+  bo->attrs = DMA_ATTR_WRITE_COMBINE;
>
>-  count = bo->size >> PAGE_SHIFT;
>+  bo->virt = dma_alloc_attrs(gmu->dev, bo->size, &bo->iova,
>GFP_KERNEL,
>+  bo->attrs);

I see that there is a dma_alloc_wc()/dma_free_wc() which appears to do the
same set up that you are using here.

Could you use those wrappers, or do you need to keep track of the bo->attrs
elsewhere?
 
Mike

>-  bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
>-  if (!bo->pages) {
>+  if (!bo->virt) {
>   kfree(bo);
>   return ERR_PTR(-ENOMEM);
>   }
>
>-  for (i = 0; i < count; i++) {
>-  bo->pages[i] = alloc_page(GFP_KERNEL);
>-  if (!bo->pages[i])
>-  goto err;
>-  }
>-
>-  bo->iova = gmu->uncached_iova_base;
>-
>-  for (i = 0; i < count; i++) {
>-  ret = iommu_map(gmu->domain,
>-  bo->iova + (PAGE_SIZE * i),
>-  page_to_phys(bo->pages[i]), PAGE_SIZE,
>-  IOMMU_READ | IOMMU_WRITE);
>-
>-  if (ret) {
>-  DRM_DEV_ERROR(gmu->dev, "Unable to map GMU
>buffer object\n");
>-
>-  for (i = i - 1 ; i >= 0; i--)
>-  iommu_unmap(gmu->domain,
>-  bo->iova + (PAGE_SIZE * i),
>-  PAGE_SIZE);
>-
>-  goto err;
>-  }
>-  }
>-
>-  bo->virt = vmap(bo->pages, count, VM_IOREMAP,
>-  pgprot_writecombine(PAGE_KERNEL));
>-  if (!bo->virt)
>-  goto err;
>-
>-  /* Align future IOVA addresses on 1MB boundaries */
>-  gmu->uncached_iova_base += ALIGN(size, SZ_1M);
>-
>   return bo;
>-
>-err:
>-  for (i = 0; i < count; i++) {
>-  if (bo->pages[i])
>-  __free_pages(bo->pages[i], 0);
>-  }
>-
>-  kfree(bo->pages);
>-  kfree(bo);
>-
>-  return ERR_PTR(-ENOMEM);
>-}
>-
>-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
>-{
>-  int ret;
>-
>-  /*
>-   * The GMU address space is hardcoded to treat the range
>-   * 0x6000 - 0x8000 as un-cached memory. All buffers shared
>-   * between the GMU and the CPU will live in this space
>-   */
>-  gmu->uncached_iova_base = 0x6000;
>-
>-
>-  gmu->domain = iommu_domain_alloc(&platform_bus_type);
>-  if (!gmu->domain)
>-  return -ENODEV;
>-
>-  ret = iommu_attach_device(gmu->domain, gmu->dev);
>-
>-  if (ret) {
>-  iommu_domain_free(gmu->

Re: [Freedreno] [PATCH v4 2/2] drm/msm/a6xx: Use the DMA API for GMU memory objects

2020-03-02 Thread Ruhl, Michael J 
>-Original Message-
>From: dri-devel  On Behalf Of
>Jordan Crouse
>Sent: Monday, March 2, 2020 3:48 PM
>To: linux-arm-...@vger.kernel.org
>Cc: Douglas Anderson ; David Airlie
>; freedreno@lists.freedesktop.org;
>smase...@codeaurora.org; linux-ker...@vger.kernel.org; dri-
>de...@lists.freedesktop.org; Stephen Boyd ; Ruhl,
>Michael J ; Sean Paul 
>Subject: [PATCH v4 2/2] drm/msm/a6xx: Use the DMA API for GMU memory
>objects
>
>The GMU has very few memory allocations and uses a flat memory space so
>there is no good reason to go out of our way to bypass the DMA APIs which
>were basically designed for this exact scenario.
>
>v4: Use dma_alloc_wc()

The patch and the update look good to me.

Reviewed-by: Michael J. Ruhl 

Mike

>v3: Set the dma mask correctly and use dma_addr_t for the iova type
>v2: Pass force_dma false to of_dma_configure to require that the DMA
>region be set up and return error from of_dma_configure to fail probe.
>
>Signed-off-by: Jordan Crouse 
>---
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 113 ---
>---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h |   6 +-
> 2 files changed, 12 insertions(+), 107 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>index 748cd37..dd51dd0 100644
>--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>@@ -2,6 +2,7 @@
> /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
>
> #include 
>+#include 
> #include 
> #include 
> #include 
>@@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
>
> static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct
>a6xx_gmu_bo *bo)
> {
>-  int count, i;
>-  u64 iova;
>-
>   if (IS_ERR_OR_NULL(bo))
>   return;
>
>-  count = bo->size >> PAGE_SHIFT;
>-  iova = bo->iova;
>-
>-  for (i = 0; i < count; i++, iova += PAGE_SIZE) {
>-  iommu_unmap(gmu->domain, iova, PAGE_SIZE);
>-  __free_pages(bo->pages[i], 0);
>-  }
>-
>-  kfree(bo->pages);
>+  dma_free_wc(gmu->dev, bo->size, bo->virt, bo->iova);
>   kfree(bo);
> }
>
>@@ -942,7 +932,6 @@ static struct a6xx_gmu_bo
>*a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
>   size_t size)
> {
>   struct a6xx_gmu_bo *bo;
>-  int ret, count, i;
>
>   bo = kzalloc(sizeof(*bo), GFP_KERNEL);
>   if (!bo)
>@@ -950,86 +939,14 @@ static struct a6xx_gmu_bo
>*a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
>
>   bo->size = PAGE_ALIGN(size);
>
>-  count = bo->size >> PAGE_SHIFT;
>+  bo->virt = dma_alloc_wc(gmu->dev, bo->size, &bo->iova,
>GFP_KERNEL);
>
>-  bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
>-  if (!bo->pages) {
>+  if (!bo->virt) {
>   kfree(bo);
>   return ERR_PTR(-ENOMEM);
>   }
>
>-  for (i = 0; i < count; i++) {
>-  bo->pages[i] = alloc_page(GFP_KERNEL);
>-  if (!bo->pages[i])
>-  goto err;
>-  }
>-
>-  bo->iova = gmu->uncached_iova_base;
>-
>-  for (i = 0; i < count; i++) {
>-  ret = iommu_map(gmu->domain,
>-  bo->iova + (PAGE_SIZE * i),
>-  page_to_phys(bo->pages[i]), PAGE_SIZE,
>-  IOMMU_READ | IOMMU_WRITE);
>-
>-  if (ret) {
>-  DRM_DEV_ERROR(gmu->dev, "Unable to map GMU
>buffer object\n");
>-
>-  for (i = i - 1 ; i >= 0; i--)
>-  iommu_unmap(gmu->domain,
>-  bo->iova + (PAGE_SIZE * i),
>-  PAGE_SIZE);
>-
>-  goto err;
>-  }
>-  }
>-
>-  bo->virt = vmap(bo->pages, count, VM_IOREMAP,
>-  pgprot_writecombine(PAGE_KERNEL));
>-  if (!bo->virt)
>-  goto err;
>-
>-  /* Align future IOVA addresses on 1MB boundaries */
>-  gmu->uncached_iova_base += ALIGN(size, SZ_1M);
>-
>   return bo;
>-
>-err:
>-  for (i = 0; i < count; i++) {
>-  if (bo->pages[i])
>-  __free_pages(bo->pages[i], 0);
>-  }
>-
>-  kfree(bo->pages);
>-  kfree(bo);
>-
>-  return ERR_PTR(-ENOMEM);
>-}
>-
>-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
>-{
>-  int ret;
>-
>-  /*
>-   * The GMU address space is hardcoded to treat the range
>-   * 0x6000 - 0x8000 as un-cached memory. All buffers shared
>-   * between the GMU and the CPU will live in this space
>-   */
>-  gmu->uncached_iova_base = 0x6000;
>-
>-
>-  gmu->domain = iommu_domain_alloc(&platform_bus_type);
>-  if (!gmu->domain)
>-  return -ENODEV;
>-
>-  ret = iommu_attach_device(gmu->domain, gmu->dev);
>-
>-  if (ret) {
>-  iommu_domain_free(gmu->domain);
>-  gmu->domain = NULL;
>-  }
>-
>-  return ret;
> }
>
> /* Return the 'arc-le

Re: [Freedreno] [PATCH v4 02/22] drm: Add get_scanout_position() to struct drm_crtc_helper_funcs

2020-03-02 Thread Daniel Vetter 
On Thu, Jan 23, 2020 at 2:59 PM Thomas Zimmermann  wrote:
>
> The new callback get_scanout_position() reads the current location
> of the scanout process. The operation is currently located in struct
> drm_driver, but really belongs to the CRTC. Drivers will be converted
> in separate patches.
>
> To help with the conversion, the timestamp calculation has been
> moved from drm_calc_vbltimestamp_from_scanoutpos() to
> drm_crtc_vblank_helper_get_vblank_timestamp_internal(). The helper
> function supports the new and old interface of get_scanout_position().
> drm_calc_vbltimestamp_from_scanoutpos() remains as a wrapper around
> the new function.
>
> Callback functions return the scanout position from the CRTC. The
> legacy version of the interface receives the device and pipe index,
> the modern version receives a pointer to the CRTC. We keep the
> legacy version until all drivers have been converted.
>
> v4:
> * 80-character line fixes
> v3:
> * refactor drm_calc_vbltimestamp_from_scanoutpos() to minimize
>   code duplication
> * define types for get_scanout_position() callbacks
> v2:
> * fix logical op in drm_calc_vbltimestamp_from_scanoutpos()
>
> Signed-off-by: Thomas Zimmermann 
> Tested-by: Yannick Fertré 
> Reviewed-by: Ville Syrjälä 

This patch causes new kerneldoc build warnings:

./drivers/gpu/drm/drm_vblank.c:623: warning: Excess function parameter
'dev' description in
'drm_crtc_vblank_helper_get_vblank_timestamp_internal'
./drivers/gpu/drm/drm_vblank.c:623: warning: Excess function parameter
'pipe' description in
'drm_crtc_vblank_helper_get_vblank_timestamp_internal'
./drivers/gpu/drm/drm_vblank.c:624: warning: Function parameter or
member 'crtc' not described in
'drm_crtc_vblank_helper_get_vblank_timestamp_internal'
./drivers/gpu/drm/drm_vblank.c:624: warning: Excess function parameter
'dev' description in
'drm_crtc_vblank_helper_get_vblank_timestamp_internal'
./drivers/gpu/drm/drm_vblank.c:624: warning: Excess function parameter
'pipe' description in
'drm_crtc_vblank_helper_get_vblank_timestamp_internal'


Please fix.
-Daniel

> ---
>  drivers/gpu/drm/drm_vblank.c | 101 +++
>  include/drm/drm_drv.h|   7 +-
>  include/drm/drm_modeset_helper_vtables.h |  47 +++
>  include/drm/drm_vblank.h |  25 ++
>  4 files changed, 157 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
> index 326db52f2ad8..7e962c29780c 100644
> --- a/drivers/gpu/drm/drm_vblank.c
> +++ b/drivers/gpu/drm/drm_vblank.c
> @@ -30,6 +30,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>
> @@ -577,7 +578,7 @@ EXPORT_SYMBOL(drm_calc_timestamping_constants);
>   * Implements calculation of exact vblank timestamps from given 
> drm_display_mode
>   * timings and current video scanout position of a CRTC. This can be directly
>   * used as the &drm_driver.get_vblank_timestamp implementation of a kms 
> driver
> - * if &drm_driver.get_scanout_position is implemented.
> + * if &drm_crtc_helper_funcs.get_scanout_position is implemented.
>   *
>   * The current implementation only handles standard video modes. For double 
> scan
>   * and interlaced modes the driver is supposed to adjust the hardware mode
> @@ -599,28 +600,85 @@ bool drm_calc_vbltimestamp_from_scanoutpos(struct 
> drm_device *dev,
>ktime_t *vblank_time,
>bool in_vblank_irq)
>  {
> -   struct timespec64 ts_etime, ts_vblank_time;
> -   ktime_t stime, etime;
> -   bool vbl_status;
> struct drm_crtc *crtc;
> -   const struct drm_display_mode *mode;
> -   struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
> -   int vpos, hpos, i;
> -   int delta_ns, duration_ns;
>
> if (!drm_core_check_feature(dev, DRIVER_MODESET))
> return false;
>
> crtc = drm_crtc_from_index(dev, pipe);
> +   if (!crtc)
> +   return false;
>
> -   if (pipe >= dev->num_crtcs || !crtc) {
> +   return drm_crtc_vblank_helper_get_vblank_timestamp_internal(crtc,
> +   max_error,
> +   
> vblank_time,
> +   
> in_vblank_irq,
> +   
> crtc->helper_private->get_scanout_position,
> +   
> dev->driver->get_scanout_position);
> +}
> +EXPORT_SYMBOL(drm_calc_vbltimestamp_from_scanoutpos);
> +
> +/**
> + * drm_crtc_vblank_helper_get_vblank_timestamp_internal - precise vblank
> + *timestamp helper
> + * @dev: DRM device
> + * @pipe: index of CRTC whose vblank timestamp to r

Re: [Freedreno] [PATCH v3 1/2] dt-bindings: display: msm: Convert GMU bindings to YAML

2020-03-02 Thread Sam Ravnborg 
Hi Jordan.

On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote:
> Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
> text bindings.
> 
> Signed-off-by: Jordan Crouse 
> ---
> 
>  .../devicetree/bindings/display/msm/gmu.txt| 116 ---
> -
> -Required properties:
> -- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
> -for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
> -  Note that you need to list the less specific "qcom,adreno-gmu"
> -  for generic matches and the more specific identifier to identify
> -  the specific device.
> -- reg: Physical base address and length of the GMU registers.
> -- reg-names: Matching names for the register regions
> -  * "gmu"
> -  * "gmu_pdc"
> -  * "gmu_pdc_seg"
> -- interrupts: The interrupt signals from the GMU.
> -- interrupt-names: Matching names for the interrupts
> -  * "hfi"
> -  * "gmu"
> -- clocks: phandles to the device clocks
> -- clock-names: Matching names for the clocks
> -   * "gmu"
> -   * "cxo"
> -   * "axi"
> -   * "mnoc"
The new binding - and arch/arm64/boot/dts/qcom/sdm845.dtsi agrees that
"mnoc" is wrong.

> -- power-domains: should be:
> - <&clock_gpucc GPU_CX_GDSC>
> - <&clock_gpucc GPU_GX_GDSC>
> -- power-domain-names: Matching names for the power domains
> -- iommus: phandle to the adreno iommu
> -- operating-points-v2: phandle to the OPP operating points
> -
> -Optional properties:
> -- sram: phandle to the On Chip Memory (OCMEM) that's present on some 
> Snapdragon
> -SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
This property is not included in the new binding.

Everything else looked fine to me.
With sram added - or expalined in commit why it is dropped:
Acked-by: Sam Ravnborg 

Sam
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[Freedreno] [PATCH v4 1/2] dt-bindings: display: msm: Convert GMU bindings to YAML

2020-03-02 Thread Jordan Crouse 
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.

Signed-off-by: Jordan Crouse 
---

 .../devicetree/bindings/display/msm/gmu.txt| 116 ---
 .../devicetree/bindings/display/msm/gmu.yaml   | 123 +
 2 files changed, 123 insertions(+), 116 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt 
b/Documentation/devicetree/bindings/display/msm/gmu.txt
deleted file mode 100644
index bf9c7a2..000
--- a/Documentation/devicetree/bindings/display/msm/gmu.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-Qualcomm adreno/snapdragon GMU (Graphics management unit)
-
-The GMU is a programmable power controller for the GPU. the CPU controls the
-GMU which in turn handles power controls for the GPU.
-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"
-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
-  * "hfi"
-  * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
-   * "gmu"
-   * "cxo"
-   * "axi"
-   * "mnoc"
-- power-domains: should be:
-   <&clock_gpucc GPU_CX_GDSC>
-   <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
-
-Example:
-
-/ {
-   ...
-
-   gmu: gmu@506a000 {
-   compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
-
-   reg = <0x506a000 0x3>,
-   <0xb28 0x1>,
-   <0xb48 0x1>;
-   reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
-
-   interrupts = ,
-;
-   interrupt-names = "hfi", "gmu";
-
-   clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
-   <&gpucc GPU_CC_CXO_CLK>,
-   <&gcc GCC_DDRSS_GPU_AXI_CLK>,
-   <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
-   clock-names = "gmu", "cxo", "axi", "memnoc";
-
-   power-domains = <&gpucc GPU_CX_GDSC>,
-   <&gpucc GPU_GX_GDSC>;
-   power-domain-names = "cx", "gx";
-
-   iommus = <&adreno_smmu 5>;
-
-   operating-points-v2 = <&gmu_opp_table>;
-   };
-};
-
-a3xx example with OCMEM support:
-
-/ {
-   ...
-
-   gpu: adreno@fdb0 {
-   compatible = "qcom,adreno-330.2",
-"qcom,adreno";
-   reg = <0xfdb0 0x1>;
-   reg-names = "kgsl_3d0_reg_memory";
-   interrupts = ;
-   interrupt-names = "kgsl_3d0_irq";
-   clock-names = "core",
- "iface",
- "mem_iface";
-   clocks = <&mmcc OXILI_GFX3D_CLK>,
-<&mmcc OXILICX_AHB_CLK>,
-<&mmcc OXILICX_AXI_CLK>;
-   sram = <&gmu_sram>;
-   power-domains = <&mmcc OXILICX_GDSC>;
-   operating-points-v2 = <&gpu_opp_table>;
-   iommus = <&gpu_iommu 0>;
-   };
-
-   ocmem@fdd0 {
-   compatible = "qcom,msm8974-ocmem";
-
-   reg = <0xfdd0 0x2000>,
- <0xfec0 0x18>;
-   reg-names = "ctrl",
-"mem";
-
-   clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
-<&mmcc OCMEMCX_OCMEMNOC_CLK>;
-   clock-names = "core",
- "iface";
-
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   gmu_sram: gmu-sram@0 {
-   reg = <0x0 0x10>;
-   ranges = <0 0 0xfec0 0x10>;
-   };
-   };
-};
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml 
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
new file mode 100644
index 000..0b8736a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
+%YAML 1.2
+---
+
+$id: "http:

[Freedreno] [PATCH v4 0/2] msm/gpu/a6xx: use the DMA-API for GMU memory allocations

2020-03-02 Thread Jordan Crouse 
When CONFIG_INIT_ON_ALLOC_DEFAULT_ON the GMU memory allocator runs afoul of
cache coherency issues because it is mapped as write-combine without clearing
the cache after it was zeroed.

Rather than duplicate the hacky workaround we use in the GEM allocator for the
same reason it turns out that we don't need to have a bespoke memory allocator
for the GMU anyway. It uses a flat, global address space and there are only
two relatively minor allocations anyway. In short, this is essentially what the
DMA API was created for so replace a bunch of memory management code with two
calls to allocate and free DMA memory and we're fine.

In a previous version of this series I added the dma-ranges property to the
device tree file for the GMU and updated the bindings to YAML. Rob correctly
pointed out that we didn't need dma-ranges any more but I'm still pushing the
YAML conversion because it is good and we'll eventually need it anyway so why
not.

v4: Use dma_alloc_wc() wrappers per Michael Ruhl.

v3: Fix YAML description per RobH and remove dma-ranges and replace it with the
correct DMA mask in the GMU device. Convert the iova type to a dma_attr_t to
make it 32 bit friendly.

v2: Fix the example bindings for dma-ranges - the third item is the size
Pass false to of_dma_configure so that it fails probe if the DMA region is not
set up.

Jordan Crouse (2):
  dt-bindings: display: msm: Convert GMU bindings to YAML
  drm/msm/a6xx: Use the DMA API for GMU memory objects

 .../devicetree/bindings/display/msm/gmu.txt| 116 ---
 .../devicetree/bindings/display/msm/gmu.yaml   | 123 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c  | 113 ++-
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h  |   6 +-
 4 files changed, 135 insertions(+), 223 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml

-- 
2.7.4
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[Freedreno] [PATCH v4 2/2] drm/msm/a6xx: Use the DMA API for GMU memory objects

2020-03-02 Thread Jordan Crouse 
The GMU has very few memory allocations and uses a flat memory space so
there is no good reason to go out of our way to bypass the DMA APIs which
were basically designed for this exact scenario.

v4: Use dma_alloc_wc()
v3: Set the dma mask correctly and use dma_addr_t for the iova type
v2: Pass force_dma false to of_dma_configure to require that the DMA
region be set up and return error from of_dma_configure to fail probe.

Signed-off-by: Jordan Crouse 
---

 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 113 --
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h |   6 +-
 2 files changed, 12 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 748cd37..dd51dd0 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2,6 +2,7 @@
 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
 
 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo)
 {
-   int count, i;
-   u64 iova;
-
if (IS_ERR_OR_NULL(bo))
return;
 
-   count = bo->size >> PAGE_SHIFT;
-   iova = bo->iova;
-
-   for (i = 0; i < count; i++, iova += PAGE_SIZE) {
-   iommu_unmap(gmu->domain, iova, PAGE_SIZE);
-   __free_pages(bo->pages[i], 0);
-   }
-
-   kfree(bo->pages);
+   dma_free_wc(gmu->dev, bo->size, bo->virt, bo->iova);
kfree(bo);
 }
 
@@ -942,7 +932,6 @@ static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct 
a6xx_gmu *gmu,
size_t size)
 {
struct a6xx_gmu_bo *bo;
-   int ret, count, i;
 
bo = kzalloc(sizeof(*bo), GFP_KERNEL);
if (!bo)
@@ -950,86 +939,14 @@ static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct 
a6xx_gmu *gmu,
 
bo->size = PAGE_ALIGN(size);
 
-   count = bo->size >> PAGE_SHIFT;
+   bo->virt = dma_alloc_wc(gmu->dev, bo->size, &bo->iova, GFP_KERNEL);
 
-   bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
-   if (!bo->pages) {
+   if (!bo->virt) {
kfree(bo);
return ERR_PTR(-ENOMEM);
}
 
-   for (i = 0; i < count; i++) {
-   bo->pages[i] = alloc_page(GFP_KERNEL);
-   if (!bo->pages[i])
-   goto err;
-   }
-
-   bo->iova = gmu->uncached_iova_base;
-
-   for (i = 0; i < count; i++) {
-   ret = iommu_map(gmu->domain,
-   bo->iova + (PAGE_SIZE * i),
-   page_to_phys(bo->pages[i]), PAGE_SIZE,
-   IOMMU_READ | IOMMU_WRITE);
-
-   if (ret) {
-   DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer 
object\n");
-
-   for (i = i - 1 ; i >= 0; i--)
-   iommu_unmap(gmu->domain,
-   bo->iova + (PAGE_SIZE * i),
-   PAGE_SIZE);
-
-   goto err;
-   }
-   }
-
-   bo->virt = vmap(bo->pages, count, VM_IOREMAP,
-   pgprot_writecombine(PAGE_KERNEL));
-   if (!bo->virt)
-   goto err;
-
-   /* Align future IOVA addresses on 1MB boundaries */
-   gmu->uncached_iova_base += ALIGN(size, SZ_1M);
-
return bo;
-
-err:
-   for (i = 0; i < count; i++) {
-   if (bo->pages[i])
-   __free_pages(bo->pages[i], 0);
-   }
-
-   kfree(bo->pages);
-   kfree(bo);
-
-   return ERR_PTR(-ENOMEM);
-}
-
-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
-{
-   int ret;
-
-   /*
-* The GMU address space is hardcoded to treat the range
-* 0x6000 - 0x8000 as un-cached memory. All buffers shared
-* between the GMU and the CPU will live in this space
-*/
-   gmu->uncached_iova_base = 0x6000;
-
-
-   gmu->domain = iommu_domain_alloc(&platform_bus_type);
-   if (!gmu->domain)
-   return -ENODEV;
-
-   ret = iommu_attach_device(gmu->domain, gmu->dev);
-
-   if (ret) {
-   iommu_domain_free(gmu->domain);
-   gmu->domain = NULL;
-   }
-
-   return ret;
 }
 
 /* Return the 'arc-level' for the given frequency */
@@ -1289,10 +1206,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
 
a6xx_gmu_memory_free(gmu, gmu->hfi);
 
-   iommu_detach_device(gmu->domain, gmu->dev);
-
-   iommu_domain_free(gmu->domain);
-
free_irq(gmu->gmu_irq, gmu);
free_irq(gmu->hfi_irq, gmu);
 
@@ -1313,7 +1226,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct 
device_node *node)
 
gmu->dev = &pdev->dev;
 
-   of_dma_configure(gmu->dev, node, true);
+   /* Pass force_dma false to require the DT to set the dma region */
+

Re: [Freedreno] [PATCH v3 2/2] drm/msm/a6xx: Use the DMA API for GMU memory objects

2020-03-02 Thread Jordan Crouse 
On Mon, Mar 02, 2020 at 06:56:47PM +, Ruhl, Michael J wrote:
> >-Original Message-
> >From: dri-devel  On Behalf Of
> >Jordan Crouse
> >Sent: Monday, March 2, 2020 1:24 PM
> >To: linux-arm-...@vger.kernel.org
> >Cc: David Airlie ; freedreno@lists.freedesktop.org;
> >smase...@codeaurora.org; linux-ker...@vger.kernel.org; dri-
> >de...@lists.freedesktop.org; Douglas Anderson ;
> >Sean Paul 
> >Subject: [PATCH v3 2/2] drm/msm/a6xx: Use the DMA API for GMU memory
> >objects
> >
> >The GMU has very few memory allocations and uses a flat memory space so
> >there is no good reason to go out of our way to bypass the DMA APIs which
> >were basically designed for this exact scenario.
> >
> >v3: Set the dma mask correctly and use dma_addr_t for the iova type
> >
> >v2: Pass force_dma false to of_dma_configure to require that the DMA
> >region be set up and return error from of_dma_configure to fail probe.
> >
> >Signed-off-by: Jordan Crouse 
> >---
> >
> > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 ---
> >---
> > drivers/gpu/drm/msm/adreno/a6xx_gmu.h |   7 +--
> > 2 files changed, 15 insertions(+), 107 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >index 748cd37..854ba30 100644
> >--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> >@@ -2,6 +2,7 @@
> > /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
> >
> > #include 
> >+#include 
> > #include 
> > #include 
> > #include 
> >@@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
> >
> > static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct
> >a6xx_gmu_bo *bo)
> > {
> >-int count, i;
> >-u64 iova;
> >-
> > if (IS_ERR_OR_NULL(bo))
> > return;
> >
> >-count = bo->size >> PAGE_SHIFT;
> >-iova = bo->iova;
> >-
> >-for (i = 0; i < count; i++, iova += PAGE_SIZE) {
> >-iommu_unmap(gmu->domain, iova, PAGE_SIZE);
> >-__free_pages(bo->pages[i], 0);
> >-}
> >-
> >-kfree(bo->pages);
> >+dma_free_attrs(gmu->dev, bo->size, bo->virt, bo->iova, bo->attrs);
> > kfree(bo);
> > }
> >
> >@@ -942,94 +932,23 @@ static struct a6xx_gmu_bo
> >*a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu,
> > size_t size)
> > {
> > struct a6xx_gmu_bo *bo;
> >-int ret, count, i;
> >
> > bo = kzalloc(sizeof(*bo), GFP_KERNEL);
> > if (!bo)
> > return ERR_PTR(-ENOMEM);
> >
> > bo->size = PAGE_ALIGN(size);
> >+bo->attrs = DMA_ATTR_WRITE_COMBINE;
> >
> >-count = bo->size >> PAGE_SHIFT;
> >+bo->virt = dma_alloc_attrs(gmu->dev, bo->size, &bo->iova,
> >GFP_KERNEL,
> >+bo->attrs);
> 
> I see that there is a dma_alloc_wc()/dma_free_wc() which appears to do the
> same set up that you are using here.
> 
> Could you use those wrappers, or do you need to keep track of the bo->attrs
> elsewhere?

I didn't know those wrappers existed but now I am very happy to use them.

Jordan

> Mike
> 
> >-bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
> >-if (!bo->pages) {
> >+if (!bo->virt) {
> > kfree(bo);
> > return ERR_PTR(-ENOMEM);
> > }
> >
> >-for (i = 0; i < count; i++) {
> >-bo->pages[i] = alloc_page(GFP_KERNEL);
> >-if (!bo->pages[i])
> >-goto err;
> >-}
> >-
> >-bo->iova = gmu->uncached_iova_base;
> >-
> >-for (i = 0; i < count; i++) {
> >-ret = iommu_map(gmu->domain,
> >-bo->iova + (PAGE_SIZE * i),
> >-page_to_phys(bo->pages[i]), PAGE_SIZE,
> >-IOMMU_READ | IOMMU_WRITE);
> >-
> >-if (ret) {
> >-DRM_DEV_ERROR(gmu->dev, "Unable to map GMU
> >buffer object\n");
> >-
> >-for (i = i - 1 ; i >= 0; i--)
> >-iommu_unmap(gmu->domain,
> >-bo->iova + (PAGE_SIZE * i),
> >-PAGE_SIZE);
> >-
> >-goto err;
> >-}
> >-}
> >-
> >-bo->virt = vmap(bo->pages, count, VM_IOREMAP,
> >-pgprot_writecombine(PAGE_KERNEL));
> >-if (!bo->virt)
> >-goto err;
> >-
> >-/* Align future IOVA addresses on 1MB boundaries */
> >-gmu->uncached_iova_base += ALIGN(size, SZ_1M);
> >-
> > return bo;
> >-
> >-err:
> >-for (i = 0; i < count; i++) {
> >-if (bo->pages[i])
> >-__free_pages(bo->pages[i], 0);
> >-}
> >-
> >-kfree(bo->pages);
> >-kfree(bo);
> >-
> >-return ERR_PTR(-ENOMEM);
> >-}
> >-
> >-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
> >-{
> >-int ret;
> >-
> >-/*
> >- * The GMU address space is hardcoded to treat the range
> >- * 0x6000 - 0x8000 as un-cached memory. All buffers shared
> >- * between the GMU and the CPU will live

[Freedreno] [PATCH v3 1/2] dt-bindings: display: msm: Convert GMU bindings to YAML

2020-03-02 Thread Jordan Crouse 
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.

Signed-off-by: Jordan Crouse 
---

 .../devicetree/bindings/display/msm/gmu.txt| 116 ---
 .../devicetree/bindings/display/msm/gmu.yaml   | 123 +
 2 files changed, 123 insertions(+), 116 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt 
b/Documentation/devicetree/bindings/display/msm/gmu.txt
deleted file mode 100644
index bf9c7a2..000
--- a/Documentation/devicetree/bindings/display/msm/gmu.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-Qualcomm adreno/snapdragon GMU (Graphics management unit)
-
-The GMU is a programmable power controller for the GPU. the CPU controls the
-GMU which in turn handles power controls for the GPU.
-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
-  Note that you need to list the less specific "qcom,adreno-gmu"
-  for generic matches and the more specific identifier to identify
-  the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
-  * "gmu"
-  * "gmu_pdc"
-  * "gmu_pdc_seg"
-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
-  * "hfi"
-  * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
-   * "gmu"
-   * "cxo"
-   * "axi"
-   * "mnoc"
-- power-domains: should be:
-   <&clock_gpucc GPU_CX_GDSC>
-   <&clock_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
-
-Example:
-
-/ {
-   ...
-
-   gmu: gmu@506a000 {
-   compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
-
-   reg = <0x506a000 0x3>,
-   <0xb28 0x1>,
-   <0xb48 0x1>;
-   reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
-
-   interrupts = ,
-;
-   interrupt-names = "hfi", "gmu";
-
-   clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
-   <&gpucc GPU_CC_CXO_CLK>,
-   <&gcc GCC_DDRSS_GPU_AXI_CLK>,
-   <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
-   clock-names = "gmu", "cxo", "axi", "memnoc";
-
-   power-domains = <&gpucc GPU_CX_GDSC>,
-   <&gpucc GPU_GX_GDSC>;
-   power-domain-names = "cx", "gx";
-
-   iommus = <&adreno_smmu 5>;
-
-   operating-points-v2 = <&gmu_opp_table>;
-   };
-};
-
-a3xx example with OCMEM support:
-
-/ {
-   ...
-
-   gpu: adreno@fdb0 {
-   compatible = "qcom,adreno-330.2",
-"qcom,adreno";
-   reg = <0xfdb0 0x1>;
-   reg-names = "kgsl_3d0_reg_memory";
-   interrupts = ;
-   interrupt-names = "kgsl_3d0_irq";
-   clock-names = "core",
- "iface",
- "mem_iface";
-   clocks = <&mmcc OXILI_GFX3D_CLK>,
-<&mmcc OXILICX_AHB_CLK>,
-<&mmcc OXILICX_AXI_CLK>;
-   sram = <&gmu_sram>;
-   power-domains = <&mmcc OXILICX_GDSC>;
-   operating-points-v2 = <&gpu_opp_table>;
-   iommus = <&gpu_iommu 0>;
-   };
-
-   ocmem@fdd0 {
-   compatible = "qcom,msm8974-ocmem";
-
-   reg = <0xfdd0 0x2000>,
- <0xfec0 0x18>;
-   reg-names = "ctrl",
-"mem";
-
-   clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
-<&mmcc OCMEMCX_OCMEMNOC_CLK>;
-   clock-names = "core",
- "iface";
-
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   gmu_sram: gmu-sram@0 {
-   reg = <0x0 0x10>;
-   ranges = <0 0 0xfec0 0x10>;
-   };
-   };
-};
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml 
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
new file mode 100644
index 000..0b8736a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
+%YAML 1.2
+---
+
+$id: "http:

[Freedreno] [PATCH v3 2/2] drm/msm/a6xx: Use the DMA API for GMU memory objects

2020-03-02 Thread Jordan Crouse 
The GMU has very few memory allocations and uses a flat memory space so
there is no good reason to go out of our way to bypass the DMA APIs which
were basically designed for this exact scenario.

v3: Set the dma mask correctly and use dma_addr_t for the iova type

v2: Pass force_dma false to of_dma_configure to require that the DMA
region be set up and return error from of_dma_configure to fail probe.

Signed-off-by: Jordan Crouse 
---

 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 --
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h |   7 +--
 2 files changed, 15 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 748cd37..854ba30 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2,6 +2,7 @@
 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -920,21 +921,10 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
 
 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo)
 {
-   int count, i;
-   u64 iova;
-
if (IS_ERR_OR_NULL(bo))
return;
 
-   count = bo->size >> PAGE_SHIFT;
-   iova = bo->iova;
-
-   for (i = 0; i < count; i++, iova += PAGE_SIZE) {
-   iommu_unmap(gmu->domain, iova, PAGE_SIZE);
-   __free_pages(bo->pages[i], 0);
-   }
-
-   kfree(bo->pages);
+   dma_free_attrs(gmu->dev, bo->size, bo->virt, bo->iova, bo->attrs);
kfree(bo);
 }
 
@@ -942,94 +932,23 @@ static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct 
a6xx_gmu *gmu,
size_t size)
 {
struct a6xx_gmu_bo *bo;
-   int ret, count, i;
 
bo = kzalloc(sizeof(*bo), GFP_KERNEL);
if (!bo)
return ERR_PTR(-ENOMEM);
 
bo->size = PAGE_ALIGN(size);
+   bo->attrs = DMA_ATTR_WRITE_COMBINE;
 
-   count = bo->size >> PAGE_SHIFT;
+   bo->virt = dma_alloc_attrs(gmu->dev, bo->size, &bo->iova, GFP_KERNEL,
+   bo->attrs);
 
-   bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL);
-   if (!bo->pages) {
+   if (!bo->virt) {
kfree(bo);
return ERR_PTR(-ENOMEM);
}
 
-   for (i = 0; i < count; i++) {
-   bo->pages[i] = alloc_page(GFP_KERNEL);
-   if (!bo->pages[i])
-   goto err;
-   }
-
-   bo->iova = gmu->uncached_iova_base;
-
-   for (i = 0; i < count; i++) {
-   ret = iommu_map(gmu->domain,
-   bo->iova + (PAGE_SIZE * i),
-   page_to_phys(bo->pages[i]), PAGE_SIZE,
-   IOMMU_READ | IOMMU_WRITE);
-
-   if (ret) {
-   DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer 
object\n");
-
-   for (i = i - 1 ; i >= 0; i--)
-   iommu_unmap(gmu->domain,
-   bo->iova + (PAGE_SIZE * i),
-   PAGE_SIZE);
-
-   goto err;
-   }
-   }
-
-   bo->virt = vmap(bo->pages, count, VM_IOREMAP,
-   pgprot_writecombine(PAGE_KERNEL));
-   if (!bo->virt)
-   goto err;
-
-   /* Align future IOVA addresses on 1MB boundaries */
-   gmu->uncached_iova_base += ALIGN(size, SZ_1M);
-
return bo;
-
-err:
-   for (i = 0; i < count; i++) {
-   if (bo->pages[i])
-   __free_pages(bo->pages[i], 0);
-   }
-
-   kfree(bo->pages);
-   kfree(bo);
-
-   return ERR_PTR(-ENOMEM);
-}
-
-static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
-{
-   int ret;
-
-   /*
-* The GMU address space is hardcoded to treat the range
-* 0x6000 - 0x8000 as un-cached memory. All buffers shared
-* between the GMU and the CPU will live in this space
-*/
-   gmu->uncached_iova_base = 0x6000;
-
-
-   gmu->domain = iommu_domain_alloc(&platform_bus_type);
-   if (!gmu->domain)
-   return -ENODEV;
-
-   ret = iommu_attach_device(gmu->domain, gmu->dev);
-
-   if (ret) {
-   iommu_domain_free(gmu->domain);
-   gmu->domain = NULL;
-   }
-
-   return ret;
 }
 
 /* Return the 'arc-level' for the given frequency */
@@ -1289,10 +1208,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
 
a6xx_gmu_memory_free(gmu, gmu->hfi);
 
-   iommu_detach_device(gmu->domain, gmu->dev);
-
-   iommu_domain_free(gmu->domain);
-
free_irq(gmu->gmu_irq, gmu);
free_irq(gmu->hfi_irq, gmu);
 
@@ -1313,7 +1228,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct 
device_node *node)
 
gmu->dev = &pdev->dev;
 
-   of_dma_configure(gmu->dev, node, true);
+   /* Pass force_dma false to require the DT to set the dma

[Freedreno] [PATCH v3 0/2] msm/gpu/a6xx: use the DMA-API for GMU memory allocations

2020-03-02 Thread Jordan Crouse 
When CONFIG_INIT_ON_ALLOC_DEFAULT_ON the GMU memory allocator runs afoul of
cache coherency issues because it is mapped as write-combine without clearing
the cache after it was zeroed.

Rather than duplicate the hacky workaround we use in the GEM allocator for the
same reason it turns out that we don't need to have a bespoke memory allocator
for the GMU anyway. It uses a flat, global address space and there are only
two relatively minor allocations anyway. In short, this is essentially what the
DMA API was created for so replace a bunch of memory management code with two
calls to allocate and free DMA memory and we're fine.

In a previous version of this series I added the dma-ranges property to the
device tree file for the GMU and updated the bindings to YAML. Rob correctly
pointed out that we should set the dma mask instead of using dma-ranges so I
removed that bit, but I'm still pushing the YAML conversion because it is good
and we'll eventually need it anyway.

v3: Fix YAML description per RobH and remove dma-ranges and replace it with the
correct DMA mask in the GMU device. Convert the iova type to a dma_attr_t to
make it 32 bit friendly.

v2: Fix the example bindings for dma-ranges - the third item is the size
Pass false to of_dma_configure so that it fails probe if the DMA region is not
set up.

Jordan Crouse (2):
  dt-bindings: display: msm: Convert GMU bindings to YAML
  drm/msm/a6xx: Use the DMA API for GMU memory objects

 .../devicetree/bindings/display/msm/gmu.txt| 116 ---
 .../devicetree/bindings/display/msm/gmu.yaml   | 123 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c  | 115 +++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h  |   7 +-
 4 files changed, 138 insertions(+), 223 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml

-- 
2.7.4
___
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Re: [Freedreno] [PATCH] drm: msm: a6x: Disable interrupts before recovery

2020-03-02 Thread Jordan Crouse 
On Mon, Mar 02, 2020 at 02:17:16PM +0530, Sharat Masetty wrote:
> This patch disables interrupts in the GPU RBBM hang detect fault handler
> before going to recovery.

Okay, but why?  What were you seeing?  A little bit of extra description would
make it easier to understand this change in the future.

> 
> Signed-off-by: Sharat Masetty 
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index dc8ec2c..4dd0f62 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -676,6 +676,9 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
>   gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
>   gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
>  
> + /* Disable interrupts before going for a recovery*/
> + gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 0);
> +

And this is turning off all the interrupts, but the commit log only mentions the
hang detect. In my experience, the hang detect usually only fires once until
after reset, but if there are other interrupts that are bothering you then it
makes sense to disable them but, again, this is good information for the commit
log and or a code comment.

Jordan

>   /* Turn off the hangcheck timer to keep it from bothering us */
>   del_timer(&gpu->hangcheck_timer);
>  
> -- 
> 1.9.1
> 
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[Freedreno] [PATCH] drm: msm: a6x: Disable interrupts before recovery

2020-03-02 Thread Sharat Masetty 
This patch disables interrupts in the GPU RBBM hang detect fault handler
before going to recovery.

Signed-off-by: Sharat Masetty 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index dc8ec2c..4dd0f62 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -676,6 +676,9 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
 
+   /* Disable interrupts before going for a recovery*/
+   gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 0);
+
/* Turn off the hangcheck timer to keep it from bothering us */
del_timer(&gpu->hangcheck_timer);
 
-- 
1.9.1
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