[Freedreno] [PATCH] drm/msm/adreno: fix updating ring fence
From: Rob Clark
We need to set it to the most recent completed fence, not the most
recent submitted. Otherwise we have races where we think we can retire
submits that the GPU is not finished with, if the GPU doesn't manage to
overwrite the seqno before we look at it.
This can show up with hang recovery if one of the submits after the
crashing submit also hangs after it is replayed.
Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers")
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index f9e3badf2fca..34e6242c1767 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -405,7 +405,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
ring->next = ring->start;
/* reset completed fence seqno: */
- ring->memptrs->fence = ring->seqno;
+ ring->memptrs->fence = ring->fctx->completed_fence;
ring->memptrs->rptr = 0;
}
--
2.26.2
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Re: [Freedreno] [PATCH v5] arm64: dts: qcom: sc7180: Add Display Port dt node
On 2020-08-11 12:30, Stephen Boyd wrote:
Quoting Tanmay Shah (2020-08-10 19:15:53)
@@ -2440,6 +2447,71 @@ dsi_phy: dsi-phy@ae94400 {
status = "disabled";
};
+
+ msm_dp: displayport-controller@ae9 {
+ status = "disabled";
+ compatible = "qcom,sc7180-dp";
+
+ reg = <0 0x0ae9 0 0x1400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12 IRQ_TYPE_NONE>;
Please drop the flags. It's not required per the binding. It should
just
be a single number, i.e. <12>.
Sure. I will change DP-bindings accordingly as well.
+
+ clocks = <&dispcc
DISP_CC_MDSS_AHB_CLK>,
+<&dispcc
DISP_CC_MDSS_DP_AUX_CLK>,
+<&dispcc
DISP_CC_MDSS_DP_LINK_CLK>,
+<&dispcc
DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+<&dispcc
DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface",
"core_aux",
"ctrl_link",
+ "ctrl_link_iface",
"stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&msm_dp 0>,
<&msm_dp 1>;
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SC7180_CX>;
Can you send another patch to add the hpd pinctrl binding for the hpd
function? It would be useful to have that in the SoC level in case any
board wants to use the hpd pin on this SoC without having to implement
it themselves. It could be assigned here too as the pinctrl but I'm not
sure if that is correct. Probably better to just have it in the SoC
file
and then let boards pick to use it.
We have tlmm node in sc7180.dtsi. We can define pinctrl definition for
"dp_hot" funtionality there.
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+
remote-endpoint
= <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: dp-opp-table {
Can this be called opp-table? I don't see the need to make it more
specific given that it doesn't share the namespace at this level with
anything else that is an opp table.
DSI and MDP's OPP table names were posted here:
https://lore.kernel.org/dri-devel/1594292674-15632-4-git-send-email-rna...@codeaurora.org/
So, It makes sense to keep naming conventions similar to dsi and mdp's
opp table.
+ compatible =
"operating-points-v2";
+
+ opp-16000 {
+ opp-hz = /bits/ 64
<16000>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+ };
+
+ opp-27000 {
+ opp-hz = /bits/ 64
<27000>;
+ required-opps =
<&rpmhpd_opp_svs>;
+ };
+
+ opp-54000 {
+ opp-hz = /bits/ 64
<54000>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-81000 {
+ opp-hz = /bits/ 64
<81000>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ };
+ };
+ };
};
dispcc: clock-controller@af0 {
@@ -2449,8 +2521,8 @@ dispcc: clock-controller@af0 {
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy
Re: [Freedreno] stable-rc 4.14: arm64: Internal error: Oops: clk_reparent __clk_set_parent_before on db410c
Quoting Stephen Boyd (2020-07-23 03:26:02)
> Quoting Naresh Kamboju (2020-07-23 03:10:37)
> > On Thu, 23 Jul 2020 at 13:36, Stephen Boyd wrote:
> > >
> > > It sounds like maybe you need this patch?
> > >
> > > bdcf1dc25324 ("clk: Evict unregistered clks from parent caches")
> >
> > Cherry-pick did not work on stable-rc 4.14
> > this patch might need backporting.
> > I am not sure.
> >
>
> Ok. That commit fixes a regression in the 3.x series of the kernel so it
> should go back to any LTS kernels. It looks like at least on 4.14 it's a
> trivial conflict. Here's a backport to 4.14
Did this help?
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Re: [Freedreno] [PATCH] drm/msm/a6xx: add module param to enable debugbus snapshot
On Tue, Aug 11, 2020 at 04:36:57PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> For production devices, the debugbus sections will typically be fused
> off and empty in the gpu device coredump. But since this may contain
> data like cache contents, don't capture it by default.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 3 ++-
> drivers/gpu/drm/msm/adreno/adreno_device.c | 4
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++
> 3 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> index 959656ad6987..b12f5b4a1bea 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> @@ -938,7 +938,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu
> *gpu)
> msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
> }
>
> - a6xx_get_debugbus(gpu, a6xx_state);
> + if (snapshot_debugbus)
> + a6xx_get_debugbus(gpu, a6xx_state);
>
> return &a6xx_state->base;
> }
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
> b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 4e84f3c76f4f..9eeb46bf2a5d 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -14,6 +14,10 @@ bool hang_debug = false;
> MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be
> slow!)");
> module_param_named(hang_debug, hang_debug, bool, 0600);
>
> +bool snapshot_debugbus = false;
> +MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU
> devcoredump (if not fused off)");
> +module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
> +
> static const struct adreno_info gpulist[] = {
> {
> .rev = ADRENO_REV(2, 0, 0, 0),
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 99bb468f5f24..e55abae365b5 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -21,6 +21,8 @@
> #define REG_SKIP ~0
> #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
>
> +extern bool snapshot_debugbus;
> +
> /**
> * adreno_regs: List of registers that are used in across all
> * 3D devices. Each device type has different offset value for the same
> --
> 2.26.2
>
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