Re: [Freedreno] [PATCH] drm/msm/dp: remove most of usbpd-related remains
On Sat 15 May 14:56 CDT 2021, Dmitry Baryshkov wrote: > Remove most of remains of downstream usbpd code. Mainline kernel uses > different approach for managing Type-C / USB-PD, so this remains unused. > Do not touch usbpd callbacks for now, since they look usefull enough as > an example of how to handle connect/disconnect (to be rewritten into . > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/Makefile| 1 - > drivers/gpu/drm/msm/dp/dp_ctrl.c| 4 +- > drivers/gpu/drm/msm/dp/dp_ctrl.h| 3 +- > drivers/gpu/drm/msm/dp/dp_debug.c | 6 +-- > drivers/gpu/drm/msm/dp/dp_debug.h | 4 +- > drivers/gpu/drm/msm/dp/dp_display.c | 36 ++- > drivers/gpu/drm/msm/dp/dp_hpd.c | 69 - > drivers/gpu/drm/msm/dp/dp_hpd.h | 51 - > drivers/gpu/drm/msm/dp/dp_power.c | 2 +- > drivers/gpu/drm/msm/dp/dp_power.h | 3 +- > 10 files changed, 11 insertions(+), 168 deletions(-) > delete mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.c > [..] > diff --git a/drivers/gpu/drm/msm/dp/dp_hpd.c b/drivers/gpu/drm/msm/dp/dp_hpd.c It seems to me that this would be a reasonable place to plug in the typec_mux stuff. And as we're starting that exercise we should perhaps hold off on applying until we've figured out how that would look? Regards, Bjorn ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v1 3/3] drm/msm/dpu: simplify interrupt managing
On Sun 11 Apr 19:09 CDT 2021, Dmitry Baryshkov wrote:
> Change huge lookup table to contain just sensible entries. IRQ index is
> now not an index in the table, but just register id (multiplied by 32,
> the amount of IRQs in the register) plus offset in the register. This
> allows us to remove all the "reserved" entries from dpu_irq_map. The
> table is now only used for lookups, individual functions calculate
> register and mask using the irq_idx.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 10 +-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1151 +++--
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |4 +-
> 3 files changed, 196 insertions(+), 969 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index fd11a2aeab6c..4e2ad03df903 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -70,7 +70,7 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms,
> int irq_idx)
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -133,7 +133,7 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms,
> int irq_idx)
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -208,7 +208,7 @@ int dpu_core_irq_register_callback(struct dpu_kms
> *dpu_kms, int irq_idx,
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -243,7 +243,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms
> *dpu_kms, int irq_idx,
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -328,7 +328,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
> spin_lock_init(_kms->irq_obj.cb_lock);
>
> /* Create irq callbacks for all possible irq_idx */
> - dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
> + dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
> dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
> sizeof(struct list_head), GFP_KERNEL);
> dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 8bd22e060437..2cb6800047c3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -32,142 +32,142 @@
> /**
> * WB interrupt status bit definitions
> */
> -#define DPU_INTR_WB_0_DONE BIT(0)
> -#define DPU_INTR_WB_1_DONE BIT(1)
> -#define DPU_INTR_WB_2_DONE BIT(4)
> +#define DPU_INTR_WB_0_DONE 0
> +#define DPU_INTR_WB_1_DONE 1
> +#define DPU_INTR_WB_2_DONE 4
>
> /**
> * WDOG timer interrupt status bit definitions
> */
> -#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
> -#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
> -#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
> -#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
> -#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
> +#define DPU_INTR_WD_TIMER_0_DONE 2
> +#define DPU_INTR_WD_TIMER_1_DONE 3
> +#define DPU_INTR_WD_TIMER_2_DONE 5
> +#define DPU_INTR_WD_TIMER_3_DONE 6
> +#define DPU_INTR_WD_TIMER_4_DONE 7
>
> /**
> * Pingpong interrupt status bit definitions
> */
> -#define DPU_INTR_PING_PONG_0_DONE BIT(8)
> -#define DPU_INTR_PING_PONG_1_DONE BIT(9)
> -#define DPU_INTR_PING_PONG_2_DONE BIT(10)
> -#define DPU_INTR_PING_PONG_3_DONE BIT(11)
> -#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
> -#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
> -#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
> -#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
> -#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
> -#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
> -#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
> -#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
> -#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
> -#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
> -#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
>
Re: [Freedreno] [PATCH v1 2/3] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock
On Sun 11 Apr 19:09 CDT 2021, Dmitry Baryshkov wrote:
> Always call dpu_hw_intr_clear_intr_status_nolock() from the
> dpu_hw_intr_dispatch_irqs(). This simplifies the callback function
> (which call clears the interrupts anyway) and enforces clearing the hw
> interrupt status.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 9 -
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 39 +--
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 9 -
> 3 files changed, 18 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index 54b34746a587..fd11a2aeab6c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -41,15 +41,6 @@ static void dpu_core_irq_callback_handler(void *arg, int
> irq_idx)
> if (cb->func)
> cb->func(cb->arg, irq_idx);
> spin_unlock_irqrestore(_kms->irq_obj.cb_lock, irq_flags);
> -
> - /*
> - * Clear pending interrupt status in HW.
> - * NOTE: dpu_core_irq_callback_handler is protected by top-level
> - * spinlock, so it is safe to clear any interrupt status here.
> - */
> - dpu_kms->hw_intr->ops.clear_intr_status_nolock(
> - dpu_kms->hw_intr,
> - irq_idx);
> }
>
> int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index cf9bfd45aa59..8bd22e060437 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -1362,6 +1362,22 @@ static int dpu_hw_intr_irqidx_lookup(struct
> dpu_hw_intr *intr,
> return -EINVAL;
> }
>
> +static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
> + int irq_idx)
> +{
> + int reg_idx;
> +
> + if (!intr)
> + return;
> +
> + reg_idx = dpu_irq_map[irq_idx].reg_idx;
> + DPU_REG_WRITE(>hw, dpu_intr_set[reg_idx].clr_off,
> + dpu_irq_map[irq_idx].irq_mask);
> +
> + /* ensure register writes go through */
> + wmb();
> +}
> +
> static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
> void (*cbfunc)(void *, int),
> void *arg)
> @@ -1430,9 +1446,8 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr
> *intr,
>*/
> if (cbfunc)
> cbfunc(arg, irq_idx);
> - else
> - intr->ops.clear_intr_status_nolock(
> - intr, irq_idx);
> +
> + dpu_hw_intr_clear_intr_status_nolock(intr,
> irq_idx);
>
> /*
>* When callback finish, clear the irq_status
> @@ -1597,23 +1612,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr
> *intr)
> return 0;
> }
>
> -
> -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
> - int irq_idx)
> -{
> - int reg_idx;
> -
> - if (!intr)
> - return;
> -
> - reg_idx = dpu_irq_map[irq_idx].reg_idx;
> - DPU_REG_WRITE(>hw, dpu_intr_set[reg_idx].clr_off,
> - dpu_irq_map[irq_idx].irq_mask);
> -
> - /* ensure register writes go through */
> - wmb();
> -}
> -
> static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
> int irq_idx, bool clear)
> {
> @@ -1655,7 +1653,6 @@ static void __setup_intr_ops(struct dpu_hw_intr_ops
> *ops)
> ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
> ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
> ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
> - ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
> ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 5a1c304ba93f..5bade5637ecc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -142,15 +142,6 @@ struct dpu_hw_intr_ops {
> void (*cbfunc)(void *arg, int irq_idx),
> void *arg);
>
> - /**
> - * clear_intr_status_nolock() - clears the HW interrupts without lock
> - * @intr: HW interrupt handle
> - * @irq_idx:Lookup irq index return from irq_idx_lookup
> - */
> - void (*clear_intr_status_nolock)(
> - struct dpu_hw_intr *intr,
> - int irq_idx);
> -
> /**
>
Re: [Freedreno] [PATCH v1 1/3] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs
On Sun 11 Apr 19:09 CDT 2021, Dmitry Baryshkov wrote:
> There is little sense in reading interrupt statuses and right after that
> going after the array of statuses to dispatch them. Merge both loops
> into single function doing read and dispatch.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 10 +--
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 66 ++-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 8 ---
> 3 files changed, 20 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index cdec3fbe6ff4..54b34746a587 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -376,15 +376,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
>
> irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
> {
> - /*
> - * Read interrupt status from all sources. Interrupt status are
> - * stored within hw_intr.
> - * Function will also clear the interrupt status after reading.
> - * Individual interrupt status bit will only get stored if it
> - * is enabled.
> - */
> - dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr);
> -
> /*
>* Dispatch to HW driver to handle interrupt lookup that is being
>* fired. When matching interrupt is located, HW driver will call to
> @@ -392,6 +383,7 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
>* dpu_core_irq_callback_handler will perform the registered function
>* callback, and do the interrupt status clearing once the registered
>* callback is finished.
> + * Function will also clear the interrupt status after reading.
>*/
> dpu_kms->hw_intr->ops.dispatch_irqs(
> dpu_kms->hw_intr,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 48c96b812126..cf9bfd45aa59 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -1371,6 +1371,7 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr
> *intr,
> int start_idx;
> int end_idx;
> u32 irq_status;
> + u32 enable_mask;
> unsigned long irq_flags;
>
> if (!intr)
> @@ -1383,8 +1384,6 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr
> *intr,
>*/
> spin_lock_irqsave(>irq_lock, irq_flags);
> for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> - irq_status = intr->save_irq_status[reg_idx];
> -
> /*
>* Each Interrupt register has a range of 64 indexes, and
>* that is static for dpu_irq_map.
> @@ -1396,6 +1395,20 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
> start_idx >= ARRAY_SIZE(dpu_irq_map))
> continue;
>
> + /* Read interrupt status */
> + irq_status = DPU_REG_READ(>hw,
> dpu_intr_set[reg_idx].status_off);
> +
> + /* Read enable mask */
> + enable_mask = DPU_REG_READ(>hw,
> dpu_intr_set[reg_idx].en_off);
> +
> + /* and clear the interrupt */
> + if (irq_status)
> + DPU_REG_WRITE(>hw, dpu_intr_set[reg_idx].clr_off,
> + irq_status);
> +
> + /* Finally update IRQ status based on enable mask */
> + irq_status &= enable_mask;
> +
> /*
>* Search through matching intr status from irq map.
>* start_idx and end_idx defined the search range in
> @@ -1429,6 +1442,10 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
> irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
> }
> }
> +
> + /* ensure register writes go through */
> + wmb();
> +
> spin_unlock_irqrestore(>irq_lock, irq_flags);
> }
>
> @@ -1580,41 +1597,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr
> *intr)
> return 0;
> }
>
> -static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
> -{
> - int i;
> - u32 enable_mask;
> - unsigned long irq_flags;
> -
> - if (!intr)
> - return;
> -
> - spin_lock_irqsave(>irq_lock, irq_flags);
> - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> - if (!test_bit(i, >irq_mask))
> - continue;
> -
> - /* Read interrupt status */
> - intr->save_irq_status[i] = DPU_REG_READ(>hw,
> - dpu_intr_set[i].status_off);
> -
> - /* Read enable mask */
> - enable_mask = DPU_REG_READ(>hw, dpu_intr_set[i].en_off);
> -
> - /* and clear the
Re: [Freedreno] [PATCH 3/4] drm/msm/dpu: Add SC8180x to hw catalog
On Wed 12 May 17:58 CDT 2021, Dmitry Baryshkov wrote:
> On Tue, 11 May 2021 at 07:19, Bjorn Andersson
> wrote:
> >
> > From: Rob Clark
> >
> > Add SC8180x to the hardware catalog, for initial support for the
> > platform. Due to limitations in the DP driver only one of the four DP
> > interfaces is left enabled.
> >
> > The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
> > the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
> > is flagged appropriately to ensure widebus is disabled - for now.
> >
> > Signed-off-by: Rob Clark
> > Signed-off-by: Bjorn Andersson
> > ---
> > .../devicetree/bindings/display/msm/dpu.txt | 4 +-
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 121 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> > drivers/gpu/drm/msm/msm_drv.c | 1 +
> > 5 files changed, 128 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
> > b/Documentation/devicetree/bindings/display/msm/dpu.txt
> > index 586e6eac5b08..b98258374a60 100644
> > --- a/Documentation/devicetree/bindings/display/msm/dpu.txt
> > +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
> > @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
> >
> > MDSS:
> > Required properties:
> > -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
> > +- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sc8180x-mdss"
> > - reg: physical base address and length of controller's registers.
> > - reg-names: register region names. The following region is required:
> >* "mdss"
> > @@ -41,7 +41,7 @@ Optional properties:
> >
> > MDP:
> > Required properties:
> > -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
> > +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sc8180x-dpu"
> > - reg: physical base address and length of controller's registers.
> > - reg-names : register region names. The following region is required:
> >* "mdp"
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index b569030a0847..81c429ce94a9 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -56,6 +56,10 @@
> >
> > #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
> >
> > +#define INTF_SC8180X_MASK BIT(DPU_INTF_INPUT_CTRL) | \
> > + BIT(DPU_INTF_TE) | \
> > + BIT(DPU_INTF_WIDEBUS)
> > +
> > #define INTR_SC7180_MASK \
> > (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
> > BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
> > @@ -197,6 +201,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
> > .max_vdeci_exp = MAX_VERT_DECIMATION,
> > };
> >
> > +static const struct dpu_caps sc8180_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0xb,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED3,
>
> Is it qseed3 or qseed3lite?
>
> > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > + .ubwc_version = DPU_HW_UBWC_VER_30,
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .has_3d_merge = false, /* I think? */
>
> Hmm. Are you sure? Judging from two DSI interfaces you might have merge3d.
>
> > + .max_linewidth = 4096,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > + .max_hdeci_exp = MAX_HORZ_DECIMATION,
> > + .max_vdeci_exp = MAX_VERT_DECIMATION,
> > +};
> > +
> > static const struct dpu_caps sm8250_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0xb,
> > @@ -265,6 +285,35 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
> > },
> > };
> >
> > +static const struct dpu_mdp_cfg sc8180_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + // TODO check len
> > + .base = 0x0, .len = 0x45C,
> > + .features = 0,
> > + .highest_bank_bit = 0x3,
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > + .reg_off = 0x2AC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > + .reg_off = 0x2B4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > + .reg_off = 0x2BC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > + .reg_off = 0x2C4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > + .reg_off = 0x2AC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > + .reg_off = 0x2B4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > + .reg_off = 0x2BC, .bit_off = 8},
> > +
Re: [Freedreno] [PATCH v2 5/6] drm/msm/dpu: drop unused lm_max_width from RM
Hi Dmitry,
Le dim. 16 mai 2021 à 00:58, Dmitry Baryshkov
a écrit :
>
> No code uses lm_max_width from resource manager, so drop it.
I have a pending patch which uses this value to properly determine the
number of LMs to use in the topology. Currently the code uses a
hardcoded value of MAX_HDISPLAY_SPLIT (1080), but in reality I believe
it should be the lm max width (typically 2560). This will avoid using
two LMs to render resolutions like 1280x720 or 1920x1080.
I haven't managed to make hdmi work yet on DPU (testing on MSM8998) so
I'm not ready to send the patch yet, but it doesn't seem to trigger
any error.
-Arnaud
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 4
> 2 files changed, 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index c36700a06ff2..ec4387ad1182 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -88,18 +88,6 @@ int dpu_rm_init(struct dpu_rm *rm,
> goto fail;
> }
> rm->mixer_blks[lm->id - LM_0] = >base;
> -
> - if (!rm->lm_max_width) {
> - rm->lm_max_width = lm->sblk->maxwidth;
> - } else if (rm->lm_max_width != lm->sblk->maxwidth) {
> - /*
> -* Don't expect to have hw where lm max widths differ.
> -* If found, take the min.
> -*/
> - DPU_ERROR("unsupported: lm maxwidth differs\n");
> - if (rm->lm_max_width > lm->sblk->maxwidth)
> - rm->lm_max_width = lm->sblk->maxwidth;
> - }
> }
>
> for (i = 0; i < cat->ctl_count; i++) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index ee90b1233430..0c9113581d71 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -17,14 +17,10 @@ struct dpu_global_state;
> * struct dpu_rm - DPU dynamic hardware resource manager
> * @mixer_blks: array of layer mixer hardware resources
> * @ctl_blks: array of ctl hardware resources
> - * @lm_max_width: cached layer mixer maximum width
> - * @rm_lock: resource manager mutex
> */
> struct dpu_rm {
> struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
> struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
> -
> - uint32_t lm_max_width;
> };
>
> struct dpu_kms;
> --
> 2.30.2
>
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[Freedreno] [PATCH v2 5/6] drm/msm/dpu: drop unused lm_max_width from RM
No code uses lm_max_width from resource manager, so drop it.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 4
2 files changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index c36700a06ff2..ec4387ad1182 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -88,18 +88,6 @@ int dpu_rm_init(struct dpu_rm *rm,
goto fail;
}
rm->mixer_blks[lm->id - LM_0] = >base;
-
- if (!rm->lm_max_width) {
- rm->lm_max_width = lm->sblk->maxwidth;
- } else if (rm->lm_max_width != lm->sblk->maxwidth) {
- /*
-* Don't expect to have hw where lm max widths differ.
-* If found, take the min.
-*/
- DPU_ERROR("unsupported: lm maxwidth differs\n");
- if (rm->lm_max_width > lm->sblk->maxwidth)
- rm->lm_max_width = lm->sblk->maxwidth;
- }
}
for (i = 0; i < cat->ctl_count; i++) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index ee90b1233430..0c9113581d71 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -17,14 +17,10 @@ struct dpu_global_state;
* struct dpu_rm - DPU dynamic hardware resource manager
* @mixer_blks: array of layer mixer hardware resources
* @ctl_blks: array of ctl hardware resources
- * @lm_max_width: cached layer mixer maximum width
- * @rm_lock: resource manager mutex
*/
struct dpu_rm {
struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
-
- uint32_t lm_max_width;
};
struct dpu_kms;
--
2.30.2
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[Freedreno] [PATCH v2 6/6] drm/msm/dpu: simplify peer LM handling
For each LM there is at max 1 peer LM which can be driven by the same
CTL, so there no need to have a mask instead of just an ID of the peer
LM.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 4 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 30 +--
3 files changed, 11 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b569030a0847..e7b132dce849 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -571,7 +571,7 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
.features = _fmask, \
.sblk = _sblk, \
.pingpong = _pp, \
- .lm_pair_mask = (1 << _lmpair), \
+ .lm_pair = _lmpair, \
.dspp = _dspp \
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4dfd8a20ad5c..3199bf8dc085 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -498,14 +498,14 @@ struct dpu_sspp_cfg {
* @features bit mask identifying sub-blocks/features
* @sblk: LM Sub-blocks information
* @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
- * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
+ * @lm_pair: ID of LM that can be controlled by same CTL
*/
struct dpu_lm_cfg {
DPU_HW_BLK_INFO;
const struct dpu_lm_sub_blks *sblk;
u32 pingpong;
u32 dspp;
- unsigned long lm_pair_mask;
+ unsigned long lm_pair;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index ec4387ad1182..030bc30aba64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -121,28 +121,19 @@ static bool _dpu_rm_needs_split_display(const struct
msm_display_topology *top)
}
/**
- * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary
+ * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary
* @rm: dpu resource manager handle
* @primary_idx: index of primary mixer in rm->mixer_blks[]
- * @peer_idx: index of other mixer in rm->mixer_blks[]
- * Return: true if rm->mixer_blks[peer_idx] is a peer of
- * rm->mixer_blks[primary_idx]
*/
-static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx,
- int peer_idx)
+static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx)
{
const struct dpu_lm_cfg *prim_lm_cfg;
- const struct dpu_lm_cfg *peer_cfg;
prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap;
- peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap;
- if (!test_bit(peer_cfg->id, _lm_cfg->lm_pair_mask)) {
- DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id,
- peer_cfg->id);
- return false;
- }
- return true;
+ if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX)
+ return prim_lm_cfg->lm_pair - LM_0;
+ return -EINVAL;
}
static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
@@ -176,17 +167,12 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
++lm_count;
/* Valid primary mixer found, find matching peers */
- for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) &&
- lm_count < reqs->topology.num_lm; j++) {
+ j = _dpu_rm_get_lm_peer(rm, i);
+ /* ignore the peer if there is an error or if the peer was
already processed */
+ if (j < 0 || j < i) {
if (!rm->mixer_blks[j])
continue;
- if (!_dpu_rm_check_lm_peer(rm, i, j)) {
- DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j,
- LM_0 + i);
- continue;
- }
-
if (reserved_by_other(global_state->mixer_to_enc_id, j,
enc_id)) {
DPU_DEBUG("lm %d already reserved\n", j + LM_0);
continue;
--
2.30.2
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[Freedreno] [PATCH v2 2/6] drm/msm/dpu: get MERGE_3D blocks directly rather than through RM
MERGE_3D blocks are not really handled by resource manager, they are
used by corresponding PP blocks directly, each merge_3d is used by two
known PP blocks. So allocate them outside of RM and use them directly.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 7 +++-
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 4 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 29 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 36 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h| 8 ++---
6 files changed, 45 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 55766c97c4c8..3ac53ff8c2ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -8,6 +8,7 @@
#include "dpu_hwio.h"
#include "dpu_hw_catalog.h"
#include "dpu_hw_pingpong.h"
+#include "dpu_hw_merge3d.h"
#include "dpu_kms.h"
#include "dpu_trace.h"
@@ -263,7 +264,8 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
void __iomem *addr,
- const struct dpu_mdss_cfg *m)
+ const struct dpu_mdss_cfg *m,
+ struct dpu_hw_merge_3d **merge_3d_blks)
{
struct dpu_hw_pingpong *c;
const struct dpu_pingpong_cfg *cfg;
@@ -282,6 +284,9 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum
dpu_pingpong idx,
c->caps = cfg;
_setup_pingpong_ops(c, c->caps->features);
+ if (cfg->merge_3d && cfg->merge_3d < MERGE_3D_MAX)
+ c->merge_3d = merge_3d_blks[cfg->merge_3d];
+
return c;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 89d08a715c16..75e6cb393b9c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -157,11 +157,13 @@ static inline struct dpu_hw_pingpong
*to_dpu_hw_pingpong(struct dpu_hw_blk *hw)
* @idx: Pingpong index for which driver object is required
* @addr: Mapped register io address of MDP
* @m:Pointer to mdss catalog data
+ * @merge_3d_blks: Pointer to merge 3d blocks
* Returns: Error code or allocated dpu_hw_pingpong context
*/
struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
void __iomem *addr,
- const struct dpu_mdss_cfg *m);
+ const struct dpu_mdss_cfg *m,
+ struct dpu_hw_merge_3d **merge_3d_blks);
/**
* dpu_hw_pingpong_destroy - destroys pingpong driver context
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e3aed844bf82..ca89229d9f42 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -23,6 +23,7 @@
#include "dpu_kms.h"
#include "dpu_core_irq.h"
#include "dpu_formats.h"
+#include "dpu_hw_merge3d.h"
#include "dpu_hw_vbif.h"
#include "dpu_vbif.h"
#include "dpu_encoder.h"
@@ -688,6 +689,16 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
dpu_rm_destroy(_kms->rm);
dpu_kms->rm_init = false;
+ /* After RM destroy, as PP blocks reference MERGE_3D blocks */
+ if (dpu_kms->catalog) {
+ for (i = 0; i < dpu_kms->catalog->merge_3d_count; i++) {
+ u32 merge_3d_idx = dpu_kms->catalog->merge_3d[i].id;
+
+ if ((merge_3d_idx < MERGE_3D_MAX) &&
dpu_kms->hw_merge_3d[merge_3d_idx])
+
dpu_hw_merge_3d_destroy(dpu_kms->hw_merge_3d[merge_3d_idx]);
+ }
+ }
+
if (dpu_kms->catalog)
dpu_hw_catalog_deinit(dpu_kms->catalog);
dpu_kms->catalog = NULL;
@@ -962,7 +973,23 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto power_error;
}
- rc = dpu_rm_init(_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
+ /* Before RM init so PP blocks can find MERGE_3D blocks */
+ for (i = 0; i < dpu_kms->catalog->merge_3d_count; i++) {
+ u32 merge_3d_idx = dpu_kms->catalog->merge_3d[i].id;
+
+ dpu_kms->hw_merge_3d[merge_3d_idx] =
dpu_hw_merge_3d_init(merge_3d_idx,
+ dpu_kms->mmio, dpu_kms->catalog);
+ if (IS_ERR_OR_NULL(dpu_kms->hw_merge_3d[merge_3d_idx])) {
+ rc = PTR_ERR(dpu_kms->hw_merge_3d[merge_3d_idx]);
+ if (!dpu_kms->hw_merge_3d[merge_3d_idx])
+ rc = -EINVAL;
+ DPU_ERROR("failed to init merge_3d %d: %d\n",
merge_3d_idx, rc);
+ dpu_kms->hw_merge_3d[merge_3d_idx] = NULL;
+ goto power_error;
+ }
+ }
+
+ rc =
[Freedreno] [PATCH v2 3/6] drm/msm/dpu: get PINGPONG blocks directly rather than through RM
Each PINGPONG block is tied to a single LM. No LMs can share single PINGPONG
block. So there is no need to handle PINGPONG blocks through all resource
allocation/deallocation/assignment, just receive PINGPONG block as a part of
LM hardware instance.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 10 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 99 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 +-
7 files changed, 25 insertions(+), 114 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 2b750da8b30c..3f4d2ba53604 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1004,10 +1004,9 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
struct drm_crtc *drm_crtc;
struct dpu_crtc_state *cstate;
struct dpu_global_state *global_state;
- struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
- int num_lm, num_ctl, num_pp;
+ int num_lm, num_ctl;
int i, j;
if (!drm_enc) {
@@ -1050,18 +1049,11 @@ static void dpu_encoder_virt_mode_set(struct
drm_encoder *drm_enc,
break;
/* Query resource that have been reserved in atomic check step. */
- num_pp = dpu_rm_get_assigned_resources(_kms->rm, global_state,
- drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
- ARRAY_SIZE(hw_pp));
num_ctl = dpu_rm_get_assigned_resources(_kms->rm, global_state,
drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
num_lm = dpu_rm_get_assigned_resources(_kms->rm, global_state,
drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
- dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
- : NULL;
-
cstate = to_dpu_crtc_state(drm_crtc->state);
for (i = 0; i < num_lm; i++) {
@@ -1070,6 +1062,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
cstate->mixers[i].hw_dspp = cstate->mixers[i].hw_lm->dspp;
+
+ dpu_enc->hw_pp[i] = cstate->mixers[i].hw_lm->pingpong;
}
cstate->num_mixers = num_lm;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 7f02078db7e7..04a835b9c2a3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -8,6 +8,7 @@
#include "dpu_hw_dspp.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_mdss.h"
+#include "dpu_hw_pingpong.h"
#define LM_OP_MODE0x00
#define LM_OUT_SIZE 0x04
@@ -163,7 +164,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m,
struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
void __iomem *addr,
- const struct dpu_mdss_cfg *m)
+ const struct dpu_mdss_cfg *m,
+ struct dpu_hw_merge_3d **merge_3d_blks)
{
struct dpu_hw_mixer *c;
const struct dpu_lm_cfg *cfg;
@@ -185,13 +187,17 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
if (cfg->dspp && cfg->dspp < DSPP_MAX)
c->dspp = dpu_hw_dspp_init(cfg->dspp, addr, m);
+ if (cfg->pingpong && cfg->pingpong < PINGPONG_MAX)
+ c->pingpong = dpu_hw_pingpong_init(cfg->pingpong, addr, m,
merge_3d_blks);
return c;
}
void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
{
- if (lm)
+ if (lm) {
dpu_hw_dspp_destroy(lm->dspp);
+ dpu_hw_pingpong_destroy(lm->pingpong);
+ }
kfree(lm);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
index effb78311a43..182740f2914b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
@@ -64,6 +64,7 @@ struct dpu_hw_mixer {
const struct dpu_lm_cfg *cap;
const struct dpu_mdp_cfg *mdp;
const struct dpu_ctl_cfg *ctl;
+ struct dpu_hw_pingpong *pingpong;
struct dpu_hw_dspp *dspp;
/* ops */
@@ -83,16 +84,19 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct
dpu_hw_blk *hw)
return container_of(hw, struct dpu_hw_mixer, base);
}
+struct dpu_hw_merge_3d;
/**
* dpu_hw_lm_init(): Initializes
[Freedreno] (no subject)
>From Dmitry Baryshkov # This line is ignored. From: Dmitry Baryshkov Reply-To: Subject: [PATCH v2 0/6] drm/msm/dpu: simplify RM code In-Reply-To: There is no need to request most of hardware blocks through the resource manager (RM), since typically there is 1:1 or N:1 relationship between corresponding blocks. Each LM is tied to the single PP. Each MERGE_3D can be used by the specified pair of PPs. Each DSPP is also tied to single LM. So instead of allocating them through the RM, get them via static configuration. Depends on: https://lore.kernel.org/linux-arm-msm/20210515190909.1809050-1-dmitry.barysh...@linaro.org Changes since v1: - Split into separate patch series to ease review. Dmitry Baryshkov (6): drm/msm/dpu: get DSPP blocks directly rather than through RM drm/msm/dpu: get MERGE_3D blocks directly rather than through RM drm/msm/dpu: get PINGPONG blocks directly rather than through RM drm/msm/dpu: get INTF blocks directly rather than through RM drm/msm/dpu: drop unused lm_max_width from RM drm/msm/dpu: simplify peer LM handling drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 54 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 8 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 - .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 - .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c| 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h| 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 53 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 310 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 18 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 +- 16 files changed, 115 insertions(+), 401 deletions(-) ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 1/6] drm/msm/dpu: get DSPP blocks directly rather than through RM
Each DSPP block is tied to a single LM. No LMs can share single DSPP
block. So there is no need to handle DSPP blocks through all resource
allocation/deallocation/assignment, just receive DSPP block as a part of
LM hardware instance.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 50 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 -
6 files changed, 11 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 8d942052db8a..2b750da8b30c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1007,7 +1007,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
- struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
int num_lm, num_ctl, num_pp;
int i, j;
@@ -1058,9 +1057,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
num_lm = dpu_rm_get_assigned_resources(_kms->rm, global_state,
drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
- dpu_rm_get_assigned_resources(_kms->rm, global_state,
- drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
- ARRAY_SIZE(hw_dspp));
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
@@ -1073,7 +1069,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
- cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
+ cstate->mixers[i].hw_dspp = cstate->mixers[i].hw_lm->dspp;
}
cstate->num_mixers = num_lm;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index cb6bb7a22c15..7f02078db7e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -5,6 +5,7 @@
#include "dpu_kms.h"
#include "dpu_hw_catalog.h"
#include "dpu_hwio.h"
+#include "dpu_hw_dspp.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_mdss.h"
@@ -182,10 +183,15 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
c->cap = cfg;
_setup_mixer_ops(m, >ops, c->cap->features);
+ if (cfg->dspp && cfg->dspp < DSPP_MAX)
+ c->dspp = dpu_hw_dspp_init(cfg->dspp, addr, m);
+
return c;
}
void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
{
+ if (lm)
+ dpu_hw_dspp_destroy(lm->dspp);
kfree(lm);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
index 4a6b2de19ef6..effb78311a43 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
@@ -64,6 +64,7 @@ struct dpu_hw_mixer {
const struct dpu_lm_cfg *cap;
const struct dpu_mdp_cfg *mdp;
const struct dpu_ctl_cfg *ctl;
+ struct dpu_hw_dspp *dspp;
/* ops */
struct dpu_hw_lm_ops ops;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index d6717d6672f7..195a854245fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -164,7 +164,6 @@ struct dpu_global_state {
uint32_t mixer_to_enc_id[LM_MAX - LM_0];
uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
- uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
};
struct dpu_global_state
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f9c83d6e427a..6e7b5578cc81 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -9,7 +9,6 @@
#include "dpu_hw_ctl.h"
#include "dpu_hw_pingpong.h"
#include "dpu_hw_intf.h"
-#include "dpu_hw_dspp.h"
#include "dpu_hw_merge3d.h"
#include "dpu_encoder.h"
#include "dpu_trace.h"
@@ -204,23 +203,6 @@ int dpu_rm_init(struct dpu_rm *rm,
rm->ctl_blks[ctl->id - CTL_0] = >base;
}
- for (i = 0; i < cat->dspp_count; i++) {
- struct dpu_hw_dspp *hw;
- const struct dpu_dspp_cfg *dspp = >dspp[i];
-
- if (dspp->id < DSPP_0 || dspp->id >= DSPP_MAX) {
- DPU_ERROR("skip dspp %d with invalid id\n", dspp->id);
-
[Freedreno] [PATCH] drm/msm/dp: remove most of usbpd-related remains
Remove most of remains of downstream usbpd code. Mainline kernel uses
different approach for managing Type-C / USB-PD, so this remains unused.
Do not touch usbpd callbacks for now, since they look usefull enough as
an example of how to handle connect/disconnect (to be rewritten into .
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile| 1 -
drivers/gpu/drm/msm/dp/dp_ctrl.c| 4 +-
drivers/gpu/drm/msm/dp/dp_ctrl.h| 3 +-
drivers/gpu/drm/msm/dp/dp_debug.c | 6 +--
drivers/gpu/drm/msm/dp/dp_debug.h | 4 +-
drivers/gpu/drm/msm/dp/dp_display.c | 36 ++-
drivers/gpu/drm/msm/dp/dp_hpd.c | 69 -
drivers/gpu/drm/msm/dp/dp_hpd.h | 51 -
drivers/gpu/drm/msm/dp/dp_power.c | 2 +-
drivers/gpu/drm/msm/dp/dp_power.h | 3 +-
10 files changed, 11 insertions(+), 168 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dp/dp_hpd.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 610d630326bb..8a58c1615d38 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -107,7 +107,6 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_ctrl.o \
dp/dp_display.o \
dp/dp_drm.o \
- dp/dp_hpd.o \
dp/dp_link.o \
dp/dp_panel.o \
dp/dp_parser.o \
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 1390f3547fde..7bb0f6a9b731 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1364,7 +1364,7 @@ static int dp_ctrl_enable_stream_clocks(struct
dp_ctrl_private *ctrl)
return ret;
}
-int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
+int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool reset)
{
struct dp_ctrl_private *ctrl;
struct dp_io *dp_io;
@@ -1379,8 +1379,6 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip,
bool reset)
dp_io = >parser->io;
phy = dp_io->phy;
- ctrl->dp_ctrl.orientation = flip;
-
if (reset)
dp_catalog_ctrl_reset(ctrl->catalog);
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index a836bd358447..682c3c511e8e 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -14,12 +14,11 @@
#include "dp_catalog.h"
struct dp_ctrl {
- bool orientation;
atomic_t aborted;
u32 pixel_rate;
};
-int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset);
+int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool reset);
void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl);
int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl);
int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl);
diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c
b/drivers/gpu/drm/msm/dp/dp_debug.c
index 2f6247e80e9d..eb6288dcabde 100644
--- a/drivers/gpu/drm/msm/dp/dp_debug.c
+++ b/drivers/gpu/drm/msm/dp/dp_debug.c
@@ -21,7 +21,6 @@
struct dp_debug_private {
struct dentry *root;
- struct dp_usbpd *usbpd;
struct dp_link *link;
struct dp_panel *panel;
struct drm_connector **connector;
@@ -390,14 +389,14 @@ static int dp_debug_init(struct dp_debug *dp_debug,
struct drm_minor *minor)
}
struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
- struct dp_usbpd *usbpd, struct dp_link *link,
+ struct dp_link *link,
struct drm_connector **connector, struct drm_minor *minor)
{
int rc = 0;
struct dp_debug_private *debug;
struct dp_debug *dp_debug;
- if (!dev || !panel || !usbpd || !link) {
+ if (!dev || !panel || !link) {
DRM_ERROR("invalid input\n");
rc = -EINVAL;
goto error;
@@ -410,7 +409,6 @@ struct dp_debug *dp_debug_get(struct device *dev, struct
dp_panel *panel,
}
debug->dp_debug.debug_en = false;
- debug->usbpd = usbpd;
debug->link = link;
debug->panel = panel;
debug->dev = dev;
diff --git a/drivers/gpu/drm/msm/dp/dp_debug.h
b/drivers/gpu/drm/msm/dp/dp_debug.h
index 7eaedfbb149c..c5da109143da 100644
--- a/drivers/gpu/drm/msm/dp/dp_debug.h
+++ b/drivers/gpu/drm/msm/dp/dp_debug.h
@@ -42,7 +42,7 @@ struct dp_debug {
* for debugfs input to be communicated with existing modules
*/
struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
- struct dp_usbpd *usbpd, struct dp_link *link,
+ struct dp_link *link,
struct drm_connector **connector,
struct drm_minor *minor);
@@ -59,7 +59,7 @@ void dp_debug_put(struct dp_debug *dp_debug);
static inline
struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
- struct dp_usbpd *usbpd, struct dp_link *link,
+ struct dp_link *link,
struct drm_connector **connector, struct drm_minor *minor)
[Freedreno] [PATCH v3 4/4] drm/msm/dpu: hw_blk: make dpu_hw_blk empty opaque structure
The code does not really use dpu_hw_blk fields, so drop them, making
dpu_hw_blk empty structure.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c| 24 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h| 4 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 2 --
.../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c| 2 --
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 2 +-
12 files changed, 2 insertions(+), 45 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 610d630326bb..55dbde30c2a2 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -58,7 +58,6 @@ msm-y := \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
disp/dpu1/dpu_formats.o \
- disp/dpu1/dpu_hw_blk.o \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_interrupts.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
deleted file mode 100644
index 1f2b74b9eb65..
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- */
-
-#define pr_fmt(fmt)"[drm:%s:%d] " fmt, __func__, __LINE__
-
-#include
-#include
-#include
-
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_blk.h"
-
-/**
- * dpu_hw_blk_init - initialize hw block object
- * @hw_blk: pointer to hw block object
- * @type: hw block type - enum dpu_hw_blk_type
- * @id: instance id of the hw block
- */
-void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id)
-{
- hw_blk->type = type;
- hw_blk->id = id;
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
index 7768694b558a..52e92f37eda4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
@@ -19,9 +19,7 @@ struct dpu_hw_blk;
* @refcount: reference/usage count
*/
struct dpu_hw_blk {
- u32 type;
- int id;
+ /* opaque */
};
-void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id);
#endif /*_DPU_HW_BLK_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 441f66a4fb37..f8a74f6cdc4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -613,8 +613,6 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
c->mixer_count = m->mixer_count;
c->mixer_hw_caps = m->mixer;
- dpu_hw_blk_init(>base, DPU_HW_BLK_CTL, idx);
-
return c;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 977b25968f34..a98e964c3b6f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -110,8 +110,6 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
c->cap = cfg;
_setup_dspp_ops(c, c->cap->features);
- dpu_hw_blk_init(>base, DPU_HW_BLK_DSPP, idx);
-
return c;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 17224556d5a8..116e2b5b1a90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -325,8 +325,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
c->mdss = m;
_setup_intf_ops(>ops, c->cap->features);
- dpu_hw_blk_init(>base, DPU_HW_BLK_INTF, idx);
-
return c;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 76f8b8f75b82..cb6bb7a22c15 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -182,8 +182,6 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
c->cap = cfg;
_setup_mixer_ops(m, >ops, c->cap->features);
- dpu_hw_blk_init(>base, DPU_HW_BLK_LM, idx);
-
return c;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index 406ba950a066..c06d595d5df0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -79,8 +79,6 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum
dpu_merge_3d idx,
c->caps = cfg;
_setup_merge_3d_ops(c,
[Freedreno] [PATCH v3 3/4] drm/msm/dpu: use struct dpu_hw_merge_3d in dpu_hw_pingpong
Use struct dpu_hw_merge_3d pointer in struct dpu_hw_pingpong rather
than using struct dpu_hw_blk. This is the only user of dpu_hw_blk.id,
which will be cleaned in the next patch.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 4 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 0e06b7e73c7a..4feec24162bc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -284,7 +284,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
if (phys_enc->hw_pp->merge_3d)
- intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id;
+ intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
@@ -298,11 +298,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
true,
phys_enc->hw_pp->idx);
- if (phys_enc->hw_pp->merge_3d) {
- struct dpu_hw_merge_3d *merge_3d =
to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d);
-
- merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d);
- }
+ if (phys_enc->hw_pp->merge_3d)
+
phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
intf_cfg.mode_3d);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
@@ -461,7 +458,7 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)
- ctl->ops.update_pending_flush_merge_3d(ctl,
phys_enc->hw_pp->merge_3d->id);
+ ctl->ops.update_pending_flush_merge_3d(ctl,
phys_enc->hw_pp->merge_3d->idx);
skip_flush:
DPU_DEBUG_VIDENC(phys_enc,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 845b9ce80e31..89d08a715c16 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -126,6 +126,8 @@ struct dpu_hw_pingpong_ops {
struct dpu_hw_dither_cfg *cfg);
};
+struct dpu_hw_merge_3d;
+
struct dpu_hw_pingpong {
struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw;
@@ -133,7 +135,7 @@ struct dpu_hw_pingpong {
/* pingpong */
enum dpu_pingpong idx;
const struct dpu_pingpong_cfg *caps;
- struct dpu_hw_blk *merge_3d;
+ struct dpu_hw_merge_3d *merge_3d;
/* ops */
struct dpu_hw_pingpong_ops ops;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index fd2d104f0a91..c0eec12498e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -162,7 +162,7 @@ int dpu_rm_init(struct dpu_rm *rm,
goto fail;
}
if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX)
- hw->merge_3d = rm->merge_3d_blks[pp->merge_3d -
MERGE_3D_0];
+ hw->merge_3d =
to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]);
rm->pingpong_blks[pp->id - PINGPONG_0] = >base;
}
--
2.30.2
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[Freedreno] [PATCH v3 2/4] drm/msm/dpu: drop dpu_hw_blk_destroy function
The dpu_hw_blk_destroy() function is empty, so we can drop it now.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 13 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 --
10 files changed, 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
index abad043f35f5..1f2b74b9eb65 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
@@ -22,16 +22,3 @@ void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type,
int id)
hw_blk->type = type;
hw_blk->id = id;
}
-
-/**
- * dpu_hw_blk_destroy - destroy hw block object.
- * @hw_blk: pointer to hw block object
- * return: none
- */
-void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk)
-{
- if (!hw_blk) {
- pr_err("invalid parameters\n");
- return;
- }
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
index fb3be9a36a50..7768694b558a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
@@ -24,5 +24,4 @@ struct dpu_hw_blk {
};
void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id);
-void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk);
#endif /*_DPU_HW_BLK_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 04a2c4b9a357..441f66a4fb37 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -620,7 +620,5 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx,
void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx)
{
- if (ctx)
- dpu_hw_blk_destroy(>base);
kfree(ctx);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index d2f1045a736a..977b25968f34 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -117,9 +117,6 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
{
- if (dspp)
- dpu_hw_blk_destroy(>base);
-
kfree(dspp);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 6ffe97601716..17224556d5a8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -332,8 +332,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
{
- if (intf)
- dpu_hw_blk_destroy(>base);
kfree(intf);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 554bb881de3a..76f8b8f75b82 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -189,7 +189,5 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
{
- if (lm)
- dpu_hw_blk_destroy(>base);
kfree(lm);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index 863229dd0140..406ba950a066 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -86,7 +86,5 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum
dpu_merge_3d idx,
void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw)
{
- if (hw)
- dpu_hw_blk_destroy(>base);
kfree(hw);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 334d5b28f533..92cd724263ce 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -289,7 +289,5 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum
dpu_pingpong idx,
void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
{
- if (pp)
- dpu_hw_blk_destroy(>base);
kfree(pp);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index ceb2488ea270..8734a47040aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -740,8 +740,6 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx)
[Freedreno] [PATCH v3 1/4] drm/msm/dpu: remove unused dpu_hw_blk features
Remove all unused dpu_hw_blk features and functions:
- dpu_hw_blk_get()/_put() and respective refcounting,
- global list of all dpu_hw_blk instances,
- dpu_hw_blk_ops and empty implementation inside each hw_blk subdriver.
This leaves dpu_hw_blk as a placeholder with just type and index.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c| 104 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h| 19 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 4 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c| 4 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 4 +-
10 files changed, 10 insertions(+), 145 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
index 819b26e660b9..abad043f35f5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
@@ -11,33 +11,16 @@
#include "dpu_hw_mdss.h"
#include "dpu_hw_blk.h"
-/* Serialization lock for dpu_hw_blk_list */
-static DEFINE_MUTEX(dpu_hw_blk_lock);
-
-/* List of all hw block objects */
-static LIST_HEAD(dpu_hw_blk_list);
-
/**
* dpu_hw_blk_init - initialize hw block object
* @hw_blk: pointer to hw block object
* @type: hw block type - enum dpu_hw_blk_type
* @id: instance id of the hw block
- * @ops: Pointer to block operations
*/
-void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id,
- struct dpu_hw_blk_ops *ops)
+void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id)
{
- INIT_LIST_HEAD(_blk->list);
hw_blk->type = type;
hw_blk->id = id;
- atomic_set(_blk->refcount, 0);
-
- if (ops)
- hw_blk->ops = *ops;
-
- mutex_lock(_hw_blk_lock);
- list_add(_blk->list, _hw_blk_list);
- mutex_unlock(_hw_blk_lock);
}
/**
@@ -51,89 +34,4 @@ void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk)
pr_err("invalid parameters\n");
return;
}
-
- if (atomic_read(_blk->refcount))
- pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type,
- hw_blk->id);
-
- mutex_lock(_hw_blk_lock);
- list_del(_blk->list);
- mutex_unlock(_hw_blk_lock);
-}
-
-/**
- * dpu_hw_blk_get - get hw_blk from free pool
- * @hw_blk: if specified, increment reference count only
- * @type: if hw_blk is not specified, allocate the next available of this type
- * @id: if specified (>= 0), allocate the given instance of the above type
- * return: pointer to hw block object
- */
-struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id)
-{
- struct dpu_hw_blk *curr;
- int rc, refcount;
-
- if (!hw_blk) {
- mutex_lock(_hw_blk_lock);
- list_for_each_entry(curr, _hw_blk_list, list) {
- if ((curr->type != type) ||
- (id >= 0 && curr->id != id) ||
- (id < 0 &&
- atomic_read(>refcount)))
- continue;
-
- hw_blk = curr;
- break;
- }
- mutex_unlock(_hw_blk_lock);
- }
-
- if (!hw_blk) {
- pr_debug("no hw_blk:%d\n", type);
- return NULL;
- }
-
- refcount = atomic_inc_return(_blk->refcount);
-
- if (refcount == 1 && hw_blk->ops.start) {
- rc = hw_blk->ops.start(hw_blk);
- if (rc) {
- pr_err("failed to start hw_blk:%d rc:%d\n", type, rc);
- goto error_start;
- }
- }
-
- pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type,
- hw_blk->id, refcount);
- return hw_blk;
-
-error_start:
- dpu_hw_blk_put(hw_blk);
- return ERR_PTR(rc);
-}
-
-/**
- * dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero
- * @hw_blk: hw block to be freed
- */
-void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk)
-{
- if (!hw_blk) {
- pr_err("invalid parameters\n");
- return;
- }
-
- pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id,
- atomic_read(_blk->refcount));
-
- if (!atomic_read(_blk->refcount)) {
- pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id);
- return;
- }
-
- if (atomic_dec_return(_blk->refcount))
- return;
-
- if (hw_blk->ops.stop)
- hw_blk->ops.stop(hw_blk);
}
diff --git
[Freedreno] [PATCH v3 0/3] drm/msm/dpu: simplify dpu_hw_blk handling
Drop most of "extra" features of dpu_hw_blk. Changes since v2: - Include a patch to fix compilation issue with merge3d id handling Changes since v1: - Make dpu_hw_blk an empty structure - Split this into separate patchset Dmitry Baryshkov (4): drm/msm/dpu: remove unused dpu_hw_blk features drm/msm/dpu: drop dpu_hw_blk_destroy function drm/msm/dpu: use struct dpu_hw_merge_3d in dpu_hw_pingpong drm/msm/dpu: hw_blk: make dpu_hw_blk empty opaque structure drivers/gpu/drm/msm/Makefile | 1 - .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 139 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 22 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c| 7 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c| 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h| 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 6 - drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 4 +- 14 files changed, 10 insertions(+), 220 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v2 1/1] drm/msm/dpu: Fix error return code in dpu_mdss_init()
On 10/05/2021 06:16, Zhen Lei wrote:
The error code returned by platform_get_irq() is stored in 'irq', it's
forgotten to be copied to 'ret' before being returned. As a result, the
value 0 of 'ret' is returned incorrectly.
After the above fix is completed, initializing the local variable 'ret'
to 0 is no longer needed, remove it.
In addition, when dpu_mdss_init() is successfully returned, the value of
'ret' is always 0. Therefore, replace "return ret" with "return 0" to make
the code clearer.
Fixes: 070e64dc1bbc ("drm/msm/dpu: Convert to a chained irq chip")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 06b56fec04e047a..6b0a7bc87eb75b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -225,7 +225,7 @@ int dpu_mdss_init(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct dpu_mdss *dpu_mdss;
struct dss_module_power *mp;
- int ret = 0;
+ int ret;
int irq;
dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
@@ -253,8 +253,10 @@ int dpu_mdss_init(struct drm_device *dev)
goto irq_domain_error;
irq = platform_get_irq(pdev, 0);
- if (irq < 0)
+ if (irq < 0) {
+ ret = irq;
goto irq_error;
+ }
irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
dpu_mdss);
@@ -263,7 +265,7 @@ int dpu_mdss_init(struct drm_device *dev)
pm_runtime_enable(dev->dev);
- return ret;
+ return 0;
irq_error:
_dpu_mdss_irq_domain_fini(dpu_mdss);
--
With best wishes
Dmitry
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Re: [Freedreno] [PATCH 1/1] drm/msm: Fix error return code in msm_drm_init()
On 08/05/2021 05:28, Zhen Lei wrote:
Fix to return a negative error code from the error handling case instead
of 0, as done elsewhere in this function.
Fixes: 7f9743abaa79 ("drm/msm: validate display and event threads")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index e1104d2454e2..ebd856dde1f1 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -523,6 +523,7 @@ static int msm_drm_init(struct device *dev, const struct
drm_driver *drv)
priv->event_thread[i].worker = kthread_create_worker(0,
"crtc_event:%d", priv->event_thread[i].crtc_id);
if (IS_ERR(priv->event_thread[i].worker)) {
+ ret = PTR_ERR(priv->event_thread[i].worker);
DRM_DEV_ERROR(dev, "failed to create crtc_event
kthread\n");
goto err_msm_uninit;
}
--
With best wishes
Dmitry
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[Freedreno] [PATCH 3/8] arm64: dts: qcom: sdm845-mtp: assign DSI clock source parents
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 1372fe8601f5..9e550e3ad678 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -413,6 +413,9 @@ {
qcom,dual-dsi-mode;
+ /* DSI1 is slave, so use DSI0 clocks */
+ assigned-clock-parents = <_phy 0>, <_phy 1>;
+
ports {
port@1 {
endpoint {
--
2.30.2
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[Freedreno] [PATCH 8/8] drm/msm/dsi: remove msm_dsi_dphy_timing from msm_dsi_phy
Remove struct msm_dsi_dphy_timing field from the struct msm_dsi_phy.
There is no need to store them.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 18 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 10 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 11 +++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 11 +++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 10 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12
.../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c| 10 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 13 -
8 files changed, 40 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 53a02c02dd6e..47145cab6b55 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -453,6 +453,8 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing
*timing,
tmax = 255;
timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125,
1) + tmin;
+ timing->bitclk_rate = bit_rate;
+
DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
timing->clk_zero, timing->clk_trail, timing->clk_prepare,
timing->hs_exit,
@@ -756,6 +758,7 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
struct msm_dsi_phy_shared_timings *shared_timings)
{
struct device *dev = >pdev->dev;
+ struct msm_dsi_dphy_timing timing;
int ret;
if (!phy || !phy->cfg->ops.enable)
@@ -775,15 +778,22 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
goto reg_en_fail;
}
- ret = phy->cfg->ops.enable(phy, clk_req);
+ if (!phy->cfg->ops.dphy_timing_calc ||
+ phy->cfg->ops.dphy_timing_calc(, clk_req)) {
+ DRM_DEV_ERROR(>pdev->dev,
+ "%s: D-PHY timing calculation failed\n", __func__);
+ return -EINVAL;
+ }
+
+ memcpy(shared_timings, _timings,
+ sizeof(*shared_timings));
+
+ ret = phy->cfg->ops.enable(phy, );
if (ret) {
DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__,
ret);
goto phy_en_fail;
}
- memcpy(shared_timings, >timing.shared_timings,
- sizeof(*shared_timings));
-
/*
* Resetting DSI PHY silently changes its PLL registers to reset status,
* which will confuse clock driver and result in wrong output rate of
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 94a77ac364d3..9ba03a242d24 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -17,10 +17,14 @@
#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data),
(offset)); udelay(delay_us); }
#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data),
(offset)); ndelay(delay_ns); }
+struct msm_dsi_dphy_timing;
+
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
- int (*enable)(struct msm_dsi_phy *phy,
+ int (*dphy_timing_calc)(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req);
+ int (*enable)(struct msm_dsi_phy *phy,
+ struct msm_dsi_dphy_timing *timing);
void (*disable)(struct msm_dsi_phy *phy);
void (*save_pll_state)(struct msm_dsi_phy *phy);
int (*restore_pll_state)(struct msm_dsi_phy *phy);
@@ -73,6 +77,9 @@ struct msm_dsi_dphy_timing {
u32 hs_prep_dly_ckln;
u8 hs_halfbyte_en;
u8 hs_halfbyte_en_ckln;
+
+ /* For PHY v4 only */
+ unsigned long bitclk_rate;
};
#define DSI_BYTE_PLL_CLK 0
@@ -90,7 +97,6 @@ struct msm_dsi_phy {
struct clk *ahb_clk;
struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
- struct msm_dsi_dphy_timing timing;
const struct msm_dsi_phy_cfg *cfg;
enum msm_dsi_phy_usecase usecase;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 34bc93548fcf..bc838ee4f9b9 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -789,24 +789,17 @@ static void dsi_phy_hw_v3_0_lane_settings(struct
msm_dsi_phy *phy)
}
static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_clk_request *clk_req)
+ struct msm_dsi_dphy_timing *timing)
{
int ret;
u32 status;
u32 const delay_us = 5;
u32 const timeout_us = 1000;
- struct msm_dsi_dphy_timing *timing = >timing;
void __iomem *base = phy->base;
u32 data;
DBG("");
- if
[Freedreno] [PATCH 6/8] drm/msm/dsi: phy: use of_device_get_match_data
Use of_device_get_match-data() instead of of_match_node().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index f2b5e0f63a16..feaeb34b7071 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -625,17 +625,12 @@ static int dsi_phy_driver_probe(struct platform_device
*pdev)
{
struct msm_dsi_phy *phy;
struct device *dev = >dev;
- const struct of_device_id *match;
int ret;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
return -ENOMEM;
- match = of_match_node(dsi_phy_dt_match, dev->of_node);
- if (!match)
- return -ENODEV;
-
phy->provided_clocks = devm_kzalloc(dev,
struct_size(phy->provided_clocks, hws,
NUM_PROVIDED_CLKS),
GFP_KERNEL);
@@ -644,7 +639,10 @@ static int dsi_phy_driver_probe(struct platform_device
*pdev)
phy->provided_clocks->num = NUM_PROVIDED_CLKS;
- phy->cfg = match->data;
+ phy->cfg = of_device_get_match_data(>dev);
+ if (!phy->cfg)
+ return -ENODEV;
+
phy->pdev = pdev;
phy->id = dsi_phy_get_id(phy);
--
2.30.2
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[Freedreno] [PATCH 7/8] drm/msm/dsi: drop msm_dsi_phy_get_shared_timings
Instead of fetching shared timing through an extra function call, get
them directly from msm_dsi_phy_enable. This would allow removing phy
timings from the struct msm_dsi_phy in the next patch.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 5 ++---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 3 +--
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 13 +
3 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 2041980548f0..84f9900ff878 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -163,10 +163,9 @@ struct msm_dsi_phy_clk_request {
void msm_dsi_phy_driver_register(void);
void msm_dsi_phy_driver_unregister(void);
int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_clk_request *clk_req);
+ struct msm_dsi_phy_clk_request *clk_req,
+ struct msm_dsi_phy_shared_timings *shared_timings);
void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
-void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_shared_timings *shared_timing);
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc);
void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 12efc8c69046..88d56a2bc8ab 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -118,8 +118,7 @@ static int enable_phy(struct msm_dsi *msm_dsi,
msm_dsi_host_get_phy_clk_req(msm_dsi->host, _req, is_dual_dsi);
- ret = msm_dsi_phy_enable(msm_dsi->phy, _req);
- msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);
+ ret = msm_dsi_phy_enable(msm_dsi->phy, _req, shared_timings);
return ret;
}
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index feaeb34b7071..53a02c02dd6e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -752,7 +752,8 @@ void __exit msm_dsi_phy_driver_unregister(void)
}
int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_clk_request *clk_req)
+ struct msm_dsi_phy_clk_request *clk_req,
+ struct msm_dsi_phy_shared_timings *shared_timings)
{
struct device *dev = >pdev->dev;
int ret;
@@ -780,6 +781,9 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
goto phy_en_fail;
}
+ memcpy(shared_timings, >timing.shared_timings,
+ sizeof(*shared_timings));
+
/*
* Resetting DSI PHY silently changes its PLL registers to reset status,
* which will confuse clock driver and result in wrong output rate of
@@ -819,13 +823,6 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
dsi_phy_disable_resource(phy);
}
-void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
- struct msm_dsi_phy_shared_timings *shared_timings)
-{
- memcpy(shared_timings, >timing.shared_timings,
- sizeof(*shared_timings));
-}
-
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc)
{
--
2.30.2
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[Freedreno] [PATCH 5/8] drm/msm/dsi: stop setting clock parents manually
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping this manual
setup allows us to drop repeating code and to move registration of hw
clock providers to generic place.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 --
drivers/gpu/drm/msm/dsi/dsi_host.c| 51 ---
drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 ---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 11 --
4 files changed, 69 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 7abfeab08165..2041980548f0 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -169,8 +169,6 @@ void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
struct msm_dsi_phy_shared_timings *shared_timing);
void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
enum msm_dsi_phy_usecase uc);
-int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
- struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy);
int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 8a10e4343281..1f444101e551 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2223,57 +2223,6 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host
*host, u32 dma_base,
wmb();
}
-int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
- struct msm_dsi_phy *src_phy)
-{
- struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
- struct clk *byte_clk_provider, *pixel_clk_provider;
- int ret;
-
- ret = msm_dsi_phy_get_clk_provider(src_phy,
- _clk_provider, _clk_provider);
- if (ret) {
- pr_info("%s: can't get provider from pll, don't set parent\n",
- __func__);
- return 0;
- }
-
- ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
-
- if (msm_host->dsi_clk_src) {
- ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
- }
-
- if (msm_host->esc_clk_src) {
- ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
- if (ret) {
- pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
- __func__, ret);
- goto exit;
- }
- }
-
-exit:
- return ret;
-}
-
void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index cd016576e8c5..12efc8c69046 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -78,7 +78,6 @@ static int dsi_mgr_setup_components(int id)
return ret;
msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE);
- ret = msm_dsi_host_set_src_pll(msm_dsi->host, msm_dsi->phy);
} else if (!other_dsi) {
ret = 0;
} else {
@@ -105,10 +104,6 @@ static int dsi_mgr_setup_components(int id)
MSM_DSI_PHY_MASTER);
msm_dsi_phy_set_usecase(clk_slave_dsi->phy,
MSM_DSI_PHY_SLAVE);
- ret = msm_dsi_host_set_src_pll(msm_dsi->host,
clk_master_dsi->phy);
- if (ret)
- return ret;
- ret = msm_dsi_host_set_src_pll(other_dsi->host,
clk_master_dsi->phy);
}
return ret;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index ff7f2ec42030..f2b5e0f63a16 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -835,17 +835,6 @@ void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
phy->usecase = uc;
}
-int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
- struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
-{
- if (byte_clk_provider)
-
[Freedreno] [PATCH 4/8] arm64: dts: qcom: sm8250: assign DSI clock source parents
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..b6ed94497e8a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2445,6 +2445,9 @@ dsi0: dsi@ae94000 {
"iface",
"bus";
+ assigned-clocks = <
DISP_CC_MDSS_BYTE0_CLK_SRC>, < DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
operating-points-v2 = <_opp_table>;
power-domains = < SM8250_MMCX>;
@@ -2512,6 +2515,9 @@ dsi1: dsi@ae96000 {
"iface",
"bus";
+ assigned-clocks = <
DISP_CC_MDSS_BYTE1_CLK_SRC>, < DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
operating-points-v2 = <_opp_table>;
power-domains = < SM8250_MMCX>;
--
2.30.2
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[Freedreno] [PATCH 1/8] arm64: dts: qcom: sc7180: assign DSI clock source parents
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 1ea3344ab62c..4e8708cce1cc 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3090,6 +3090,9 @@ dsi0: dsi@ae94000 {
"iface",
"bus";
+ assigned-clocks = <
DISP_CC_MDSS_BYTE0_CLK_SRC>, < DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
operating-points-v2 = <_opp_table>;
power-domains = < SC7180_CX>;
--
2.30.2
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[Freedreno] [PATCH 2/8] arm64: dts: qcom: sdm845: assign DSI clock source parents
Assign DSI clock source parents to DSI PHY clocks.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 454f794af547..2166549382c1 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4113,6 +4113,9 @@ dsi0: dsi@ae94000 {
"core",
"iface",
"bus";
+ assigned-clocks = <
DISP_CC_MDSS_BYTE0_CLK_SRC>, < DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
operating-points-v2 = <_opp_table>;
power-domains = < SDM845_CX>;
@@ -4179,6 +4182,9 @@ dsi1: dsi@ae96000 {
"core",
"iface",
"bus";
+ assigned-clocks = <
DISP_CC_MDSS_BYTE1_CLK_SRC>, < DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
operating-points-v2 = <_opp_table>;
power-domains = < SDM845_CX>;
--
2.30.2
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[Freedreno] [PATCH 0/8] dsi: rework clock parents and timing handling
This patch series brings back several patches targeting assigning dispcc clock parents, that were removed from the massive dsi rework patchset earlier. Few notes: - assign-clock-parents is a mandatory proprety according to the current dsi.txt description. - There is little point in duplicating this functionality with the ad-hoc implementation in the dsi code. On top of that come few minor cleanups for the DSI PHY drivers. I'd kindly ask to bring all dts changes also through the drm tree, so that there won't be any breakage of the functionality. The following changes since commit f2f46b878777e0d3f885c7ddad48f477b4dea247: drm/msm/dp: initialize audio_comp when audio starts (2021-05-06 16:26:57 -0700) are available in the Git repository at: https://git.linaro.org/people/dmitry.baryshkov/kernel.git dsi-phy-update for you to fetch changes up to f1fd3b113cbb98febad682fc11ea1c6e717434c2: drm/msm/dsi: remove msm_dsi_dphy_timing from msm_dsi_phy (2021-05-14 22:55:11 +0300) Dmitry Baryshkov (8): arm64: dts: qcom: sc7180: assign DSI clock source parents arm64: dts: qcom: sdm845: assign DSI clock source parents arm64: dts: qcom: sdm845-mtp: assign DSI clock source parents arm64: dts: qcom: sm8250: assign DSI clock source parents drm/msm/dsi: stop setting clock parents manually drm/msm/dsi: phy: use of_device_get_match_data drm/msm/dsi: drop msm_dsi_phy_get_shared_timings drm/msm/dsi: remove msm_dsi_dphy_timing from msm_dsi_phy arch/arm64/boot/dts/qcom/sc7180.dtsi| 3 ++ arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi| 6 +++ arch/arm64/boot/dts/qcom/sm8250.dtsi| 6 +++ drivers/gpu/drm/msm/dsi/dsi.h | 7 +--- drivers/gpu/drm/msm/dsi/dsi_host.c | 51 - drivers/gpu/drm/msm/dsi/dsi_manager.c | 8 +--- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 46 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 10 - drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 11 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 11 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 10 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 10 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 13 ++- 15 files changed, 67 insertions(+), 140 deletions(-) ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
