Re: [Freedreno] [PATCH v1 1/4] dt-bindings: msm: add DT bindings for sc7280
Quoting Krishna Manikandan (2021-08-18 03:27:01) > MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks > like DPU display controller, DSI, EDP etc. Add required DPU > device tree bindings for SC7280. > > Signed-off-by: Krishna Manikandan > --- Please send a cover-letter next time. Do you have the display port dts bits and driver code ready too? Can it be part of this patch series?
Re: [Freedreno] [PATCH v1 4/4] arm64: dts: qcom: sc7280: add edp display dt nodes
Quoting Krishna Manikandan (2021-08-18 03:27:04)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index aadf55d..5be318e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1412,7 +1412,7 @@
> reg = <0 0xaf0 0 0x2>;
> clocks = < RPMH_CXO_CLK>,
> < GCC_DISP_GPLL0_CLK_SRC>,
> -<0>, <0>, <0>, <0>, <0>, <0>;
> +<0>, <0>, <0>, <0>, <_phy 0>, <_phy
> 1>;
> clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
> "dsi0_phy_pll_out_byteclk",
> "dsi0_phy_pll_out_dsiclk",
> @@ -1493,6 +1493,12 @@
> remote-endpoint =
> <_in>;
> };
> };
Newline here please.
> + port@1 {
> + reg = <1>;
> + dpu_intf5_out: endpoint {
> + remote-endpoint =
> <_in>;
> + };
> + };
> };
>
> mdp_opp_table: mdp-opp-table {
> @@ -1608,6 +1614,101 @@
>
> status = "disabled";
> };
> +
> + msm_edp: edp@aea {
> + status = "disabled";
Please pick a place to put status disabled. I don't know what qcom
maintainers want, but please be consistent.
> + compatible = "qcom,sc7280-edp";
> + reg = <0 0xaea 0 0x200>,
> + <0 0xaea0200 0 0x200>,
> + <0 0xaea0400 0 0xc00>,
> + <0 0xaea1000 0 0x400>;
> +
> + interrupt-parent = <>;
> + interrupts = <14 IRQ_TYPE_NONE>;
Drop flags.
> +
> + clocks = < RPMH_CXO_CLK>,
> +< GCC_EDP_CLKREF_EN>,
> +< DISP_CC_MDSS_AHB_CLK>,
> +< DISP_CC_MDSS_EDP_AUX_CLK>,
> +< DISP_CC_MDSS_EDP_LINK_CLK>,
> +<
> DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
> +< DISP_CC_MDSS_EDP_PIXEL_CLK>;
> + clock-names = "core_xo", "core_ref",
> + "core_iface", "core_aux",
> "ctrl_link",
> + "ctrl_link_iface",
> "stream_pixel";
One line per string please.
> + #clock-cells = <1>;
> + assigned-clocks = <
> DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
> + <
> DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <_phy 0>,
> <_phy 1>;
> +
> + phys = <_phy>;
> + phy-names = "dp";
> +
> + vdda-1p2-supply = <_l6b_1p2>;
> + vdda-0p9-supply = <_l10c_0p8>;
Can this be done here? Probably needs to move to the board dts/dtsi
file.
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_hot_plug_det>,
> <_panel_power_on>;
> +
> + panel-bklt-gpio = <_gpios 7
> GPIO_ACTIVE_HIGH>;
> + panel-pwm-gpio = <_gpios 8
> GPIO_ACTIVE_HIGH>;
Please no panel-bklt-gpio and panel-pwm-gpio properties.
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + edp_in: endpoint {
> + remote-endpoint =
> <_intf5_out>;
> + };
> + };
> + };
> +
> + edp_opp_table: edp-opp-table {
edp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> +
Re: [Freedreno] [PATCH v1 3/4] arm64: dts: qcom: sc7280: Add DSI display nodes
Quoting Krishna Manikandan (2021-08-18 03:27:03)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index fd7ff1c..aadf55d 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1507,6 +1519,95 @@
> };
> };
> };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
Drop flags as the #interrupt-cells is 0 for mdss
> +
> + clocks = < DISP_CC_MDSS_BYTE0_CLK>,
> +<
> DISP_CC_MDSS_BYTE0_INTF_CLK>,
> +< DISP_CC_MDSS_PCLK0_CLK>,
> +< DISP_CC_MDSS_ESC0_CLK>,
> +< DISP_CC_MDSS_AHB_CLK>,
> +< GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> + phys = <_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint =
> <_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + dsi_opp_table: dsi-opp-table {
dsi_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-18750 {
> + opp-hz = /bits/ 64
> <18750>;
> + required-opps =
> <_opp_low_svs>;
> + };
> +
> + opp-3 {
> + opp-hz = /bits/ 64
> <3>;
> + required-opps =
> <_opp_svs>;
> + };
> +
> + opp-35800 {
> + opp-hz = /bits/ 64
> <35800>;
> + required-opps =
> <_opp_svs_l1>;
> + };
> + };
> + };
> +
> + dsi_phy: dsi-phy@ae94400 {
phy@ae94400
> + compatible = "qcom,sc7280-dsi-phy-7nm";
> + reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x280>;
> + reg-names = "dsi_phy",
> + "dsi_phy_lane",
> + "dsi_pll";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> +< RPMH_CXO_CLK>;
> + clock-names = "iface", "ref";
> +
> + status = "disabled";
> + };
Re: [Freedreno] [PATCH v1 2/4] arm64: dts: qcom: sc7280: add display dt nodes
Quoting Krishna Manikandan (2021-08-18 03:27:02)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..fd7ff1c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -5,6 +5,7 @@
> * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> */
>
> +#include
> #include
> #include
> #include
> @@ -1424,6 +1425,90 @@
> #power-domain-cells = <1>;
> };
>
> + mdss: mdss@ae0 {
subsystem@ae0
> + compatible = "qcom,sc7280-mdss";
> + reg = <0 0x0ae0 0 0x1000>;
> + reg-names = "mdss";
> +
> + power-domains = < DISP_CC_MDSS_CORE_GDSC>;
> +
> + clocks = < GCC_DISP_AHB_CLK>,
> +< DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "ahb", "core";
> +
> + assigned-clocks = < DISP_CC_MDSS_MDP_CLK>;
> + assigned-clock-rates = <3>;
> +
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interconnects = <_noc MASTER_MDP0 0 _virt
> SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem";
> +
> + iommus = <_smmu 0x900 0x402>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdp: mdp@ae01000 {
display-controller@ae01000
> + compatible = "qcom,sc7280-dpu";
> + reg = <0 0x0ae01000 0 0x8f030>,
> + <0 0x0aeb 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = < GCC_DISP_HF_AXI_CLK>,
> + < GCC_DISP_SF_AXI_CLK>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_MDP_LUT_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>,
> + < DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus", "nrt_bus", "iface",
> "lut", "core",
> + "vsync";
One line per string please.
> + assigned-clocks = <
> DISP_CC_MDSS_MDP_CLK>,
> + <
> DISP_CC_MDSS_VSYNC_CLK>,
> + <
> DISP_CC_MDSS_AHB_CLK>;
> + assigned-clock-rates = <3>,
> + <1920>,
> + <1920>;
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> + interrupt-parent = <>;
> + interrupts = <0>;
> +
> + status = "disabled";
> +
> + mdp_opp_table: mdp-opp-table {
mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-2 {
> + opp-hz = /bits/ 64
> <2>;
> + required-opps =
> <_opp_low_svs>;
> + };
> +
> + opp-3 {
> + opp-hz = /bits/ 64
> <3>;
> + required-opps =
> <_opp_svs>;
> + };
> +
> + opp-38000 {
> + opp-hz = /bits/ 64
> <38000>;
> + required-opps =
> <_opp_svs_l1>;
> + };
> +
> + opp-50667 {
> + opp-hz = /bits/ 64
> <50667>;
> + required-opps =
> <_opp_nom>;
> + };
> + };
> + };
> + };
> +
Re: [Freedreno] [PATCH v1 1/4] dt-bindings: msm: add DT bindings for sc7280
Quoting Krishna Manikandan (2021-08-18 03:27:01)
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
> b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
> new file mode 100644
> index 000..3d256c0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
> @@ -0,0 +1,228 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SC7280 target
Drop "target"?
> +
> +maintainers:
> + - Krishna Manikandan
> +
> +description: |
> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that
> encapsulates
Space after Subsystem please.
> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
> tree
> + bindings of MDSS and DPU are mentioned for SC7280 target.
Drop "target"?
> +
> +properties:
> + compatible:
> +items:
Will there be anymore? If not, drop items and only have const.
> + - const: qcom,sc7280-mdss
> +
> + reg:
> +maxItems: 1
> +
> + reg-names:
> +const: mdss
> +
> + power-domains:
> +maxItems: 1
> +
> + clocks:
> +items:
> + - description: Display AHB clock from gcc
> + - description: Display AHB clock from dispcc
> + - description: Display core clock
> +
> + clock-names:
> +items:
> + - const: iface
> + - const: ahb
> + - const: core
> +
> + interrupts:
> +maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#address-cells": true
> +
> + "#size-cells": true
> +
> + "#interrupt-cells":
> +const: 1
> +
> + iommus:
> +items:
> + - description: Phandle to apps_smmu node with SID mask for Hard-Fail
> port0
> +
> + ranges: true
> +
> + interconnects:
> +items:
> + - description: Interconnect path specifying the port ids for data bus
> +
> + interconnect-names:
> +const: mdp0-mem
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> +type: object
> +description: Node containing the properties of DPU.
> +
> +properties:
> + compatible:
> +items:
> + - const: qcom,sc7280-dpu
Will there be anymore? If not, drop items and only have const.
> +
> + reg:
> +items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> +items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> +items:
> + - description: Display hf axi clock
> + - description: Display sf axi clock
> + - description: Display ahb clock
> + - description: Display lut clock
> + - description: Display core clock
> + - description: Display vsync clock
> +
> + clock-names:
> +items:
> + - const: bus
> + - const: nrt_bus
> + - const: iface
> + - const: lut
> + - const: core
> + - const: vsync
> +
> + interrupts:
> +maxItems: 1
> +
> + power-domains:
> +maxItems: 1
> +
> + operating-points-v2: true
> +
> + ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +description: |
> + Contains the list of output ports from DPU device. These ports
> + connect to interfaces that are external to the DPU hardware,
> + such as DSI, DP etc. Each output port contains an endpoint that
> + describes how it is connected to an external interface.
> +
> +properties:
> + port@0:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: DPU_INTF1 (DSI)
> +
> + port@1:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: DPU_INTF5 (EDP)
> +
> +required:
> + - port@0
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - interrupts
> + - power-domains
> + - operating-points-v2
> + - ports
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - power-domains
> + - clocks
> + - interrupts
> + - interrupt-controller
> + - iommus
> + - ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +display-subsystem@ae0 {
Maybe just 'subsystem' as that is generic enough.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "qcom,sc7280-mdss";
> + reg = <0xae0 0x1000>;
> + reg-names = "mdss";
> + power-domains = < DISP_CC_MDSS_CORE_GDSC>;
> + clocks = < GCC_DISP_AHB_CLK>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>;
> +
Re: [Freedreno] [PATCH] drm/msm/dpu: add support for alpha blending properties
On 17/08/2021 20:48, abhin...@codeaurora.org wrote:
On 2021-06-28 12:19, Dmitry Baryshkov wrote:
Add support for alpha blending properties. Setup the plane blend state
according to those properties.
Signed-off-by: Dmitry Baryshkov
I think this has already been picked up by Rob but just had a couple of
comments
below.
Also, how has this been validated? On RB boards i dont think all the
paths get
executed.
I've used modetest to set pixel blending properties. The results looked
logical from my point of view.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 43 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 --
2 files changed, 37 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9a5c70c87cc8..768012243b44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -30,12 +30,6 @@
#include "dpu_core_perf.h"
#include "dpu_trace.h"
-#define DPU_DRM_BLEND_OP_NOT_DEFINED 0
-#define DPU_DRM_BLEND_OP_OPAQUE 1
-#define DPU_DRM_BLEND_OP_PREMULTIPLIED 2
-#define DPU_DRM_BLEND_OP_COVERAGE 3
-#define DPU_DRM_BLEND_OP_MAX 4
-
/* layer mixer index on dpu_crtc */
#define LEFT_MIXER 0
#define RIGHT_MIXER 1
@@ -146,20 +140,43 @@ static void _dpu_crtc_setup_blend_cfg(struct
dpu_crtc_mixer *mixer,
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
uint32_t blend_op;
+ uint32_t fg_alpha, bg_alpha;
- /* default to opaque blending */
- blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
- DPU_BLEND_BG_ALPHA_BG_CONST;
+ fg_alpha = pstate->base.alpha >> 8;
+ bg_alpha = 0xff - fg_alpha;
- if (format->alpha_enable) {
+ /* default to opaque blending */
+ if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
+ !format->alpha_enable) {
+ blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
+ DPU_BLEND_BG_ALPHA_BG_CONST;
+ } else if (pstate->base.pixel_blend_mode ==
DRM_MODE_BLEND_PREMULTI) {
+ blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
+ DPU_BLEND_BG_ALPHA_FG_PIXEL;
+ if (fg_alpha != 0xff) {
+ bg_alpha = fg_alpha;
+ blend_op |= DPU_BLEND_BG_MOD_ALPHA |
+ DPU_BLEND_BG_INV_MOD_ALPHA;
+ } else {
+ blend_op |= DPU_BLEND_BG_INV_ALPHA;
+ }
+ } else {
/* coverage blending */
blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
- DPU_BLEND_BG_ALPHA_FG_PIXEL |
- DPU_BLEND_BG_INV_ALPHA;
+ DPU_BLEND_BG_ALPHA_FG_PIXEL;
+ if (fg_alpha != 0xff) {
+ bg_alpha = fg_alpha;
+ blend_op |= DPU_BLEND_FG_MOD_ALPHA |
+ DPU_BLEND_FG_INV_MOD_ALPHA |
comparing this with the blend rule downstream, is this inversion necessary?
I only see below rule downstream:
628 if (fg_alpha != 0xff) {
629 bg_alpha = fg_alpha;
630 blend_op |= SDE_BLEND_FG_MOD_ALPHA |
631 SDE_BLEND_BG_MOD_ALPHA |
632 SDE_BLEND_BG_INV_MOD_ALPHA;
I've also stumbled upon this for quite some time. If you check old
kernel trees, you'll see that up to 4.9 there was an inversion. But
during the import to 4.14 this line was silently removed. I suspect that
it got lost because of some mistake during the import.
The same code (with the inversion) was present in the mdp5 driver.
Could you please check against the manual, how these bits should work?
See
https://www.kernel.org/doc/html/latest/gpu/drm-kms.html#plane-composition-properties
for the expected formulas.
+ DPU_BLEND_BG_MOD_ALPHA |
+ DPU_BLEND_BG_INV_MOD_ALPHA;
+ } else {
+ blend_op |= DPU_BLEND_BG_INV_ALPHA;
+ }
}
lm->ops.setup_blend_config(lm, pstate->stage,
- 0xFF, 0, blend_op);
+ fg_alpha, bg_alpha, blend_op);
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
>base.pixel_format, format->alpha_enable, blend_op);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index ec4a6f04394a..c989621209aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1339,9 +1339,7 @@ static void dpu_plane_reset(struct drm_plane
*plane)
return;
}
- pstate->base.plane = plane;
-
- plane->state = >base;
+ __drm_atomic_helper_plane_reset(plane, >base);
}
#ifdef CONFIG_DEBUG_FS
@@ -1647,6 +1645,12 @@ struct drm_plane *dpu_plane_init(struct
drm_device *dev,
if (ret)
DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
+ drm_plane_create_alpha_property(plane);
+ drm_plane_create_blend_mode_property(plane,
+ BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE));
+
Re: [Freedreno] [PATCH v1 3/4] arm64: dts: qcom: sc7280: Add DSI display nodes
On Wed, Aug 18, 2021 at 03:57:03PM +0530, Krishna Manikandan wrote:
> From: Rajeev Nandan
>
> Add DSI controller and PHY nodes for sc7280.
>
> Signed-off-by: Rajeev Nandan
You should sign off patches you send, even if you aren't the original author.
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 101
> +++
> 1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index fd7ff1c..aadf55d 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1483,6 +1483,18 @@
>
> status = "disabled";
>
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint =
> <_in>;
> + };
> + };
> + };
> +
> mdp_opp_table: mdp-opp-table {
> compatible = "operating-points-v2";
>
> @@ -1507,6 +1519,95 @@
> };
> };
> };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = < DISP_CC_MDSS_BYTE0_CLK>,
> + < DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + < DISP_CC_MDSS_PCLK0_CLK>,
> + < DISP_CC_MDSS_ESC0_CLK>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> + phys = <_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint =
> <_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + dsi_opp_table: dsi-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-18750 {
> + opp-hz = /bits/ 64 <18750>;
> + required-opps =
> <_opp_low_svs>;
> + };
> +
> + opp-3 {
> + opp-hz = /bits/ 64 <3>;
> + required-opps =
> <_opp_svs>;
> + };
> +
> + opp-35800 {
> + opp-hz = /bits/ 64 <35800>;
> + required-opps =
> <_opp_svs_l1>;
> + };
> + };
> + };
> +
> + dsi_phy: dsi-phy@ae94400 {
> + compatible = "qcom,sc7280-dsi-phy-7nm";
>
Re: [Freedreno] [PATCH v1 4/4] arm64: dts: qcom: sc7280: add edp display dt nodes
On Wed, Aug 18, 2021 at 03:57:04PM +0530, Krishna Manikandan wrote:
> From: Sankeerth Billakanti
>
> Add edp controller and phy DT nodes for sc7280.
>
> Signed-off-by: Sankeerth Billakanti
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 127
> ++-
> 1 file changed, 126 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index aadf55d..5be318e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1412,7 +1412,7 @@
> reg = <0 0xaf0 0 0x2>;
> clocks = < RPMH_CXO_CLK>,
>< GCC_DISP_GPLL0_CLK_SRC>,
> - <0>, <0>, <0>, <0>, <0>, <0>;
> + <0>, <0>, <0>, <0>, <_phy 0>, <_phy 1>;
> clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
> "dsi0_phy_pll_out_byteclk",
> "dsi0_phy_pll_out_dsiclk",
> @@ -1493,6 +1493,12 @@
> remote-endpoint =
> <_in>;
> };
> };
> + port@1 {
> + reg = <1>;
> + dpu_intf5_out: endpoint {
> + remote-endpoint =
> <_in>;
> + };
> + };
> };
>
> mdp_opp_table: mdp-opp-table {
> @@ -1608,6 +1614,101 @@
>
> status = "disabled";
> };
> +
> + msm_edp: edp@aea {
> + status = "disabled";
> + compatible = "qcom,sc7280-edp";
> + reg = <0 0xaea 0 0x200>,
> + <0 0xaea0200 0 0x200>,
> + <0 0xaea0400 0 0xc00>,
> + <0 0xaea1000 0 0x400>;
> +
> + interrupt-parent = <>;
> + interrupts = <14 IRQ_TYPE_NONE>;
> +
> + clocks = < RPMH_CXO_CLK>,
> + < GCC_EDP_CLKREF_EN>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_EDP_AUX_CLK>,
> + < DISP_CC_MDSS_EDP_LINK_CLK>,
> + <
> DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
> + < DISP_CC_MDSS_EDP_PIXEL_CLK>;
> + clock-names = "core_xo", "core_ref",
> + "core_iface", "core_aux",
> "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + #clock-cells = <1>;
> + assigned-clocks = <
> DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
> + <
> DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <_phy 0>,
> <_phy 1>;
> +
> + phys = <_phy>;
> + phy-names = "dp";
> +
> + vdda-1p2-supply = <_l6b_1p2>;
> + vdda-0p9-supply = <_l10c_0p8>;
These regulators are defined in the board .dts (sc7280-idp.dts), hence the SoC
.dtsi shouldn't depend on them. My impression is that pm7325.dtsi and
pm8350c.dtsi
should include definitions for regulators that supply basic SoC blocks. If the
configuration can vary depending on the SoC there could be SoC specific includes
for each PMIC. If a board uses a different configuration it could overwrite the
PMIC .dtsi settings.
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_hot_plug_det>,
> <_panel_power_on>;
> +
> + panel-bklt-gpio = <_gpios 7
> GPIO_ACTIVE_HIGH>;
> + panel-pwm-gpio = <_gpios 8
> GPIO_ACTIVE_HIGH>;
The pins are board specific, hence they shouldn't be configured in the .dtsi of
the SoC.
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + edp_in: endpoint {
> +
Re: [Freedreno] [PATCH v1 1/4] dt-bindings: msm: add DT bindings for sc7280
On Wed, 18 Aug 2021 15:57:01 +0530, Krishna Manikandan wrote: > MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks > like DPU display controller, DSI, EDP etc. Add required DPU > device tree bindings for SC7280. > > Signed-off-by: Krishna Manikandan > --- > .../bindings/display/msm/dpu-sc7280.yaml | 228 > + > 1 file changed, 228 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/msm/dpu-sc7280.example.dts:19:18: fatal error: dt-bindings/clock/qcom,dispcc-sc7280.h: No such file or directory 19 | #include | ^~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/display/msm/dpu-sc7280.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs make: *** [Makefile:1419: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1517976 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
[Freedreno] [PATCH v1 2/4] arm64: dts: qcom: sc7280: add display dt nodes
Add mdss and mdp DT nodes for sc7280.
Signed-off-by: Krishna Manikandan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 85
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0..fd7ff1c 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5,6 +5,7 @@
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
+#include
#include
#include
#include
@@ -1424,6 +1425,90 @@
#power-domain-cells = <1>;
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sc7280-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = < DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = < GCC_DISP_AHB_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ assigned-clocks = < DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <3>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <_noc MASTER_MDP0 0 _virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem";
+
+ iommus = <_smmu 0x900 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdp: mdp@ae01000 {
+ compatible = "qcom,sc7280-dpu";
+ reg = <0 0x0ae01000 0 0x8f030>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "nrt_bus", "iface", "lut",
"core",
+ "vsync";
+ assigned-clocks = <
DISP_CC_MDSS_MDP_CLK>,
+ <
DISP_CC_MDSS_VSYNC_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>;
+ assigned-clock-rates = <3>,
+ <1920>,
+ <1920>;
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SC7280_CX>;
+
+ interrupt-parent = <>;
+ interrupts = <0>;
+
+ status = "disabled";
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-2 {
+ opp-hz = /bits/ 64 <2>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ required-opps =
<_opp_svs>;
+ };
+
+ opp-38000 {
+ opp-hz = /bits/ 64 <38000>;
+ required-opps =
<_opp_svs_l1>;
+ };
+
+ opp-50667 {
+ opp-hz = /bits/ 64 <50667>;
+ required-opps =
<_opp_nom>;
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b22 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b22 0 0x3>;
--
2.7.4
[Freedreno] [PATCH v1 3/4] arm64: dts: qcom: sc7280: Add DSI display nodes
From: Rajeev Nandan
Add DSI controller and PHY nodes for sc7280.
Signed-off-by: Rajeev Nandan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 101 +++
1 file changed, 101 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fd7ff1c..aadf55d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1483,6 +1483,18 @@
status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+
mdp_opp_table: mdp-opp-table {
compatible = "operating-points-v2";
@@ -1507,6 +1519,95 @@
};
};
};
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+< DISP_CC_MDSS_BYTE0_INTF_CLK>,
+< DISP_CC_MDSS_PCLK0_CLK>,
+< DISP_CC_MDSS_ESC0_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SC7280_CX>;
+
+ phys = <_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint =
<_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: dsi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-18750 {
+ opp-hz = /bits/ 64 <18750>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ required-opps =
<_opp_svs>;
+ };
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ required-opps =
<_opp_svs_l1>;
+ };
+ };
+ };
+
+ dsi_phy: dsi-phy@ae94400 {
+ compatible = "qcom,sc7280-dsi-phy-7nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94900 0 0x280>;
+ reg-names =
[Freedreno] [PATCH v1 4/4] arm64: dts: qcom: sc7280: add edp display dt nodes
From: Sankeerth Billakanti
Add edp controller and phy DT nodes for sc7280.
Signed-off-by: Sankeerth Billakanti
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 127 ++-
1 file changed, 126 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index aadf55d..5be318e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1412,7 +1412,7 @@
reg = <0 0xaf0 0 0x2>;
clocks = < RPMH_CXO_CLK>,
< GCC_DISP_GPLL0_CLK_SRC>,
-<0>, <0>, <0>, <0>, <0>, <0>;
+<0>, <0>, <0>, <0>, <_phy 0>, <_phy 1>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
@@ -1493,6 +1493,12 @@
remote-endpoint =
<_in>;
};
};
+ port@1 {
+ reg = <1>;
+ dpu_intf5_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
};
mdp_opp_table: mdp-opp-table {
@@ -1608,6 +1614,101 @@
status = "disabled";
};
+
+ msm_edp: edp@aea {
+ status = "disabled";
+ compatible = "qcom,sc7280-edp";
+ reg = <0 0xaea 0 0x200>,
+ <0 0xaea0200 0 0x200>,
+ <0 0xaea0400 0 0xc00>,
+ <0 0xaea1000 0 0x400>;
+
+ interrupt-parent = <>;
+ interrupts = <14 IRQ_TYPE_NONE>;
+
+ clocks = < RPMH_CXO_CLK>,
+< GCC_EDP_CLKREF_EN>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_EDP_AUX_CLK>,
+< DISP_CC_MDSS_EDP_LINK_CLK>,
+<
DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
+< DISP_CC_MDSS_EDP_PIXEL_CLK>;
+ clock-names = "core_xo", "core_ref",
+ "core_iface", "core_aux",
"ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <
DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
+ <
DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
+ phys = <_phy>;
+ phy-names = "dp";
+
+ vdda-1p2-supply = <_l6b_1p2>;
+ vdda-0p9-supply = <_l10c_0p8>;
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SC7280_CX>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_hot_plug_det>,
<_panel_power_on>;
+
+ panel-bklt-gpio = <_gpios 7
GPIO_ACTIVE_HIGH>;
+ panel-pwm-gpio = <_gpios 8
GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint =
<_intf5_out>;
+ };
+ };
+ };
+
+ edp_opp_table: edp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-16000 {
+ opp-hz = /bits/ 64 <16000>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-27000 {
+
[Freedreno] [PATCH v1 1/4] dt-bindings: msm: add DT bindings for sc7280
MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI, EDP etc. Add required DPU
device tree bindings for SC7280.
Signed-off-by: Krishna Manikandan
---
.../bindings/display/msm/dpu-sc7280.yaml | 228 +
1 file changed, 228 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
new file mode 100644
index 000..3d256c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
@@ -0,0 +1,228 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SC7280 target
+
+maintainers:
+ - Krishna Manikandan
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
+ bindings of MDSS and DPU are mentioned for SC7280 target.
+
+properties:
+ compatible:
+items:
+ - const: qcom,sc7280-mdss
+
+ reg:
+maxItems: 1
+
+ reg-names:
+const: mdss
+
+ power-domains:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock from dispcc
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ interrupts:
+maxItems: 1
+
+ interrupt-controller: true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interrupt-cells":
+const: 1
+
+ iommus:
+items:
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail
port0
+
+ ranges: true
+
+ interconnects:
+items:
+ - description: Interconnect path specifying the port ids for data bus
+
+ interconnect-names:
+const: mdp0-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+description: Node containing the properties of DPU.
+
+properties:
+ compatible:
+items:
+ - const: qcom,sc7280-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+ interrupts:
+maxItems: 1
+
+ power-domains:
+maxItems: 1
+
+ operating-points-v2: true
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface.
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: DPU_INTF1 (DSI)
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: DPU_INTF5 (EDP)
+
+required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - interrupts
+ - power-domains
+ - operating-points-v2
+ - ports
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,sc7280-mdss";
+ reg = <0xae0 0x1000>;
+ reg-names = "mdss";
+ power-domains = < DISP_CC_MDSS_CORE_GDSC>;
+ clocks = < GCC_DISP_AHB_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <_noc MASTER_MDP0 _virt SLAVE_EBI1>;
+ interconnect-names = "mdp0-mem";
+
+ iommus = <_smmu 0x900 0x402>;
+
