[Freedreno] [pull] drm/msm: drm-msm-next-2022-03-08 for 5.18
Hi Dave & Daniel, Follow-up pull req for v5.18 to pull in some important fixes. The following changes since commit afab9d91d872819f98a792c32c302d9e3261f1a1: drm/msm/adreno: Expose speedbin to userspace (2022-02-25 13:29:57 -0800) are available in the Git repository at: https://gitlab.freedesktop.org/drm/msm.git drm-msm-next-2022-03-08 for you to fetch changes up to 05afd57f4d34602a652fdaf58e0a2756b3c20fd4: drm/msm/gpu: Fix crash on devices without devfreq support (v2) (2022-03-08 13:55:23 -0800) Dan Carpenter (1): drm/msm/adreno: fix cast in adreno_get_param() Dmitry Baryshkov (1): dt-bindings: display/msm: add missing brace in dpu-qcm2290.yaml Rob Clark (8): drm/msm: Update generated headers drm/msm: Add SET_PARAM ioctl drm/msm: Add SYSPROF param (v2) drm/msm/a6xx: Zap counters across context switch drm/msm: Add MSM_SUBMIT_FENCE_SN_IN drm/msm/a6xx: Fix missing ARRAY_SIZE() check drm/msm: Fix dirtyfb refcounting drm/msm/gpu: Fix crash on devices without devfreq support (v2) Rob Herring (1): dt-bindings: display/msm: Drop bogus interrupt flags cell on MDSS nodes .../bindings/display/msm/dpu-msm8998.yaml | 4 +- .../bindings/display/msm/dpu-qcm2290.yaml | 5 +- drivers/gpu/drm/msm/adreno/a2xx.xml.h | 26 +- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a3xx.xml.h | 30 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a4xx.xml.h | 112 +++- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a5xx.xml.h | 63 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 1 + drivers/gpu/drm/msm/adreno/a6xx.xml.h | 674 + drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 26 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 42 +- drivers/gpu/drm/msm/adreno/adreno_common.xml.h | 31 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c| 22 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h| 2 + drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h| 46 +- drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h | 37 +- drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h | 37 +- drivers/gpu/drm/msm/disp/mdp_common.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h | 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h| 37 +- drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h | 480 --- drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h | 43 +- drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 37 +- drivers/gpu/drm/msm/dsi/sfpb.xml.h | 37 +- drivers/gpu/drm/msm/hdmi/hdmi.xml.h| 37 +- drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 37 +- drivers/gpu/drm/msm/msm_drv.c | 31 +- drivers/gpu/drm/msm/msm_fb.c | 4 +- drivers/gpu/drm/msm/msm_gem_submit.c | 42 +- drivers/gpu/drm/msm/msm_gpu.c | 2 + drivers/gpu/drm/msm/msm_gpu.h | 29 + drivers/gpu/drm/msm/msm_gpu_devfreq.c | 30 +- drivers/gpu/drm/msm/msm_submitqueue.c | 39 ++ include/uapi/drm/msm_drm.h | 32 +- 40 files changed, 1144 insertions(+), 1156 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h
Re: [Freedreno] [PATCH] drm/msm/gpu: Fix crash on devices without devfreq support (v2)
On Tue, 8 Mar 2022 at 21:48, Rob Clark wrote: > > From: Rob Clark > > Avoid going down devfreq paths on devices where devfreq is not > initialized. > > v2: Change has_devfreq() logic [Dmitry] > > Reported-by: Linux Kernel Functional Testing > Reported-by: Anders Roxell > Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/msm_gpu_devfreq.c | 30 ++- > 1 file changed, 25 insertions(+), 5 deletions(-) > -- With best wishes Dmitry
Re: [Freedreno] [PATCH v5 3/5] drm/msm/dp: set stream_pixel rate directly
Quoting Dmitry Baryshkov (2022-03-03 23:58:58)
> On Fri, 4 Mar 2022 at 07:31, Stephen Boyd wrote:
> >
> > Quoting Dmitry Baryshkov (2022-03-03 20:23:06)
> > > On Fri, 4 Mar 2022 at 01:32, Stephen Boyd wrote:
> > > >
> > > > Quoting Dmitry Baryshkov (2022-02-16 21:55:27)
> > > > > The only clock for which we set the rate is the "stream_pixel". Rather
> > > > > than storing the rate and then setting it by looping over all the
> > > > > clocks, set the clock rate directly.
> > > > >
> > > > > Signed-off-by: Dmitry Baryshkov
> > > > [...]
> > > > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> > > > > b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> > > > > index 07f6bf7e1acb..8e6361dedd77 100644
> > > > > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> > > > > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> > > > > @@ -1315,7 +1315,7 @@ static void dp_ctrl_set_clock_rate(struct
> > > > > dp_ctrl_private *ctrl,
> > > > > DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name);
> > > > >
> > > > > if (num)
> > > > > - cfg->rate = rate;
> > > > > + clk_set_rate(cfg->clk, rate);
> > > >
> > > > This looks bad. From what I can tell we set the rate of the pixel clk
> > > > after enabling the phy and configuring it. See the order of operations
> > > > in dp_ctrl_enable_mainlink_clocks() and note how dp_power_clk_enable()
> > > > is the one that eventually sets a rate through dp_power_clk_set_rate()
> > > >
> > > > dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
> > > > ctrl->link->link_params.rate *
> > > > 1000);
> > > >
> > > > phy_configure(phy, &dp_io->phy_opts);
> > > > phy_power_on(phy);
> > > >
> > > > ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
> > >
> > > This code has been changed in the previous patch.
> > >
> > > Let's get back a bit.
> > > Currently dp_ctrl_set_clock_rate() doesn't change the clock rate. It
> > > just stores the rate in the config so that later the sequence of
> > > dp_power_clk_enable() -> dp_power_clk_set_rate() ->
> > > [dp_power_clk_set_link_rate() -> dev_pm_opp_set_rate() or
> > > msm_dss_clk_set_rate() -> clk_set_rate()] will use that.
> > >
> > > There are only two users of dp_ctrl_set_clock_rate():
> > > - dp_ctrl_enable_mainlink_clocks(), which you have quoted above.
> > > This case is handled in the patch 1 from this series. It makes
> >
> > Patch 1 form this series says DP is unaffected. Huh?
> >
> > > dp_ctrl_enable_mainlink_clocks() call dev_pm_opp_set_rate() directly
> > > without storing (!) the rate in the config, calling
> > > phy_configure()/phy_power_on() and then setting the opp via the
> > > sequence of calls specified above
>
> Note, this handles the "ctrl_link" clock.
>
> > >
> > > - dp_ctrl_enable_stream_clocks(), which calls dp_power_clk_enable()
> > > immediately afterwards. This call would set the stream_pixel rate
> > > while enabling stream clocks. As far as I can see, the stream_pixel is
> > > the only stream clock. So this patch sets the clock rate without
> > > storing in the interim configuration data.
> > >
> > > Could you please clarify, what exactly looks bad to you?
> > >
>
> Note, this handles the "stream_pixel" clock.
>
> >
> > I'm concerned about the order of operations changing between the
> > phy being powered on and the pixel clk frequency being set. From what I
> > recall the pixel clk rate operations depend on the phy frequency being
> > set (which is done through phy_configure?) so if we call clk_set_rate()
> > on the pixel clk before the phy is set then the clk frequency will be
> > calculated badly and probably be incorrect.
>
> But the order of operations is mostly unchanged. The only major change
> is that the opp point is now set before calling the
> phy_configure()/phy_power_on()
Yes that's my concern. The qmp phy driver has a couple clk_set_rate()
calls in the .configure_dp_phy callback. That is called from
phy_power_on() (see qcom_qmp_phy_power_on() and qcom_qmp_phy_dp_ops).
Looking at qcom_qmp_v3_phy_configure_dp_phy() it does
clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 10);
clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
and I believe the child of dp_pixel_hw is find_clock("stream_pixel").
Looks like that is DISP_CC_MDSS_DP_PIXEL_CLK which is
disp_cc_mdss_dp_pixel_clk_src for the rate settable part. That has
clk_dp_ops which is clk_rcg2_dp_set_rate() for the set rate part. That
wants the parent clk frequency to be something non-zero to use in
rational_best_approximation(). If the clk_set_rate("stream_pixel") call
is made before phy_power_on() then the parent_rate in
clk_rcg2_dp_set_rate() won't be valid and the pixel clk frequency will
be wrong.
>
> For the pixel clock the driver has:
> static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
> {
> int ret = 0;
>
> dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
>
Re: [Freedreno] [PATCH v3 5/5] drm/msm: allow compile time selection of driver components
Quoting Dmitry Baryshkov (2022-03-03 19:21:06) > MSM DRM driver already allows one to compile out the DP or DSI support. > Add support for disabling other features like MDP4/MDP5/DPU drivers or > direct HDMI output support. > > Suggested-by: Stephen Boyd > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Stephen Boyd
Re: [Freedreno] [PATCH v3 4/5] drm/msm: stop using device's match data pointer
Quoting Dmitry Baryshkov (2022-03-03 19:21:05) > Let's make the match's data pointer a (sub-)driver's private data. The > only user currently is the msm_drm_init() function, using this data to > select kms_init callback. Pass this callback through the driver's > private data instead. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Stephen Boyd
Re: [Freedreno] [PATCH v3 3/5] drm/msm: split the main platform driver
Quoting Dmitry Baryshkov (2022-03-03 19:21:04)
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 857eefbb8649..c89de88ed2d1 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -255,3 +258,170 @@ struct msm_mdss *msm_mdss_init(struct platform_device
> *pdev, bool is_mdp5)
[...]
> +
> +static int mdss_probe(struct platform_device *pdev)
> +{
> + struct msm_mdss *mdss;
> + struct msm_drm_private *priv;
> + int mdp_ver = get_mdp_ver(pdev);
> + struct device *mdp_dev;
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, priv);
Is this set here so that msm_mdss_init() can use it? Can we pass 'priv'
as an argument to that function if so?
> +
> + mdss = msm_mdss_init(pdev, mdp_ver == KMS_MDP5);
> + if (IS_ERR(mdss)) {
> + ret = PTR_ERR(mdss);
> + platform_set_drvdata(pdev, NULL);
Is this platform_set_drvdata to NULL really necessary? It would be nice
to skip it so the mental load of this probe is lower.
> +
> + return ret;
> + }
> +
Re: [Freedreno] [PATCH v3 2/5] drm/msm: remove extra indirection for msm_mdss
Quoting Dmitry Baryshkov (2022-03-03 19:21:03) > Since now there is just one mdss subdriver, drop all the indirection, > make msm_mdss struct completely opaque (and defined inside msm_mdss.c) > and call mdss functions directly. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Stephen Boyd
Re: [Freedreno] [PATCH v3 1/5] drm/msm: unify MDSS drivers
Quoting Dmitry Baryshkov (2022-03-03 19:21:02) > MDP5 and DPU1 both provide the driver handling the MDSS region, which > handles the irq domain and (incase of DPU1) adds some init for the UBWC > controller. Unify those two pieces of code into a common driver. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Stephen Boyd
Re: [Freedreno] [PATCH] drm/msm/adreno: fix cast in adreno_get_param()
Quoting Dan Carpenter (2022-03-07 05:31:05)
> These casts need to happen before the shift. The only time it would
> matter would be if "rev.core" is >= 128. In that case the sign bit
> would be extended and we do not want that.
>
> Fixes: afab9d91d872 ("drm/msm/adreno: Expose speedbin to userspace")
> Signed-off-by: Dan Carpenter
> ---
Reviewed-by: Stephen Boyd
Re: [Freedreno] [PATCH v5 1/5] arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk
Quoting Vinod Polimera (2022-03-08 08:54:56)
> Kernel clock driver assumes that initial rate is the
> max rate for that clock and was not allowing it to scale
> beyond the assigned clock value.
How? I see ftbl_disp_cc_mdss_mdp_clk_src[] has multiple frequencies and
clk_rcg2_shared_ops so it doesn't look like anything in the clk driver
is preventing the frequency from changing beyond the assigned value.
>
> Drop the assigned clock rate property and vote on the mdp clock as per
> calculated value during the usecase.
>
> Changes in v2:
> - Remove assigned-clock-rate property and set mdp clk during resume sequence.
> - Add fixes tag.
>
> Changes in v3:
> - Remove extra line after fixes tag.(Stephen Boyd)
This changelog should be removed.
>
> Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes")
I thought folks were saying that this is bad to keep? I don't really
mind either way, but I guess it's better to drop the fixes tag because
this is largely a performance improvement?
> Signed-off-by: Vinod Polimera
> Reviewed-by: Stephen Boyd
Re: [Freedreno] [RESEND PATCH] dt-bindings: display/msm: add missing brace in dpu-qcm2290.yaml
On Tue, Mar 1, 2022 at 6:14 PM Dmitry Baryshkov wrote: > > Add missing brace in dpu-qcm2290.yaml. While we are at it, also fix > indentation for another brace, so it matches the corresponding line. > > Reported-by: Rob Herring > Cc: Loic Poulain > Reviewed-by: Bjorn Andersson > Signed-off-by: Dmitry Baryshkov > --- > Didn't include freedreno@ in the first email, so resending. > --- > Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Now that the example actually builds, we get just schema warnings: /builds/robherring/linux-dt/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.example.dt.yaml: mdss@5e0: compatible: ['qcom,qcm2290-mdss', 'qcom,mdss'] is too long >From schema: >/builds/robherring/linux-dt/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml /builds/robherring/linux-dt/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.example.dt.yaml: mdss@5e0: 'mdp@5e01000' does not match any of the regexes: '^display-controller@[0-9a-f]+$', 'pinctrl-[0-9]+' >From schema: >/builds/robherring/linux-dt/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml I would have assumed upon reporting errors with 'make dt_binding_check' that the fixes would be tested with 'make dt_binding_check'... Rob
Re: [Freedreno] [PATCH] drm/msm/gpu: Fix crash on devices without devfreq support (v2)
On Tue, Mar 8, 2022 at 10:53 AM Fabio Estevam wrote:
>
> On Tue, Mar 8, 2022 at 3:48 PM Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > Avoid going down devfreq paths on devices where devfreq is not
> > initialized.
> >
> > v2: Change has_devfreq() logic [Dmitry]
> >
> > Reported-by: Linux Kernel Functional Testing
> > Reported-by: Anders Roxell
Fixes: 6aa89ae1fb04 ("drm/msm/gpu: Cancel idle/boost work on suspend")
> > Signed-off-by: Rob Clark
>
> Does this need a Fixes tag?
Yes, sorry, patchwork had picked up the fixes tag from previous
version but I'd forgot to add it locally
BR,
-R
Re: [Freedreno] [PATCH] drm/msm/gpu: Fix crash on devices without devfreq support (v2)
On Tue, Mar 8, 2022 at 3:48 PM Rob Clark wrote: > > From: Rob Clark > > Avoid going down devfreq paths on devices where devfreq is not > initialized. > > v2: Change has_devfreq() logic [Dmitry] > > Reported-by: Linux Kernel Functional Testing > Reported-by: Anders Roxell > Signed-off-by: Rob Clark Does this need a Fixes tag?
[Freedreno] [PATCH] drm/msm/gpu: Fix crash on devices without devfreq support (v2)
From: Rob Clark
Avoid going down devfreq paths on devices where devfreq is not
initialized.
v2: Change has_devfreq() logic [Dmitry]
Reported-by: Linux Kernel Functional Testing
Reported-by: Anders Roxell
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gpu_devfreq.c | 30 ++-
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index 9bf319be11f6..12641616acd3 100644
--- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
+++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
@@ -83,6 +83,12 @@ static struct devfreq_dev_profile msm_devfreq_profile = {
static void msm_devfreq_boost_work(struct kthread_work *work);
static void msm_devfreq_idle_work(struct kthread_work *work);
+static bool has_devfreq(struct msm_gpu *gpu)
+{
+ struct msm_gpu_devfreq *df = &gpu->devfreq;
+ return !!df->devfreq;
+}
+
void msm_devfreq_init(struct msm_gpu *gpu)
{
struct msm_gpu_devfreq *df = &gpu->devfreq;
@@ -149,6 +155,9 @@ void msm_devfreq_cleanup(struct msm_gpu *gpu)
{
struct msm_gpu_devfreq *df = &gpu->devfreq;
+ if (!has_devfreq(gpu))
+ return;
+
devfreq_cooling_unregister(gpu->cooling);
dev_pm_qos_remove_request(&df->boost_freq);
dev_pm_qos_remove_request(&df->idle_freq);
@@ -156,16 +165,24 @@ void msm_devfreq_cleanup(struct msm_gpu *gpu)
void msm_devfreq_resume(struct msm_gpu *gpu)
{
- gpu->devfreq.busy_cycles = 0;
- gpu->devfreq.time = ktime_get();
+ struct msm_gpu_devfreq *df = &gpu->devfreq;
- devfreq_resume_device(gpu->devfreq.devfreq);
+ if (!has_devfreq(gpu))
+ return;
+
+ df->busy_cycles = 0;
+ df->time = ktime_get();
+
+ devfreq_resume_device(df->devfreq);
}
void msm_devfreq_suspend(struct msm_gpu *gpu)
{
struct msm_gpu_devfreq *df = &gpu->devfreq;
+ if (!has_devfreq(gpu))
+ return;
+
devfreq_suspend_device(df->devfreq);
cancel_idle_work(df);
@@ -185,6 +202,9 @@ void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor)
struct msm_gpu_devfreq *df = &gpu->devfreq;
uint64_t freq;
+ if (!has_devfreq(gpu))
+ return;
+
freq = get_freq(gpu);
freq *= factor;
@@ -207,7 +227,7 @@ void msm_devfreq_active(struct msm_gpu *gpu)
struct devfreq_dev_status status;
unsigned int idle_time;
- if (!df->devfreq)
+ if (!has_devfreq(gpu))
return;
/*
@@ -253,7 +273,7 @@ void msm_devfreq_idle(struct msm_gpu *gpu)
{
struct msm_gpu_devfreq *df = &gpu->devfreq;
- if (!df->devfreq)
+ if (!has_devfreq(gpu))
return;
msm_hrtimer_queue_work(&df->idle_work, ms_to_ktime(1),
--
2.35.1
Re: [Freedreno] [PATCH v5 5/5] drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe
On Tue, 8 Mar 2022 at 19:55, Vinod Polimera wrote: > > use max clock during probe/bind sequence from the opp table. > The clock will be scaled down when framework sends an update. > > Signed-off-by: Vinod Polimera > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index d550f90..d9922b9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1221,6 +1221,7 @@ static int dpu_bind(struct device *dev, struct device > *master, void *data) > struct dpu_kms *dpu_kms; > struct dss_module_power *mp; > int ret = 0; > + unsigned long max_freq = ULONG_MAX; > > dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); > if (!dpu_kms) > @@ -1243,6 +1244,8 @@ static int dpu_bind(struct device *dev, struct device > *master, void *data) > return ret; > } > > + dev_pm_opp_find_freq_floor(dev, &max_freq); You leak a reference to the opp here. The function returns a value, which should be dev_pm_opp_put(). Moreover judging from the dev_pm_opp_set_rate() code I think you don't have to find an exact frequency, as it will call clk_round_rate()/_find_freq_ceil() anyway. Could you please check that it works? > + dev_pm_opp_set_rate(dev, max_freq); > platform_set_drvdata(pdev, dpu_kms); > > ret = msm_kms_init(&dpu_kms->base, &kms_funcs); > -- > 2.7.4 > -- With best wishes Dmitry
[Freedreno] [PATCH v5 0/5] Update mdp clk to max supported value to support higher refresh rates
Kernel clock driver assumes that initial rate is the max rate for that clock and was not allowing it to scale beyond the assigned clock value. Drop the assigned clock rate property and vote on the mdp clock as per calculated value during the usecase. Changes in v2: - Remove assigned-clock-rate property and set mdp clk during resume sequence. - Add fixes tag. Changes in v3: - Remove extra line after fixes tag.(Stephen Boyd) - Add similar changes for sc7180, sdm845 which uses opp table for voting mdp clk.(Stephen Boyd) - Drop patch: "drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table" Changes in v4: - Add similar change for sm8250.(Dmitry) Changes in v5: - Add change to set mdp clk to max frequency in opp table during mdp probe/bind. Vinod Polimera (5): arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk arm64/dts/qcom/sc7180: remove assigned-clock-rate property for mdp clk arm64/dts/qcom/sdm845: remove assigned-clock-rate property for mdp clk arm64/dts/qcom/sm8250: remove assigned-clock-rate property for mdp clk drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe arch/arm64/boot/dts/qcom/sc7180.dtsi| 9 ++--- arch/arm64/boot/dts/qcom/sc7280.dtsi| 9 ++--- arch/arm64/boot/dts/qcom/sdm845.dtsi| 9 ++--- arch/arm64/boot/dts/qcom/sm8250.dtsi| 9 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++ 5 files changed, 11 insertions(+), 28 deletions(-) -- 2.7.4
[Freedreno] [PATCH v5 4/5] arm64/dts/qcom/sm8250: remove assigned-clock-rate property for mdp clk
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Fixes: 7c1dffd471("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index fdaf303..2105eb7 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3164,9 +3164,6 @@
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "bus", "nrt_bus", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <46000>;
-
interrupts = ;
interrupt-controller;
#interrupt-cells = <1>;
@@ -3191,10 +3188,8 @@
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface", "bus", "core", "vsync";
- assigned-clocks = <&dispcc
DISP_CC_MDSS_MDP_CLK>,
- <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <46000>,
- <1920>;
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
--
2.7.4
[Freedreno] [PATCH v5 5/5] drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe
use max clock during probe/bind sequence from the opp table. The clock will be scaled down when framework sends an update. Signed-off-by: Vinod Polimera --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index d550f90..d9922b9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1221,6 +1221,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) struct dpu_kms *dpu_kms; struct dss_module_power *mp; int ret = 0; + unsigned long max_freq = ULONG_MAX; dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); if (!dpu_kms) @@ -1243,6 +1244,8 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) return ret; } + dev_pm_opp_find_freq_floor(dev, &max_freq); + dev_pm_opp_set_rate(dev, max_freq); platform_set_drvdata(pdev, dpu_kms); ret = msm_kms_init(&dpu_kms->base, &kms_funcs); -- 2.7.4
[Freedreno] [PATCH v5 2/5] arm64/dts/qcom/sc7180: remove assigned-clock-rate property for mdp clk
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Fixes: a3db7ad1af("arm64: dts: qcom: sc7180: add display dt nodes")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index e1c46b8..eaab746 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2900,9 +2900,6 @@
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "ahb", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <3>;
-
interrupts = ;
interrupt-controller;
#interrupt-cells = <1>;
@@ -2932,12 +2929,10 @@
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "rot", "lut",
"core",
"vsync";
- assigned-clocks = <&dispcc
DISP_CC_MDSS_MDP_CLK>,
- <&dispcc
DISP_CC_MDSS_VSYNC_CLK>,
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc
DISP_CC_MDSS_ROT_CLK>,
<&dispcc
DISP_CC_MDSS_AHB_CLK>;
- assigned-clock-rates = <3>,
- <1920>,
+ assigned-clock-rates = <1920>,
<1920>,
<1920>;
operating-points-v2 = <&mdp_opp_table>;
--
2.7.4
[Freedreno] [PATCH v5 1/5] arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Changes in v2:
- Remove assigned-clock-rate property and set mdp clk during resume sequence.
- Add fixes tag.
Changes in v3:
- Remove extra line after fixes tag.(Stephen Boyd)
Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index baf1653..408cf6c 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2856,9 +2856,6 @@
"ahb",
"core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <3>;
-
interrupts = ;
interrupt-controller;
#interrupt-cells = <1>;
@@ -2892,11 +2889,9 @@
"lut",
"core",
"vsync";
- assigned-clocks = <&dispcc
DISP_CC_MDSS_MDP_CLK>,
- <&dispcc
DISP_CC_MDSS_VSYNC_CLK>,
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>;
- assigned-clock-rates = <3>,
- <1920>,
+ assigned-clock-rates = <1920>,
<1920>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;
--
2.7.4
[Freedreno] [PATCH v5 3/5] arm64/dts/qcom/sdm845: remove assigned-clock-rate property for mdp clk
Kernel clock driver assumes that initial rate is the
max rate for that clock and was not allowing it to scale
beyond the assigned clock value.
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
Fixes: 08c2a076d1("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file")
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0d6286d..80dc486 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4181,9 +4181,6 @@
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <3>;
-
interrupts = ;
interrupt-controller;
#interrupt-cells = <1>;
@@ -4214,10 +4211,8 @@
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "gcc-bus", "iface", "bus",
"core", "vsync";
- assigned-clocks = <&dispcc
DISP_CC_MDSS_MDP_CLK>,
- <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <3>,
- <1920>;
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
--
2.7.4
Re: [Freedreno] [PATCH v1 02/10] drm/msm/a6xx: Send NMI to gmu when it is hung
Hi Akhil,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-intel/for-linux-next drm-tip/drm-tip
drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next v5.17-rc7 next-20220308]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Akhil-P-Oommen/Support-for-GMU-coredump-and-some-related-improvements/20220303-013028
base: git://anongit.freedesktop.org/drm/drm drm-next
config: riscv-randconfig-r042-20220307
(https://download.01.org/0day-ci/archive/20220308/202203082018.ici00nvs-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
d271fc04d5b97b12e6b797c6067d3c96a8d7470e)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install riscv cross compiling tool for clang build
# apt-get install binutils-riscv64-linux-gnu
#
https://github.com/0day-ci/linux/commit/23953efc645803299a93f178e9a32f2ae97dae39
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Akhil-P-Oommen/Support-for-GMU-coredump-and-some-related-improvements/20220303-013028
git checkout 23953efc645803299a93f178e9a32f2ae97dae39
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=riscv SHELL=/bin/bash drivers/gpu/drm/msm/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:967:6: warning: no previous
>> prototype for function 'a6xx_get_gmu_state' [-Wmissing-prototypes]
void a6xx_get_gmu_state(struct msm_gpu *gpu, struct a6xx_gpu_state
*a6xx_state)
^
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:967:1: note: declare 'static' if
the function is not intended to be used outside of this translation unit
void a6xx_get_gmu_state(struct msm_gpu *gpu, struct a6xx_gpu_state
*a6xx_state)
^
static
1 warning generated.
vim +/a6xx_get_gmu_state +967 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
966
> 967 void a6xx_get_gmu_state(struct msm_gpu *gpu, struct a6xx_gpu_state
> *a6xx_state)
968 {
969 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
970 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
971 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
972
973 if (gmu->hung)
974 a6xx_gmu_send_nmi(gmu);
975
976 a6xx_get_gmu_registers(gpu, a6xx_state);
977 }
978
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
