[Freedreno] [PATCH v2] drm/msm/dpu: Fix memory leak in msm_mdss_parse_data_bus_icc_path
of_icc_get() alloc resources for path1, we should release it when not
need anymore. Early return when IS_ERR_OR_NULL(path0) may leak path1.
Defer getting path1 to fix this.
Fixes: b9364eed9232 ("drm/msm/dpu: Move min BW request and full BW disable back
to mdss")
Signed-off-by: Miaoqian Lin
---
changes in v2:
- move getting path1 after error check for path0.
---
drivers/gpu/drm/msm/msm_mdss.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e13c5c12b775..3b8d6991b04e 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -46,15 +46,17 @@ struct msm_mdss {
static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
struct msm_mdss *msm_mdss)
{
- struct icc_path *path0 = of_icc_get(dev, "mdp0-mem");
- struct icc_path *path1 = of_icc_get(dev, "mdp1-mem");
+ struct icc_path *path0;
+ struct icc_path *path1;
+ path0 = of_icc_get(dev, "mdp0-mem");
if (IS_ERR_OR_NULL(path0))
return PTR_ERR_OR_ZERO(path0);
msm_mdss->path[0] = path0;
msm_mdss->num_paths = 1;
+ path1 = of_icc_get(dev, "mdp1-mem");
if (!IS_ERR_OR_NULL(path1)) {
msm_mdss->path[1] = path1;
msm_mdss->num_paths++;
--
2.25.1
[Freedreno] [PATCH v4 5/5] arm64: dts: qcom: sm8450-hdk: Enable HDMI Display
From: Vinod Koul
Add the HDMI display nodes and link it to DSI.
Signed-off-by: Vinod Koul
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 4f345786352a..166458963c2f 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+ };
+
lt9611_1v2: lt9611-vdd12-regulator {
compatible = "regulator-fixed";
regulator-name = "LT9611_1V2";
@@ -392,6 +403,27 @@ lt9611_codec: hdmi-bridge@2b {
pinctrl-names = "default";
pinctrl-0 = <_irq_pin _rst_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <_connector_out>;
+ };
+ };
+ };
};
};
@@ -404,6 +436,11 @@ _dsi0 {
status = "okay";
};
+_dsi0_out {
+ remote-endpoint = <_a>;
+ data-lanes = <0 1 2 3>;
+};
+
_dsi0_phy {
vdds-supply = <_l5b_0p88>;
status = "okay";
--
2.35.1
[Freedreno] [PATCH v4 3/5] arm64: dts: qcom: sm8450-hdk: enable display hardware
Enable MDSS/DPU/DSI0 on SM8450-HDK device.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 2dd4f8c8f931..75b7aecb7d8e 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -349,6 +349,28 @@ vreg_l7e_2p8: ldo7 {
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_dsi0 {
+ vdda-supply = <_l6b_1p2>;
+ status = "okay";
+};
+
+_dsi0_phy {
+ vdds-supply = <_l5b_0p88>;
+ status = "okay";
+};
+
+_mdp {
+ status = "okay";
+};
+
{
status = "okay";
max-link-speed = <2>;
--
2.35.1
[Freedreno] [PATCH v4 2/5] arm64: dts: qcom: sm8450: add display hardware devices
Add devices tree nodes describing display hardware on SM8450:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs
This does not provide support for DP controllers present on SM8450.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 283 ++-
1 file changed, 279 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 8cc9f62f7645..3a3819852eae 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2394,6 +2394,281 @@ camcc: clock-controller@ade {
status = "disabled";
};
+ mdss: display-subsystem@ae0 {
+ compatible = "qcom,sm8450-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <_noc MASTER_MDP_DISP 0 _virt
SLAVE_EBI1_DISP 0>,
+ <_noc MASTER_MDP_DISP 0 _virt
SLAVE_EBI1_DISP 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ resets = < DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = < MDSS_GDSC>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_smmu 0x2800 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8450-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SM8450_MMCX>;
+
+ interrupt-parent = <>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint =
<_dsi1_in>;
+ };
+ };
+
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-17200 {
+ opp-hz = /bits/ 64 <17200>;
+ required-opps =
<_opp_low_svs_d1>;
+ };
+
+ opp-2 {
+ opp-hz = /bits/ 64 <2>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+
[Freedreno] [PATCH v4 1/5] arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1
Add another power saving state used on SM8450. Unfortunately adding it
in proper place causes renumbering of all the opp states in sm8450.dtsi
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20
include/dt-bindings/power/qcom-rpmpd.h | 1 +
2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index f20db5456765..8cc9f62f7645 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3211,35 +3211,39 @@ rpmhpd_opp_min_svs: opp2 {
opp-level =
;
};
- rpmhpd_opp_low_svs: opp3 {
+ rpmhpd_opp_low_svs_d1: opp3 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_low_svs: opp4 {
opp-level =
;
};
- rpmhpd_opp_svs: opp4 {
+ rpmhpd_opp_svs: opp5 {
opp-level =
;
};
- rpmhpd_opp_svs_l1: opp5 {
+ rpmhpd_opp_svs_l1: opp6 {
opp-level =
;
};
- rpmhpd_opp_nom: opp6 {
+ rpmhpd_opp_nom: opp7 {
opp-level =
;
};
- rpmhpd_opp_nom_l1: opp7 {
+ rpmhpd_opp_nom_l1: opp8 {
opp-level =
;
};
- rpmhpd_opp_nom_l2: opp8 {
+ rpmhpd_opp_nom_l2: opp9 {
opp-level =
;
};
- rpmhpd_opp_turbo: opp9 {
+ rpmhpd_opp_turbo: opp10 {
opp-level =
;
};
- rpmhpd_opp_turbo_l1: opp10 {
+ rpmhpd_opp_turbo_l1: opp11 {
opp-level =
;
};
};
diff --git a/include/dt-bindings/power/qcom-rpmpd.h
b/include/dt-bindings/power/qcom-rpmpd.h
index 7b2e4b66419a..701401c8b945 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -174,6 +174,7 @@
/* SDM845 Power Domain performance levels */
#define RPMH_REGULATOR_LEVEL_RETENTION 16
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D156
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
#define RPMH_REGULATOR_LEVEL_SVS 128
#define RPMH_REGULATOR_LEVEL_SVS_L0144
--
2.35.1
[Freedreno] [PATCH v4 0/5] arm64: dts: qcom: sm8450-hdk: enable HDMI output
Add device tree nodes for MDSS, DPU and DSI devices on Qualcomm SM8450 platform. Enable these devices and add the HDMI bridge configuration on SM8450 HDK. Changes since v3: - Renamed mdss node to display-subsystem@ (Krzysztof) - Dropped empty line from the patch4 (Krzysztof) - Renamed HDMI connector endpoint to hdmi_connector_out Changes since v2: - Dropped clock-names from mdss device node - Fixed pinctrl configuration used by lt9611uxc (Krzysztof) Changes since v1: - Reorder properties, making status the last one - Rename opp nodes to follow the schema - Renamed display-controller and phy device nodes - Dropped phy-names for DSI PHYs - Renamed DSI and DSI PHY labels to include mdss_ prefix - Renamed 3v3 regulator device node to add -regulator suffix Dmitry Baryshkov (3): arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1 arm64: dts: qcom: sm8450: add display hardware devices arm64: dts: qcom: sm8450-hdk: enable display hardware Vinod Koul (2): arm64: dts: qcom: sm8450-hdk: Add LT9611uxc HDMI bridge arm64: dts: qcom: sm8450-hdk: Enable HDMI Display arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 117 + arch/arm64/boot/dts/qcom/sm8450.dtsi| 303 +++- include/dt-bindings/power/qcom-rpmpd.h | 1 + 3 files changed, 409 insertions(+), 12 deletions(-) -- 2.35.1
[Freedreno] [PATCH v4 4/5] arm64: dts: qcom: sm8450-hdk: Add LT9611uxc HDMI bridge
From: Vinod Koul
Add the LT9611uxc DSI-HDMI bridge and supplies
Signed-off-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 58 +
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 75b7aecb7d8e..4f345786352a 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -20,6 +20,28 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ lt9611_1v2: lt9611-vdd12-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <_pwr>;
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ gpio = < 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ lt9611_3v3: lt9611-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <_bob>;
+ gpio = < 109 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ enable-active-high;
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -353,6 +375,26 @@ {
status = "okay";
};
+ {
+ clock-frequency = <40>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = < 44 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = < 107 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <_1v2>;
+ vcc-supply = <_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_irq_pin _rst_pin>;
+ };
+};
+
{
status = "okay";
};
@@ -416,6 +458,10 @@ _id_0 {
status = "okay";
};
+_id_1 {
+ status = "okay";
+};
+
_2 {
cd-gpios = < 92 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
@@ -431,6 +477,18 @@ _2 {
{
gpio-reserved-ranges = <28 4>, <36 4>;
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio44";
+ function = "gpio";
+ bias-disable;
+ };
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio107";
+ function = "gpio";
+ output-high;
+ };
+
sdc2_card_det_n: sd-card-det-n-state {
pins = "gpio92";
function = "gpio";
--
2.35.1
[Freedreno] [PATCH v6 11/11] drm/msm: mdss add support for SM8450
Add support for the MDSS block on SM8450 platform.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 86b28add1fff..144c8dd82be1 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -287,6 +287,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
+ case DPU_HW_VER_810:
+ /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
+ break;
}
return ret;
@@ -516,6 +520,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sm6115-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8450-mdss" },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
--
2.35.1
[Freedreno] [PATCH v6 08/11] drm/msm/dpu: merge all MDP TOP registers to dpu_hwio.h
There is a separate header containing some of MDP TOP register
definitions, dpu_hwio.h. Move missing register definitions from
dpu_hw_top.c to the mentioned header.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 25 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 18
2 files changed, 18 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index c3110a25a30d..2bb02e17ee52 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -7,40 +7,17 @@
#include "dpu_hw_top.h"
#include "dpu_kms.h"
-#define SSPP_SPARE0x28
-
#define FLD_SPLIT_DISPLAY_CMD BIT(1)
#define FLD_SMART_PANEL_FREE_RUN BIT(2)
#define FLD_INTF_1_SW_TRG_MUX BIT(4)
#define FLD_INTF_2_SW_TRG_MUX BIT(8)
#define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0x
-#define DANGER_STATUS 0x360
-#define SAFE_STATUS 0x364
-
-#define TE_LINE_INTERVAL 0x3F4
-
#define TRAFFIC_SHAPER_EN BIT(31)
#define TRAFFIC_SHAPER_RD_CLIENT(num) (0x030 + (num * 4))
#define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4))
#define TRAFFIC_SHAPER_FIXPOINT_FACTOR4
-#define MDP_WD_TIMER_0_CTL0x380
-#define MDP_WD_TIMER_0_CTL2 0x384
-#define MDP_WD_TIMER_0_LOAD_VALUE 0x388
-#define MDP_WD_TIMER_1_CTL0x390
-#define MDP_WD_TIMER_1_CTL2 0x394
-#define MDP_WD_TIMER_1_LOAD_VALUE 0x398
-#define MDP_WD_TIMER_2_CTL0x420
-#define MDP_WD_TIMER_2_CTL2 0x424
-#define MDP_WD_TIMER_2_LOAD_VALUE 0x428
-#define MDP_WD_TIMER_3_CTL0x430
-#define MDP_WD_TIMER_3_CTL2 0x434
-#define MDP_WD_TIMER_3_LOAD_VALUE 0x438
-#define MDP_WD_TIMER_4_CTL0x440
-#define MDP_WD_TIMER_4_CTL2 0x444
-#define MDP_WD_TIMER_4_LOAD_VALUE 0x448
-
#define MDP_TICK_COUNT16
#define XO_CLK_RATE 19200
#define MS_TICKS_IN_SEC 1000
@@ -48,8 +25,6 @@
#define CALCULATE_WD_LOAD_VALUE(fps) \
((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
-#define DCE_SEL 0x450
-
static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
struct split_pipe_cfg *cfg)
{
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
index c8156ed4b7fb..86c423e63b61 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
@@ -16,6 +16,7 @@
#define INTR_CLEAR 0x018
#define INTR2_EN0x008
#define INTR2_STATUS0x00c
+#define SSPP_SPARE 0x028
#define INTR2_CLEAR 0x02c
#define HIST_INTR_EN0x01c
#define HIST_INTR_STATUS0x020
@@ -28,7 +29,15 @@
#define DSPP_IGC_COLOR0_RAM_LUTN0x300
#define DSPP_IGC_COLOR1_RAM_LUTN0x304
#define DSPP_IGC_COLOR2_RAM_LUTN0x308
+#define DANGER_STATUS 0x360
+#define SAFE_STATUS 0x364
#define HW_EVENTS_CTL 0x37C
+#define MDP_WD_TIMER_0_CTL 0x380
+#define MDP_WD_TIMER_0_CTL2 0x384
+#define MDP_WD_TIMER_0_LOAD_VALUE 0x388
+#define MDP_WD_TIMER_1_CTL 0x390
+#define MDP_WD_TIMER_1_CTL2 0x394
+#define MDP_WD_TIMER_1_LOAD_VALUE 0x398
#define CLK_CTRL3 0x3A8
#define CLK_STATUS3 0x3AC
#define CLK_CTRL4 0x3B0
@@ -43,6 +52,15 @@
#define HDMI_DP_CORE_SELECT 0x408
#define MDP_OUT_CTL_0 0x410
#define MDP_VSYNC_SEL 0x414
+#define MDP_WD_TIMER_2_CTL 0x420
+#define MDP_WD_TIMER_2_CTL2 0x424
+#define MDP_WD_TIMER_2_LOAD_VALUE 0x428
+#define MDP_WD_TIMER_3_CTL 0x430
+#define MDP_WD_TIMER_3_CTL2 0x434
+#define MDP_WD_TIMER_3_LOAD_VALUE 0x438
+#define MDP_WD_TIMER_4_CTL 0x440
+#define MDP_WD_TIMER_4_CTL2 0x444
+#define MDP_WD_TIMER_4_LOAD_VALUE 0x448
#define DCE_SEL 0x450
#endif /*_DPU_HWIO_H */
--
2.35.1
[Freedreno] [PATCH v6 09/11] drm/msm/dpu: add support for MDP_TOP blackhole
On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 11 +--
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 3b645d5aa9aa..a9d161daf786 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -83,6 +83,8 @@ enum {
* @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
* compression initial revision
* @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
+ * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results
+ *in a failure
* @DPU_MDP_MAXMaximum value
*/
@@ -93,6 +95,7 @@ enum {
DPU_MDP_UBWC_1_0,
DPU_MDP_UBWC_1_5,
DPU_MDP_AUDIO_SELECT,
+ DPU_MDP_PERIPH_0_REMOVED,
DPU_MDP_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
index 86c423e63b61..feb9a729844a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
@@ -63,4 +63,7 @@
#define MDP_WD_TIMER_4_LOAD_VALUE 0x448
#define DCE_SEL 0x450
+#define MDP_PERIPH_TOP0MDP_WD_TIMER_0_CTL
+#define MDP_PERIPH_TOP0_ENDCLK_CTRL3
+
#endif /*_DPU_HWIO_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index b71199511a52..987a74fb7fad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state
*disp_state, struct msm_k
msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
- msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
- dpu_kms->mmio + cat->mdp[0].base, "top");
+ if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
+ msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
+ dpu_kms->mmio + cat->mdp[0].base, "top");
+ msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len -
MDP_PERIPH_TOP0_END,
+ dpu_kms->mmio + cat->mdp[0].base +
MDP_PERIPH_TOP0_END, "top_2");
+ } else {
+ msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
+ dpu_kms->mmio + cat->mdp[0].base, "top");
+ }
pm_runtime_put_sync(_kms->pdev->dev);
}
--
2.35.1
[Freedreno] [PATCH v6 07/11] drm/msm/dsi: add support for DSI 2.6.0
Add support for DSI 2.6.0 (block used on sm8450).
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 7e97c239ed48..59a4cc95a251 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[]
= {
_dsi_cfg, _dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
_dsi_cfg, _dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
+ _dsi_cfg, _dsi_6g_v2_host_ops},
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 8f04e685a74e..95957fab499d 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -25,6 +25,7 @@
#define MSM_DSI_6G_VER_MINOR_V2_4_00x2004
#define MSM_DSI_6G_VER_MINOR_V2_4_10x20040001
#define MSM_DSI_6G_VER_MINOR_V2_5_00x2005
+#define MSM_DSI_6G_VER_MINOR_V2_6_00x2006
#define MSM_DSI_V2_VER_MINOR_8064 0x0
--
2.35.1
[Freedreno] [PATCH v6 04/11] dt-bindings: display/msm: add support for the display on SM8450
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM8450 platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/qcom,sm8450-dpu.yaml | 139 +++
.../display/msm/qcom,sm8450-mdss.yaml | 343 ++
2 files changed, 482 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
new file mode 100644
index ..0d17ece1c453
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8450 Display DPU
+
+maintainers:
+ - Dmitry Baryshkov
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8450-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi
+ - description: Display sf axi
+ - description: Display ahb
+ - description: Display lut
+ - description: Display core
+ - description: Display vsync
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8450-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_LUT_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SM8450_MMCX>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+dpu_intf2_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-17200{
+opp-hz = /bits/ 64 <17200>;
+required-opps = <_opp_low_svs_d1>;
+};
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <_opp_low_svs>;
+};
+
+opp-32500 {
+opp-hz = /bits/ 64 <32500>;
+required-opps = <_opp_svs>;
+};
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <_opp_nom>;
+};
+};
+};
+...
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
new file mode 100644
index ..c268e0b662cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
@@ -0,0 +1,343 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8450 Display MDSS
+
+maintainers:
+ - Dmitry Baryshkov
+
+description:
+ SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
[Freedreno] [PATCH v6 10/11] drm/msm/dpu: add support for SM8450
Add definitions for the display hardware used on Qualcomm SM8450
platform.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 224 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 229 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2196e205efa5..b4ca123d8e69 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -124,6 +124,15 @@
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR))
+#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
@@ -379,6 +388,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8450_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -529,6 +552,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8450_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2BC, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -687,6 +737,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8450_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features =
[Freedreno] [PATCH v6 05/11] drm/msm/dsi/phy: rework register setting for 7nm PHY
In preparation to adding the sm8350 and sm8450 PHYs support, rearrange
register values calculations in dsi_7nm_phy_enable(). This change bears
no functional changes itself, it is merely a preparation for the next
patch.
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 26 +++
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 9e7fa7d88ead..0b780f9d3d0a 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -858,23 +858,34 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
/* Alter PHY configurations if data rate less than 1.5GHZ*/
less_than_1500_mhz = (clk_req->bitclk_rate <= 15);
+ if (phy->cphy_mode) {
+ vreg_ctrl_0 = 0x51;
+ vreg_ctrl_1 = 0x55;
+ glbl_pemph_ctrl_0 = 0x11;
+ lane_ctrl0 = 0x17;
+ } else {
+ vreg_ctrl_1 = 0x5c;
+ glbl_pemph_ctrl_0 = 0x00;
+ lane_ctrl0 = 0x1f;
+ }
+
if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
- vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
if (phy->cphy_mode) {
glbl_rescode_top_ctrl = 0x00;
glbl_rescode_bot_ctrl = 0x3c;
} else {
+ vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :
0x00;
glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 :
0x3c;
}
glbl_str_swi_cal_sel_ctrl = 0x00;
glbl_hstx_str_ctrl_0 = 0x88;
} else {
- vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
if (phy->cphy_mode) {
glbl_str_swi_cal_sel_ctrl = 0x03;
glbl_hstx_str_ctrl_0 = 0x66;
} else {
+ vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 :
0x00;
glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
}
@@ -882,17 +893,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
glbl_rescode_bot_ctrl = 0x3c;
}
- if (phy->cphy_mode) {
- vreg_ctrl_0 = 0x51;
- vreg_ctrl_1 = 0x55;
- glbl_pemph_ctrl_0 = 0x11;
- lane_ctrl0 = 0x17;
- } else {
- vreg_ctrl_1 = 0x5c;
- glbl_pemph_ctrl_0 = 0x00;
- lane_ctrl0 = 0x1f;
- }
-
/* de-assert digital and pll power down */
data = BIT(6) | BIT(5);
dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
--
2.35.1
[Freedreno] [PATCH v6 02/11] dt-bindings: display/msm: *mdss.yaml: split required properties clauses
Require only properties declared in given schema, which makes the code a bit more readable and easy to follow. Suggested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/mdss-common.yaml | 1 - .../devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml | 3 +++ .../devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 3 +++ .../devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml | 3 +++ .../devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml | 3 +++ .../devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml | 3 +++ .../devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml | 3 +++ 7 files changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index 27d7242657b2..59f17ac898aa 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -70,7 +70,6 @@ properties: - description: MDSS_CORE reset required: - - compatible - reg - reg-names - power-domains diff --git a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml index cf52ff77a41a..fc6969c9c52e 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml @@ -55,6 +55,9 @@ patternProperties: compatible: const: qcom,dsi-phy-10nm-8998 +required: + - compatible + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index d6f043a4b08d..0c2f9755125e 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -61,6 +61,9 @@ patternProperties: compatible: const: qcom,dsi-phy-14nm-2290 +required: + - compatible + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml index 13e396d61a51..fb835a4d9114 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml @@ -67,6 +67,9 @@ patternProperties: compatible: const: qcom,dsi-phy-10nm +required: + - compatible + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index a3de1744ba11..a4e3ada2affc 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -74,6 +74,9 @@ patternProperties: - qcom,sc7280-dsi-phy-7nm - qcom,sc7280-edp-phy +required: + - compatible + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml index 31ca6f99fc22..2a0960bf3052 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml @@ -59,6 +59,9 @@ patternProperties: compatible: const: qcom,dsi-phy-10nm +required: + - compatible + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml index 0d3be5386b3f..d752fd022ac5 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml @@ -63,6 +63,9 @@ patternProperties: compatible: const: qcom,dsi-phy-7nm +required: + - compatible + unevaluatedProperties: false examples: -- 2.35.1
[Freedreno] [PATCH v6 06/11] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.
Co-developed-by: Robert Foss
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 6 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 119 --
4 files changed, 118 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 3c9dfdb0b328..e7b100d97f88 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
Choose this option if DSI PHY on SDM845 is used on the platform.
config DRM_MSM_DSI_7NM_PHY
- bool "Enable DSI 7nm PHY driver in MSM DRM"
+ bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
default y
help
- Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
- the platform.
+ Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
+ is used on the platform.
config DRM_MSM_HDMI
bool "Enable HDMI support in MSM DRM driver"
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index ee6051367679..0c956fdab23e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -569,6 +569,10 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = _phy_7nm_8150_cfgs },
{ .compatible = "qcom,sc7280-dsi-phy-7nm",
.data = _phy_7nm_7280_cfgs },
+ { .compatible = "qcom,dsi-phy-5nm-8350",
+ .data = _phy_5nm_8350_cfgs },
+ { .compatible = "qcom,dsi-phy-5nm-8450",
+ .data = _phy_5nm_8450_cfgs },
#endif
{}
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 1096afedd616..f7a907ed2b4b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 0b780f9d3d0a..7b2c16b3a36c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -39,8 +39,14 @@
#define VCO_REF_CLK_RATE 1920
#define FRAC_BITS 18
+/* Hardware is pre V4.1 */
+#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
/* Hardware is V4.1 */
-#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
+#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
+/* Hardware is V4.2 */
+#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
+/* Hardware is V4.3 */
+#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
struct dsi_pll_config {
bool enable_ssc;
@@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll,
struct dsi_pll_config
dec_multiple = div_u64(pll_freq * multiplier, divider);
dec = div_u64_rem(dec_multiple, multiplier, );
- if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
+ if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
config->pll_clock_inverters = 0x28;
else if (pll_freq <= 10ULL)
config->pll_clock_inverters = 0xa0;
@@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm
*pll)
void __iomem *base = pll->phy->pll_base;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
- if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
+ if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
if (pll->vco_current_rate >= 31ULL)
analog_controls_five_1 = 0x03;
+ if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
if (pll->vco_current_rate < 152000ULL)
vco_config_1 = 0x08;
else if (pll->vco_current_rate < 299000ULL)
vco_config_1 = 0x01;
}
+ if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
+ (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
+ if (pll->vco_current_rate < 152000ULL)
+ vco_config_1 = 0x08;
+ else if (pll->vco_current_rate >= 299000ULL)
+ vco_config_1 = 0x01;
+ }
+
dsi_phy_write(base +
[Freedreno] [PATCH v6 01/11] dt-bindings: display/msm: *dpu.yaml: split required properties clauses
Require only properties declared in given schema, which makes the code a bit more readable and easy to follow. Suggested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dpu-common.yaml| 4 .../devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml | 7 +++ .../devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml | 7 +++ .../devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml | 7 +++ .../devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml | 7 +++ .../devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml | 7 +++ .../devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml | 7 +++ 7 files changed, 42 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml index 8ffbc30c6b7f..870158bb2aa0 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -40,10 +40,6 @@ properties: - port@0 required: - - compatible - - reg - - reg-names - - clocks - interrupts - power-domains - operating-points-v2 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml index b02adba36e9e..479ce75bd451 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml @@ -46,6 +46,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml index a7b382f01b56..e794f0dd8ef4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml @@ -42,6 +42,13 @@ properties: - const: lut - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index bd590a6b5b96..0dfdf8f3c5b4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -44,6 +44,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 924059b387b6..512d23f8d629 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -43,6 +43,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml index 5719b45f2860..d5a55e898b11 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml @@ -42,6 +42,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml index 9ff8a265c85f..687c8c170cd4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml @@ -39,6 +39,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: -- 2.35.1
[Freedreno] [PATCH v6 03/11] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs
SM8350 and SM8450 platforms use the same driver and same bindings as the existing 7nm DSI PHYs. Add corresponding compatibility strings. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index c851770bbdf2..bffd161fedfd 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -15,6 +15,8 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-5nm-8350 + - qcom,dsi-phy-5nm-8450 - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,sc7280-dsi-phy-7nm -- 2.35.1
[Freedreno] [PATCH v6 00/11] drm/msm: add support for SM8450
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform. Change since v5: - Added defines to be used for the MDP_PERIPH_TOP0 blackhole Change since v4: - Fixed commit messages for the first two patches (Krzysztof) - Dropped clock-names requirement patch - Removed clock-names from qcom,sm8450-mdss.yaml schema - Fixed the schema changes lost between v3 and v4 (thanks Krzysztof) - Added kernel doc for DPU_MDP_PERIPH_0_REMOVED (Abhinav) - Fixed build issue in dpu_kms_mdp_snapshot() (Niel) Change since v3: - Reworked the dpu-common.yaml / mdss-common.yaml to require properties from the same schema where they are defined (Krzysztof) - Reworked PHY register settings to make it easier to understand (Konrad) Change since v2: - Rebased onto msm-next-lumag - Cleaned up bindings according to Krzysztof's suggestions Change since v1: - Fixed the regdma pointer in sm8450_dpu_cfg - Rebased onto pending msm-next-lumag - Added DT bindings for corresponding devices Dmitry Baryshkov (11): dt-bindings: display/msm: *dpu.yaml: split required properties clauses dt-bindings: display/msm: *mdss.yaml: split required properties clauses dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs dt-bindings: display/msm: add support for the display on SM8450 drm/msm/dsi/phy: rework register setting for 7nm PHY drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 drm/msm/dsi: add support for DSI 2.6.0 drm/msm/dpu: merge all MDP TOP registers to dpu_hwio.h drm/msm/dpu: add support for MDP_TOP blackhole drm/msm/dpu: add support for SM8450 drm/msm: mdss add support for SM8450 .../bindings/display/msm/dpu-common.yaml | 4 - .../bindings/display/msm/dsi-phy-7nm.yaml | 2 + .../bindings/display/msm/mdss-common.yaml | 1 - .../display/msm/qcom,msm8998-dpu.yaml | 7 + .../display/msm/qcom,msm8998-mdss.yaml| 3 + .../display/msm/qcom,qcm2290-dpu.yaml | 7 + .../display/msm/qcom,qcm2290-mdss.yaml| 3 + .../bindings/display/msm/qcom,sc7180-dpu.yaml | 7 + .../display/msm/qcom,sc7180-mdss.yaml | 3 + .../bindings/display/msm/qcom,sc7280-dpu.yaml | 7 + .../display/msm/qcom,sc7280-mdss.yaml | 3 + .../bindings/display/msm/qcom,sdm845-dpu.yaml | 7 + .../display/msm/qcom,sdm845-mdss.yaml | 3 + .../bindings/display/msm/qcom,sm8250-dpu.yaml | 7 + .../display/msm/qcom,sm8250-mdss.yaml | 3 + .../bindings/display/msm/qcom,sm8450-dpu.yaml | 139 +++ .../display/msm/qcom,sm8450-mdss.yaml | 343 ++ drivers/gpu/drm/msm/Kconfig | 6 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 224 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 4 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 25 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 21 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 141 +-- drivers/gpu/drm/msm/msm_mdss.c| 5 + 30 files changed, 943 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml -- 2.35.1
Re: [Freedreno] [PATCH v5 08/10] drm/msm/dpu: add support for MDP_TOP blackhole
On 25/11/2022 08:01, Abhinav Kumar wrote:
On 11/23/2022 1:04 PM, Dmitry Baryshkov wrote:
On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.
Tested-by: Vinod Koul
Reviewed-by: Vinod Koul
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38ab1568..8da4c5ba6dc3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -82,6 +82,8 @@ enum {
* @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
* compression initial revision
* @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
+ * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0
block results
+ * in a failure
shouldnt this be that "indicates that the top register block is not
contiguous and the two sub-blocks are separated by an offset"
Not so sure. Your suggestion is closer to the dynamic case, where all
the sizes are dynamic in catalog. Since the patch uses fixed offsets,
I'd mention periph0 instead (like the downstream does).
* @DPU_MDP_MAX Maximum value
*/
@@ -92,6 +94,7 @@ enum {
DPU_MDP_UBWC_1_0,
DPU_MDP_UBWC_1_5,
DPU_MDP_AUDIO_SELECT,
+ DPU_MDP_PERIPH_0_REMOVED,
DPU_MDP_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index f3660cd14f4f..4ac14de55139 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct
msm_disp_state *disp_state, struct msm_k
msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
- msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
- dpu_kms->mmio + cat->mdp[0].base, "top");
+ if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
+ msm_disp_snapshot_add_block(disp_state, 0x380,
+ dpu_kms->mmio + cat->mdp[0].base, "top");
+ msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8,
+ dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2");
I recall one of the comments from konrad that this should come from the
catalog rather than a hard-coded offset which you wanted to keep it for
a later time. I am fine with that.
But instead of a hard-coded offset, do you want to have a macro so that
atleast we know what the value means and can fix it in the future?
Otherwise it would end up being one of those numbers which someone later
on wouldnt understand where it comes from and what it means.
Yes, I macro makes sense to me. I'll fix in v6.
+ } else {
+ msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
+ dpu_kms->mmio + cat->mdp[0].base, "top");
+ }
pm_runtime_put_sync(_kms->pdev->dev);
}
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 1/4] drm/msm/adreno: Fix null ptr access in adreno_gpu_cleanup()
On 12/5/2022 2:10 PM, Dan Carpenter wrote:
> On Sun, Dec 04, 2022 at 04:11:41AM +0530, Akhil P Oommen wrote:
>> Fix the below kernel panic due to null pointer access:
>> [ 18.504431] Unable to handle kernel NULL pointer dereference at virtual
>> address 0048
>> [ 18.513464] Mem abort info:
>> [ 18.516346] ESR = 0x9605
>> [ 18.520204] EC = 0x25: DABT (current EL), IL = 32 bits
>> [ 18.525706] SET = 0, FnV = 0
>> [ 18.528878] EA = 0, S1PTW = 0
>> [ 18.532117] FSC = 0x05: level 1 translation fault
>> [ 18.537138] Data abort info:
>> [ 18.540110] ISV = 0, ISS = 0x0005
>> [ 18.544060] CM = 0, WnR = 0
>> [ 18.547109] user pgtable: 4k pages, 39-bit VAs, pgdp=000112826000
>> [ 18.553738] [0048] pgd=,
>> p4d=, pud=
>> [ 18.562690] Internal error: Oops: 9605 [#1] PREEMPT SMP
>> **Snip**
>> [ 18.696758] Call trace:
>> [ 18.699278] adreno_gpu_cleanup+0x30/0x88
>> [ 18.703396] a6xx_destroy+0xc0/0x130
>> [ 18.707066] a6xx_gpu_init+0x308/0x424
> Fixes: 17e822f7591f ("drm/msm: fix unbalanced pm_runtime_enable in
> adreno_gpu_{init, cleanup}")
>
> Let's add Jonathan to the CC list so he can Ack your patch.
Thanks, will post a v2.
-Akhil.
>
> Although the real issue is that a6xx_gpu_init has bad error handling.
>
> The a6xx_destroy() function supposed to free *everything* so then the
> question becomes how do we avoid freeing something which was not
> allocated? With normal kernel style we just free things one by one
> in the reverse order from how they were allocated. See my blog for more
> details:
> https://staticthinking.wordpress.com/2022/04/28/free-the-last-thing-style/
Nice post. Thanks for sharing.
>
> However this code is written in One Function Frees Everything Style
> which is difficult to review and prone to bugs. The common mistakes are
> the kind of NULL dereference that you've seen, double frees, and missing
> frees.
>
> The only way to read this code is to open a new text editor window and
> line up the allocations with the frees.
>
> 1725 static void a6xx_destroy(struct msm_gpu *gpu)
> 1726 {
> 1727 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> 1728 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> 1729
> 1730 if (a6xx_gpu->sqe_bo) {
> 1731 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
> 1732 drm_gem_object_put(a6xx_gpu->sqe_bo);
>
> These unpin/put must be done together and should be in their own
> function. The ->sqe_bo pointer is allocated in a6xx_ucode_init(). It's
> assigned to an error pointer, but then set to NULL on error or after a
> free. So this is okay.
Agree. This warrants a helper function. I count 11 instances where it will be
useful.
>
> 1733 }
> 1734
> 1735 if (a6xx_gpu->shadow_bo) {
>
> ->shadow_bo is allocated in hw_init(). Should there be a call to
> msm_gem_put_vaddr(a6xx_gpu->shadow)? It's unclear. [QUESTION #1]
Yes. This should be freed with msm_gem_kernel_put() which takes care of freeing
vaddr.
>
> 1736 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
> 1737 drm_gem_object_put(a6xx_gpu->shadow_bo);
> 1738 }
> 1739
> 1740 a6xx_llc_slices_destroy(a6xx_gpu);
>
> This has IS_ERR_OR_NULL() checks so it's okay.
>
> 1741
> 1742 a6xx_gmu_remove(a6xx_gpu);
>
> This uses a gmu->initialized flag which allows it to safely clean up
> everything. Fine.
>
> 1743
> 1744 adreno_gpu_cleanup(adreno_gpu);
>
> This function has the bug that you identified. Let's dig into it.
> (With normal kernel error handling you can read the error handling by
> looking at the label name but with this style we need to jump around and
> compare code from different files).
>
> 1745
> 1746 kfree(a6xx_gpu);
> 1747 }
>
> drivers/gpu/drm/msm/adreno/adreno_gpu.c
> 1079 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
> 1080 {
> 1081 struct msm_gpu *gpu = _gpu->base;
> 1082 struct msm_drm_private *priv = gpu->dev->dev_private;
> 1083 unsigned int i;
> 1084
> 1085 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
> 1086 release_firmware(adreno_gpu->fw[i]);
>
> This is okay. ->fw[i] is either valid or NULL and releasing a NULL is
> fine.
>
> 1087
> 1088 if (pm_runtime_enabled(>gpu_pdev->dev))
>
> This is the bug you found.
>
> 1089 pm_runtime_disable(>gpu_pdev->dev);
> 1090
> 1091 msm_gpu_cleanup(_gpu->base);
>
> Let's dig into msm_gpu_cleanup().
>
> 1092 }
>
> drivers/gpu/drm/msm/msm_gpu.c
> 1006 void msm_gpu_cleanup(struct msm_gpu *gpu)
> 1007 {
> 1008 int i;
> 1009
> 1010 DBG("%s", gpu->name);
> 1011
> 1012 for (i = 0; i <
Re: [Freedreno] [PATCH v7 0/6] clk/qcom: Support gdsc collapse polling using 'reset' interface
On 12/2/2022 12:30 PM, Akhil P Oommen wrote: > On 12/2/2022 4:27 AM, Bjorn Andersson wrote: >> On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote: >> @Ulf, Akhil has a power-domain for a piece of hardware which may be >> voted active by multiple different subsystems (co-processors/execution >> contexts) in the system. >> >> As such, during the powering down sequence we don't wait for the >> power-domain to turn off. But in the event of an error, the recovery >> mechanism relies on waiting for the hardware to settle in a powered off >> state. >> >> The proposal here is to use the reset framework to wait for this state >> to be reached, before continuing with the recovery mechanism in the >> client driver. >> >> Given our other discussions on quirky behavior, do you have any >> input/suggestions on this? Ulf, Gentle ping! Could you please share your feedback? -Akhil. >> >>> Some clients like adreno gpu driver would like to ensure that its gdsc >>> is collapsed at hardware during a gpu reset sequence. This is because it >>> has a votable gdsc which could be ON due to a vote from another subsystem >>> like tz, hyp etc or due to an internal hardware signal. To allow >>> this, gpucc driver can expose an interface to the client driver using >>> reset framework. Using this the client driver can trigger a polling within >>> the gdsc driver. >> @Akhil, this description is fairly generic. As we've reached the state >> where the hardware has settled and we return to the client, what >> prevents it from being powered up again? >> >> Or is it simply a question of it hitting the powered-off state, not >> necessarily staying there? > Correct. It doesn't need to stay there. The intention is to hit the > powered-off state at least once to clear all the internal hw states > (basically a hw reset). > > -Akhil. >> Regards, >> Bjorn >> >>> This series is rebased on top of qcom/linux:for-next branch. >>> >>> Related discussion: https://patchwork.freedesktop.org/patch/493144/ >>> >>> Changes in v7: >>> - Update commit message (Bjorn) >>> - Rebased on top of qcom/linux:for-next branch. >>> >>> Changes in v6: >>> - No code changes in this version. Just captured the Acked-by tags >>> >>> Changes in v5: >>> - Nit: Remove a duplicate blank line (Krzysztof) >>> >>> Changes in v4: >>> - Update gpu dt-binding schema >>> - Typo fix in commit text >>> >>> Changes in v3: >>> - Use pointer to const for "struct qcom_reset_ops" in qcom_reset_map >>> (Krzysztof) >>> >>> Changes in v2: >>> - Return error when a particular custom reset op is not implemented. >>> (Dmitry) >>> >>> Akhil P Oommen (6): >>> dt-bindings: clk: qcom: Support gpu cx gdsc reset >>> clk: qcom: Allow custom reset ops >>> clk: qcom: gdsc: Add a reset op to poll gdsc collapse >>> clk: qcom: gpucc-sc7280: Add cx collapse reset support >>> dt-bindings: drm/msm/gpu: Add optional resets >>> arm64: dts: qcom: sc7280: Add Reset support for gpu >>> >>> .../devicetree/bindings/display/msm/gpu.yaml | 6 + >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ >>> drivers/clk/qcom/gdsc.c| 23 ++ >>> drivers/clk/qcom/gdsc.h| 7 ++ >>> drivers/clk/qcom/gpucc-sc7280.c| 10 >>> drivers/clk/qcom/reset.c | 27 >>> +- >>> drivers/clk/qcom/reset.h | 8 +++ >>> include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ >>> 8 files changed, 82 insertions(+), 5 deletions(-) >>> >>> -- >>> 2.7.4 >>>
[Freedreno] [PATCH] drm/msm: Add MSM_SUBMIT_BO_NO_IMPLICIT
From: Rob Clark
In cases where implicit sync is used, it is still useful (for things
like sub-allocation, etc) to allow userspace to opt-out of implicit
sync on per-BO basis.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c| 3 ++-
drivers/gpu/drm/msm/msm_gem_submit.c | 11 +++
include/uapi/drm/msm_drm.h | 4 +++-
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 017a512982a2..e0e1199a822f 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -45,9 +45,10 @@
* - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
* - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
* - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
+ * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT
*/
#define MSM_VERSION_MAJOR 1
-#define MSM_VERSION_MINOR 9
+#define MSM_VERSION_MINOR 10
#define MSM_VERSION_PATCHLEVEL 0
static const struct drm_mode_config_funcs mode_config_funcs = {
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index eb3536e3d66a..8bad07a04f85 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -334,9 +334,20 @@ static int submit_fence_sync(struct msm_gem_submit
*submit, bool no_implicit)
if (ret)
return ret;
+ /* If userspace has determined that explicit fencing is
+* used, it can disable implicit sync on the entire
+* submit:
+*/
if (no_implicit)
continue;
+ /* Otherwise userspace can ask for implicit sync to be
+* disabled on specific buffers. This is useful for internal
+* usermode driver managed buffers, suballocation, etc.
+*/
+ if (submit->bos[i].flags & MSM_SUBMIT_BO_NO_IMPLICIT)
+ continue;
+
ret = drm_sched_job_add_implicit_dependencies(>base,
obj,
write);
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index f54b48ef6a2d..329100016e7c 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -222,10 +222,12 @@ struct drm_msm_gem_submit_cmd {
#define MSM_SUBMIT_BO_READ 0x0001
#define MSM_SUBMIT_BO_WRITE0x0002
#define MSM_SUBMIT_BO_DUMP 0x0004
+#define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008
#define MSM_SUBMIT_BO_FLAGS(MSM_SUBMIT_BO_READ | \
MSM_SUBMIT_BO_WRITE | \
- MSM_SUBMIT_BO_DUMP)
+ MSM_SUBMIT_BO_DUMP | \
+ MSM_SUBMIT_BO_NO_IMPLICIT)
struct drm_msm_gem_submit_bo {
__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
--
2.38.1
Re: [Freedreno] (subset) [PATCH v2 00/12] SM6115 DTS changes
On Wed, 30 Nov 2022 21:09:38 +0100, Adam Skladowski wrote: > This patch series adds bunch of new nodes > also it fixes some small nitpicks in yamls and adds compatible. > > Changes since v1 > > 1. Changed title for mdss yaml patch > 2. Added missing dmas to spi0 > 3. Wired freq domains to CPUs > 4. Added R-b/Ack tags > 5. Reworded smmu dts patch > > [...] Applied, thanks! [03/12] arm64: dts: qcom: sm6115: Add cpufreq-hw support commit: aff96846c63ed3e3ed7d5212ea636a422d9694a3 [04/12] arm64: dts: qcom: sm6115: Add TSENS node commit: 7b74cba6b13f4bbe1f15e3417f386ed1907ab0ef [05/12] arm64: dts: qcom: sm6115: Add PRNG node commit: fc676b15c065b8d4c750bbaab9914f24829a7a13 [06/12] arm64: dts: qcom: sm6115: Add rpm-stats node commit: d18c0077963ae2b6d232f6f3f25fb1ceb875ce7f [07/12] arm64: dts: qcom: sm6115: Add dispcc node commit: 884f95411ba4030ca44436217c6d8df4a960c555 [08/12] arm64: dts: qcom: sm6115: Add mdss/dpu node commit: 705e50427d8148211ffd05922bfa6a2520781338 [09/12] arm64: dts: qcom: sm6115: Add GPI DMA commit: 1586c5793511d7fb389139ab7aa5dae9118666ad [10/12] arm64: dts: qcom: sm6115: Add i2c/spi nodes commit: 323647d32e83fae7f1a81b40e12ca6b0b63e880c [11/12] arm64: dts: qcom: sm6115: Add WCN node. commit: 245bb9a37c16dc324be60764aa2597aa4704a8e3 [12/12] arm64: dts: qcom: sm6115: Add smmu fallback to qcom generic compatible commit: 58a9e83605478e931139b574e43d453851de3a26 Best regards, -- Bjorn Andersson
Re: [Freedreno] [PATCH] drm/msm/dpu: Add check for cstate
On 12/6/2022 12:05 AM, Jiasheng Jiang wrote:
As kzalloc may fail and return NULL pointer,
it should be better to check cstate
in order to avoid the NULL pointer dereference
in __drm_atomic_helper_crtc_reset.
You have wrapped around your lines too short. Please try to utilize the
full word limit for each line.
With that fixed,
Reviewed-by: Abhinav Kumar
Fixes: 1cff7440a86e ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for
reset.")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..22c2787b7b38 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -968,7 +968,10 @@ static void dpu_crtc_reset(struct drm_crtc *crtc)
if (crtc->state)
dpu_crtc_destroy_state(crtc, crtc->state);
- __drm_atomic_helper_crtc_reset(crtc, >base);
+ if (cstate)
+ __drm_atomic_helper_crtc_reset(crtc, >base);
+ else
+ __drm_atomic_helper_crtc_reset(crtc, NULL);
}
/**
Re: [Freedreno] [PATCH] drm/msm/dpu: Fix memory leak in msm_mdss_parse_data_bus_icc_path
Hi,
On Mon, Dec 5, 2022 at 11:55 PM Miaoqian Lin wrote:
>
> of_icc_get() alloc resources for path1, we should release it when not
> need anymore. Early return when IS_ERR_OR_NULL(path0) may leak path1.
> Add icc_put(path1) in the error path to fix this.
>
> Fixes: b9364eed9232 ("drm/msm/dpu: Move min BW request and full BW disable
> back to mdss")
> Signed-off-by: Miaoqian Lin
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index e13c5c12b775..a38fa9a9a3d6 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -49,8 +49,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
> *dev,
> struct icc_path *path0 = of_icc_get(dev, "mdp0-mem");
> struct icc_path *path1 = of_icc_get(dev, "mdp1-mem");
>
> - if (IS_ERR_OR_NULL(path0))
> + if (IS_ERR_OR_NULL(path0)) {
> + icc_put(path1);
> return PTR_ERR_OR_ZERO(path0);
> + }
>
> msm_mdss->path[0] = path0;
> msm_mdss->num_paths = 1;
Hmmm. I guess the original author of the code (which wasn't me--I just
restored the code that was deleted by a previous change) was assuming
that if mdp0-mem had a problem that mdp1-mem would also have a
problem. That would mean that you wouldn't need to call icc_put() on
it.
...and, in fact, your patch doesn't handle that case, does it? If
_both_ of the two are error or NULL then you'll be calling icc_put()
on something invalid. I guess icc_put() handles those cases without
crashing but it will give a WARN_ON() splat if it happens to be an
error...
Really, there's a better solution anyway. Instead, you should do:
path0 = of_icc_get(dev, "mdp0-mem");
if (IS_ERR_OR_NULL(path0))
return PTR_ERR_OR_ZERO(path0);
msm_mdss->path[0] = path0;
msm_mdss->num_paths = 1;
path1 = of_icc_get(dev, "mdp1-mem");
if (!IS_ERR_OR_NULL(path1)) {
...
}
In other words just defer getting path1 until after you've checked
path0 for an error.
-Doug
Re: [Freedreno] [PATCH v9 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property
On Mon, 05 Dec 2022 15:08:11 -0800, Kuogee Hsieh wrote: > Add both data-lanes and link-frequencies property into endpoint > > Changes in v7: > -- split yaml out of dtsi patch > -- link-frequencies from link rate to symbol rate > -- deprecation of old data-lanes property > > Changes in v8: > -- correct Bjorn mail address to kernel.org > > Signed-off-by: Kuogee Hsieh ` > --- > Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 9 > + > 1 file changed, 9 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/display/msm/dp-controller.yaml:108:21: [error] syntax error: mapping values are not allowed here (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/display/msm/dp-controller.example.dts' Documentation/devicetree/bindings/display/msm/dp-controller.yaml:108:21: mapping values are not allowed here make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/display/msm/dp-controller.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs ./Documentation/devicetree/bindings/display/msm/dp-controller.yaml:108:21: mapping values are not allowed here /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml: ignoring, error parsing file make: *** [Makefile:1492: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/1670281694-13281-3-git-send-email-quic_khs...@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
[Freedreno] [PATCH] drm/msm/dpu: Add check for cstate
As kzalloc may fail and return NULL pointer,
it should be better to check cstate
in order to avoid the NULL pointer dereference
in __drm_atomic_helper_crtc_reset.
Fixes: 1cff7440a86e ("drm/msm: Convert to using
__drm_atomic_helper_crtc_reset() for reset.")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..22c2787b7b38 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -968,7 +968,10 @@ static void dpu_crtc_reset(struct drm_crtc *crtc)
if (crtc->state)
dpu_crtc_destroy_state(crtc, crtc->state);
- __drm_atomic_helper_crtc_reset(crtc, >base);
+ if (cstate)
+ __drm_atomic_helper_crtc_reset(crtc, >base);
+ else
+ __drm_atomic_helper_crtc_reset(crtc, NULL);
}
/**
--
2.25.1
[Freedreno] [PATCH] drm/msm/dpu: Add check for pstates
As kzalloc may fail and return NULL pointer,
it should be better to check pstates
in order to avoid the NULL pointer dereference.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..f51cb46ecfd6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1150,6 +1150,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
+ if (!pstates)
+ return -ENOMEM;
if (!crtc_state->enable || !crtc_state->active) {
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip
atomic_check\n",
--
2.25.1
[Freedreno] [PATCH] drm/msm/dpu: Add check for cstate
As kzalloc may fail and return NULL pointer,
it should be better to check pstates
in order to avoid the NULL pointer dereference
later.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..f51cb46ecfd6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1150,6 +1150,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
+ if (!pstates)
+ return -ENOMEM;
if (!crtc_state->enable || !crtc_state->active) {
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip
atomic_check\n",
--
2.25.1
