Re: [Freedreno] [PATCH] drm/msm: another fix for the headless Adreno GPU
Hi Dmitry,
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-msm-another-fix-for-the-headless-Adreno-GPU/20221231-103022
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20221231022937.286491-1-dmitry.baryshkov%40linaro.org
patch subject: [PATCH] drm/msm: another fix for the headless Adreno GPU
config: loongarch-randconfig-m031-20230101
compiler: loongarch64-linux-gcc (GCC) 12.1.0
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot
| Reported-by: Dan Carpenter
smatch warnings:
drivers/gpu/drm/msm/msm_atomic.c:194 msm_atomic_commit_tail() error:
uninitialized symbol 'async'.
vim +/async +194 drivers/gpu/drm/msm/msm_atomic.c
d4d2c60497cfc5 Rob Clark2019-08-29 181
d14659f5de7d28 Sean Paul2018-02-28 182 void
msm_atomic_commit_tail(struct drm_atomic_state *state)
cf3a7e4ce08e68 Rob Clark2014-11-08 183 {
cf3a7e4ce08e68 Rob Clark2014-11-08 184 struct drm_device *dev
= state->dev;
0b776d457b9476 Rob Clark2015-01-30 185 struct msm_drm_private
*priv = dev->dev_private;
0b776d457b9476 Rob Clark2015-01-30 186 struct msm_kms *kms =
priv->kms;
2d99ced787e3d0 Rob Clark2019-08-29 187 struct drm_crtc
*async_crtc = NULL;
d4d2c60497cfc5 Rob Clark2019-08-29 188 unsigned crtc_mask =
get_crtc_mask(state);
91a514e50f1157 Dmitry Baryshkov 2022-12-31 189 bool async;
^^^
91a514e50f1157 Dmitry Baryshkov 2022-12-31 190
91a514e50f1157 Dmitry Baryshkov 2022-12-31 191 if (!kms)
91a514e50f1157 Dmitry Baryshkov 2022-12-31 192 return;
0b776d457b9476 Rob Clark2015-01-30 193
d934a712c5e6a3 Rob Clark2019-08-29 @194
trace_msm_atomic_commit_tail_start(async, crtc_mask);
^
Unitialized.
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Re: [Freedreno] [PATCH v3] drm/msm: another fix for the headless Adreno GPU
On 1/4/2023 5:47 PM, Dmitry Baryshkov wrote:
Fix another oops reproducible when rebooting the board with the Adreno
GPU working in the headless mode (e.g. iMX platforms).
Unable to handle kernel NULL pointer dereference at virtual address
when read
[] *pgd=74936831, *pte=, *ppte=
Internal error: Oops: 17 [#1] ARM
CPU: 0 PID: 51 Comm: reboot Not tainted 6.2.0-rc1-dirty #11
Hardware name: Freescale i.MX53 (Device Tree Support)
PC is at msm_atomic_commit_tail+0x50/0x970
LR is at commit_tail+0x9c/0x188
pc : []lr : []psr: 600e0013
sp : e0851d30 ip : ee4eb7eb fp : 00090acc
r10: 0058 r9 : c2193014 r8 : c431
r7 : c4759380 r6 : 07bef61d r5 : r4 :
r3 : c44cc440 r2 : r1 : r0 :
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 74910019 DAC: 0051
Register r0 information: NULL pointer
Register r1 information: NULL pointer
Register r2 information: NULL pointer
Register r3 information: slab kmalloc-1k start c44cc400 pointer offset 64 size
1024
Register r4 information: NULL pointer
Register r5 information: NULL pointer
Register r6 information: non-paged memory
Register r7 information: slab kmalloc-128 start c4759380 pointer offset 0 size
128
Register r8 information: slab kmalloc-2k start c431 pointer offset 0 size
2048
Register r9 information: non-slab/vmalloc memory
Register r10 information: non-paged memory
Register r11 information: non-paged memory
Register r12 information: non-paged memory
Process reboot (pid: 51, stack limit = 0xc80046d9)
Stack: (0xe0851d30 to 0xe0852000)
1d20: c4759380 fbd77200 05ff 002b9c70
1d40: c4759380 c4759380 07bef61d 0600 c0d6fe7c c2193014 0058
1d60: 00090acc c067a214 c4759380 c431 c44cc854 c067a89c
1d80: c4310468 c4759380 c431 c4310468
1da0: c4310470 c0643258 c4759380 c0c4ee24 c44cc810
1dc0: c0c4ee24 c44cc810 0347d2a8 e0851e00 e0851e00
1de0: c4759380 c067ad20 c431 c44cc810 c27f8718 c44cc854 c067adb8
1e00: c4933000 0002 0001 c2130850 c2130854
1e20: c25fc488 c0ff162c 0001 0002
1e40: c43102c0 c43102c0 0347d2a8 c44cc810 c44cc814 c2133da8 c06d1a60
1e60: 00079028 c2012f24 fee1dead c4933000 0058 c01431e4
1e80: 01234567 c0143a20
1ea0:
1ec0:
1ee0:
1f00:
1f20:
1f40:
1f60:
1f80: 0347d2a8 0002 0004 0078 0058
1fa0: c010028c c0100060 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6 600e0030 fee1dead
msm_atomic_commit_tail from commit_tail+0x9c/0x188
commit_tail from drm_atomic_helper_commit+0x160/0x188
drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe0
drm_atomic_commit from drm_atomic_helper_disable_all+0x1b0/0x1c0
drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x88/0x140
drm_atomic_helper_shutdown from device_shutdown+0x16c/0x240
device_shutdown from kernel_restart+0x38/0x90
kernel_restart from __do_sys_reboot+0x174/0x224
__do_sys_reboot from ret_fast_syscall+0x0/0x1c
Exception stack(0xe0851fa8 to 0xe0851ff0)
1fa0: 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6
Code: 15922088 1184421c e153 1af8 (e5953000)
---[ end trace ]---
Fixes: 0a58d2ae572a ("drm/msm: Make .remove and .shutdown HW shutdown
consistent")
Reported-by: kernel test robot
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
Changes since v2:
- Moved the condition check from msm_atomic_commit_tail() to msm_drv_shutdown()
Changes since v1:
- Moved setting of `async' before the call to trace to fix the
uninitialized variable warning
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 8b0b0ac74a6f..45e81eb148a8 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1278,7 +1278,7 @@ void
Re: [Freedreno] [PATCH v3] drm/msm: another fix for the headless Adreno GPU
On Wed, Jan 4, 2023 at 5:47 PM Dmitry Baryshkov
wrote:
>
> Fix another oops reproducible when rebooting the board with the Adreno
> GPU working in the headless mode (e.g. iMX platforms).
>
> Unable to handle kernel NULL pointer dereference at virtual address
> when read
> [] *pgd=74936831, *pte=, *ppte=
> Internal error: Oops: 17 [#1] ARM
> CPU: 0 PID: 51 Comm: reboot Not tainted 6.2.0-rc1-dirty #11
> Hardware name: Freescale i.MX53 (Device Tree Support)
> PC is at msm_atomic_commit_tail+0x50/0x970
> LR is at commit_tail+0x9c/0x188
> pc : []lr : []psr: 600e0013
> sp : e0851d30 ip : ee4eb7eb fp : 00090acc
> r10: 0058 r9 : c2193014 r8 : c431
> r7 : c4759380 r6 : 07bef61d r5 : r4 :
> r3 : c44cc440 r2 : r1 : r0 :
> Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
> Control: 10c5387d Table: 74910019 DAC: 0051
> Register r0 information: NULL pointer
> Register r1 information: NULL pointer
> Register r2 information: NULL pointer
> Register r3 information: slab kmalloc-1k start c44cc400 pointer offset 64
> size 1024
> Register r4 information: NULL pointer
> Register r5 information: NULL pointer
> Register r6 information: non-paged memory
> Register r7 information: slab kmalloc-128 start c4759380 pointer offset 0
> size 128
> Register r8 information: slab kmalloc-2k start c431 pointer offset 0 size
> 2048
> Register r9 information: non-slab/vmalloc memory
> Register r10 information: non-paged memory
> Register r11 information: non-paged memory
> Register r12 information: non-paged memory
> Process reboot (pid: 51, stack limit = 0xc80046d9)
> Stack: (0xe0851d30 to 0xe0852000)
> 1d20: c4759380 fbd77200 05ff 002b9c70
> 1d40: c4759380 c4759380 07bef61d 0600 c0d6fe7c c2193014 0058
> 1d60: 00090acc c067a214 c4759380 c431 c44cc854 c067a89c
> 1d80: c4310468 c4759380 c431 c4310468
> 1da0: c4310470 c0643258 c4759380 c0c4ee24 c44cc810
> 1dc0: c0c4ee24 c44cc810 0347d2a8 e0851e00 e0851e00
> 1de0: c4759380 c067ad20 c431 c44cc810 c27f8718 c44cc854 c067adb8
> 1e00: c4933000 0002 0001 c2130850 c2130854
> 1e20: c25fc488 c0ff162c 0001 0002
> 1e40: c43102c0 c43102c0 0347d2a8 c44cc810 c44cc814 c2133da8 c06d1a60
> 1e60: 00079028 c2012f24 fee1dead c4933000 0058 c01431e4
> 1e80: 01234567 c0143a20
> 1ea0:
> 1ec0:
> 1ee0:
> 1f00:
> 1f20:
> 1f40:
> 1f60:
> 1f80: 0347d2a8 0002 0004 0078 0058
> 1fa0: c010028c c0100060 0002 0004 fee1dead 28121969 01234567 00079028
> 1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
> 1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6 600e0030 fee1dead
> msm_atomic_commit_tail from commit_tail+0x9c/0x188
> commit_tail from drm_atomic_helper_commit+0x160/0x188
> drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe0
> drm_atomic_commit from drm_atomic_helper_disable_all+0x1b0/0x1c0
> drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x88/0x140
> drm_atomic_helper_shutdown from device_shutdown+0x16c/0x240
> device_shutdown from kernel_restart+0x38/0x90
> kernel_restart from __do_sys_reboot+0x174/0x224
> __do_sys_reboot from ret_fast_syscall+0x0/0x1c
> Exception stack(0xe0851fa8 to 0xe0851ff0)
> 1fa0: 0002 0004 fee1dead 28121969 01234567 00079028
> 1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
> 1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6
> Code: 15922088 1184421c e153 1af8 (e5953000)
> ---[ end trace ]---
>
> Fixes: 0a58d2ae572a ("drm/msm: Make .remove and .shutdown HW shutdown
> consistent")
> Reported-by: kernel test robot
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Rob Clark
We generally want to not go down any kms related call paths as high up
the stack as possible, otherwise it is just going to be whack-a-mole
fixing the issues
BR,
-R
> ---
>
> Changes since v2:
> - Moved the condition check from msm_atomic_commit_tail() to
> msm_drv_shutdown()
>
> Changes since v1:
> - Moved setting of `async' before the call to trace to fix the
> uni
Re: [Freedreno] [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550
On Wed, 04 Jan 2023 10:08:44 +0100, Neil Armstrong wrote: > Document the MDSS and DPU blocks found on the Qualcomm SM8550 > platform. > > Signed-off-by: Neil Armstrong > --- > .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 + > .../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 > + > 2 files changed, 465 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.example.dts:21:18: fatal error: dt-bindings/clock/qcom,sm8550-dispcc.h: No such file or directory 21 | #include | ^~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:434: Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs make: *** [Makefile:1508: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230103-topic-sm8550-upstream-mdss-dsi-v1-2-9ccd7e652...@linaro.org The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Re: [Freedreno] [RFC PATCH v3 3/3] drm/msm/dpu: Use color_fill property for DPU planes
On 05/01/2023 01:40, Jessica Zhang wrote:
Initialize and use the color_fill properties for planes in DPU driver. In
addition, relax framebuffer requirements within atomic commit path and
add checks for NULL framebuffers. Finally, drop DPU_PLANE_COLOR_FILL_FLAG
as it's unused.
Changes since V2:
- Fixed dropped 'const' warning
- Dropped use of solid_fill_format
- Switched to using drm_plane_solid_fill_enabled helper method
- Added helper to convert color fill to BGR888 (Rob)
- Added support for solid fill on planes of varying sizes
- Removed DPU_PLANE_COLOR_FILL_FLAG
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 65 ++-
2 files changed, 49 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..0695b70ea1b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -409,6 +409,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
+ const struct msm_format *fmt;
struct dpu_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
@@ -441,7 +442,13 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
sspp_idx - SSPP_VIG0,
state->fb ? state->fb->base.id : -1);
- format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
+ if (pstate->base.fb)
+ fmt = msm_framebuffer_format(pstate->base.fb);
+ else
+ fmt = dpu_get_msm_format(&_dpu_crtc_get_kms(crtc)->base,
+ DRM_FORMAT_ABGR, 0);
+
+ format = to_dpu_format(fmt);
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 86719020afe2..51a7507373f7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -44,7 +44,6 @@
#define DPU_NAME_SIZE 12
-#define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
#define DPU_ZPOS_MAX 255
/* multirect rect index */
@@ -105,7 +104,6 @@ struct dpu_plane {
enum dpu_sspp pipe;
struct dpu_hw_pipe *pipe_hw;
- uint32_t color_fill;
bool is_error;
bool is_rt_pipe;
const struct dpu_mdss_cfg *catalog;
@@ -678,6 +676,17 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
&scaler3_cfg);
}
+static uint32_t _dpu_plane_get_fill_color(struct drm_solid_fill solid_fill)
+{
+ uint32_t ret = 0;
+
+ ret |= ((uint8_t) solid_fill.b) << 16;
+ ret |= ((uint8_t) solid_fill.g) << 8;
+ ret |= ((uint8_t) solid_fill.r);
+
+ return ret;
+}
+
/**
* _dpu_plane_color_fill - enables color fill on plane
* @pdpu: Pointer to DPU plane object
@@ -1001,12 +1010,17 @@ static int dpu_plane_atomic_check(struct drm_plane
*plane,
dst = drm_plane_state_dest(new_plane_state);
- fb_rect.x2 = new_plane_state->fb->width;
- fb_rect.y2 = new_plane_state->fb->height;
+ if (new_plane_state->fb) {
+ fb_rect.x2 = new_plane_state->fb->width;
+ fb_rect.y2 = new_plane_state->fb->height;
+ }
max_linewidth = pdpu->catalog->caps->max_linewidth;
- fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+ if (new_plane_state->fb)
+ fmt =
to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+ else
+ fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR);
I think this should be more explicit:
if (solid_fill)
fmt = dpu_get_dpu_format(...)
else
fmt = to_dpu_format(msm_framebuffer_format(...).
And in the _dpu_crtc_blend_setup_mixer() too.
Maybe the code can be extracted to a helper.
min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
@@ -1018,7 +1032,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/* check src bounds */
- } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
+ } else if (new_plane_state->fb && !dpu_plane_validate_src(&src,
&fb_rect, min_src_size)) {
DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
DRM_RECT_ARG(&src));
return -E2BIG;
@@ -1086,9 +1100,10 @@ void dpu_plane_flush(struct drm_plane *plane)
if (pdpu->is_error)
/* force white frame with 100% alpha pipe output on error */
_dpu_plane_color_fill(pdpu, 0xFF, 0xFF);
- else if (pdpu->color_fill & DPU
Re: [Freedreno] [RFC PATCH v3 1/3] drm: Introduce solid fill property for drm plane
On 05/01/2023 01:40, Jessica Zhang wrote:
Add support for solid_fill property to drm_plane. In addition, add
support for setting and getting the values for solid_fill.
solid_fill holds data for supporting solid fill planes. The property
accepts an RGB323232 value and the driver data is formatted as such:
struct drm_solid_fill {
u32 r;
u32 g;
u32 b;
};
To enable solid fill planes, userspace must assigned solid_fill to a
property blob containing the following information:
struct drm_solid_fill_info {
u8 version;
u32 r, g, b;
BTW: should we add support for alpha too? DPU hardware supports using
RGBA as a fill colour format, doesn't it?
But then we face the obvious question, how do we communicate to
userspace if the hardware support RGB or RGBA?
};
Changes in V2:
- Changed solid_fill property to a property blob (Simon, Dmitry)
- Added drm_solid_fill struct (Simon)
- Added drm_solid_fill_info struct (Simon)
Changes in V3:
- Corrected typo in drm_solid_fill struct documentation
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_state_helper.c | 9
drivers/gpu/drm/drm_atomic_uapi.c | 59 +++
drivers/gpu/drm/drm_blend.c | 17 +++
include/drm/drm_blend.h | 1 +
include/drm/drm_plane.h | 43 +
5 files changed, 129 insertions(+)
--
With best wishes
Dmitry
Re: [Freedreno] [RFC PATCH v3 2/3] drm: Adjust atomic checks for solid fill color
On 05/01/2023 01:40, Jessica Zhang wrote:
Loosen the requirements for atomic and legacy commit so that, in cases
where solid fill planes is enabled (and FB_ID is NULL), the commit can
still go through.
In addition, add framebuffer NULL checks in other areas to account for
FB being NULL when solid fill is enabled.
Changes in V2:
- Changed to checks for if solid_fill_blob is set (Dmitry)
- Abstracted (plane_state && !solid_fill_blob) checks to helper method
(Dmitry)
- Fixed indentation issue (Dmitry)
Changes in V3:
- Created drm_plane_has_visible_data() helper and corrected CRTC and FB
NULL-check logic (Dmitry)
- Merged `if (fb)` blocks in drm_atomic_plane_check() and abstracted
them into helper method (Dmitry)
- Inverted `if (solid_fill_enabled) else if (fb)` check order (Dmitry)
- Fixed indentation (Dmitry)
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 136
drivers/gpu/drm/drm_atomic_helper.c | 34 ---
drivers/gpu/drm/drm_plane.c | 8 +-
include/drm/drm_atomic_helper.h | 5 +-
include/drm/drm_plane.h | 19
5 files changed, 124 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index f197f59f6d99..63f34b430479 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -580,6 +580,76 @@ plane_switching_crtc(const struct drm_plane_state
*old_plane_state,
return true;
}
+static int drm_atomic_check_fb(const struct drm_plane_state *state)
This change should go to a separate patch. Please don't mix refactoring
(moving of the code) with the actual functionality changes.
+{
+ struct drm_plane *plane = state->plane;
+ const struct drm_framebuffer *fb = state->fb;
+ struct drm_mode_rect *clips;
+
+ uint32_t num_clips;
+ unsigned int fb_width, fb_height;
+ int ret;
+
+ /* Check whether this plane supports the fb pixel format. */
+ ret = drm_plane_check_pixel_format(plane, fb->format->format,
+ fb->modifier);
+
+ if (ret) {
+ drm_dbg_atomic(plane->dev,
+ "[PLANE:%d:%s] invalid pixel format %p4cc, modifier
0x%llx\n",
+ plane->base.id, plane->name,
+ &fb->format->format, fb->modifier);
+ return ret;
+ }
+
+ fb_width = fb->width << 16;
+ fb_height = fb->height << 16;
+
+ /* Make sure source coordinates are inside the fb. */
+ if (state->src_w > fb_width ||
+ state->src_x > fb_width - state->src_w ||
+ state->src_h > fb_height ||
+ state->src_y > fb_height - state->src_h) {
+ drm_dbg_atomic(plane->dev,
+ "[PLANE:%d:%s] invalid source coordinates "
+ "%u.%06ux%u.%06u+%u.%06u+%u.%06u (fb %ux%u)\n",
+ plane->base.id, plane->name,
+ state->src_w >> 16,
+ ((state->src_w & 0x) * 15625) >> 10,
+ state->src_h >> 16,
+ ((state->src_h & 0x) * 15625) >> 10,
+ state->src_x >> 16,
+ ((state->src_x & 0x) * 15625) >> 10,
+ state->src_y >> 16,
+ ((state->src_y & 0x) * 15625) >> 10,
+ fb->width, fb->height);
+ return -ENOSPC;
+ }
+
+ clips = __drm_plane_get_damage_clips(state);
+ num_clips = drm_plane_get_damage_clips_count(state);
+
+ /* Make sure damage clips are valid and inside the fb. */
+ while (num_clips > 0) {
+ if (clips->x1 >= clips->x2 ||
+ clips->y1 >= clips->y2 ||
+ clips->x1 < 0 ||
+ clips->y1 < 0 ||
+ clips->x2 > fb_width ||
+ clips->y2 > fb_height) {
+ drm_dbg_atomic(plane->dev,
+ "[PLANE:%d:%s] invalid damage clip %d %d %d
%d\n",
+ plane->base.id, plane->name, clips->x1,
+ clips->y1, clips->x2, clips->y2);
+ return -EINVAL;
+ }
+ clips++;
+ num_clips--;
+ }
+
+ return 0;
+}
+
/**
* drm_atomic_plane_check - check plane state
* @old_plane_state: old plane state to check
@@ -596,13 +666,12 @@ static int drm_atomic_plane_check(const struct
drm_plane_state *old_plane_state,
struct drm_plane *plane = new_plane_state->plane;
struct drm_crtc *crtc = new_plane_state->crtc;
const struct drm_framebuffer *fb = new_plane_state->fb;
- unsigned int fb_width, fb_height;
- struct drm_mode_rect *clips
Re: [Freedreno] [RFC PATCH v3 1/3] drm: Introduce solid fill property for drm plane
On 05/01/2023 01:40, Jessica Zhang wrote:
Add support for solid_fill property to drm_plane. In addition, add
support for setting and getting the values for solid_fill.
solid_fill holds data for supporting solid fill planes. The property
accepts an RGB323232 value and the driver data is formatted as such:
struct drm_solid_fill {
u32 r;
u32 g;
u32 b;
};
This description is unnecessary (and confusing), since you describe
drm_solid_fill_info below.
To enable solid fill planes, userspace must assigned solid_fill to a
must assign. Also the phrasing seems strange. The blob is assigned to
the 'solid_fill' property, not the other way around.
property blob containing the following information:
This should clearly describe if solid_fill overrides FB or if FB
overrides solid_fill. Also please extend properties documentation in
Documentation/gpu/drm-kms.rst.
struct drm_solid_fill_info {
u8 version;
u32 r, g, b;
};
Changes in V2:
- Changed solid_fill property to a property blob (Simon, Dmitry)
- Added drm_solid_fill struct (Simon)
- Added drm_solid_fill_info struct (Simon)
Changes in V3:
- Corrected typo in drm_solid_fill struct documentation
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_state_helper.c | 9
drivers/gpu/drm/drm_atomic_uapi.c | 59 +++
drivers/gpu/drm/drm_blend.c | 17 +++
include/drm/drm_blend.h | 1 +
include/drm/drm_plane.h | 43 +
5 files changed, 129 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index dfb57217253b..c96fd1f2ad99 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -253,6 +253,11 @@ void __drm_atomic_helper_plane_state_reset(struct
drm_plane_state *plane_state,
plane_state->alpha = DRM_BLEND_ALPHA_OPAQUE;
plane_state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
+ if (plane_state->solid_fill_blob) {
+ drm_property_blob_put(plane_state->solid_fill_blob);
+ plane_state->solid_fill_blob = NULL;
+ }
+
if (plane->color_encoding_property) {
if (!drm_object_property_get_default_value(&plane->base,
plane->color_encoding_property,
@@ -335,6 +340,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
if (state->fb)
drm_framebuffer_get(state->fb);
+ if (state->solid_fill_blob)
+ drm_property_blob_get(state->solid_fill_blob);
+
state->fence = NULL;
state->commit = NULL;
state->fb_damage_clips = NULL;
@@ -384,6 +392,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_crtc_commit_put(state->commit);
drm_property_blob_put(state->fb_damage_clips);
+ drm_property_blob_put(state->solid_fill_blob);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index c06d0639d552..8a1d2fb7a757 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -316,6 +316,55 @@ drm_atomic_set_crtc_for_connector(struct
drm_connector_state *conn_state,
}
EXPORT_SYMBOL(drm_atomic_set_crtc_for_connector);
+static void drm_atomic_convert_solid_fill_info(struct drm_solid_fill *out,
+ struct drm_solid_fill_info *in)
No need for a separate function, you can inline this.
+{
+ out->r = in->r;
+ out->g = in->g;
+ out->b = in->b;
+}
+
+static int drm_atomic_set_solid_fill_prop(struct drm_plane_state *state,
+ struct drm_property_blob *blob)
+{
+ int ret = 0;
+ int blob_version;
+
+ if (blob == state->solid_fill_blob)
+ return 0;
+
+ drm_property_blob_put(state->solid_fill_blob);
+ state->solid_fill_blob = NULL;
+
+ memset(&state->solid_fill, 0, sizeof(state->solid_fill));
+
+ if (blob) {
+ if (blob->length != sizeof(struct drm_solid_fill_info)) {
+ drm_dbg_atomic(state->plane->dev,
+ "[PLANE:%d:%s] bad solid fill blob length:
%zu\n",
+ state->plane->base.id,
state->plane->name,
+ blob->length);
+ return -EINVAL;
+ }
+
+ blob_version = ((struct drm_solid_fill_info
*)blob->data)->version;
Please assign blob->data to temporary var.
+
+ /* Append with more versions if necessary */
s/Append/Add/
+ if (blob_version == 1) {
+ drm_atomic_convert_solid_fill_info(&state->solid_fill,
blob->data);
+ } else {
+ drm_dbg_atom
[Freedreno] [PATCH v3] drm/msm: another fix for the headless Adreno GPU
Fix another oops reproducible when rebooting the board with the Adreno
GPU working in the headless mode (e.g. iMX platforms).
Unable to handle kernel NULL pointer dereference at virtual address
when read
[] *pgd=74936831, *pte=, *ppte=
Internal error: Oops: 17 [#1] ARM
CPU: 0 PID: 51 Comm: reboot Not tainted 6.2.0-rc1-dirty #11
Hardware name: Freescale i.MX53 (Device Tree Support)
PC is at msm_atomic_commit_tail+0x50/0x970
LR is at commit_tail+0x9c/0x188
pc : []lr : []psr: 600e0013
sp : e0851d30 ip : ee4eb7eb fp : 00090acc
r10: 0058 r9 : c2193014 r8 : c431
r7 : c4759380 r6 : 07bef61d r5 : r4 :
r3 : c44cc440 r2 : r1 : r0 :
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 74910019 DAC: 0051
Register r0 information: NULL pointer
Register r1 information: NULL pointer
Register r2 information: NULL pointer
Register r3 information: slab kmalloc-1k start c44cc400 pointer offset 64 size
1024
Register r4 information: NULL pointer
Register r5 information: NULL pointer
Register r6 information: non-paged memory
Register r7 information: slab kmalloc-128 start c4759380 pointer offset 0 size
128
Register r8 information: slab kmalloc-2k start c431 pointer offset 0 size
2048
Register r9 information: non-slab/vmalloc memory
Register r10 information: non-paged memory
Register r11 information: non-paged memory
Register r12 information: non-paged memory
Process reboot (pid: 51, stack limit = 0xc80046d9)
Stack: (0xe0851d30 to 0xe0852000)
1d20: c4759380 fbd77200 05ff 002b9c70
1d40: c4759380 c4759380 07bef61d 0600 c0d6fe7c c2193014 0058
1d60: 00090acc c067a214 c4759380 c431 c44cc854 c067a89c
1d80: c4310468 c4759380 c431 c4310468
1da0: c4310470 c0643258 c4759380 c0c4ee24 c44cc810
1dc0: c0c4ee24 c44cc810 0347d2a8 e0851e00 e0851e00
1de0: c4759380 c067ad20 c431 c44cc810 c27f8718 c44cc854 c067adb8
1e00: c4933000 0002 0001 c2130850 c2130854
1e20: c25fc488 c0ff162c 0001 0002
1e40: c43102c0 c43102c0 0347d2a8 c44cc810 c44cc814 c2133da8 c06d1a60
1e60: 00079028 c2012f24 fee1dead c4933000 0058 c01431e4
1e80: 01234567 c0143a20
1ea0:
1ec0:
1ee0:
1f00:
1f20:
1f40:
1f60:
1f80: 0347d2a8 0002 0004 0078 0058
1fa0: c010028c c0100060 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6 600e0030 fee1dead
msm_atomic_commit_tail from commit_tail+0x9c/0x188
commit_tail from drm_atomic_helper_commit+0x160/0x188
drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe0
drm_atomic_commit from drm_atomic_helper_disable_all+0x1b0/0x1c0
drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x88/0x140
drm_atomic_helper_shutdown from device_shutdown+0x16c/0x240
device_shutdown from kernel_restart+0x38/0x90
kernel_restart from __do_sys_reboot+0x174/0x224
__do_sys_reboot from ret_fast_syscall+0x0/0x1c
Exception stack(0xe0851fa8 to 0xe0851ff0)
1fa0: 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6
Code: 15922088 1184421c e153 1af8 (e5953000)
---[ end trace ]---
Fixes: 0a58d2ae572a ("drm/msm: Make .remove and .shutdown HW shutdown
consistent")
Reported-by: kernel test robot
Signed-off-by: Dmitry Baryshkov
---
Changes since v2:
- Moved the condition check from msm_atomic_commit_tail() to msm_drv_shutdown()
Changes since v1:
- Moved setting of `async' before the call to trace to fix the
uninitialized variable warning
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 8b0b0ac74a6f..45e81eb148a8 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1278,7 +1278,7 @@ void msm_drv_shutdown(struct platform_device *pdev)
* msm_drm_init, drm_dev->registered
[Freedreno] [RFC PATCH v3 3/3] drm/msm/dpu: Use color_fill property for DPU planes
Initialize and use the color_fill properties for planes in DPU driver. In
addition, relax framebuffer requirements within atomic commit path and
add checks for NULL framebuffers. Finally, drop DPU_PLANE_COLOR_FILL_FLAG
as it's unused.
Changes since V2:
- Fixed dropped 'const' warning
- Dropped use of solid_fill_format
- Switched to using drm_plane_solid_fill_enabled helper method
- Added helper to convert color fill to BGR888 (Rob)
- Added support for solid fill on planes of varying sizes
- Removed DPU_PLANE_COLOR_FILL_FLAG
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 65 ++-
2 files changed, 49 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 13ce321283ff..0695b70ea1b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -409,6 +409,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
+ const struct msm_format *fmt;
struct dpu_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
@@ -441,7 +442,13 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
sspp_idx - SSPP_VIG0,
state->fb ? state->fb->base.id : -1);
- format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
+ if (pstate->base.fb)
+ fmt = msm_framebuffer_format(pstate->base.fb);
+ else
+ fmt = dpu_get_msm_format(&_dpu_crtc_get_kms(crtc)->base,
+ DRM_FORMAT_ABGR, 0);
+
+ format = to_dpu_format(fmt);
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 86719020afe2..51a7507373f7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -44,7 +44,6 @@
#define DPU_NAME_SIZE 12
-#define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
#define DPU_ZPOS_MAX 255
/* multirect rect index */
@@ -105,7 +104,6 @@ struct dpu_plane {
enum dpu_sspp pipe;
struct dpu_hw_pipe *pipe_hw;
- uint32_t color_fill;
bool is_error;
bool is_rt_pipe;
const struct dpu_mdss_cfg *catalog;
@@ -678,6 +676,17 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu,
&scaler3_cfg);
}
+static uint32_t _dpu_plane_get_fill_color(struct drm_solid_fill solid_fill)
+{
+ uint32_t ret = 0;
+
+ ret |= ((uint8_t) solid_fill.b) << 16;
+ ret |= ((uint8_t) solid_fill.g) << 8;
+ ret |= ((uint8_t) solid_fill.r);
+
+ return ret;
+}
+
/**
* _dpu_plane_color_fill - enables color fill on plane
* @pdpu: Pointer to DPU plane object
@@ -1001,12 +1010,17 @@ static int dpu_plane_atomic_check(struct drm_plane
*plane,
dst = drm_plane_state_dest(new_plane_state);
- fb_rect.x2 = new_plane_state->fb->width;
- fb_rect.y2 = new_plane_state->fb->height;
+ if (new_plane_state->fb) {
+ fb_rect.x2 = new_plane_state->fb->width;
+ fb_rect.y2 = new_plane_state->fb->height;
+ }
max_linewidth = pdpu->catalog->caps->max_linewidth;
- fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+ if (new_plane_state->fb)
+ fmt =
to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+ else
+ fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR);
min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
@@ -1018,7 +1032,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -EINVAL;
/* check src bounds */
- } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) {
+ } else if (new_plane_state->fb && !dpu_plane_validate_src(&src,
&fb_rect, min_src_size)) {
DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
DRM_RECT_ARG(&src));
return -E2BIG;
@@ -1086,9 +1100,10 @@ void dpu_plane_flush(struct drm_plane *plane)
if (pdpu->is_error)
/* force white frame with 100% alpha pipe output on error */
_dpu_plane_color_fill(pdpu, 0xFF, 0xFF);
- else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
+ else if (!(plane->state->fb) &&
drm_plane_solid_fill_enabled(plane->state))
/* force 100% alpha */
- _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
+ _dpu_plane_color_fil
[Freedreno] [RFC PATCH v3 1/3] drm: Introduce solid fill property for drm plane
Add support for solid_fill property to drm_plane. In addition, add
support for setting and getting the values for solid_fill.
solid_fill holds data for supporting solid fill planes. The property
accepts an RGB323232 value and the driver data is formatted as such:
struct drm_solid_fill {
u32 r;
u32 g;
u32 b;
};
To enable solid fill planes, userspace must assigned solid_fill to a
property blob containing the following information:
struct drm_solid_fill_info {
u8 version;
u32 r, g, b;
};
Changes in V2:
- Changed solid_fill property to a property blob (Simon, Dmitry)
- Added drm_solid_fill struct (Simon)
- Added drm_solid_fill_info struct (Simon)
Changes in V3:
- Corrected typo in drm_solid_fill struct documentation
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_state_helper.c | 9
drivers/gpu/drm/drm_atomic_uapi.c | 59 +++
drivers/gpu/drm/drm_blend.c | 17 +++
include/drm/drm_blend.h | 1 +
include/drm/drm_plane.h | 43 +
5 files changed, 129 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index dfb57217253b..c96fd1f2ad99 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -253,6 +253,11 @@ void __drm_atomic_helper_plane_state_reset(struct
drm_plane_state *plane_state,
plane_state->alpha = DRM_BLEND_ALPHA_OPAQUE;
plane_state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
+ if (plane_state->solid_fill_blob) {
+ drm_property_blob_put(plane_state->solid_fill_blob);
+ plane_state->solid_fill_blob = NULL;
+ }
+
if (plane->color_encoding_property) {
if (!drm_object_property_get_default_value(&plane->base,
plane->color_encoding_property,
@@ -335,6 +340,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
if (state->fb)
drm_framebuffer_get(state->fb);
+ if (state->solid_fill_blob)
+ drm_property_blob_get(state->solid_fill_blob);
+
state->fence = NULL;
state->commit = NULL;
state->fb_damage_clips = NULL;
@@ -384,6 +392,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_crtc_commit_put(state->commit);
drm_property_blob_put(state->fb_damage_clips);
+ drm_property_blob_put(state->solid_fill_blob);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index c06d0639d552..8a1d2fb7a757 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -316,6 +316,55 @@ drm_atomic_set_crtc_for_connector(struct
drm_connector_state *conn_state,
}
EXPORT_SYMBOL(drm_atomic_set_crtc_for_connector);
+static void drm_atomic_convert_solid_fill_info(struct drm_solid_fill *out,
+ struct drm_solid_fill_info *in)
+{
+ out->r = in->r;
+ out->g = in->g;
+ out->b = in->b;
+}
+
+static int drm_atomic_set_solid_fill_prop(struct drm_plane_state *state,
+ struct drm_property_blob *blob)
+{
+ int ret = 0;
+ int blob_version;
+
+ if (blob == state->solid_fill_blob)
+ return 0;
+
+ drm_property_blob_put(state->solid_fill_blob);
+ state->solid_fill_blob = NULL;
+
+ memset(&state->solid_fill, 0, sizeof(state->solid_fill));
+
+ if (blob) {
+ if (blob->length != sizeof(struct drm_solid_fill_info)) {
+ drm_dbg_atomic(state->plane->dev,
+ "[PLANE:%d:%s] bad solid fill blob
length: %zu\n",
+ state->plane->base.id,
state->plane->name,
+ blob->length);
+ return -EINVAL;
+ }
+
+ blob_version = ((struct drm_solid_fill_info
*)blob->data)->version;
+
+ /* Append with more versions if necessary */
+ if (blob_version == 1) {
+ drm_atomic_convert_solid_fill_info(&state->solid_fill,
blob->data);
+ } else {
+ drm_dbg_atomic(state->plane->dev,
+ "[PLANE:%d:%s] failed to set solid fill
(ret=%d)\n",
+ state->plane->base.id,
state->plane->name,
+ ret);
+ return -EINVAL;
+ }
+ state->solid_fill_blob = drm_property_blob_get(blob);
+ }
+
+ return ret;
+}
+
static void set_out_fence_for_crtc(struct drm_atomic_state *state,
struct drm_crtc *crtc, s32 __user *fence_ptr)
{
@@ -544,
[Freedreno] [RFC PATCH v3 2/3] drm: Adjust atomic checks for solid fill color
Loosen the requirements for atomic and legacy commit so that, in cases
where solid fill planes is enabled (and FB_ID is NULL), the commit can
still go through.
In addition, add framebuffer NULL checks in other areas to account for
FB being NULL when solid fill is enabled.
Changes in V2:
- Changed to checks for if solid_fill_blob is set (Dmitry)
- Abstracted (plane_state && !solid_fill_blob) checks to helper method
(Dmitry)
- Fixed indentation issue (Dmitry)
Changes in V3:
- Created drm_plane_has_visible_data() helper and corrected CRTC and FB
NULL-check logic (Dmitry)
- Merged `if (fb)` blocks in drm_atomic_plane_check() and abstracted
them into helper method (Dmitry)
- Inverted `if (solid_fill_enabled) else if (fb)` check order (Dmitry)
- Fixed indentation (Dmitry)
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 136
drivers/gpu/drm/drm_atomic_helper.c | 34 ---
drivers/gpu/drm/drm_plane.c | 8 +-
include/drm/drm_atomic_helper.h | 5 +-
include/drm/drm_plane.h | 19
5 files changed, 124 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index f197f59f6d99..63f34b430479 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -580,6 +580,76 @@ plane_switching_crtc(const struct drm_plane_state
*old_plane_state,
return true;
}
+static int drm_atomic_check_fb(const struct drm_plane_state *state)
+{
+ struct drm_plane *plane = state->plane;
+ const struct drm_framebuffer *fb = state->fb;
+ struct drm_mode_rect *clips;
+
+ uint32_t num_clips;
+ unsigned int fb_width, fb_height;
+ int ret;
+
+ /* Check whether this plane supports the fb pixel format. */
+ ret = drm_plane_check_pixel_format(plane, fb->format->format,
+ fb->modifier);
+
+ if (ret) {
+ drm_dbg_atomic(plane->dev,
+ "[PLANE:%d:%s] invalid pixel format %p4cc,
modifier 0x%llx\n",
+ plane->base.id, plane->name,
+ &fb->format->format, fb->modifier);
+ return ret;
+ }
+
+ fb_width = fb->width << 16;
+ fb_height = fb->height << 16;
+
+ /* Make sure source coordinates are inside the fb. */
+ if (state->src_w > fb_width ||
+ state->src_x > fb_width - state->src_w ||
+ state->src_h > fb_height ||
+ state->src_y > fb_height - state->src_h) {
+ drm_dbg_atomic(plane->dev,
+ "[PLANE:%d:%s] invalid source coordinates "
+ "%u.%06ux%u.%06u+%u.%06u+%u.%06u (fb %ux%u)\n",
+ plane->base.id, plane->name,
+ state->src_w >> 16,
+ ((state->src_w & 0x) * 15625) >> 10,
+ state->src_h >> 16,
+ ((state->src_h & 0x) * 15625) >> 10,
+ state->src_x >> 16,
+ ((state->src_x & 0x) * 15625) >> 10,
+ state->src_y >> 16,
+ ((state->src_y & 0x) * 15625) >> 10,
+ fb->width, fb->height);
+ return -ENOSPC;
+ }
+
+ clips = __drm_plane_get_damage_clips(state);
+ num_clips = drm_plane_get_damage_clips_count(state);
+
+ /* Make sure damage clips are valid and inside the fb. */
+ while (num_clips > 0) {
+ if (clips->x1 >= clips->x2 ||
+ clips->y1 >= clips->y2 ||
+ clips->x1 < 0 ||
+ clips->y1 < 0 ||
+ clips->x2 > fb_width ||
+ clips->y2 > fb_height) {
+ drm_dbg_atomic(plane->dev,
+ "[PLANE:%d:%s] invalid damage clip %d %d
%d %d\n",
+ plane->base.id, plane->name, clips->x1,
+ clips->y1, clips->x2, clips->y2);
+ return -EINVAL;
+ }
+ clips++;
+ num_clips--;
+ }
+
+ return 0;
+}
+
/**
* drm_atomic_plane_check - check plane state
* @old_plane_state: old plane state to check
@@ -596,13 +666,12 @@ static int drm_atomic_plane_check(const struct
drm_plane_state *old_plane_state,
struct drm_plane *plane = new_plane_state->plane;
struct drm_crtc *crtc = new_plane_state->crtc;
const struct drm_framebuffer *fb = new_plane_state->fb;
- unsigned int fb_width, fb_height;
- struct drm_mode_rect *clips;
- uint32_t num_clips;
int ret;
- /* either *both* CRTC and FB must be set, or neither */
- if (crtc && !fb) {
+ /* When solid_fill is disabled,
+* eithe
[Freedreno] [RFC PATCH v3 0/3] Support for Solid Fill Planes
Introduce and add support for a solid_fill property. When the solid_fill property is set, and the framebuffer is set to NULL, memory fetch will be disabled. In addition, loosen the NULL FB checks within the atomic commit callstack to allow a NULL FB when the solid_fill property is set and add FB checks in methods where the FB was previously assumed to be non-NULL. Finally, have the DPU driver use drm_plane_state.solid_fill and instead of dpu_plane_state.color_fill, and add extra checks in the DPU atomic commit callstack to account for a NULL FB in cases where solid_fill is set. Some drivers support hardware that have optimizations for solid fill planes. This series aims to expose these capabilities to userspace as some compositors have a solid fill flag (ex. SOLID_COLOR in the Android hardware composer HAL) that can be set by apps like the Android Gears app. Userspace can set the solid_fill property to a blob containing the appropriate version number and solid fill color (in RGB323232 format) and setting the framebuffer to NULL. Note: Currently, there's only one version of the solid_fill blob property. However if other drivers want to support a similar feature, but require more than just the solid fill color, they can extend this feature by creating additional versions of the drm_solid_fill struct. Changes in V2: - Dropped SOLID_FILL_FORMAT property (Simon) - Switched to implementing solid_fill property as a blob (Simon, Dmitry) - Changed to checks for if solid_fill_blob is set (Dmitry) - Abstracted (plane_state && !solid_fill_blob) checks to helper method (Dmitry) - Removed DPU_PLANE_COLOR_FILL_FLAG - Fixed whitespace and indentation issues (Dmitry) Changes in V3: - Fixed some logic errors in atomic checks (Dmitry) - Introduced drm_plane_has_visible_data() and drm_atomic_check_fb() helper methods (Dmitry) Jessica Zhang (3): drm: Introduce solid fill property for drm plane drm: Adjust atomic checks for solid fill color drm/msm/dpu: Use color_fill property for DPU planes drivers/gpu/drm/drm_atomic.c | 136 +- drivers/gpu/drm/drm_atomic_helper.c | 34 +++--- drivers/gpu/drm/drm_atomic_state_helper.c | 9 ++ drivers/gpu/drm/drm_atomic_uapi.c | 59 ++ drivers/gpu/drm/drm_blend.c | 17 +++ drivers/gpu/drm/drm_plane.c | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 65 +++ include/drm/drm_atomic_helper.h | 5 +- include/drm/drm_blend.h | 1 + include/drm/drm_plane.h | 62 ++ 11 files changed, 302 insertions(+), 103 deletions(-) -- 2.38.1
Re: [Freedreno] [PATCH v2] drm/msm: another fix for the headless Adreno GPU
On 04/01/2023 20:15, Rob Clark wrote:
On Wed, Jan 4, 2023 at 10:09 AM Abhinav Kumar wrote:
On 1/3/2023 7:51 AM, Dmitry Baryshkov wrote:
Fix another oops reproducible when rebooting the board with the Adreno
GPU wokring in the headless mode (e.g. iMX platforms).
wokring ---> working
Unable to handle kernel NULL pointer dereference at virtual address
when read
[] *pgd=74936831, *pte=, *ppte=
Internal error: Oops: 17 [#1] ARM
CPU: 0 PID: 51 Comm: reboot Not tainted 6.2.0-rc1-dirty #11
Hardware name: Freescale i.MX53 (Device Tree Support)
PC is at msm_atomic_commit_tail+0x50/0x970
LR is at commit_tail+0x9c/0x188
pc : []lr : []psr: 600e0013
sp : e0851d30 ip : ee4eb7eb fp : 00090acc
r10: 0058 r9 : c2193014 r8 : c431
r7 : c4759380 r6 : 07bef61d r5 : r4 :
r3 : c44cc440 r2 : r1 : r0 :
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 74910019 DAC: 0051
Register r0 information: NULL pointer
Register r1 information: NULL pointer
Register r2 information: NULL pointer
Register r3 information: slab kmalloc-1k start c44cc400 pointer offset 64 size
1024
Register r4 information: NULL pointer
Register r5 information: NULL pointer
Register r6 information: non-paged memory
Register r7 information: slab kmalloc-128 start c4759380 pointer offset 0 size
128
Register r8 information: slab kmalloc-2k start c431 pointer offset 0 size
2048
Register r9 information: non-slab/vmalloc memory
Register r10 information: non-paged memory
Register r11 information: non-paged memory
Register r12 information: non-paged memory
Process reboot (pid: 51, stack limit = 0xc80046d9)
Stack: (0xe0851d30 to 0xe0852000)
1d20: c4759380 fbd77200 05ff 002b9c70
1d40: c4759380 c4759380 07bef61d 0600 c0d6fe7c c2193014 0058
1d60: 00090acc c067a214 c4759380 c431 c44cc854 c067a89c
1d80: c4310468 c4759380 c431 c4310468
1da0: c4310470 c0643258 c4759380 c0c4ee24 c44cc810
1dc0: c0c4ee24 c44cc810 0347d2a8 e0851e00 e0851e00
1de0: c4759380 c067ad20 c431 c44cc810 c27f8718 c44cc854 c067adb8
1e00: c4933000 0002 0001 c2130850 c2130854
1e20: c25fc488 c0ff162c 0001 0002
1e40: c43102c0 c43102c0 0347d2a8 c44cc810 c44cc814 c2133da8 c06d1a60
1e60: 00079028 c2012f24 fee1dead c4933000 0058 c01431e4
1e80: 01234567 c0143a20
1ea0:
1ec0:
1ee0:
1f00:
1f20:
1f40:
1f60:
1f80: 0347d2a8 0002 0004 0078 0058
1fa0: c010028c c0100060 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6 600e0030 fee1dead
msm_atomic_commit_tail from commit_tail+0x9c/0x188
commit_tail from drm_atomic_helper_commit+0x160/0x188
drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe0
drm_atomic_commit from drm_atomic_helper_disable_all+0x1b0/0x1c0
drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x88/0x140
drm_atomic_helper_shutdown from device_shutdown+0x16c/0x240
device_shutdown from kernel_restart+0x38/0x90
kernel_restart from __do_sys_reboot+0x174/0x224
__do_sys_reboot from ret_fast_syscall+0x0/0x1c
Exception stack(0xe0851fa8 to 0xe0851ff0)
1fa0: 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6
Code: 15922088 1184421c e153 1af8 (e5953000)
---[ end trace ]---
Fixes: 0a58d2ae572a ("drm/msm: Make .remove and .shutdown HW shutdown
consistent")
Reported-by: kernel test robot
Signed-off-by: Dmitry Baryshkov
How is this null pointer hitting?
priv->kms is assigned in the msm_drm_init() which happens in the bind.
The headless A200 (e.g. on i.MX53) doesn't have KMS. This has been a
frequent case causing issues in .shutdown path.
I think we want to solve this higher up.. hitting atomic commit path
on a device which has no kms resources (planes, CRTCs, etc) seems
pretty wrong
Fine with me. Would it be better to skip a call
Re: [Freedreno] [PATCH v2] drm/msm: another fix for the headless Adreno GPU
On Wed, Jan 4, 2023 at 10:09 AM Abhinav Kumar wrote:
>
>
>
> On 1/3/2023 7:51 AM, Dmitry Baryshkov wrote:
> > Fix another oops reproducible when rebooting the board with the Adreno
> > GPU wokring in the headless mode (e.g. iMX platforms).
> wokring ---> working
> >
> > Unable to handle kernel NULL pointer dereference at virtual address
> > when read
> > [] *pgd=74936831, *pte=, *ppte=
> > Internal error: Oops: 17 [#1] ARM
> > CPU: 0 PID: 51 Comm: reboot Not tainted 6.2.0-rc1-dirty #11
> > Hardware name: Freescale i.MX53 (Device Tree Support)
> > PC is at msm_atomic_commit_tail+0x50/0x970
> > LR is at commit_tail+0x9c/0x188
> > pc : []lr : []psr: 600e0013
> > sp : e0851d30 ip : ee4eb7eb fp : 00090acc
> > r10: 0058 r9 : c2193014 r8 : c431
> > r7 : c4759380 r6 : 07bef61d r5 : r4 :
> > r3 : c44cc440 r2 : r1 : r0 :
> > Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
> > Control: 10c5387d Table: 74910019 DAC: 0051
> > Register r0 information: NULL pointer
> > Register r1 information: NULL pointer
> > Register r2 information: NULL pointer
> > Register r3 information: slab kmalloc-1k start c44cc400 pointer offset 64
> > size 1024
> > Register r4 information: NULL pointer
> > Register r5 information: NULL pointer
> > Register r6 information: non-paged memory
> > Register r7 information: slab kmalloc-128 start c4759380 pointer offset 0
> > size 128
> > Register r8 information: slab kmalloc-2k start c431 pointer offset 0
> > size 2048
> > Register r9 information: non-slab/vmalloc memory
> > Register r10 information: non-paged memory
> > Register r11 information: non-paged memory
> > Register r12 information: non-paged memory
> > Process reboot (pid: 51, stack limit = 0xc80046d9)
> > Stack: (0xe0851d30 to 0xe0852000)
> > 1d20: c4759380 fbd77200 05ff
> > 002b9c70
> > 1d40: c4759380 c4759380 07bef61d 0600 c0d6fe7c c2193014
> > 0058
> > 1d60: 00090acc c067a214 c4759380 c431 c44cc854
> > c067a89c
> > 1d80: c4310468 c4759380 c431
> > c4310468
> > 1da0: c4310470 c0643258 c4759380 c0c4ee24
> > c44cc810
> > 1dc0: c0c4ee24 c44cc810 0347d2a8 e0851e00
> > e0851e00
> > 1de0: c4759380 c067ad20 c431 c44cc810 c27f8718 c44cc854
> > c067adb8
> > 1e00: c4933000 0002 0001 c2130850
> > c2130854
> > 1e20: c25fc488 c0ff162c 0001 0002
> >
> > 1e40: c43102c0 c43102c0 0347d2a8 c44cc810 c44cc814 c2133da8
> > c06d1a60
> > 1e60: 00079028 c2012f24 fee1dead c4933000 0058
> > c01431e4
> > 1e80: 01234567 c0143a20
> >
> > 1ea0:
> >
> > 1ec0:
> >
> > 1ee0:
> >
> > 1f00:
> >
> > 1f20:
> >
> > 1f40:
> >
> > 1f60:
> >
> > 1f80: 0347d2a8 0002 0004 0078
> > 0058
> > 1fa0: c010028c c0100060 0002 0004 fee1dead 28121969 01234567
> > 00079028
> > 1fc0: 0002 0004 0078 0058 0002fdc5
> > 00090acc
> > 1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6 600e0030 fee1dead
> >
> > msm_atomic_commit_tail from commit_tail+0x9c/0x188
> > commit_tail from drm_atomic_helper_commit+0x160/0x188
> > drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe0
> > drm_atomic_commit from drm_atomic_helper_disable_all+0x1b0/0x1c0
> > drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x88/0x140
> > drm_atomic_helper_shutdown from device_shutdown+0x16c/0x240
> > device_shutdown from kernel_restart+0x38/0x90
> > kernel_restart from __do_sys_reboot+0x174/0x224
> > __do_sys_reboot from ret_fast_syscall+0x0/0x1c
> > Exception stack(0xe0851fa8 to 0xe0851ff0)
> > 1fa0: 0002 0004 fee1dead 28121969 01234567
> > 00079028
> > 1fc0: 0002 0004 0078 0058 0002fdc5
> > 00090acc
> > 1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6
> > Code: 15922088 1184421c e153 1af8 (e5953000)
> > ---[ end trace ]---
> >
> > Fixes: 0a58d2ae572a ("drm/msm: Make .remove and .shutdown HW shutdown
> > consistent")
> > Reported-by: kernel test robot
> > Signed-off-by: Dmitry Baryshkov
>
> How is this null pointer hitting
Re: [Freedreno] [PATCH v2] drm/msm: another fix for the headless Adreno GPU
On 1/3/2023 7:51 AM, Dmitry Baryshkov wrote:
Fix another oops reproducible when rebooting the board with the Adreno
GPU wokring in the headless mode (e.g. iMX platforms).
wokring ---> working
Unable to handle kernel NULL pointer dereference at virtual address
when read
[] *pgd=74936831, *pte=, *ppte=
Internal error: Oops: 17 [#1] ARM
CPU: 0 PID: 51 Comm: reboot Not tainted 6.2.0-rc1-dirty #11
Hardware name: Freescale i.MX53 (Device Tree Support)
PC is at msm_atomic_commit_tail+0x50/0x970
LR is at commit_tail+0x9c/0x188
pc : []lr : []psr: 600e0013
sp : e0851d30 ip : ee4eb7eb fp : 00090acc
r10: 0058 r9 : c2193014 r8 : c431
r7 : c4759380 r6 : 07bef61d r5 : r4 :
r3 : c44cc440 r2 : r1 : r0 :
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 74910019 DAC: 0051
Register r0 information: NULL pointer
Register r1 information: NULL pointer
Register r2 information: NULL pointer
Register r3 information: slab kmalloc-1k start c44cc400 pointer offset 64 size
1024
Register r4 information: NULL pointer
Register r5 information: NULL pointer
Register r6 information: non-paged memory
Register r7 information: slab kmalloc-128 start c4759380 pointer offset 0 size
128
Register r8 information: slab kmalloc-2k start c431 pointer offset 0 size
2048
Register r9 information: non-slab/vmalloc memory
Register r10 information: non-paged memory
Register r11 information: non-paged memory
Register r12 information: non-paged memory
Process reboot (pid: 51, stack limit = 0xc80046d9)
Stack: (0xe0851d30 to 0xe0852000)
1d20: c4759380 fbd77200 05ff 002b9c70
1d40: c4759380 c4759380 07bef61d 0600 c0d6fe7c c2193014 0058
1d60: 00090acc c067a214 c4759380 c431 c44cc854 c067a89c
1d80: c4310468 c4759380 c431 c4310468
1da0: c4310470 c0643258 c4759380 c0c4ee24 c44cc810
1dc0: c0c4ee24 c44cc810 0347d2a8 e0851e00 e0851e00
1de0: c4759380 c067ad20 c431 c44cc810 c27f8718 c44cc854 c067adb8
1e00: c4933000 0002 0001 c2130850 c2130854
1e20: c25fc488 c0ff162c 0001 0002
1e40: c43102c0 c43102c0 0347d2a8 c44cc810 c44cc814 c2133da8 c06d1a60
1e60: 00079028 c2012f24 fee1dead c4933000 0058 c01431e4
1e80: 01234567 c0143a20
1ea0:
1ec0:
1ee0:
1f00:
1f20:
1f40:
1f60:
1f80: 0347d2a8 0002 0004 0078 0058
1fa0: c010028c c0100060 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6 600e0030 fee1dead
msm_atomic_commit_tail from commit_tail+0x9c/0x188
commit_tail from drm_atomic_helper_commit+0x160/0x188
drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe0
drm_atomic_commit from drm_atomic_helper_disable_all+0x1b0/0x1c0
drm_atomic_helper_disable_all from drm_atomic_helper_shutdown+0x88/0x140
drm_atomic_helper_shutdown from device_shutdown+0x16c/0x240
device_shutdown from kernel_restart+0x38/0x90
kernel_restart from __do_sys_reboot+0x174/0x224
__do_sys_reboot from ret_fast_syscall+0x0/0x1c
Exception stack(0xe0851fa8 to 0xe0851ff0)
1fa0: 0002 0004 fee1dead 28121969 01234567 00079028
1fc0: 0002 0004 0078 0058 0002fdc5 00090acc
1fe0: 0058 becc9c64 b6e97e05 b6e0e5f6
Code: 15922088 1184421c e153 1af8 (e5953000)
---[ end trace ]---
Fixes: 0a58d2ae572a ("drm/msm: Make .remove and .shutdown HW shutdown
consistent")
Reported-by: kernel test robot
Signed-off-by: Dmitry Baryshkov
How is this null pointer hitting?
priv->kms is assigned in the msm_drm_init() which happens in the bind.
Only then we register the dri card for the commit which means commit
cannot come before that.
So, how can this sequence be possible?
---
Changes since v1:
- Moved setting of `async' before the call to trace to fix the
uninitialized variable warning
---
drivers/gpu/drm/msm/msm_atomic.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm
Re: [Freedreno] [PATCH 3/6] drm/msm/dpu: add support for SM8550
On Wed, 4 Jan 2023 at 12:08, Neil Armstrong wrote:
>
> On 04/01/2023 10:45, Dmitry Baryshkov wrote:
> > On 04/01/2023 11:08, Neil Armstrong wrote:
> >> Add definitions for the display hardware used on Qualcomm SM8550
> >> platform.
> >>
> >> Signed-off-by: Neil Armstrong
> >> ---
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197
> >> +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 2 +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
> >> 4 files changed, 201 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> index b4ca123d8e69..adf5e25269dc 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>
>
>
> >> @@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
> >> },
> >> };
> >> +static const struct dpu_ctl_cfg sm8550_ctl[] = {
> >> +{
> >> +.name = "ctl_0", .id = CTL_0,
> >> +.base = 0x15000, .len = 0x290,?
> >> +.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
> >> BIT(DPU_CTL_FETCH_ACTIVE),
> >
> > CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY) ?
>
> Indeed DPU_CTL_VM_CFG is missing, will switch to that.
>
> >
> >> +.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> >> +},
> >> +{
> >> +.name = "ctl_1", .id = CTL_1,
> >> +.base = 0x16000, .len = 0x290,
> >> +.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
> >> BIT(DPU_CTL_FETCH_ACTIVE),
> >> +.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> >> +},
> >> +{
> >> +.name = "ctl_2", .id = CTL_2,
> >> +.base = 0x17000, .len = 0x290,
> >> +.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >
> > CTL_SC7280_MASK?
>
> Ack
>
> >
> >> +.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> >> +},
> >> +{
> >> +.name = "ctl_3", .id = CTL_3,
> >> +.base = 0x18000, .len = 0x290,
> >> +.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >> +.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> >> +},
> >> +{
> >> +.name = "ctl_4", .id = CTL_4,
> >> +.base = 0x19000, .len = 0x290,
> >> +.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >> +.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> >> +},
> >> +{
> >> +.name = "ctl_5", .id = CTL_5,
> >> +.base = 0x1a000, .len = 0x290,
> >> +.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
> >> +.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> >> +},
> >> +};
> >> +
> >> static const struct dpu_ctl_cfg sc7280_ctl[] = {
> >> {
> >> .name = "ctl_0", .id = CTL_0,
>
>
>
> >> @@ -1268,6 +1386,16 @@ static const struct dpu_pingpong_sub_blks
> >> sc7280_pp_sblk = {
> >> .len = 0x20, .version = 0x2},
> >> };
> >> +#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr)
> >> \
> >> +{\
> >> +.name = _name, .id = _id, \
> >> +.base = _base, .len = 0, \
> >
> > len = 0 looks incorrect. Any particular reason why can't we use plain
> > PP_BLK here?
>
> The TE block has been moved to the DSI INTF blocks since SM8350 I think, or
> earlier.
I think, 8150. Marijn has been working on adding support for INTF-based TE.
> This removes the DPU_PINGPONG_DITHER feature used downstream to enable the PP
> TE callbacks.
> Since there's only the DIPHER sub-block remaining, this is why I set len to 0.
I went on with some research. Usually PP len is 0xd4. However it seems
since 8350 (since the change of DSC block) the PP size should be 0x0),
despite dowsnstream DTs having sde-pp-size=0xd4 for sm8350 and sm8450
(or 0x4 for neo, DPU 9.1.0).
So, it looks like you are correct here (and we should fix 8350/8450
patches instead).
>
> >
> >> +.features = BIT(DPU_PINGPONG_DITHER), \
> >> +.merge_3d = _merge_3d, \
> >> +.sblk = &_sblk, \
> >> +.intr_done = _done, \
> >> +.intr_rdptr = _rdptr, \
> >> +}
> >> #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
> >> {\
> >> .name = _name, .id = _id, \
>
>
>
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
On Wed, 4 Jan 2023 at 12:11, Neil Armstrong wrote:
>
> On 04/01/2023 10:53, Dmitry Baryshkov wrote:
> > On 04/01/2023 11:08, Neil Armstrong wrote:
> >> SM8550 use a 4nm DSI PHYs, which share register definitions
> >> with 7nm DSI PHYs. Rather than duplicating the driver, handle
> >> 4nm variant inside the common 5+7nm driver.
> >>
> >> Signed-off-by: Neil Armstrong
> >> ---
> >> drivers/gpu/drm/msm/Kconfig | 4 +-
> >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
> >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
> >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102
> >> --
> >> 4 files changed, 89 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> >> index e7b100d97f88..949b18a29a55 100644
> >> --- a/drivers/gpu/drm/msm/Kconfig
> >> +++ b/drivers/gpu/drm/msm/Kconfig
> >> @@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
> >> Choose this option if DSI PHY on SDM845 is used on the platform.
> >> config DRM_MSM_DSI_7NM_PHY
> >> -bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
> >> +bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
> >> depends on DRM_MSM_DSI
> >> default y
> >> help
> >> - Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
> >> + Choose this option if DSI PHY on
> >> SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
> >> is used on the platform.
> >> config DRM_MSM_HDMI
> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> >> index 0c956fdab23e..54e03cc9fbe7 100644
> >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> >> @@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> >> .data = &dsi_phy_5nm_8350_cfgs },
> >> { .compatible = "qcom,dsi-phy-5nm-8450",
> >> .data = &dsi_phy_5nm_8450_cfgs },
> >> +{ .compatible = "qcom,dsi-phy-4nm-8550",
> >> + .data = &dsi_phy_4nm_8550_cfgs },
> >> #endif
> >> {}
> >> };
> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >> index f7a907ed2b4b..58f9e09f5224 100644
> >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> >> @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg
> >> dsi_phy_7nm_8150_cfgs;
> >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
> >> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
> >> extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
> >> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
> >> struct msm_dsi_dphy_timing {
> >> u32 clk_zero;
> >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> index 7b2c16b3a36c..11629c431c30 100644
> >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> >> @@ -47,6 +47,8 @@
> >> #define DSI_PHY_7NM_QUIRK_V4_2BIT(2)
> >> /* Hardware is V4.3 */
> >> #define DSI_PHY_7NM_QUIRK_V4_3BIT(3)
> >> +/* Hardware is V5.2 */
> >> +#define DSI_PHY_7NM_QUIRK_V5_2BIT(4)
> >> struct dsi_pll_config {
> >> bool enable_ssc;
> >> @@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm
> >> *pll, struct dsi_pll_config
> >> if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
> >> config->pll_clock_inverters = 0x28;
> >> -else if (pll_freq <= 10ULL)
> >> -config->pll_clock_inverters = 0xa0;
> >> -else if (pll_freq <= 25ULL)
> >> -config->pll_clock_inverters = 0x20;
> >> -else if (pll_freq <= 302000ULL)
> >> -config->pll_clock_inverters = 0x00;
> >> -else
> >> -config->pll_clock_inverters = 0x40;
> >> +else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >> +if (pll_freq <= 13ULL)
> >> +config->pll_clock_inverters = 0xa0;
> >> +else if (pll_freq <= 25ULL)
> >> +config->pll_clock_inverters = 0x20;
> >> +else if (pll_freq <= 40ULL)
> >> +config->pll_clock_inverters = 0x00;
> >> +else
> >> +config->pll_clock_inverters = 0x40;
> >> +} else {
> >> +if (pll_freq <= 10ULL)
> >> +config->pll_clock_inverters = 0xa0;
> >> +else if (pll_freq <= 25ULL)
> >> +config->pll_clock_inverters = 0x20;
> >> +else if (pll_freq <= 302000ULL)
> >> +config->pll_clock_inverters = 0x00;
> >> +else
> >> +config->pll_clock_inverters = 0x40;
> >> +}
> >> config->decimal_div_start = dec;
> >> config->frac_div_start = frac;
> >> @@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct
> >> dsi_pll_7nm *pll)
> >> vco_config_1 = 0x01;
> >>
Re: [Freedreno] [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
On 04/01/2023 10:53, Dmitry Baryshkov wrote:
On 04/01/2023 11:08, Neil Armstrong wrote:
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 --
4 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index e7b100d97f88..949b18a29a55 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
Choose this option if DSI PHY on SDM845 is used on the platform.
config DRM_MSM_DSI_7NM_PHY
- bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
+ bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
default y
help
- Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
+ Choose this option if DSI PHY on
SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
is used on the platform.
config DRM_MSM_HDMI
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 0c956fdab23e..54e03cc9fbe7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_5nm_8350_cfgs },
{ .compatible = "qcom,dsi-phy-5nm-8450",
.data = &dsi_phy_5nm_8450_cfgs },
+ { .compatible = "qcom,dsi-phy-4nm-8550",
+ .data = &dsi_phy_4nm_8550_cfgs },
#endif
{}
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f7a907ed2b4b..58f9e09f5224 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 7b2c16b3a36c..11629c431c30 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -47,6 +47,8 @@
#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
/* Hardware is V4.3 */
#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
+/* Hardware is V5.2 */
+#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
struct dsi_pll_config {
bool enable_ssc;
@@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm
*pll, struct dsi_pll_config
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
config->pll_clock_inverters = 0x28;
- else if (pll_freq <= 10ULL)
- config->pll_clock_inverters = 0xa0;
- else if (pll_freq <= 25ULL)
- config->pll_clock_inverters = 0x20;
- else if (pll_freq <= 302000ULL)
- config->pll_clock_inverters = 0x00;
- else
- config->pll_clock_inverters = 0x40;
+ else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll_freq <= 13ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 25ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 40ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ } else {
+ if (pll_freq <= 10ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 25ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 302000ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ }
config->decimal_div_start = dec;
config->frac_div_start = frac;
@@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm
*pll)
vco_config_1 = 0x01;
}
+ if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll->vco_current_rate < 155700ULL)
+ vco_config_1 = 0x08;
+ else
+ vco_config_1 = 0x01;
+ }
+
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
analog_controls_five_1);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
@@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
pr_warn("PLL turned on before configuring PHY\n");
/* Request for REFGEN READY */
- if (phy->cfg->qui
Re: [Freedreno] [PATCH 3/6] drm/msm/dpu: add support for SM8550
On 04/01/2023 10:45, Dmitry Baryshkov wrote:
On 04/01/2023 11:08, Neil Armstrong wrote:
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 201 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b4ca123d8e69..adf5e25269dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8550_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x290,?
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY) ?
Indeed DPU_CTL_VM_CFG is missing, will switch to that.
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
CTL_SC7280_MASK?
Ack
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1268,6 +1386,16 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk
= {
.len = 0x20, .version = 0x2},
};
+#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
+ {\
+ .name = _name, .id = _id, \
+ .base = _base, .len = 0, \
len = 0 looks incorrect. Any particular reason why can't we use plain PP_BLK
here?
The TE block has been moved to the DSI INTF blocks since SM8350 I think, or
earlier.
This removes the DPU_PINGPONG_DITHER feature used downstream to enable the PP
TE callbacks.
Since there's only the DIPHER sub-block remaining, this is why I set len to 0.
+ .features = BIT(DPU_PINGPONG_DITHER), \
+ .merge_3d = _merge_3d, \
+ .sblk = &_sblk, \
+ .intr_done = _done, \
+ .intr_rdptr = _rdptr, \
+ }
#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
{\
.name = _name, .id = _id, \
Re: [Freedreno] [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0
On 04/01/2023 11:08, Neil Armstrong wrote: Add support for DSI 2.7.0 (block used on sm8550). Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 17 insertions(+) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [Freedreno] [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
On 04/01/2023 11:08, Neil Armstrong wrote:
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 --
4 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index e7b100d97f88..949b18a29a55 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
Choose this option if DSI PHY on SDM845 is used on the platform.
config DRM_MSM_DSI_7NM_PHY
- bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
+ bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
default y
help
- Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
+ Choose this option if DSI PHY on
SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
is used on the platform.
config DRM_MSM_HDMI
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 0c956fdab23e..54e03cc9fbe7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_5nm_8350_cfgs },
{ .compatible = "qcom,dsi-phy-5nm-8450",
.data = &dsi_phy_5nm_8450_cfgs },
+ { .compatible = "qcom,dsi-phy-4nm-8550",
+ .data = &dsi_phy_4nm_8550_cfgs },
#endif
{}
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f7a907ed2b4b..58f9e09f5224 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 7b2c16b3a36c..11629c431c30 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -47,6 +47,8 @@
#define DSI_PHY_7NM_QUIRK_V4_2BIT(2)
/* Hardware is V4.3 */
#define DSI_PHY_7NM_QUIRK_V4_3BIT(3)
+/* Hardware is V5.2 */
+#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
struct dsi_pll_config {
bool enable_ssc;
@@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm
*pll, struct dsi_pll_config
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
config->pll_clock_inverters = 0x28;
- else if (pll_freq <= 10ULL)
- config->pll_clock_inverters = 0xa0;
- else if (pll_freq <= 25ULL)
- config->pll_clock_inverters = 0x20;
- else if (pll_freq <= 302000ULL)
- config->pll_clock_inverters = 0x00;
- else
- config->pll_clock_inverters = 0x40;
+ else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll_freq <= 13ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 25ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 40ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ } else {
+ if (pll_freq <= 10ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 25ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 302000ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ }
config->decimal_div_start = dec;
config->frac_div_start = frac;
@@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm
*pll)
vco_config_1 = 0x01;
}
+ if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll->vco_current_rate < 155700ULL)
+ vco_config_1 = 0x08;
+ else
+ vco_config_1 = 0x01;
+ }
+
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
analog
Re: [Freedreno] [PATCH 4/6] drm/msm: mdss: add support for SM8550
On 04/01/2023 11:08, Neil Armstrong wrote:
Add support for the MDSS block on SM8550 platform.
Signed-off-by: Neil Armstrong
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 144c8dd82be1..54483fe30ffd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -288,6 +288,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
case DPU_HW_VER_810:
+ case DPU_HW_VER_900:
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
break;
@@ -521,6 +522,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
+ { .compatible = "qcom,sm8550-mdss" },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 3/6] drm/msm/dpu: add support for SM8550
On 04/01/2023 11:08, Neil Armstrong wrote:
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 201 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b4ca123d8e69..adf5e25269dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -402,6 +402,20 @@ static const struct dpu_caps sm8450_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8550_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -579,6 +593,37 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8550_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x4330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x6330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x8330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0xa330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x24330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x26330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = {
+ .reg_off = 0x28330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = {
+ .reg_off = 0x2a330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2c330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2e330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8550_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x290,?
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY) ?
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
CTL_SC7280_MASK?
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1032,6 +1116,40 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
+static const struct
Re: [Freedreno] [PATCH v6 07/18] dt-bindings: display/msm: Add list of mdss-dsi-ctrl compats
On 04/01/2023 02:29, Rob Herring wrote: On Fri, Dec 23, 2022 at 02:10:14AM +, Bryan O'Donoghue wrote: Add the list of current compats absent the deprecated qcm2290 to the list of dsi compats listed here. Several MDSS yaml files exist which document the dsi sub-node. For each existing SoC MDSS yaml, provide the right dsi compat string. Signed-off-by: Bryan O'Donoghue --- .../bindings/display/msm/qcom,mdss.yaml | 16 +++- .../bindings/display/msm/qcom,msm8998-mdss.yaml | 8 +--- .../bindings/display/msm/qcom,sc7180-mdss.yaml | 6 -- .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 -- .../bindings/display/msm/qcom,sdm845-mdss.yaml | 8 +--- .../bindings/display/msm/qcom,sm8250-mdss.yaml | 8 +--- 6 files changed, 38 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index ba0460268731b..86bb43489bf4a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -94,7 +94,21 @@ patternProperties: type: object properties: compatible: -const: qcom,mdss-dsi-ctrl +items: + - enum: + - qcom,apq8064-dsi-ctrl + - qcom,msm8916-dsi-ctrl + - qcom,msm8953-dsi-ctrl + - qcom,msm8974-dsi-ctrl + - qcom,msm8996-dsi-ctrl + - qcom,msm8998-dsi-ctrl + - qcom,qcm2290-dsi-ctrl + - qcom,sc7180-dsi-ctrl + - qcom,sc7280-dsi-ctrl + - qcom,sdm660-dsi-ctrl + - qcom,sdm845-dsi-ctrl + - qcom,sm8250-dsi-ctrl + - const: qcom,mdss-dsi-ctrl No need to have an exact match here. Just this is enough: compatible: contains: const: qcom,mdss-dsi-ctrl Then the DSI schema will check the rest. I think the intent here should have been to list DSI variants usable with the qcom,mdss device. But then the list should be shortened a bit. E.g. apq8064 is pre-MDSS and sc7180/7280 and sm8250 are used with qcom,SoC-mdss devices rather than just qcom,mdss. Same for the rest. Rob -- With best wishes Dmitry
[Freedreno] [PATCH 5/6] drm/msm/dsi: add support for DSI-PHY on SM8550
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/Kconfig | 4 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 --
4 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index e7b100d97f88..949b18a29a55 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
Choose this option if DSI PHY on SDM845 is used on the platform.
config DRM_MSM_DSI_7NM_PHY
- bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
+ bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
default y
help
- Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
+ Choose this option if DSI PHY on
SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
is used on the platform.
config DRM_MSM_HDMI
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 0c956fdab23e..54e03cc9fbe7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_5nm_8350_cfgs },
{ .compatible = "qcom,dsi-phy-5nm-8450",
.data = &dsi_phy_5nm_8450_cfgs },
+ { .compatible = "qcom,dsi-phy-4nm-8550",
+ .data = &dsi_phy_4nm_8550_cfgs },
#endif
{}
};
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f7a907ed2b4b..58f9e09f5224 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
struct msm_dsi_dphy_timing {
u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 7b2c16b3a36c..11629c431c30 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -47,6 +47,8 @@
#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
/* Hardware is V4.3 */
#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
+/* Hardware is V5.2 */
+#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
struct dsi_pll_config {
bool enable_ssc;
@@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm
*pll, struct dsi_pll_config
if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
config->pll_clock_inverters = 0x28;
- else if (pll_freq <= 10ULL)
- config->pll_clock_inverters = 0xa0;
- else if (pll_freq <= 25ULL)
- config->pll_clock_inverters = 0x20;
- else if (pll_freq <= 302000ULL)
- config->pll_clock_inverters = 0x00;
- else
- config->pll_clock_inverters = 0x40;
+ else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll_freq <= 13ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 25ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 40ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ } else {
+ if (pll_freq <= 10ULL)
+ config->pll_clock_inverters = 0xa0;
+ else if (pll_freq <= 25ULL)
+ config->pll_clock_inverters = 0x20;
+ else if (pll_freq <= 302000ULL)
+ config->pll_clock_inverters = 0x00;
+ else
+ config->pll_clock_inverters = 0x40;
+ }
config->decimal_div_start = dec;
config->frac_div_start = frac;
@@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm
*pll)
vco_config_1 = 0x01;
}
+ if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
+ if (pll->vco_current_rate < 155700ULL)
+ vco_config_1 = 0x08;
+ else
+ vco_config_1 = 0x01;
+ }
+
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
analog_controls_five_1);
dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CO
[Freedreno] [PATCH 6/6] drm/msm/dsi: add support for DSI 2.7.0
Add support for DSI 2.7.0 (block used on sm8550).
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 59a4cc95a251..33884ebd2f86 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -181,6 +181,20 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
.num_dsi = 2,
};
+static const struct regulator_bulk_data sm8550_dsi_regulators[] = {
+ { .supply = "vdda", .init_load_uA = 16800 },/* 1.2 V */
+};
+
+static const struct msm_dsi_config sm8550_dsi_cfg = {
+ .io_offset = DSI_6G_REG_SHIFT,
+ .regulator_data = sm8550_dsi_regulators,
+ .num_regulators = ARRAY_SIZE(sm8550_dsi_regulators),
+ .bus_clk_names = dsi_sdm845_bus_clk_names,
+ .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
+ .io_start = { 0xae94000, 0xae96000 },
+ .num_dsi = 2,
+};
+
static const struct regulator_bulk_data sc7180_dsi_regulators[] = {
{ .supply = "vdda", .init_load_uA = 21800 },/* 1.2 V */
};
@@ -302,6 +316,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[]
= {
&sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
+ &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 95957fab499d..44be4a88aa83 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -26,6 +26,7 @@
#define MSM_DSI_6G_VER_MINOR_V2_4_10x20040001
#define MSM_DSI_6G_VER_MINOR_V2_5_00x2005
#define MSM_DSI_6G_VER_MINOR_V2_6_00x2006
+#define MSM_DSI_6G_VER_MINOR_V2_7_00x2007
#define MSM_DSI_V2_VER_MINOR_8064 0x0
--
2.34.1
[Freedreno] [PATCH 4/6] drm/msm: mdss: add support for SM8550
Add support for the MDSS block on SM8550 platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/msm_mdss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 144c8dd82be1..54483fe30ffd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -288,6 +288,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
case DPU_HW_VER_810:
+ case DPU_HW_VER_900:
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
break;
@@ -521,6 +522,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
+ { .compatible = "qcom,sm8550-mdss" },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
--
2.34.1
[Freedreno] [PATCH 3/6] drm/msm/dpu: add support for SM8550
Add definitions for the display hardware used on Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 201 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b4ca123d8e69..adf5e25269dc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -402,6 +402,20 @@ static const struct dpu_caps sm8450_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8550_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -579,6 +593,37 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8550_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x4330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x6330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x8330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0xa330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x24330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x26330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = {
+ .reg_off = 0x28330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = {
+ .reg_off = 0x2a330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2c330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2e330, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -776,6 +821,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8550_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) |
BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x290,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1032,6 +1116,40 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
+static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
+ _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED3LITE);
+static const struc
[Freedreno] [PATCH 2/6] dt-bindings: display/msm: document the display hardware for SM8550
Document the MDSS and DPU blocks found on the Qualcomm SM8550
platform.
Signed-off-by: Neil Armstrong
---
.../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +
.../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +
2 files changed, 465 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
new file mode 100644
index ..c3d5a98fe3c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8550 Display DPU
+
+maintainers:
+ - Neil Armstrong
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8550-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf axi
+ - description: Display MDSS ahb
+ - description: Display lut
+ - description: Display core
+ - description: Display vsync
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8550-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_AHB_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_CLK>,
+<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8550_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+dpu_intf2_out: endpoint {
+remote-endpoint = <&dsi1_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-32500 {
+opp-hz = /bits/ 64 <32500>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-51400 {
+opp-hz = /bits/ 64 <51400>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+};
+};
+...
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
new file mode 100644
index ..71b5b5f75969
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
@@ -0,0 +1,331 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8550 Display MDSS
+
+maintainers:
+ - Neil Armstrong
+
+description:
+ SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8550-mdss
+
+ clocks:
+items:
+ - description: Display MDSS AHB
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+
[Freedreno] [PATCH 1/6] dt-bindings: display/msm: document the SM8550 DSI PHY
Document the SM8550 DSI PHY which is very close from the 7nm and 5nm DSI PHYs found in earlier platforms. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index bffd161fedfd..f72727f81076 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -15,6 +15,7 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-4nm-8550 - qcom,dsi-phy-5nm-8350 - qcom,dsi-phy-5nm-8450 - qcom,dsi-phy-7nm -- 2.34.1
[Freedreno] [PATCH 0/6] drm/msm: add support for SM8450
This adds support for the MDSS/DPU/DSI on the Qualcomm SM8550 platform. This patchset is based on the SM8450 display support serie at [1]. In order to work, the following patchsets are required: - PM8550 LDO fix at [2] - DISPCC driver at [3] + the DT changes. [1] https://lore.kernel.org/all/20221207012231.112059-1-dmitry.barysh...@linaro.org/ [2] https://lore.kernel.org/all/20230102-topic-sm8550-upstream-fixes-reg-l11b-nldo-v1-1-d97def246...@linaro.org/ [3] https://lore.kernel.org/all/20230103-topic-sm8550-upstream-dispcc-v1-0-81bfcc26b...@linaro.org/ To: Rob Clark To: Abhinav Kumar To: Dmitry Baryshkov To: Sean Paul To: David Airlie To: Daniel Vetter To: Rob Herring To: Krzysztof Kozlowski To: Jonathan Marek Cc: linux-arm-...@vger.kernel.org Cc: dri-de...@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Cc: devicet...@vger.kernel.org Cc: linux-ker...@vger.kernel.org Signed-off-by: Neil Armstrong --- Neil Armstrong (6): dt-bindings: display/msm: document the SM8550 DSI PHY dt-bindings: display/msm: document the display hardware for SM8550 drm/msm/dpu: add support for SM8550 drm/msm: mdss: add support for SM8550 drm/msm/dsi: add support for DSI-PHY on SM8550 drm/msm/dsi: add support for DSI 2.7.0 .../bindings/display/msm/dsi-phy-7nm.yaml | 1 + .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 + .../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 + drivers/gpu/drm/msm/Kconfig| 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h| 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 + drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 + drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 102 +-- drivers/gpu/drm/msm/msm_mdss.c | 2 + 14 files changed, 775 insertions(+), 20 deletions(-) --- base-commit: d862fd95b9c924bd0a257f7708a6e3868d39ff43 change-id: 20230103-topic-sm8550-upstream-mdss-dsi-35ca8acea529 Best regards, -- Neil Armstrong
Re: [Freedreno] [PATCH v3 0/7] drm/bridge_connector: perform HPD enablement automatically
On 04/01/2023 08:29, Tomi Valkeinen wrote: On 28/12/2022 23:58, Dmitry Baryshkov wrote: On 02/11/2022 20:06, Dmitry Baryshkov wrote: From all the drivers using drm_bridge_connector only iMX/dcss and OMAP DRM driver do a proper work of calling drm_bridge_connector_en/disable_hpd() in right places. Rather than teaching each and every driver how to properly handle drm_bridge_connector's HPD, make that automatic. Add two additional drm_connector helper funcs: enable_hpd() and disable_hpd(). Make drm_kms_helper_poll_* functions call them (as this is the time where the drm_bridge_connector's functions are called by the drivers too). Since we are at the beginning of the development window, gracious ping for this patchset. It would be nice to finally handle the bridge_connector's hpd properly. Calling drm_bridge_connector_enable_hpd() from drm_bridge_connector_init() is not a proper way to do this. It results in calling bridge->funcs->hpd_enable() before the rest of the pipeline was set up properly. For the series: Reviewed-by: Tomi Valkeinen I've been using this series in my local branch for quite a while to fix the HPD issues. Works for me. I still think the "fix" aspect should be highlighted more here, as the current upstream triggers a WARN for "Hot plug detection already enabled" (at least) on OMAP. LGTM then ! Tomi, Dmitry, I can push the whole serie via drm-misc-next or -fixes then, as you wish. Neil Tomi
