Re: [Freedreno] [PATCH 3/6] dt-bindings: display: msm: Add SDM670 MDSS
On Mon, 25 Sep 2023 19:26:30 -0400, Richard Acayan wrote: > Add documentation for the SDM670 display subsystem, adapted from the > SDM845 and SM6125 documentation. > > Signed-off-by: Richard Acayan > --- > .../display/msm/qcom,sdm670-mdss.yaml | 280 ++ > 1 file changed, 280 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.example.dts:198.43-200.27: Warning (graph_endpoint): /example-0/display-subsystem@ae0/dsi@ae96000/ports/port@0/endpoint: graph connection to node '/example-0/display-subsystem@ae0/display-controller@ae01000/ports/port@1/endpoint' is not bidirectional doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230925232625.84-12-mailingrad...@gmail.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
[Freedreno] [PATCH 6/6] arm64: dts: qcom: sdm670: add display subsystem
The Snapdragon 670 has a display subsystem for controlling and
outputting to the display. Add support for it in the device tree.
Signed-off-by: Richard Acayan
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 294 +++
1 file changed, 294 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi
b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 84cd2e39266f..427415ed4e4a 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -6,6 +6,7 @@
* Copyright (c) 2022, Richard Acayan. All rights reserved.
*/
+#include
#include
#include
#include
@@ -400,6 +401,30 @@ cpu6_opp10: opp-199680 {
};
};
+ dsi_opp_table: opp-table-dsi {
+ compatible = "operating-points-v2";
+
+ opp-1920 {
+ opp-hz = /bits/ 64 <1920>;
+ required-opps = <_opp_min_svs>;
+ };
+
+ opp-18000 {
+ opp-hz = /bits/ 64 <18000>;
+ required-opps = <_opp_low_svs>;
+ };
+
+ opp-27500 {
+ opp-hz = /bits/ 64 <27500>;
+ required-opps = <_opp_svs>;
+ };
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ required-opps = <_opp_svs_l1>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1352,6 +1377,275 @@ spmi_bus: spmi@c44 {
#interrupt-cells = <4>;
};
+ mdss: display-subsystem@ae0 {
+ compatible = "qcom,sdm670-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = < MDSS_GDSC>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <_noc MASTER_MDP_PORT0 0 _noc
SLAVE_EBI_CH0 0>,
+ <_noc MASTER_MDP_PORT1 0 _noc
SLAVE_EBI_CH0 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ iommus = <_smmu 0x880 0x8>,
+<_smmu 0xc80 0x8>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sdm670-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "gcc-bus", "iface", "bus",
"core", "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SDM670_CX>;
+
+ interrupt-parent = <>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint =
<_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+
[Freedreno] [PATCH 4/6] drm/msm: mdss: add support for SDM670
Add support for the MDSS block on the SDM670 platform.
Signed-off-by: Richard Acayan
---
drivers/gpu/drm/msm/msm_mdss.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 2e87dd6cb17b..2afb843271aa 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -551,6 +551,12 @@ static const struct msm_mdss_data sc8280xp_data = {
.macrotile_mode = 1,
};
+static const struct msm_mdss_data sdm670_data = {
+ .ubwc_enc_version = UBWC_2_0,
+ .ubwc_dec_version = UBWC_2_0,
+ .highest_bank_bit = 1,
+};
+
static const struct msm_mdss_data sdm845_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
@@ -609,6 +615,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = _data },
{ .compatible = "qcom,qcm2290-mdss", .data = _data },
+ { .compatible = "qcom,sdm670-mdss", .data = _data },
{ .compatible = "qcom,sdm845-mdss", .data = _data },
{ .compatible = "qcom,sc7180-mdss", .data = _data },
{ .compatible = "qcom,sc7280-mdss", .data = _data },
--
2.42.0
[Freedreno] [PATCH 5/6] drm/msm/dpu: Add hw revision 4.1 (SDM670)
The Snapdragon 670 uses similar clocks (with one frequency added) to the
Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU
with configuration from the Pixel 3a downstream kernel.
Since revision 4.0 is SDM845, reuse some configuration from its catalog
entry.
Link:
https://android.googlesource.com/kernel/msm/+/368478b0ae76566927a2769a2bf24dfe7f38bb78/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi
Signed-off-by: Richard Acayan
---
.../msm/disp/dpu1/catalog/dpu_4_1_sdm670.h| 105 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 6 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 113 insertions(+)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
new file mode 100644
index ..eaccb16b5db9
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Richard Acayan. All rights reserved.
+ */
+
+#ifndef _DPU_4_1_SDM670_H
+#define _DPU_4_1_SDM670_H
+
+static const struct dpu_mdp_cfg sdm670_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x45c,
+ .features = BIT(DPU_MDP_AUDIO_SELECT),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0},
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0},
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8},
+ },
+};
+
+static const struct dpu_sspp_cfg sdm670_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x1c8,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = _vig_sblk_0,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x1c8,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = _vig_sblk_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x1c8,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = _dma_sblk_0,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA0,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x1c8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = _dma_sblk_1,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA1,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x1c8,
+ .features = DMA_CURSOR_SDM845_MASK_SDMA,
+ .sblk = _dma_sblk_2,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ .clk_ctrl = DPU_CLK_CTRL_DMA2,
+ },
+};
+
+static struct dpu_dsc_cfg sdm670_dsc[] = {
+ {
+ .name = "dsc_0", .id = DSC_0,
+ .base = 0x8, .len = 0x140,
+ },
+ {
+ .name = "dsc_1", .id = DSC_1,
+ .base = 0x80400, .len = 0x140,
+ },
+};
+
+static struct dpu_mdss_version sdm670_mdss_ver = {
+ .core_major_ver = 4,
+ .core_minor_ver = 1,
+};
+
+const struct dpu_mdss_cfg dpu_sdm670_cfg = {
+ .mdss_ver = _mdss_ver,
+ .caps = _dpu_caps,
+ .mdp = _mdp,
+ .ctl_count = ARRAY_SIZE(sdm845_ctl),
+ .ctl = sdm845_ctl,
+ .sspp_count = ARRAY_SIZE(sdm670_sspp),
+ .sspp = sdm670_sspp,
+ .mixer_count = ARRAY_SIZE(sdm845_lm),
+ .mixer = sdm845_lm,
+ .pingpong_count = ARRAY_SIZE(sdm845_pp),
+ .pingpong = sdm845_pp,
+ .dsc_count = ARRAY_SIZE(sdm670_dsc),
+ .dsc = sdm670_dsc,
+ .intf_count = ARRAY_SIZE(sdm845_intf),
+ .intf = sdm845_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = _perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 713dfc079718..63b274ae032a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -313,6 +313,11 @@ static const struct
[Freedreno] [PATCH 3/6] dt-bindings: display: msm: Add SDM670 MDSS
Add documentation for the SDM670 display subsystem, adapted from the
SDM845 and SM6125 documentation.
Signed-off-by: Richard Acayan
---
.../display/msm/qcom,sdm670-mdss.yaml | 280 ++
1 file changed, 280 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml
new file mode 100644
index ..839b372759ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml
@@ -0,0 +1,280 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM670 Display MDSS
+
+maintainers:
+ - Richard Acayan
+
+description:
+ SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sdm670-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: core
+
+ iommus:
+maxItems: 2
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sdm670-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sdm670-dp
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+items:
+ - const: qcom,sdm670-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-10nm
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sdm670-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+power-domains = < MDSS_GDSC>;
+
+clocks = < GCC_DISP_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "core";
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <_smmu 0x880 0x8>,
+ <_smmu 0xc80 0x8>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sdm670-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < GCC_DISP_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_AXI_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
+
+interrupt-parent = <>;
+interrupts = <0>;
+power-domains = < SDM670_CX>;
+operating-points-v2 = <_opp_table>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <_dsi0_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+dpu_intf2_out: endpoint {
+remote-endpoint = <_dsi1_in>;
+};
+};
+};
+};
+
+dsi@ae94000 {
+compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+reg = <0x0ae94000 0x400>;
+reg-names = "dsi_ctrl";
+
+interrupt-parent = <>;
+interrupts = <4>;
+
+clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+ < DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ < DISP_CC_MDSS_PCLK0_CLK>,
+ < DISP_CC_MDSS_ESC0_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_AXI_CLK>;
+clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+assigned-clocks = < DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ < DISP_CC_MDSS_PCLK0_CLK_SRC>;
+assigned-clock-parents = <_dsi0_phy 0>, <_dsi0_phy 1>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SDM670_CX>;
+
+
[Freedreno] [PATCH 1/6] dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible
The SDM670 has DSI ports. Add the compatible for the controller. Signed-off-by: Richard Acayan --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index c6dbab65d5f7..887c7dcaf438 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -25,6 +25,7 @@ properties: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl + - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl -- 2.42.0
[Freedreno] [PATCH 0/6] SDM670 display subsystem support
This series adds support for the display subsystem on the Snapdragon 670. It is based on an earlier patch a few versions back, which had missing device tree bindings and device tree changes. There is a separate IOMMU patch which adds the MDSS compatible to a workaround. Richard Acayan (6): dt-bindings: display/msm: dsi-controller-main: add SDM670 compatible dt-bindings: display/msm: sdm845-dpu: Describe SDM670 dt-bindings: display: msm: Add SDM670 MDSS drm/msm: mdss: add support for SDM670 drm/msm/dpu: Add hw revision 4.1 (SDM670) arm64: dts: qcom: sdm670: add display subsystem .../display/msm/dsi-controller-main.yaml | 1 + .../display/msm/qcom,sdm670-mdss.yaml | 280 + .../bindings/display/msm/qcom,sdm845-dpu.yaml | 4 +- arch/arm64/boot/dts/qcom/sdm670.dtsi | 294 ++ .../msm/disp/dpu1/catalog/dpu_4_1_sdm670.h| 105 +++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 6 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 7 + 9 files changed, 698 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sdm670-mdss.yaml create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h -- 2.42.0
[Freedreno] [PATCH 2/2] dt-bindings: display: msm: Make "additionalProperties: true" explicit
Make it explicit that child nodes have additional properties and the child node schema is not complete. The complete schemas are applied separately based the compatible strings. Signed-off-by: Rob Herring --- .../bindings/display/msm/qcom,msm8998-mdss.yaml| 6 ++ .../bindings/display/msm/qcom,qcm2290-mdss.yaml| 6 ++ .../bindings/display/msm/qcom,sc7180-mdss.yaml | 8 .../bindings/display/msm/qcom,sc7280-mdss.yaml | 10 ++ .../bindings/display/msm/qcom,sc8280xp-mdss.yaml | 4 .../bindings/display/msm/qcom,sdm845-mdss.yaml | 8 .../bindings/display/msm/qcom,sm6115-mdss.yaml | 6 ++ .../bindings/display/msm/qcom,sm6125-mdss.yaml | 6 ++ .../bindings/display/msm/qcom,sm6350-mdss.yaml | 6 ++ .../bindings/display/msm/qcom,sm6375-mdss.yaml | 6 ++ .../bindings/display/msm/qcom,sm8150-mdss.yaml | 6 ++ .../bindings/display/msm/qcom,sm8250-mdss.yaml | 6 ++ .../bindings/display/msm/qcom,sm8350-mdss.yaml | 8 .../bindings/display/msm/qcom,sm8450-mdss.yaml | 8 .../bindings/display/msm/qcom,sm8550-mdss.yaml | 8 15 files changed, 102 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml index e320ab1de6de..2d9edab5a30d 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml @@ -38,12 +38,16 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,msm8998-dpu "^dsi@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: items: @@ -52,6 +56,8 @@ patternProperties: "^phy@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,dsi-phy-10nm-8998 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index 4184b84d4c21..5ad155612b6c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -44,18 +44,24 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,qcm2290-dpu "^dsi@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,dsi-ctrl-6g-qcm2290 "^phy@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,dsi-phy-14nm-2290 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml index 3b9c103e504a..3432a2407caa 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml @@ -44,18 +44,24 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,sc7180-dpu "^displayport-controller@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,sc7180-dp "^dsi@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: items: @@ -64,6 +70,8 @@ patternProperties: "^phy@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,dsi-phy-10nm diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index 43500dad66e7..bbb727831fca 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -44,18 +44,24 @@ properties: patternProperties: "^display-controller@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,sc7280-dpu "^displayport-controller@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: const: qcom,sc7280-dp "^dsi@[0-9a-f]+$": type: object +additionalProperties: true + properties: compatible: items: @@ -64,12 +70,16 @@ patternProperties: "^edp@[0-9a-f]+$": type: object +additionalProperties: true +
Re: [Freedreno] [PATCH] drm/msm/a6xx: don't set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA with coherent SMMU
On 2023-04-10 19:52, Dmitry Baryshkov wrote:
If the Adreno SMMU is dma-coherent, allocation will fail unless we
disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
coherent SMMUs (like we have on sm8350 platform).
Hmm, but is it right that it should fail in the first place? The fact is
that if the SMMU is coherent then walks *will* be outer-WBWA, so I
honestly can't see why the io-pgtable code is going out of its way to
explicitly reject a request to give them the same attribute it's already
giving then anyway :/
Even if the original intent was for the quirk to have an over-specific
implication of representing inner-NC as well, that hardly seems useful
if what we've ended up with in practice is a nonsensical-looking check
in one place and then a weird hacky bodge in another purely to work
around it.
Does anyone know a good reason why this is the way it is?
[ just came across this code in the tree while trying to figure out what
to do with iommu_set_pgtable_quirks()... ]
Thanks,
Robin.
Fixes: 54af0ceb7595 ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU
nodes")
Reported-by: David Heidelberg
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 2942d2548ce6..f74495dcbd96 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1793,7 +1793,8 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct
platform_device *pdev)
* This allows GPU to set the bus attributes required to use system
* cache on behalf of the iommu page table walker.
*/
- if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
+ if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) &&
+ !device_iommu_capable(>dev, IOMMU_CAP_CACHE_COHERENCY))
quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
return adreno_iommu_create_address_space(gpu, pdev, quirks);
Re: [Freedreno] [PATCH 1/9] drm/amd/pm: Annotate struct smu10_voltage_dependency_table with __counted_by
On Mon, Sep 25, 2023 at 08:30:30AM +0200, Christian König wrote:
> Am 22.09.23 um 19:41 schrieb Alex Deucher:
> > On Fri, Sep 22, 2023 at 1:32 PM Kees Cook wrote:
> > > Prepare for the coming implementation by GCC and Clang of the __counted_by
> > > attribute. Flexible array members annotated with __counted_by can have
> > > their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
> > > (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
> > > functions).
> > >
> > > As found with Coccinelle[1], add __counted_by for struct
> > > smu10_voltage_dependency_table.
> > >
> > > [1]
> > > https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
> > >
> > > Cc: Evan Quan
> > > Cc: Alex Deucher
> > > Cc: "Christian König"
> > > Cc: "Pan, Xinhui"
> > > Cc: David Airlie
> > > Cc: Daniel Vetter
> > > Cc: Xiaojian Du
> > > Cc: Huang Rui
> > > Cc: Kevin Wang
> > > Cc: amd-...@lists.freedesktop.org
> > > Cc: dri-de...@lists.freedesktop.org
> > > Signed-off-by: Kees Cook
> > Acked-by: Alex Deucher
>
> Mhm, I'm not sure if this is a good idea. That is a structure filled in by
> the firmware, isn't it?
>
> That would imply that we might need to byte swap count before it is
> checkable.
The script found this instance because of this:
static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
struct smu10_voltage_dependency_table **pptable,
uint32_t num_entry, const DpmClock_t
*pclk_dependency_table)
{
uint32_t i;
struct smu10_voltage_dependency_table *ptable;
ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL);
if (NULL == ptable)
return -ENOMEM;
ptable->count = num_entry;
So the implication is that it's native byte order... but you tell me! I
certainly don't want this annotation if it's going to break stuff. :)
--
Kees Cook
Re: [Freedreno] [PATCH 3/9] drm/i915/selftests: Annotate struct perf_series with __counted_by
On Mon, Sep 25, 2023 at 12:08:36PM +0200, Andrzej Hajda wrote: > > > On 22.09.2023 19:32, Kees Cook wrote: > > Prepare for the coming implementation by GCC and Clang of the __counted_by > > attribute. Flexible array members annotated with __counted_by can have > > their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS > > (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family > > functions). > > > > As found with Coccinelle[1], add __counted_by for struct perf_series. > > > > [1] > > https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci > > > > Cc: Jani Nikula > > Cc: Joonas Lahtinen > > Cc: Rodrigo Vivi > > Cc: Tvrtko Ursulin > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: Chris Wilson > > Cc: John Harrison > > Cc: Andi Shyti > > Cc: Matthew Brost > > Cc: intel-...@lists.freedesktop.org > > Cc: dri-de...@lists.freedesktop.org > > Signed-off-by: Kees Cook > > I am surprised this is the only finding in i915, I would expected more. I'm sure there are more, but it's likely my Coccinelle pattern didn't catch it. There are many many flexible arrays in drm. :) $ grep -nRH '\[\];$' drivers/gpu/drm include/uapi/drm | grep -v :extern | wc -l 122 If anyone has some patterns I can add to the Coccinelle script, I can take another pass at it. > Anyway: > > Reviewed-by: Andrzej Hajda Thank you! -Kees -- Kees Cook
Re: [Freedreno] [PATCH v3 6/7] drm/msm/dp: add pm_runtime_force_suspend()/resume()
On 9/22/2023 6:35 PM, Abhinav Kumar wrote: Hi Stephen On 9/22/2023 2:54 PM, Stephen Boyd wrote: Quoting Dmitry Baryshkov (2023-09-19 02:50:12) On Mon, 18 Sept 2023 at 20:48, Kuogee Hsieh wrote: On 9/15/2023 6:21 PM, Dmitry Baryshkov wrote: On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote: Add pm_runtime_force_suspend()/resume() to complete incorporating pm runtime framework into DP driver. Both dp_pm_prepare() and dp_pm_complete() are added to set hpd_state to correct state. After resume, DP driver will re training its main link after .hpd_enable() callback enabled HPD interrupts and bring up display accordingly. How will it re-train the main link? What is the code path for that? 1) for edp, dp_bridge_atomic_enable(), called from framework, to start link training and bring up display. And this path doesn't use .hpd_enable() which you have mentioned in the commit message. Please don't try to shorten the commit message. You see, I have had questions to several of them, which means that they were not verbose enough. 2) for external DP, HPD_PLUG_INT will be generated to start link training and bring up display. This should be hpd_notify, who starts link training, not some event. I think this driver should train the link during atomic_enable(), not hpd_notify() (or directly from the irq handler). The drm_bridge_funcs talk a bit about when the clocks and timing signals are supposed to be enabled. For example, struct drm_bridge_funcs::atomic_pre_enable() says the "display pipe (i.e. clocks and timing signals) feeding this bridge will not yet be running when this callback is called". And struct drm_bridge_funcs::atomic_enable() says "this callback must enable the display link feeding the next bridge in the chain if there is one." That looks to me like link training, i.e. the display link, should happen in the enable path and not hpd_notify. It looks like link training could fail, but when that happens I believe the driver should call drm_connector_set_link_status_property() with DRM_MODE_LINK_STATUS_BAD. The two callers of that which exist in the tree also call drm_kms_helper_hotplug_event() or drm_kms_helper_connector_hotplug_event() after updating the link so that userspace knows to try again. It would be nice if there was some drm_bridge_set_link_status_bad() API that bridge drivers could use to signal that the link status is bad and call the hotplug helper. Maybe it could also record some diagnostics about which bridge failed to setup the link and stop the atomic_enable() chain for that connector. Doing link training when we get hpd instead of atomic_enable() is a design choice we have been following for a while because for the case when link training fails in atomic_enable() and setting the link status property as you mentioned, the compositor needs to be able to handle that and also needs to try with a different resolution or take some other corrective action. We have seen many compositors not able to handle this complexity. So the design sends the hotplug to usermode only after link training succeeds. I do not think we should change this design unless prototyped with an existing compositor such as chrome or android at this point. Thanks Abhinav We did perform link training at atomic_enable() at eDP case since we can assume link training will always success without link rate or link lane being reduced. However for external DP case, link training can not be guarantee always success without link rate or lane being reduced as Abhinav mentioned. In addition, CTS (compliance test) it required to complete link training within 10ms after hpd asserted. I am not sure do link training at atomic_enable() can meet this timing requirement.
[Freedreno] [PATCH v5 10/10] drm/msm/a6xx: Poll for GBIF unhalt status in hw_init
Some GPUs - particularly A7xx ones - are really really stubborn and sometimes take a longer-than-expected time to finish unhalting GBIF. Note that this is not caused by the request a few lines above. Poll for the unhalt ack to make sure we're not trying to write bits to an essentially dead GPU that can't receive data on its end of the bus. Failing to do this will result in inexplicable GMU timeouts or worse. This is a rather ugly hack which introduces a whole lot of latency. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 2313620084b6..11cb410e0ac7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1629,6 +1629,10 @@ static int hw_init(struct msm_gpu *gpu) mb(); } + /* Some GPUs are stubborn and take their sweet time to unhalt GBIF! */ + if (adreno_is_a7xx(adreno_gpu) && a6xx_has_gbif(adreno_gpu)) + spin_until(!gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK)); + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); if (adreno_is_a619_holi(adreno_gpu)) -- 2.42.0
[Freedreno] [PATCH v5 09/10] drm/msm/a6xx: Add A740 support
A740 builds upon the A730 IP, shuffling some values and registers
around. More differences will appear when things like BCL are
implemented.
adreno_is_a740_family is added in preparation for more A7xx GPUs,
the logic checks will be valid resulting in smaller diffs.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 88 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 27 +
drivers/gpu/drm/msm/adreno/adreno_device.c | 17 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c| 6 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 19 ++-
6 files changed, 201 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index c1934d46c0d7..0555a0134fad 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -519,6 +519,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
struct adreno_gpu *adreno_gpu = _gpu->base;
struct platform_device *pdev = to_platform_device(gmu->dev);
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
+ u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0;
void __iomem *seqptr = NULL;
uint32_t pdc_address_offset;
bool pdc_in_aop = false;
@@ -552,21 +553,26 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
- gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x8000);
+ gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4,
+ adreno_is_a740_family(adreno_gpu) ? 0x8021 :
0x8000);
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
+ /* The second spin of A7xx GPUs messed with some register offsets.. */
+ if (adreno_is_a740_family(adreno_gpu))
+ seqmem0_drv0_reg = REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740;
+
/* Load RSC sequencer uCode for sleep and wakeup */
if (adreno_is_a650_family(adreno_gpu) ||
adreno_is_a7xx(adreno_gpu)) {
- gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
- gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1,
0xe1a1ebab);
- gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2,
0xa2e0a581);
- gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3,
0xecac82e2);
- gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4,
0x0020edad);
+ gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0);
+ gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab);
+ gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581);
+ gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2);
+ gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad);
} else {
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1,
0xa1e6a6e7);
@@ -764,8 +770,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned
int state)
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
struct adreno_gpu *adreno_gpu = _gpu->base;
u32 fence_range_lower, fence_range_upper;
+ u32 chipid, chipid_min = 0;
int ret;
- u32 chipid;
/* Vote veto for FAL10 */
if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) {
@@ -824,16 +830,37 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu,
unsigned int state)
*/
gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
- /*
-* Note that the GMU has a slightly different layout for
-* chip_id, for whatever reason, so a bit of massaging
-* is needed. The upper 16b are the same, but minor and
-* patchid are packed in four bits each with the lower
-* 8b unused:
-*/
- chipid = adreno_gpu->chip_id & 0x;
- chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
- chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
+ /* NOTE: A730 may also fall in this if-condition with a future GMU fw
update. */
+ if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) {
+ /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */
+
[Freedreno] [PATCH v5 08/10] drm/msm/a6xx: Add A730 support
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 61 ++
drivers/gpu/drm/msm/adreno/adreno_device.c | 13 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 7 +-
4 files changed, 203 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 61ce8d053355..522043883290 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -837,6 +837,63 @@ const struct adreno_reglist a690_hwcg[] = {
{}
};
+const struct adreno_reglist a730_hwcg[] = {
+ { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x0222 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0202 },
+ { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0xf3cf },
+ { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x0080 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x2220 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x0022 },
+ { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x0007 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x },
+ { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x0001 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x },
+ { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x0004 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x0002 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x0100 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x2220 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
+ { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x0055 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x0011 },
+ { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
+ { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422 },
+ { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x0222 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x0022 },
+ { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x0223 },
+ { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x0022 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x },
+ { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x },
+ { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
+ { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x },
+ { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x0200 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x },
+ { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x },
+ { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x },
+ { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x },
+ { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x0002 },
+ { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x5552 },
+ { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x0223 },
+ { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
+ { REG_A6XX_RBBM_ISDB_CNT, 0x0182 },
+ { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x },
+ { REG_A6XX_RBBM_SP_HYST_CNT, 0x },
+ { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x0222 },
+ { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x0111 },
+ { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x0555 },
+ {},
+};
+
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -1048,6 +1105,59 @@ static const u32 a690_protect[] = {
A6XX_PROTECT_NORDWR(0x11c00, 0x0), /*note: infiite range */
};
+static const u32 a730_protect[] = {
+ A6XX_PROTECT_RDONLY(0x0, 0x04ff),
+ A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
+ A6XX_PROTECT_NORDWR(0x0050e, 0x),
+ A6XX_PROTECT_NORDWR(0x00510, 0x),
+ A6XX_PROTECT_NORDWR(0x00534, 0x),
+ A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
+ A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
+ A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
+ A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
+ /* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
+ A6XX_PROTECT_RDONLY(0x008de, 0x0154),
+ A6XX_PROTECT_NORDWR(0x00900, 0x004d),
+ A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
+ A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
+ A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
+ A6XX_PROTECT_NORDWR(0x00e01, 0x),
+ A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
+ A6XX_PROTECT_RDONLY(0x03cc4,
[Freedreno] [PATCH v5 07/10] drm/msm/a6xx: Mostly implement A7xx gpu_state
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++-
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 61 -
2 files changed, 110 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 4e5d650578c6..18be2d3bde09 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -948,6 +948,18 @@ static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14;
}
+static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu)
+{
+ /*
+* The value at CP_ROQ_THRESHOLDS_2[20:31] is in 4dword units.
+* That register however is not directly accessible from APSS on A7xx.
+* Program the SQE_UCODE_DBG_ADDR with offset=0x70d3 and read the value.
+*/
+ gpu_write(gpu, REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 0x70d3);
+
+ return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20);
+}
+
/* Read a block of data from an indexed register pair */
static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
@@ -1019,8 +1031,40 @@ static void a6xx_get_indexed_registers(struct msm_gpu
*gpu,
/* Restore the size in the hardware */
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size);
+}
+
+static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
+ struct a6xx_gpu_state *a6xx_state)
+{
+ int i, indexed_count, mempool_count;
+
+ indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
+ mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);
- a6xx_state->nr_indexed_regs = count;
+ a6xx_state->indexed_regs = state_kcalloc(a6xx_state,
+ indexed_count + mempool_count,
+ sizeof(*a6xx_state->indexed_regs));
+ if (!a6xx_state->indexed_regs)
+ return;
+
+ a6xx_state->nr_indexed_regs = indexed_count + mempool_count;
+
+ /* First read the common regs */
+ for (i = 0; i < indexed_count; i++)
+ a6xx_get_indexed_regs(gpu, a6xx_state, _indexed_reglist[i],
+ _state->indexed_regs[i]);
+
+ gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2));
+ gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, 0, BIT(2));
+
+ /* Get the contents of the CP_BV mempool */
+ for (i = 0; i < mempool_count; i++)
+ a6xx_get_indexed_regs(gpu, a6xx_state,
a7xx_cp_bv_mempool_indexed,
+ _state->indexed_regs[indexed_count - 1 + i]);
+
+ gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0);
+ gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0);
+ return;
}
struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
@@ -1056,6 +1100,12 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu
*gpu)
return _state->base;
/* Get the banks of indexed registers */
+ if (adreno_is_a7xx(adreno_gpu)) {
+ a7xx_get_indexed_registers(gpu, a6xx_state);
+ /* Further codeflow is untested on A7xx. */
+ return _state->base;
+ }
+
a6xx_get_indexed_registers(gpu, a6xx_state);
/*
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
index e788ed72eb0d..8d7e6f26480a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
@@ -338,6 +338,28 @@ static const struct a6xx_registers a6xx_vbif_reglist =
static const struct a6xx_registers a6xx_gbif_reglist =
REGS(a6xx_gbif_registers, 0, 0);
+static const u32 a7xx_ahb_registers[] = {
+ /* RBBM_STATUS */
+ 0x210, 0x210,
+ /* RBBM_STATUS2-3 */
+ 0x212, 0x213,
+};
+
+static const u32 a7xx_gbif_registers[] = {
+ 0x3c00, 0x3c0b,
+ 0x3c40, 0x3c42,
+ 0x3c45, 0x3c47,
+ 0x3c49, 0x3c4a,
+ 0x3cc0, 0x3cd1,
+};
+
+static const struct a6xx_registers a7xx_ahb_reglist[] = {
+ REGS(a7xx_ahb_registers, 0, 0),
+};
+
+static const struct a6xx_registers a7xx_gbif_reglist =
+ REGS(a7xx_gbif_registers, 0, 0);
+
static const u32 a6xx_gmu_gx_registers[] = {
/* GMU GX */
0x, 0x, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
@@ -384,14 +406,17 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = {
};
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
+static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);
-static struct a6xx_indexed_registers {
+struct a6xx_indexed_registers {
[Freedreno] [PATCH v5 06/10] drm/msm/a6xx: Send ACD state to QMP at GMU resume
The QMP mailbox expects to be notified of the ACD (Adaptive Clock
Distribution) state. Get a handle to the mailbox at probe time and
poke it at GMU resume.
Since we don't fully support ACD yet, hardcode the message to "val: 0"
(state = disabled).
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 15ab912d9c45..c1934d46c0d7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -989,6 +989,14 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
gmu->hung = false;
+ /* Notify AOSS about the ACD state (unimplemented for now => disable
it) */
+ if (!IS_ERR(gmu->qmp)) {
+ ret = qmp_send(gmu->qmp, "{class: gpu, res: acd, val: %d}",
+ 0 /* Hardcode ACD to be disabled for now */);
+ if (ret)
+ dev_err(gmu->dev, "failed to send GPU ACD state\n");
+ }
+
/* Turn on the resources */
pm_runtime_get_sync(gmu->dev);
@@ -1741,6 +1749,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
device_node *node)
goto detach_cxpd;
}
+ gmu->qmp = qmp_get(gmu->dev);
+ if (IS_ERR(gmu->qmp) && adreno_is_a7xx(adreno_gpu))
+ return PTR_ERR(gmu->qmp);
+
init_completion(>pd_gate);
complete_all(>pd_gate);
gmu->pd_nb.notifier_call = cxpd_notifier_cb;
@@ -1764,6 +1776,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
device_node *node)
return 0;
+ if (!IS_ERR_OR_NULL(gmu->qmp))
+ qmp_put(gmu->qmp);
+
detach_cxpd:
dev_pm_domain_detach(gmu->cxpd, false);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 236f81a43caa..592b296aab22 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include "msm_drv.h"
#include "a6xx_hfi.h"
@@ -96,6 +97,8 @@ struct a6xx_gmu {
/* For power domain callback */
struct notifier_block pd_nb;
struct completion pd_gate;
+
+ struct qmp *qmp;
};
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
--
2.42.0
[Freedreno] [PATCH v5 05/10] drm/msm/a6xx: Add skeleton A7xx support
A7xx GPUs are - from kernel's POV anyway - basically another generation
of A6xx. They build upon the A650/A660_family advancements, skipping some
writes (presumably more values are preset correctly on reset), adding
some new ones and changing others.
One notable difference is the introduction of a second shadow, called BV.
To handle this with the current code, allocate it right after the current
RPTR shadow.
BV handling and .submit are mostly based on Jonathan Marek's work.
All A7xx GPUs are assumed to have a GMU.
A702 is not an A7xx-class GPU, it's a weird forked A610.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 96 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 451
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 10 +-
drivers/gpu/drm/msm/msm_ringbuffer.h| 2 +
5 files changed, 479 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 7923129363b0..15ab912d9c45 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
+#include
#include
#include
#include
@@ -202,9 +203,10 @@ int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
static int a6xx_gmu_start(struct a6xx_gmu *gmu)
{
+ struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
+ struct adreno_gpu *adreno_gpu = _gpu->base;
+ u32 mask, reset_val, val;
int ret;
- u32 val;
- u32 mask, reset_val;
val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
if (val <= 0x20010004) {
@@ -220,7 +222,11 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu)
/* Set the log wptr index
* note: downstream saves the value in poweroff and restores it here
*/
- gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
+ if (adreno_is_a7xx(adreno_gpu))
+ gmu_write(gmu, REG_A6XX_GMU_GENERAL_9, 0);
+ else
+ gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
+
gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
@@ -520,7 +526,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
if (IS_ERR(pdcptr))
goto err;
- if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
+ if (adreno_is_a650(adreno_gpu) ||
+ adreno_is_a660_family(adreno_gpu) ||
+ adreno_is_a7xx(adreno_gpu))
pdc_in_aop = true;
else if (adreno_is_a618(adreno_gpu) ||
adreno_is_a640_family(adreno_gpu))
pdc_address_offset = 0x30090;
@@ -552,7 +560,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
/* Load RSC sequencer uCode for sleep and wakeup */
- if (adreno_is_a650_family(adreno_gpu)) {
+ if (adreno_is_a650_family(adreno_gpu) ||
+ adreno_is_a7xx(adreno_gpu)) {
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1,
0xe1a1ebab);
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2,
0xa2e0a581);
@@ -637,11 +646,18 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
/* Set up the idle state for the GMU */
static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
{
+ struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
+ struct adreno_gpu *adreno_gpu = _gpu->base;
+
/* Disable GMU WB/RB buffer */
gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
+ /* A7xx knows better by default! */
+ if (adreno_is_a7xx(adreno_gpu))
+ return;
+
gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
switch (gmu->idle_level) {
@@ -698,7 +714,7 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
u32 itcm_base = 0x;
u32 dtcm_base = 0x0004;
- if (adreno_is_a650_family(adreno_gpu))
+ if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))
dtcm_base = 0x10004000;
if (gmu->legacy) {
@@ -747,14 +763,22 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu,
unsigned int state)
{
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
struct adreno_gpu *adreno_gpu = _gpu->base;
+ u32 fence_range_lower, fence_range_upper;
int ret;
u32 chipid;
- if (adreno_is_a650_family(adreno_gpu)) {
+ /* Vote veto for FAL10 */
+ if
[Freedreno] [PATCH v5 04/10] drm/msm/a6xx: Add missing regs for A7XX
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 8
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index 1c051535fd4a..863b5e3b0e67 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -1114,6 +1114,12 @@ enum a6xx_tex_type {
#define REG_A6XX_CP_MISC_CNTL 0x0840
#define REG_A6XX_CP_APRIV_CNTL 0x0844
+#define A6XX_CP_APRIV_CNTL_CDWRITE 0x0040
+#define A6XX_CP_APRIV_CNTL_CDREAD 0x0020
+#define A6XX_CP_APRIV_CNTL_RBRPWB 0x0008
+#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x0004
+#define A6XX_CP_APRIV_CNTL_RBFETCH 0x0002
+#define A6XX_CP_APRIV_CNTL_ICACHE 0x0001
#define REG_A6XX_CP_PREEMPT_THRESHOLD 0x08c0
@@ -1939,6 +1945,8 @@ static inline uint32_t
REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00
#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x0122
+#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x012f
+
#define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL
0x05ff
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x0600
@@ -8252,5 +8260,6 @@ static inline uint32_t
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x0002
+#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x0039
#endif /* A6XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
index fcd9eb53baf8..5b66efafc901 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
@@ -360,6 +360,12 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t
val)
#define REG_A6XX_GMU_GENERAL_7 0x51cc
+#define REG_A6XX_GMU_GENERAL_8 0x51cd
+
+#define REG_A6XX_GMU_GENERAL_9 0x51ce
+
+#define REG_A6XX_GMU_GENERAL_10
0x51cf
+
#define REG_A6XX_GMU_ISENSE_CTRL 0x515d
#define REG_A6XX_GPU_CS_ENABLE_REG 0x8920
@@ -471,6 +477,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t
val)
#define REG_A6XX_RSCC_SEQ_BUSY_DRV00x0101
+#define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x0154
+
#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x0180
#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x0346
--
2.42.0
[Freedreno] [PATCH v5 03/10] dt-bindings: display/msm/gpu: Allow A7xx SKUs
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends. They use GMU for all things DVFS, just like most A6xx GPUs. Reviewed-by: Krzysztof Kozlowski Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 56b9b247e8c2..b019db954793 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -23,7 +23,7 @@ properties: The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. items: - - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$' - const: qcom,adreno - description: | The driver is parsing the compat string for Imageon to @@ -203,7 +203,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: -- 2.42.0
[Freedreno] [PATCH v5 02/10] dt-bindings: display/msm/gmu: Allow passing QMP handle
When booting the GMU, the QMP mailbox should be pinged about some tunables (e.g. adaptive clock distribution state). To achieve that, a reference to it is necessary. Allow it and require it with A730. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 428eb138881a..4e1c25b42908 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -64,6 +64,10 @@ properties: iommus: maxItems: 1 + qcom,qmp: +$ref: /schemas/types.yaml#/definitions/phandle +description: Reference to the AOSS side-channel message RAM + operating-points-v2: true opp-table: @@ -251,6 +255,9 @@ allOf: - const: hub - const: demet + required: +- qcom,qmp + - if: properties: compatible: -- 2.42.0
[Freedreno] [PATCH v5 01/10] dt-bindings: display/msm/gmu: Add Adreno 7[34]0 GMU
The GMU on the A7xx series is pretty much the same as on the A6xx parts. It's now "smarter", needs a bit less register writes and controls more things (like inter-frame power collapse) mostly internally (instead of us having to write to G[PM]U_[CG]X registers from APPS) The only difference worth mentioning is the now-required DEMET clock, which is strictly required for things like asserting reset lines, not turning it on results in GMU not being fully functional (all OOB requests would fail and HFI would hang after the first submitted OOB). Describe the A730 and A740 GMU. Reviewed-by: Krzysztof Kozlowski Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gmu.yaml | 40 +- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index d65926b4f054..428eb138881a 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -21,7 +21,7 @@ properties: compatible: oneOf: - items: - - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu - const: qcom,adreno-gmu-wrapper @@ -213,6 +213,44 @@ allOf: - const: axi - const: memnoc + - if: + properties: +compatible: + contains: +enum: + - qcom,adreno-gmu-730.1 + - qcom,adreno-gmu-740.1 +then: + properties: +reg: + items: +- description: Core GMU registers +- description: Resource controller registers +- description: GMU PDC registers +reg-names: + items: +- const: gmu +- const: rscc +- const: gmu_pdc +clocks: + items: +- description: GPU AHB clock +- description: GMU clock +- description: GPU CX clock +- description: GPU AXI clock +- description: GPU MEMNOC clock +- description: GMU HUB clock +- description: GPUSS DEMET clock +clock-names: + items: +- const: ahb +- const: gmu +- const: cxo +- const: axi +- const: memnoc +- const: hub +- const: demet + - if: properties: compatible: -- 2.42.0
[Freedreno] [PATCH v5 00/10] A7xx support
This series attempts to introduce Adreno 700 support (with A730 and A740 found on SM8450 and SM8550 respectively), reusing much of the existing A6xx code. This submission largely lays the groundwork for expansion and more or less gives us feature parity (on the kernel side, that is) with existing A6xx parts. On top of introducing a very messy set of three (!) separate and obfuscated deivce identifiers for each 7xx part, this generation introduces very sophisticated hardware multi-threading and (on some SKUs) hardware ray-tracing (not supported yet). After this series, a long-overdue cleanup of drm/msm/adreno is planned in preparation for adding more features and removing some hardcoding. The last patch is a hack that may or may not be necessary depending on your board's humour.. eh.. :/ Developed atop (and hence depends on) [1] The corresponding devicetree patches are initially available at [2] and will be posted after this series gets merged. To test it, you'll also need firmware that you need to obtain from your board (there's none with a redistributable license, sorry..). Most likely it will be in one of these directories on your stock android installation: * /vendor/firmware * /vendor/firmware_mnt * /system ..but some vendors make it hard and you have to do some grepping ;) Requires [3] to work on the userspace side. You'll almost cerainly want to test it alongside Zink with a lot of debug flags (early impl), like: TU_DEBUG=sysmem,nolrz,flushall,noubwc MESA_LOADER_DRIVER_OVERRIDE=zink kmscube [1] https://lore.kernel.org/linux-arm-msm/20230517-topic-a7xx_prep-v4-0-b16f273a9...@linaro.org/ [2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt [3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217 Signed-off-by: Konrad Dybcio --- Changes in v5: - Rebase - Link to v4: https://lore.kernel.org/all/20230628-topic-a7xx_drmmsm-v4-0-8b3e40279...@linaro.org/ Changes in v4: - Add missing bitops.h in patch 5 for arm32 compilation (Dmitry) - Link to v3: https://lore.kernel.org/r/20230628-topic-a7xx_drmmsm-v3-0-4ee67ccba...@linaro.org Changes in v3: - Pick up tags - Drop "increase HFI timeout", will revisit another day - Use family identifiers in "add skeleton a7xx support" - Drop patches that Rob already picked up - Retest on A730, didn't explode - Link to v2: https://lore.kernel.org/linux-arm-msm/20230628-topic-a7xx_drmmsm-v2-0-1439e1b23...@linaro.org/#t Changes in v2: - Rebase on chipid changes - Reuse existing description for qcom,aoss in patch 2 - Pick up tags - Link to v1: https://lore.kernel.org/r/20230628-topic-a7xx_drmmsm-v1-0-a7f4496e0...@linaro.org --- Konrad Dybcio (10): dt-bindings: display/msm/gmu: Add Adreno 7[34]0 GMU dt-bindings: display/msm/gmu: Allow passing QMP handle dt-bindings: display/msm/gpu: Allow A7xx SKUs drm/msm/a6xx: Add missing regs for A7XX drm/msm/a6xx: Add skeleton A7xx support drm/msm/a6xx: Send ACD state to QMP at GMU resume drm/msm/a6xx: Mostly implement A7xx gpu_state drm/msm/a6xx: Add A730 support drm/msm/a6xx: Add A740 support drm/msm/a6xx: Poll for GBIF unhalt status in hw_init .../devicetree/bindings/display/msm/gmu.yaml | 47 +- .../devicetree/bindings/display/msm/gpu.yaml | 4 +- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 + drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 199 +-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 + drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 8 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 653 +++-- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c| 52 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h| 61 +- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 88 +++ drivers/gpu/drm/msm/adreno/adreno_device.c | 30 + drivers/gpu/drm/msm/adreno/adreno_gpu.c| 7 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h| 32 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 2 + 14 files changed, 1073 insertions(+), 122 deletions(-) --- base-commit: 8fff9184d1b5810dca5dd1a02726d4f844af88fc change-id: 20230628-topic-a7xx_drmmsm-123f30d76cf7 Best regards, -- Konrad Dybcio
Re: [Freedreno] [PATCH 1/9] drm/amd/pm: Annotate struct smu10_voltage_dependency_table with __counted_by
On Mon, Sep 25, 2023 at 10:07 AM Alex Deucher wrote:
>
> On Mon, Sep 25, 2023 at 2:30 AM Christian König
> wrote:
> >
> > Am 22.09.23 um 19:41 schrieb Alex Deucher:
> > > On Fri, Sep 22, 2023 at 1:32 PM Kees Cook wrote:
> > >> Prepare for the coming implementation by GCC and Clang of the
> > >> __counted_by
> > >> attribute. Flexible array members annotated with __counted_by can have
> > >> their accesses bounds-checked at run-time checking via
> > >> CONFIG_UBSAN_BOUNDS
> > >> (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
> > >> functions).
> > >>
> > >> As found with Coccinelle[1], add __counted_by for struct
> > >> smu10_voltage_dependency_table.
> > >>
> > >> [1]
> > >> https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
> > >>
> > >> Cc: Evan Quan
> > >> Cc: Alex Deucher
> > >> Cc: "Christian König"
> > >> Cc: "Pan, Xinhui"
> > >> Cc: David Airlie
> > >> Cc: Daniel Vetter
> > >> Cc: Xiaojian Du
> > >> Cc: Huang Rui
> > >> Cc: Kevin Wang
> > >> Cc: amd-...@lists.freedesktop.org
> > >> Cc: dri-de...@lists.freedesktop.org
> > >> Signed-off-by: Kees Cook
> > > Acked-by: Alex Deucher
> >
> > Mhm, I'm not sure if this is a good idea. That is a structure filled in
> > by the firmware, isn't it?
> >
> > That would imply that we might need to byte swap count before it is
> > checkable.
>
> True. Good point. Same for the other amdgpu patch.
Actually the other patch is fine. That's just a local structure.
Alex
>
> Alex
>
> >
> > Regards,
> > Christian.
> >
> > >
> > >> ---
> > >> drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h | 2 +-
> > >> 1 file changed, 1 insertion(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> > >> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> > >> index 808e0ecbe1f0..42adc2a3dcbc 100644
> > >> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> > >> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> > >> @@ -192,7 +192,7 @@ struct smu10_clock_voltage_dependency_record {
> > >>
> > >> struct smu10_voltage_dependency_table {
> > >> uint32_t count;
> > >> - struct smu10_clock_voltage_dependency_record entries[];
> > >> + struct smu10_clock_voltage_dependency_record entries[]
> > >> __counted_by(count);
> > >> };
> > >>
> > >> struct smu10_clock_voltage_information {
> > >> --
> > >> 2.34.1
> > >>
> >
Re: [Freedreno] [PATCH 1/9] drm/amd/pm: Annotate struct smu10_voltage_dependency_table with __counted_by
On Mon, Sep 25, 2023 at 2:30 AM Christian König
wrote:
>
> Am 22.09.23 um 19:41 schrieb Alex Deucher:
> > On Fri, Sep 22, 2023 at 1:32 PM Kees Cook wrote:
> >> Prepare for the coming implementation by GCC and Clang of the __counted_by
> >> attribute. Flexible array members annotated with __counted_by can have
> >> their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
> >> (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
> >> functions).
> >>
> >> As found with Coccinelle[1], add __counted_by for struct
> >> smu10_voltage_dependency_table.
> >>
> >> [1]
> >> https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
> >>
> >> Cc: Evan Quan
> >> Cc: Alex Deucher
> >> Cc: "Christian König"
> >> Cc: "Pan, Xinhui"
> >> Cc: David Airlie
> >> Cc: Daniel Vetter
> >> Cc: Xiaojian Du
> >> Cc: Huang Rui
> >> Cc: Kevin Wang
> >> Cc: amd-...@lists.freedesktop.org
> >> Cc: dri-de...@lists.freedesktop.org
> >> Signed-off-by: Kees Cook
> > Acked-by: Alex Deucher
>
> Mhm, I'm not sure if this is a good idea. That is a structure filled in
> by the firmware, isn't it?
>
> That would imply that we might need to byte swap count before it is
> checkable.
True. Good point. Same for the other amdgpu patch.
Alex
>
> Regards,
> Christian.
>
> >
> >> ---
> >> drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> >> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> >> index 808e0ecbe1f0..42adc2a3dcbc 100644
> >> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> >> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
> >> @@ -192,7 +192,7 @@ struct smu10_clock_voltage_dependency_record {
> >>
> >> struct smu10_voltage_dependency_table {
> >> uint32_t count;
> >> - struct smu10_clock_voltage_dependency_record entries[];
> >> + struct smu10_clock_voltage_dependency_record entries[]
> >> __counted_by(count);
> >> };
> >>
> >> struct smu10_clock_voltage_information {
> >> --
> >> 2.34.1
> >>
>
Re: [Freedreno] [PATCH 3/9] drm/i915/selftests: Annotate struct perf_series with __counted_by
Hi Kees, On Fri, Sep 22, 2023 at 10:32:08AM -0700, Kees Cook wrote: > Prepare for the coming implementation by GCC and Clang of the __counted_by > attribute. Flexible array members annotated with __counted_by can have > their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS > (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family > functions). > > As found with Coccinelle[1], add __counted_by for struct perf_series. > > [1] > https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci > > Cc: Jani Nikula > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: Tvrtko Ursulin > Cc: David Airlie > Cc: Daniel Vetter > Cc: Chris Wilson > Cc: John Harrison > Cc: Andi Shyti > Cc: Matthew Brost > Cc: intel-...@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Kees Cook Reviewed-by: Andi Shyti Thanks, Andi
Re: [Freedreno] [PATCH RFC v6 09/10] drm/msm/dpu: Use DRM solid_fill property
On Tue, 29 Aug 2023 at 03:06, Jessica Zhang wrote:
>
> Drop DPU_PLANE_COLOR_FILL_FLAG and check the DRM solid_fill property to
> determine if the plane is solid fill. In addition drop the DPU plane
> color_fill field as we can now use drm_plane_state.solid_fill instead,
> and pass in drm_plane_state.alpha to _dpu_plane_color_fill_pipe() to
> allow userspace to configure the alpha value for the solid fill color.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 37
> +--
> 1 file changed, 25 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 114c803ff99b..639ecbeeacf8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -42,7 +42,6 @@
> #define SHARP_SMOOTH_THR_DEFAULT 8
> #define SHARP_NOISE_THR_DEFAULT2
>
> -#define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
> #define DPU_ZPOS_MAX 255
>
> /*
> @@ -82,7 +81,6 @@ struct dpu_plane {
>
> enum dpu_sspp pipe;
>
> - uint32_t color_fill;
> bool is_error;
> bool is_rt_pipe;
> const struct dpu_mdss_cfg *catalog;
> @@ -606,19 +604,35 @@ static void _dpu_plane_color_fill_pipe(struct
> dpu_plane_state *pstate,
> _dpu_plane_setup_scaler(pipe, fmt, true, _cfg, pstate->rotation);
> }
>
> +static uint32_t _dpu_plane_get_abgr_fill_color(struct drm_plane_state *state)
> +{
> + struct drm_solid_fill solid_fill = state->solid_fill;
> +
> + uint32_t ret = 0;
> + uint8_t a = state->alpha & 0xFF;
> + uint8_t b = solid_fill.b >> 24;
> + uint8_t g = solid_fill.g >> 24;
> + uint8_t r = solid_fill.r >> 24;
> +
> + ret |= a << 24;
> + ret |= b << 16;
> + ret |= g << 8;
> + ret |= r;
> +
> + return ret;
> +}
> +
> /**
> * _dpu_plane_color_fill - enables color fill on plane
> * @pdpu: Pointer to DPU plane object
> * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
> * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:632: warning: Excess
function parameter 'alpha' description in '_dpu_plane_color_fill'
> */
> -static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
> - uint32_t color, uint32_t alpha)
> +static void _dpu_plane_color_fill(struct dpu_plane *pdpu, uint32_t color)
> {
> const struct dpu_format *fmt;
> const struct drm_plane *plane = >base;
> struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
> - u32 fill_color = (color & 0xFF) | ((alpha & 0xFF) << 24);
>
> DPU_DEBUG_PLANE(pdpu, "\n");
>
> @@ -633,11 +647,11 @@ static void _dpu_plane_color_fill(struct dpu_plane
> *pdpu,
>
> /* update sspp */
> _dpu_plane_color_fill_pipe(pstate, >pipe,
> >pipe_cfg.dst_rect,
> - fill_color, fmt);
> + color, fmt);
>
> if (pstate->r_pipe.sspp)
> _dpu_plane_color_fill_pipe(pstate, >r_pipe,
> >r_pipe_cfg.dst_rect,
> - fill_color, fmt);
> + color, fmt);
> }
>
> static int dpu_plane_prepare_fb(struct drm_plane *plane,
> @@ -976,10 +990,9 @@ void dpu_plane_flush(struct drm_plane *plane)
> */
> if (pdpu->is_error)
> /* force white frame with 100% alpha pipe output on error */
> - _dpu_plane_color_fill(pdpu, 0xFF, 0xFF);
> - else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
> - /* force 100% alpha */
> - _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
> + _dpu_plane_color_fill(pdpu, 0x);
> + else if (drm_plane_solid_fill_enabled(plane->state))
> + _dpu_plane_color_fill(pdpu,
> _dpu_plane_get_abgr_fill_color(plane->state));
> else {
> dpu_plane_flush_csc(pdpu, >pipe);
> dpu_plane_flush_csc(pdpu, >r_pipe);
> @@ -1024,7 +1037,7 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane
> *plane,
> }
>
> /* override for color fill */
> - if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
> + if (drm_plane_solid_fill_enabled(plane->state)) {
> _dpu_plane_set_qos_ctrl(plane, pipe, false);
>
> /* skip remaining processing on color fill */
>
> --
> 2.42.0
>
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH 3/9] drm/i915/selftests: Annotate struct perf_series with __counted_by
On 22.09.2023 19:32, Kees Cook wrote:
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).
As found with Coccinelle[1], add __counted_by for struct perf_series.
[1]
https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: David Airlie
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: John Harrison
Cc: Andi Shyti
Cc: Matthew Brost
Cc: intel-...@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Kees Cook
I am surprised this is the only finding in i915, I would expected more.
Anyway:
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index a9b79888c193..acae30a04a94 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1924,7 +1924,7 @@ struct perf_stats {
struct perf_series {
struct drm_i915_private *i915;
unsigned int nengines;
- struct intel_context *ce[];
+ struct intel_context *ce[] __counted_by(nengines);
};
static int cmp_u32(const void *A, const void *B)
Re: [Freedreno] [PATCH v3 4/7] drm/msm/dp: incorporate pm_runtime framework into DP driver
On Thu, 21 Sept 2023 at 01:46, Kuogee Hsieh wrote:
>
>
> On 9/15/2023 6:07 PM, Dmitry Baryshkov wrote:
> > On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
> >> Currently DP driver is executed independent of PM runtime framework.
> >> This lead DP driver incompatible with others. Incorporating pm runtime
> > Why is it incompatible? Which others are mentioned here?
> >
> >> framework into DP driver so that both power and clocks to enable/disable
> >> host controller fits with PM runtime mechanism. Once pm runtime framework
> >> is incorporated into DP driver, wake up device from power up path is not
> >> necessary. Hence remove it. Both EV_POWER_PM_GET and EV_POWER_PM_PUT events
> >> are introduced to perform pm runtime control for the HPD GPIO routing to a
> >> display-connector case.
> >>
> >> Changes in v3:
> >> -- incorporate removing pm_runtime_xx() from dp_pwer.c to this patch
> >> -- use pm_runtime_resume_and_get() instead of pm_runtime_get()
> >> -- error checking pm_runtime_resume_and_get() return value
> >> -- add EV_POWER_PM_GET and PM_EV_POWER_PUT to handle HPD_GPIO case
> > Previous changelog?
> >
> >> Signed-off-by: Kuogee Hsieh
> >> ---
> >> drivers/gpu/drm/msm/dp/dp_aux.c | 5 ++
> >> drivers/gpu/drm/msm/dp/dp_display.c | 114
> >> +++-
> >> drivers/gpu/drm/msm/dp/dp_power.c | 9 ---
> >> 3 files changed, 90 insertions(+), 38 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c
> >> b/drivers/gpu/drm/msm/dp/dp_aux.c
> >> index 8e3b677..8fa93c5 100644
> >> --- a/drivers/gpu/drm/msm/dp/dp_aux.c
> >> +++ b/drivers/gpu/drm/msm/dp/dp_aux.c
> >> @@ -291,6 +291,9 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux
> >> *dp_aux,
> >> return -EINVAL;
> >> }
> >>
> >> + if (pm_runtime_resume_and_get(dp_aux->dev))
> >> + return -EINVAL;
> > Please propagate error values instead of reinventing them.
> >
> >> +
> >> mutex_lock(>mutex);
> >> if (!aux->initted) {
> >> ret = -EIO;
> >> @@ -364,6 +367,8 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux
> >> *dp_aux,
> >>
> >> exit:
> >> mutex_unlock(>mutex);
> >> + pm_runtime_mark_last_busy(dp_aux->dev);
> >> + pm_runtime_put_autosuspend(dp_aux->dev);
> > What is the reason for using autosuspend? Such design decisions should
> > be described in the commit message.
> >
> >> return ret;
> >> }
> >> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> >> b/drivers/gpu/drm/msm/dp/dp_display.c
> >> index 59f9d85..e7af7f7 100644
> >> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> >> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> >> @@ -60,6 +60,8 @@ enum {
> >> EV_IRQ_HPD_INT,
> >> EV_HPD_UNPLUG_INT,
> >> EV_USER_NOTIFICATION,
> >> + EV_POWER_PM_GET,
> >> + EV_POWER_PM_PUT,
> >> };
> >>
> >> #define EVENT_TIMEOUT (HZ/10) /* 100ms */
> >> @@ -276,13 +278,6 @@ static int dp_display_bind(struct device *dev, struct
> >> device *master,
> >> dp->dp_display.drm_dev = drm;
> >> priv->dp[dp->id] = >dp_display;
> >>
> >> - rc = dp->parser->parse(dp->parser);
> >> - if (rc) {
> >> - DRM_ERROR("device tree parsing failed\n");
> >> - goto end;
> >> - }
> >> -
> >> -
> >> dp->drm_dev = drm;
> >> dp->aux->drm_dev = drm;
> >> rc = dp_aux_register(dp->aux);
> >> @@ -291,12 +286,6 @@ static int dp_display_bind(struct device *dev, struct
> >> device *master,
> >> goto end;
> >> }
> >>
> >> - rc = dp_power_client_init(dp->power);
> >> - if (rc) {
> >> - DRM_ERROR("Power client create failed\n");
> >> - goto end;
> >> - }
> >> -
> >> rc = dp_register_audio_driver(dev, dp->audio);
> >> if (rc) {
> >> DRM_ERROR("Audio registration Dp failed\n");
> >> @@ -320,10 +309,6 @@ static void dp_display_unbind(struct device *dev,
> >> struct device *master,
> >> struct dp_display_private *dp = dev_get_dp_display_private(dev);
> >> struct msm_drm_private *priv = dev_get_drvdata(master);
> >>
> >> - /* disable all HPD interrupts */
> >> - if (dp->core_initialized)
> >> - dp_catalog_hpd_config_intr(dp->catalog,
> >> DP_DP_HPD_INT_MASK, false);
> >> -
> >> kthread_stop(dp->ev_tsk);
> >>
> >> of_dp_aux_depopulate_bus(dp->aux);
> >> @@ -467,6 +452,18 @@ static void dp_display_host_deinit(struct
> >> dp_display_private *dp)
> >> dp->core_initialized = false;
> >> }
> >>
> >> +static void dp_display_pm_get(struct dp_display_private *dp)
> >> +{
> >> + if (pm_runtime_resume_and_get(>pdev->dev))
> >> + DRM_ERROR("failed to start power\n");
> >> +}
> > Huge NAK here. This means that the error is completely ignored (other
> > than being dumped to the log). This is a short path to Sync error and
Re: [Freedreno] [PATCH v6 2/6] drm/panfrost: Add fdinfo support GPU load metrics
On 22/09/2023 16:23, Steven Price wrote:
On 22/09/2023 14:53, Tvrtko Ursulin wrote:
On 22/09/2023 11:57, Adrián Larumbe wrote:
On 20.09.2023 16:40, Tvrtko Ursulin wrote:
On 20/09/2023 00:34, Adrián Larumbe wrote:
The drm-stats fdinfo tags made available to user space are drm-engine,
drm-cycles, drm-max-freq and drm-curfreq, one per job slot.
This deviates from standard practice in other DRM drivers, where a
single
set of key:value pairs is provided for the whole render engine.
However,
Panfrost has separate queues for fragment and vertex/tiler jobs, so a
decision was made to calculate bus cycles and workload times
separately.
Maximum operating frequency is calculated at devfreq initialisation
time.
Current frequency is made available to user space because nvtop uses it
when performing engine usage calculations.
It is important to bear in mind that both GPU cycle and kernel time
numbers
provided are at best rough estimations, and always reported in
excess from
the actual figure because of two reasons:
- Excess time because of the delay between the end of a job
processing,
the subsequent job IRQ and the actual time of the sample.
- Time spent in the engine queue waiting for the GPU to pick up
the next
job.
To avoid race conditions during enablement/disabling, a reference
counting
mechanism was introduced, and a job flag that tells us whether a
given job
increased the refcount. This is necessary, because user space can
toggle
cycle counting through a debugfs file, and a given job might have
been in
flight by the time cycle counting was disabled.
The main goal of the debugfs cycle counter knob is letting tools
like nvtop
or IGT's gputop switch it at any time, to avoid power waste in case no
engine usage measuring is necessary.
Signed-off-by: Adrián Larumbe
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
---
drivers/gpu/drm/panfrost/Makefile | 2 +
drivers/gpu/drm/panfrost/panfrost_debugfs.c | 20
drivers/gpu/drm/panfrost/panfrost_debugfs.h | 13 +
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 8 +++
drivers/gpu/drm/panfrost/panfrost_devfreq.h | 3 ++
drivers/gpu/drm/panfrost/panfrost_device.c | 2 +
drivers/gpu/drm/panfrost/panfrost_device.h | 13 +
drivers/gpu/drm/panfrost/panfrost_drv.c | 57
-
drivers/gpu/drm/panfrost/panfrost_gpu.c | 41 +++
drivers/gpu/drm/panfrost/panfrost_gpu.h | 4 ++
drivers/gpu/drm/panfrost/panfrost_job.c | 24 +
drivers/gpu/drm/panfrost/panfrost_job.h | 5 ++
12 files changed, 191 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/panfrost/panfrost_debugfs.c
create mode 100644 drivers/gpu/drm/panfrost/panfrost_debugfs.h
diff --git a/drivers/gpu/drm/panfrost/Makefile
b/drivers/gpu/drm/panfrost/Makefile
index 7da2b3f02ed9..2c01c1e7523e 100644
--- a/drivers/gpu/drm/panfrost/Makefile
+++ b/drivers/gpu/drm/panfrost/Makefile
@@ -12,4 +12,6 @@ panfrost-y := \
panfrost_perfcnt.o \
panfrost_dump.o
+panfrost-$(CONFIG_DEBUG_FS) += panfrost_debugfs.o
+
obj-$(CONFIG_DRM_PANFROST) += panfrost.o
diff --git a/drivers/gpu/drm/panfrost/panfrost_debugfs.c
b/drivers/gpu/drm/panfrost/panfrost_debugfs.c
new file mode 100644
index ..cc14eccba206
--- /dev/null
+++ b/drivers/gpu/drm/panfrost/panfrost_debugfs.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023 Collabora ltd. */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "panfrost_device.h"
+#include "panfrost_gpu.h"
+#include "panfrost_debugfs.h"
+
+void panfrost_debugfs_init(struct drm_minor *minor)
+{
+ struct drm_device *dev = minor->dev;
+ struct panfrost_device *pfdev =
platform_get_drvdata(to_platform_device(dev->dev));
+
+ debugfs_create_atomic_t("profile", 0600, minor->debugfs_root,
>profile_mode);
+}
diff --git a/drivers/gpu/drm/panfrost/panfrost_debugfs.h
b/drivers/gpu/drm/panfrost/panfrost_debugfs.h
new file mode 100644
index ..db1c158bcf2f
--- /dev/null
+++ b/drivers/gpu/drm/panfrost/panfrost_debugfs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2023 Collabora ltd.
+ */
+
+#ifndef PANFROST_DEBUGFS_H
+#define PANFROST_DEBUGFS_H
+
+#ifdef CONFIG_DEBUG_FS
+void panfrost_debugfs_init(struct drm_minor *minor);
+#endif
+
+#endif /* PANFROST_DEBUGFS_H */
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 58dfb15a8757..28caffc689e2 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -58,6 +58,7 @@ static int panfrost_devfreq_get_dev_status(struct
device *dev,
spin_lock_irqsave(>lock, irqflags);
panfrost_devfreq_update_utilization(pfdevfreq);
+ pfdevfreq->current_frequency = status->current_frequency;
status->total_time = ktime_to_ns(ktime_add(pfdevfreq->busy_time,
Re: [Freedreno] [PATCH 1/9] drm/amd/pm: Annotate struct smu10_voltage_dependency_table with __counted_by
Am 22.09.23 um 19:41 schrieb Alex Deucher:
On Fri, Sep 22, 2023 at 1:32 PM Kees Cook wrote:
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).
As found with Coccinelle[1], add __counted_by for struct
smu10_voltage_dependency_table.
[1]
https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci
Cc: Evan Quan
Cc: Alex Deucher
Cc: "Christian König"
Cc: "Pan, Xinhui"
Cc: David Airlie
Cc: Daniel Vetter
Cc: Xiaojian Du
Cc: Huang Rui
Cc: Kevin Wang
Cc: amd-...@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Kees Cook
Acked-by: Alex Deucher
Mhm, I'm not sure if this is a good idea. That is a structure filled in
by the firmware, isn't it?
That would imply that we might need to byte swap count before it is
checkable.
Regards,
Christian.
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
index 808e0ecbe1f0..42adc2a3dcbc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h
@@ -192,7 +192,7 @@ struct smu10_clock_voltage_dependency_record {
struct smu10_voltage_dependency_table {
uint32_t count;
- struct smu10_clock_voltage_dependency_record entries[];
+ struct smu10_clock_voltage_dependency_record entries[]
__counted_by(count);
};
struct smu10_clock_voltage_information {
--
2.34.1
