Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
wrote:
>
> On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> >
> > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > initialize cx_mem. Copy this from downstream (minus BCL which we
> > currently don't support). On a750, this includes a new "fuse" register
> > which can be used by qcom_scm to fuse off certain features like
> > raytracing in software. The fuse is default off, and is initialized by
> > calling the method. Afterwards we have to read it to find out which
> > features were enabled.
> >
> > Signed-off-by: Connor Abbott
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > 2 files changed, 90 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > index cf0b1de1c071..fb2722574ae5 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > @@ -10,6 +10,7 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
> >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> >
> > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > *gpu)
> > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > }
> >
> > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > +{
> > + u32 status;
> > +
> > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > +
> > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > status=%8.8x\n", status);
> > +
> > + /* Ignore FASTBLEND violations, because the HW will silently fall
> > back
> > +* to legacy blending.
> > +*/
> > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > + del_timer(&gpu->hangcheck_timer);
> > +
> > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > + }
> > +}
> > +
> > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > {
> > struct msm_drm_private *priv = gpu->dev->dev_private;
> > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds
> > access\n");
> >
> > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > + a7xx_sw_fuse_violation_irq(gpu);
> > +
> > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > msm_gpu_retire(gpu);
> >
> > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > platform_device *pdev,
> > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > }
> >
> > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > +{
> > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > + struct msm_gpu *gpu = &adreno_gpu->base;
> > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > + u32 fuse_val;
> > + int ret;
> > +
> > + if (adreno_is_a740(adreno_gpu)) {
> > + /* Raytracing is always enabled on a740 */
> > + adreno_gpu->has_ray_tracing = true;
> > + }
> > +
> > + if (!qcom_scm_is_available()) {
> > + /* Assume that if qcom scm isn't available, that whatever
> > +* replacement allows writing the fuse register ourselves.
> > +* Users of alternative firmware need to make sure this
> > +* register is writeable or indicate that it's not somehow.
> > +* Print a warning because if you mess this up you're about
> > to
> > +* crash horribly.
> > +*/
> > + if (adreno_is_a750(adreno_gpu)) {
> > + dev_warn_once(gpu->dev->dev,
> > + "SCM is not available, poking fuse
> > register\n");
> > + a6xx_llc_write(a6xx_gpu,
> > REG_A7XX_CX_MISC_SW_FUSE_VALUE,
> > + A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > + A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
> > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
> > + adreno_gpu->has_ray_tr
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Thu, Apr 25, 2024 at 4:02 PM Dmitry Baryshkov
wrote:
>
> On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> >
> > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > initialize cx_mem. Copy this from downstream (minus BCL which we
> > currently don't support). On a750, this includes a new "fuse" register
> > which can be used by qcom_scm to fuse off certain features like
> > raytracing in software. The fuse is default off, and is initialized by
> > calling the method. Afterwards we have to read it to find out which
> > features were enabled.
> >
> > Signed-off-by: Connor Abbott
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > 2 files changed, 90 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > index cf0b1de1c071..fb2722574ae5 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > @@ -10,6 +10,7 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
> >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> >
> > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > *gpu)
> > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > }
> >
> > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > +{
> > + u32 status;
> > +
> > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > +
> > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > status=%8.8x\n", status);
> > +
> > + /* Ignore FASTBLEND violations, because the HW will silently fall
> > back
> > +* to legacy blending.
> > +*/
> > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > + del_timer(&gpu->hangcheck_timer);
> > +
> > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > + }
> > +}
> > +
> > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > {
> > struct msm_drm_private *priv = gpu->dev->dev_private;
> > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds
> > access\n");
> >
> > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > + a7xx_sw_fuse_violation_irq(gpu);
> > +
> > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > msm_gpu_retire(gpu);
> >
> > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > platform_device *pdev,
> > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > }
> >
> > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > +{
> > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > + struct msm_gpu *gpu = &adreno_gpu->base;
> > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > + u32 fuse_val;
> > + int ret;
> > +
> > + if (adreno_is_a740(adreno_gpu)) {
> > + /* Raytracing is always enabled on a740 */
> > + adreno_gpu->has_ray_tracing = true;
> > + }
> > +
> > + if (!qcom_scm_is_available()) {
> > + /* Assume that if qcom scm isn't available, that whatever
> > +* replacement allows writing the fuse register ourselves.
> > +* Users of alternative firmware need to make sure this
> > +* register is writeable or indicate that it's not somehow.
> > +* Print a warning because if you mess this up you're about
> > to
> > +* crash horribly.
> > +*/
> > + if (adreno_is_a750(adreno_gpu)) {
> > + dev_warn_once(gpu->dev->dev,
> > + "SCM is not available, poking fuse
> > register\n");
> > + a6xx_llc_write(a6xx_gpu,
> > REG_A7XX_CX_MISC_SW_FUSE_VALUE,
> > + A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > + A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
> > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
> > + adreno_gpu->has_ray_tra
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, Apr 26, 2024 at 1:35 PM Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> wrote:
> >
> > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > >
> > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > currently don't support). On a750, this includes a new "fuse" register
> > > which can be used by qcom_scm to fuse off certain features like
> > > raytracing in software. The fuse is default off, and is initialized by
> > > calling the method. Afterwards we have to read it to find out which
> > > features were enabled.
> > >
> > > Signed-off-by: Connor Abbott
> > > ---
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index cf0b1de1c071..fb2722574ae5 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -10,6 +10,7 @@
> > >
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > >
> > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
> > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > >
> > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > > *gpu)
> > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > }
> > >
> > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > +{
> > > + u32 status;
> > > +
> > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > +
> > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > status=%8.8x\n", status);
> > > +
> > > + /* Ignore FASTBLEND violations, because the HW will silently fall
> > > back
> > > +* to legacy blending.
> > > +*/
> > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > + del_timer(&gpu->hangcheck_timer);
> > > +
> > > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > + }
> > > +}
> > > +
> > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > {
> > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of
> > > bounds access\n");
> > >
> > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > + a7xx_sw_fuse_violation_irq(gpu);
> > > +
> > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > msm_gpu_retire(gpu);
> > >
> > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > platform_device *pdev,
> > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > }
> > >
> > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > +{
> > > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > > + struct msm_gpu *gpu = &adreno_gpu->base;
> > > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > > + u32 fuse_val;
> > > + int ret;
> > > +
> > > + if (adreno_is_a740(adreno_gpu)) {
> > > + /* Raytracing is always enabled on a740 */
> > > + adreno_gpu->has_ray_tracing = true;
> > > + }
> > > +
> > > + if (!qcom_scm_is_available()) {
> > > + /* Assume that if qcom scm isn't available, that whatever
> > > +* replacement allows writing the fuse register ourselves.
> > > +* Users of alternative firmware need to make sure this
> > > +* register is writeable or indicate that it's not
> > > somehow.
> > > +* Print a warning because if you mess this up you're
> > > about to
> > > +* crash horribly.
> > > +*/
> > > + if (adreno_is_a750(adreno_gpu)) {
> > > + dev_warn_once(gpu->dev->dev,
> > > + "SCM is not available, poking fuse
> > > register\n");
> > > + a6xx_llc_write(a6xx_gpu,
> > > REG_A7XX
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 15:46, Rob Clark wrote:
>
> On Thu, Apr 25, 2024 at 4:02 PM Dmitry Baryshkov
> wrote:
> >
> > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > >
> > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > currently don't support). On a750, this includes a new "fuse" register
> > > which can be used by qcom_scm to fuse off certain features like
> > > raytracing in software. The fuse is default off, and is initialized by
> > > calling the method. Afterwards we have to read it to find out which
> > > features were enabled.
> > >
> > > Signed-off-by: Connor Abbott
> > > ---
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > >
[...]
> > > + gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
> > > +
> > > + ret = qcom_scm_gpu_init_regs(gpu_req);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + /* On a750 raytracing may be disabled by the firmware, find out
> > > whether
> > > +* that's the case. The scm call above sets the fuse register.
> > > +*/
> > > + if (adreno_is_a750(adreno_gpu)) {
> > > + fuse_val = a6xx_llc_read(a6xx_gpu,
> > > REG_A7XX_CX_MISC_SW_FUSE_VALUE);
> >
> > This register isn't accessible with the current sm8650.dtsi. Since DT
> > and driver are going through different trees, please add safety guards
> > here, so that the driver doesn't crash if used with older dtsi
> > (not to mention that dts is considered to be an ABI and newer kernels
> > are supposed not to break with older DT files).
>
> I'd be happy if older kernels consistently worked with newer dtb, the
> other direction is too much to ask.
Well, we guarantee that newer kernels work with older dts.
> If necessary we can ask for ack
> to land the dts fix thru msm-next somehow, but since the gpu is newly
> enabled device landing in the same merge window I think that is not
> necessary.
This might work too.
--
With best wishes
Dmitry
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> wrote:
> >
> > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > >
> > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > currently don't support). On a750, this includes a new "fuse" register
> > > which can be used by qcom_scm to fuse off certain features like
> > > raytracing in software. The fuse is default off, and is initialized by
> > > calling the method. Afterwards we have to read it to find out which
> > > features were enabled.
> > >
> > > Signed-off-by: Connor Abbott
> > > ---
> > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > index cf0b1de1c071..fb2722574ae5 100644
> > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > @@ -10,6 +10,7 @@
> > >
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > >
> > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
> > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > >
> > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > > *gpu)
> > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > }
> > >
> > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > +{
> > > + u32 status;
> > > +
> > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > +
> > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > status=%8.8x\n", status);
> > > +
> > > + /* Ignore FASTBLEND violations, because the HW will silently fall
> > > back
> > > +* to legacy blending.
> > > +*/
> > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > + del_timer(&gpu->hangcheck_timer);
> > > +
> > > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > + }
> > > +}
> > > +
> > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > {
> > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of
> > > bounds access\n");
> > >
> > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > + a7xx_sw_fuse_violation_irq(gpu);
> > > +
> > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > msm_gpu_retire(gpu);
> > >
> > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > platform_device *pdev,
> > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > }
> > >
> > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > +{
> > > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > > + struct msm_gpu *gpu = &adreno_gpu->base;
> > > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > > + u32 fuse_val;
> > > + int ret;
> > > +
> > > + if (adreno_is_a740(adreno_gpu)) {
> > > + /* Raytracing is always enabled on a740 */
> > > + adreno_gpu->has_ray_tracing = true;
> > > + }
> > > +
> > > + if (!qcom_scm_is_available()) {
> > > + /* Assume that if qcom scm isn't available, that whatever
> > > +* replacement allows writing the fuse register ourselves.
> > > +* Users of alternative firmware need to make sure this
> > > +* register is writeable or indicate that it's not
> > > somehow.
> > > +* Print a warning because if you mess this up you're
> > > about to
> > > +* crash horribly.
> > > +*/
> > > + if (adreno_is_a750(adreno_gpu)) {
> > > + dev_warn_once(gpu->dev->dev,
> > > + "SCM is not available, poking fuse
> > > register\n");
> > > + a6xx_llc_write(a6xx_gpu,
> > > REG_A7XX_C
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 15:54, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 1:35 PM Connor Abbott wrote:
> >
> > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > > >
> > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > currently don't support). On a750, this includes a new "fuse" register
> > > > which can be used by qcom_scm to fuse off certain features like
> > > > raytracing in software. The fuse is default off, and is initialized by
> > > > calling the method. Afterwards we have to read it to find out which
> > > > features were enabled.
> > > >
> > > > Signed-off-by: Connor Abbott
> > > > ---
> > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > @@ -10,6 +10,7 @@
> > > >
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu
> > > > *gpu)
> > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > >
> > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > > > *gpu)
> > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > }
> > > >
> > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > +{
> > > > + u32 status;
> > > > +
> > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > +
> > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > > status=%8.8x\n", status);
> > > > +
> > > > + /* Ignore FASTBLEND violations, because the HW will silently
> > > > fall back
> > > > +* to legacy blending.
> > > > +*/
> > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > + del_timer(&gpu->hangcheck_timer);
> > > > +
> > > > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > + }
> > > > +}
> > > > +
> > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > {
> > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of
> > > > bounds access\n");
> > > >
> > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > +
> > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > msm_gpu_retire(gpu);
> > > >
> > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > platform_device *pdev,
> > > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > > }
> > > >
> > > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > > +{
> > > > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > > > + struct msm_gpu *gpu = &adreno_gpu->base;
> > > > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > > > + u32 fuse_val;
> > > > + int ret;
> > > > +
> > > > + if (adreno_is_a740(adreno_gpu)) {
> > > > + /* Raytracing is always enabled on a740 */
> > > > + adreno_gpu->has_ray_tracing = true;
> > > > + }
> > > > +
> > > > + if (!qcom_scm_is_available()) {
> > > > + /* Assume that if qcom scm isn't available, that
> > > > whatever
> > > > +* replacement allows writing the fuse register
> > > > ourselves.
> > > > +* Users of alternative firmware need to make sure this
> > > > +* register is writeable or indicate that it's not
> > > > somehow.
> > > > +* Print a warning because if you mess this up you're
> > > > about to
> > > > +* crash horribly.
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
wrote:
>
> On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
> >
> > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > wrote:
> > >
> > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > > >
> > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
> > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > currently don't support). On a750, this includes a new "fuse" register
> > > > which can be used by qcom_scm to fuse off certain features like
> > > > raytracing in software. The fuse is default off, and is initialized by
> > > > calling the method. Afterwards we have to read it to find out which
> > > > features were enabled.
> > > >
> > > > Signed-off-by: Connor Abbott
> > > > ---
> > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 -
> > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > @@ -10,6 +10,7 @@
> > > >
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu
> > > > *gpu)
> > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > >
> > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu
> > > > *gpu)
> > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > }
> > > >
> > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > +{
> > > > + u32 status;
> > > > +
> > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > +
> > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > > status=%8.8x\n", status);
> > > > +
> > > > + /* Ignore FASTBLEND violations, because the HW will silently
> > > > fall back
> > > > +* to legacy blending.
> > > > +*/
> > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > + del_timer(&gpu->hangcheck_timer);
> > > > +
> > > > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > + }
> > > > +}
> > > > +
> > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > {
> > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of
> > > > bounds access\n");
> > > >
> > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > +
> > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > msm_gpu_retire(gpu);
> > > >
> > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > platform_device *pdev,
> > > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > > }
> > > >
> > > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > > +{
> > > > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > > > + struct msm_gpu *gpu = &adreno_gpu->base;
> > > > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > > > + u32 fuse_val;
> > > > + int ret;
> > > > +
> > > > + if (adreno_is_a740(adreno_gpu)) {
> > > > + /* Raytracing is always enabled on a740 */
> > > > + adreno_gpu->has_ray_tracing = true;
> > > > + }
> > > > +
> > > > + if (!qcom_scm_is_available()) {
> > > > + /* Assume that if qcom scm isn't available, that
> > > > whatever
> > > > +* replacement allows writing the fuse register
> > > > ourselves.
> > > > +* Users of alternative firmware need to make sure this
> > > > +* register is writeable or indicate that it's not
> > > > somehow.
> > > > +* Print a warning because if you mess this up you're
> > > > about to
> > > > +* crash horribl
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott wrote:
> > > > >
> > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method
> > > > > to
> > > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > > currently don't support). On a750, this includes a new "fuse" register
> > > > > which can be used by qcom_scm to fuse off certain features like
> > > > > raytracing in software. The fuse is default off, and is initialized by
> > > > > calling the method. Afterwards we have to read it to find out which
> > > > > features were enabled.
> > > > >
> > > > > Signed-off-by: Connor Abbott
> > > > > ---
> > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > -
> > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > @@ -10,6 +10,7 @@
> > > > >
> > > > > #include
> > > > > #include
> > > > > +#include
> > > > > #include
> > > > > #include
> > > > >
> > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu
> > > > > *gpu)
> > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > >
> > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct
> > > > > msm_gpu *gpu)
> > > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > }
> > > > >
> > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > +{
> > > > > + u32 status;
> > > > > +
> > > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > +
> > > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > > > status=%8.8x\n", status);
> > > > > +
> > > > > + /* Ignore FASTBLEND violations, because the HW will silently
> > > > > fall back
> > > > > +* to legacy blending.
> > > > > +*/
> > > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > > + del_timer(&gpu->hangcheck_timer);
> > > > > +
> > > > > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > {
> > > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of
> > > > > bounds access\n");
> > > > >
> > > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > > +
> > > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > > msm_gpu_retire(gpu);
> > > > >
> > > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > > platform_device *pdev,
> > > > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > > > }
> > > > >
> > > > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > > > +{
> > > > > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > > > > + struct msm_gpu *gpu = &adreno_gpu->base;
> > > > > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > > > > + u32 fuse_val;
> > > > > + int ret;
> > > > > +
> > > > > + if (adreno_is_a740(adreno_gpu)) {
> > > > > + /* Raytracing is always enabled on a740 */
> > > > > + adreno_gpu->has_ray_tracing = true;
> > > > > + }
> > > > > +
> > > > > + if (!qcom_scm_is_available()) {
> > > > > + /* Assume that if qcom scm isn't available, that
> > > > > whatever
> > > > > +* replacement allows writing the fuse register
> > > > > ourselves.
> > > > >
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
wrote:
>
> On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
> >
> > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> > wrote:
> > >
> > > On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
> > > >
> > > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > > wrote:
> > > > >
> > > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott
> > > > > wrote:
> > > > > >
> > > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a
> > > > > > method to
> > > > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > > > currently don't support). On a750, this includes a new "fuse"
> > > > > > register
> > > > > > which can be used by qcom_scm to fuse off certain features like
> > > > > > raytracing in software. The fuse is default off, and is initialized
> > > > > > by
> > > > > > calling the method. Afterwards we have to read it to find out which
> > > > > > features were enabled.
> > > > > >
> > > > > > Signed-off-by: Connor Abbott
> > > > > > ---
> > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > > -
> > > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > @@ -10,6 +10,7 @@
> > > > > >
> > > > > > #include
> > > > > > #include
> > > > > > +#include
> > > > > > #include
> > > > > > #include
> > > > > >
> > > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct
> > > > > > msm_gpu *gpu)
> > > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > >
> > > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct
> > > > > > msm_gpu *gpu)
> > > > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > > }
> > > > > >
> > > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > > +{
> > > > > > + u32 status;
> > > > > > +
> > > > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > > +
> > > > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > > > > status=%8.8x\n", status);
> > > > > > +
> > > > > > + /* Ignore FASTBLEND violations, because the HW will
> > > > > > silently fall back
> > > > > > +* to legacy blending.
> > > > > > +*/
> > > > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > > > + del_timer(&gpu->hangcheck_timer);
> > > > > > +
> > > > > > + kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > > {
> > > > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu
> > > > > > *gpu)
> > > > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of
> > > > > > bounds access\n");
> > > > > >
> > > > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > > > +
> > > > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > > > msm_gpu_retire(gpu);
> > > > > >
> > > > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > > > platform_device *pdev,
> > > > > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > > > > }
> > > > > >
> > > > > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > > > > +{
> > > > > > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > > > > > + struct msm_gpu *gpu = &adreno_gpu->base;
> > > > > > + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
> > > > > > + u32 fuse_val;
> > > > > > + int ret;
> > > > > > +
> > > > > > + if (adreno_is_a740(adreno_gpu)) {
> > > > > > + /* Raytracing is always enabled on a740 */
> > > > > > +
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On Fri, 26 Apr 2024 at 15:35, Connor Abbott wrote:
> > > > >
> > > > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > > > wrote:
> > > > > >
> > > > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott
> > > > > > wrote:
> > > > > > >
> > > > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a
> > > > > > > method to
> > > > > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > > > > currently don't support). On a750, this includes a new "fuse"
> > > > > > > register
> > > > > > > which can be used by qcom_scm to fuse off certain features like
> > > > > > > raytracing in software. The fuse is default off, and is
> > > > > > > initialized by
> > > > > > > calling the method. Afterwards we have to read it to find out
> > > > > > > which
> > > > > > > features were enabled.
> > > > > > >
> > > > > > > Signed-off-by: Connor Abbott
> > > > > > > ---
> > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > > > -
> > > > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > @@ -10,6 +10,7 @@
> > > > > > >
> > > > > > > #include
> > > > > > > #include
> > > > > > > +#include
> > > > > > > #include
> > > > > > > #include
> > > > > > >
> > > > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct
> > > > > > > msm_gpu *gpu)
> > > > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > >
> > > > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct
> > > > > > > msm_gpu *gpu)
> > > > > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > > > }
> > > > > > >
> > > > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > > > +{
> > > > > > > + u32 status;
> > > > > > > +
> > > > > > > + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > > > +
> > > > > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > > > > > status=%8.8x\n", status);
> > > > > > > +
> > > > > > > + /* Ignore FASTBLEND violations, because the HW will
> > > > > > > silently fall back
> > > > > > > +* to legacy blending.
> > > > > > > +*/
> > > > > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > > > > + del_timer(&gpu->hangcheck_timer);
> > > > > > > +
> > > > > > > + kthread_queue_work(gpu->worker,
> > > > > > > &gpu->recover_work);
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > > > {
> > > > > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu
> > > > > > > *gpu)
> > > > > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out
> > > > > > > of bounds access\n");
> > > > > > >
> > > > > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > > > > +
> > > > > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > > > > msm_gpu_retire(gpu);
> > > > > > >
> > > > > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > > > > platform_device *pdev,
> > > > > > > a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
> > > > > > > }
> > > > > > >
> > > > > > > +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
> > > > > > > +{
> > > > > > > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> > > > > > > + struct msm_gpu *gpu =
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, Apr 26, 2024 at 4:24 PM Dmitry Baryshkov
wrote:
>
> On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote:
> >
> > On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
> > wrote:
> > >
> > > On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
> > > >
> > > > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> > > > wrote:
> > > > >
> > > > > On Fri, 26 Apr 2024 at 15:35, Connor Abbott
> > > > > wrote:
> > > > > >
> > > > > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > > > > wrote:
> > > > > > >
> > > > > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a
> > > > > > > > method to
> > > > > > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > > > > > currently don't support). On a750, this includes a new "fuse"
> > > > > > > > register
> > > > > > > > which can be used by qcom_scm to fuse off certain features like
> > > > > > > > raytracing in software. The fuse is default off, and is
> > > > > > > > initialized by
> > > > > > > > calling the method. Afterwards we have to read it to find out
> > > > > > > > which
> > > > > > > > features were enabled.
> > > > > > > >
> > > > > > > > Signed-off-by: Connor Abbott
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > > > > -
> > > > > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > >
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > > +#include
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > >
> > > > > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct
> > > > > > > > msm_gpu *gpu)
> > > > > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > > >
> > > > > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct
> > > > > > > > msm_gpu *gpu)
> > > > > > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > > > > }
> > > > > > > >
> > > > > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > > > > +{
> > > > > > > > + u32 status;
> > > > > > > > +
> > > > > > > > + status = gpu_read(gpu,
> > > > > > > > REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > > > > +
> > > > > > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > > > > > > status=%8.8x\n", status);
> > > > > > > > +
> > > > > > > > + /* Ignore FASTBLEND violations, because the HW will
> > > > > > > > silently fall back
> > > > > > > > +* to legacy blending.
> > > > > > > > +*/
> > > > > > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > > > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > > > > > + del_timer(&gpu->hangcheck_timer);
> > > > > > > > +
> > > > > > > > + kthread_queue_work(gpu->worker,
> > > > > > > > &gpu->recover_work);
> > > > > > > > + }
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > > > > {
> > > > > > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > > > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct
> > > > > > > > msm_gpu *gpu)
> > > > > > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > > > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE |
> > > > > > > > Out of bounds access\n");
> > > > > > > >
> > > > > > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > > > > > +
> > > > > > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > > > > > msm_gpu_retire(gpu);
> > > > > > > >
> > > > > > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > > > > > platform_device *pdev,
> >
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 18:36, Connor Abbott wrote:
>
> On Fri, Apr 26, 2024 at 4:24 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote:
> > >
> > > On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
> > > > >
> > > > > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> > > > > wrote:
> > > > > >
> > > > > > On Fri, 26 Apr 2024 at 15:35, Connor Abbott
> > > > > > wrote:
> > > > > > >
> > > > > > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a
> > > > > > > > > method to
> > > > > > > > > initialize cx_mem. Copy this from downstream (minus BCL which
> > > > > > > > > we
> > > > > > > > > currently don't support). On a750, this includes a new "fuse"
> > > > > > > > > register
> > > > > > > > > which can be used by qcom_scm to fuse off certain features
> > > > > > > > > like
> > > > > > > > > raytracing in software. The fuse is default off, and is
> > > > > > > > > initialized by
> > > > > > > > > calling the method. Afterwards we have to read it to find out
> > > > > > > > > which
> > > > > > > > > features were enabled.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Connor Abbott
> > > > > > > > > ---
> > > > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > > > > > -
> > > > > > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > > >
> > > > > > > > > #include
> > > > > > > > > #include
> > > > > > > > > +#include
> > > > > > > > > #include
> > > > > > > > > #include
> > > > > > > > >
> > > > > > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct
> > > > > > > > > msm_gpu *gpu)
> > > > > > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT
> > > > > > > > > | \
> > > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS |
> > > > > > > > > \
> > > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > > > >
> > > > > > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > > > > > @@ -2356,6 +2358,26 @@ static void
> > > > > > > > > a6xx_fault_detect_irq(struct msm_gpu *gpu)
> > > > > > > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > > > > > }
> > > > > > > > >
> > > > > > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > > > > > +{
> > > > > > > > > + u32 status;
> > > > > > > > > +
> > > > > > > > > + status = gpu_read(gpu,
> > > > > > > > > REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > > > > > +
> > > > > > > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse
> > > > > > > > > violation status=%8.8x\n", status);
> > > > > > > > > +
> > > > > > > > > + /* Ignore FASTBLEND violations, because the HW will
> > > > > > > > > silently fall back
> > > > > > > > > +* to legacy blending.
> > > > > > > > > +*/
> > > > > > > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > > > > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > > > > > > + del_timer(&gpu->hangcheck_timer);
> > > > > > > > > +
> > > > > > > > > + kthread_queue_work(gpu->worker,
> > > > > > > > > &gpu->recover_work);
> > > > > > > > > + }
> > > > > > > > > +}
> > > > > > > > > +
> > > > > > > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > > > > > {
> > > > > > > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > > > > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct
> > > > > > > > > msm_gpu *gpu)
> > > > > > > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > > > > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE |
> > > > > > > > > Out of bounds access\n");
> > > > > > > > >
> > > > > > > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > >
Re: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, Apr 26, 2024 at 8:24 AM Dmitry Baryshkov
wrote:
>
> On Fri, 26 Apr 2024 at 18:08, Connor Abbott wrote:
> >
> > On Fri, Apr 26, 2024 at 3:53 PM Dmitry Baryshkov
> > wrote:
> > >
> > > On Fri, 26 Apr 2024 at 17:05, Connor Abbott wrote:
> > > >
> > > > On Fri, Apr 26, 2024 at 2:31 PM Dmitry Baryshkov
> > > > wrote:
> > > > >
> > > > > On Fri, 26 Apr 2024 at 15:35, Connor Abbott
> > > > > wrote:
> > > > > >
> > > > > > On Fri, Apr 26, 2024 at 12:02 AM Dmitry Baryshkov
> > > > > > wrote:
> > > > > > >
> > > > > > > On Thu, 25 Apr 2024 at 16:44, Connor Abbott
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a
> > > > > > > > method to
> > > > > > > > initialize cx_mem. Copy this from downstream (minus BCL which we
> > > > > > > > currently don't support). On a750, this includes a new "fuse"
> > > > > > > > register
> > > > > > > > which can be used by qcom_scm to fuse off certain features like
> > > > > > > > raytracing in software. The fuse is default off, and is
> > > > > > > > initialized by
> > > > > > > > calling the method. Afterwards we have to read it to find out
> > > > > > > > which
> > > > > > > > features were enabled.
> > > > > > > >
> > > > > > > > Signed-off-by: Connor Abbott
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89
> > > > > > > > -
> > > > > > > > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
> > > > > > > > 2 files changed, 90 insertions(+), 1 deletion(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > index cf0b1de1c071..fb2722574ae5 100644
> > > > > > > > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> > > > > > > > @@ -10,6 +10,7 @@
> > > > > > > >
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > > +#include
> > > > > > > > #include
> > > > > > > > #include
> > > > > > > >
> > > > > > > > @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct
> > > > > > > > msm_gpu *gpu)
> > > > > > > >A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
> > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
> > > > > > > >A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
> > > > > > > > - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
> > > > > > > > + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
> > > > > > > > + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > > >
> > > > > > > > #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
> > > > > > > > A6XX_CP_APRIV_CNTL_RBFETCH | \
> > > > > > > > @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct
> > > > > > > > msm_gpu *gpu)
> > > > > > > > kthread_queue_work(gpu->worker, &gpu->recover_work);
> > > > > > > > }
> > > > > > > >
> > > > > > > > +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
> > > > > > > > +{
> > > > > > > > + u32 status;
> > > > > > > > +
> > > > > > > > + status = gpu_read(gpu,
> > > > > > > > REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
> > > > > > > > + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
> > > > > > > > +
> > > > > > > > + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
> > > > > > > > status=%8.8x\n", status);
> > > > > > > > +
> > > > > > > > + /* Ignore FASTBLEND violations, because the HW will
> > > > > > > > silently fall back
> > > > > > > > +* to legacy blending.
> > > > > > > > +*/
> > > > > > > > + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
> > > > > > > > + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
> > > > > > > > + del_timer(&gpu->hangcheck_timer);
> > > > > > > > +
> > > > > > > > + kthread_queue_work(gpu->worker,
> > > > > > > > &gpu->recover_work);
> > > > > > > > + }
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> > > > > > > > {
> > > > > > > > struct msm_drm_private *priv = gpu->dev->dev_private;
> > > > > > > > @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct
> > > > > > > > msm_gpu *gpu)
> > > > > > > > if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
> > > > > > > > dev_err_ratelimited(&gpu->pdev->dev, "UCHE |
> > > > > > > > Out of bounds access\n");
> > > > > > > >
> > > > > > > > + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
> > > > > > > > + a7xx_sw_fuse_violation_irq(gpu);
> > > > > > > > +
> > > > > > > > if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
> > > > > > > > msm_gpu_retire(gpu);
> > > > > > > >
> > > > > > > > @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct
> > > > > > > > platform_device *pdev,
> >
Re: [PATCH] drm/msm: Fix gen_header.py for older python3 versions
Hi all,
On 12/04/2024 17:54, Jon Hunter wrote:
The gen_header.py script is failing for older versions of python3 such
as python 3.5. Two issues observed with python 3.5 are ...
1. Python 3 versions prior to 3.6 do not support the f-string format.
2. Early python 3 versions do not support the 'required' argument for
the argparse add_subparsers().
Fix both of the above so that older versions of python 3 still work.
Fixes: 8f7abf0b86fe ("drm/msm: generate headers on the fly")
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/msm/registers/gen_header.py | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/registers/gen_header.py
b/drivers/gpu/drm/msm/registers/gen_header.py
index 9b2842d4a354..90d5c2991d05 100644
--- a/drivers/gpu/drm/msm/registers/gen_header.py
+++ b/drivers/gpu/drm/msm/registers/gen_header.py
@@ -323,7 +323,7 @@ class Array(object):
indices = []
if self.length != 1:
if self.fixed_offsets:
- indices.append((self.index_ctype(), None,
f"__offset_{self.local_name}"))
+ indices.append((self.index_ctype(), None,
"__offset_%s" % self.local_name))
else:
indices.append((self.index_ctype(),
self.stride, None))
return indices
@@ -942,7 +942,8 @@ def main():
parser.add_argument('--rnn', type=str, required=True)
parser.add_argument('--xml', type=str, required=True)
- subparsers = parser.add_subparsers(required=True)
+ subparsers = parser.add_subparsers()
+ subparsers.required = True
parser_c_defines = subparsers.add_parser('c-defines')
parser_c_defines.set_defaults(func=dump_c_defines)
Any feedback on this? All our farm builders are still broken :-(
Thanks
Jon
--
nvpublic
Re: [PATCH 1/2] drm/print: drop include debugfs.h and include where needed
On Mon, Apr 22, 2024 at 03:10:10PM GMT, Jani Nikula wrote: drivers/gpu/drm/xe/xe_debugfs.c | 1 + drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 ++ drivers/gpu/drm/xe/xe_uc_debugfs.c | 2 ++ Acked-by: Lucas De Marchi thanks Lucas De Marchi
Re: [PATCH 1/2] drm/print: drop include debugfs.h and include where needed
On 22/04/2024 13:10, Jani Nikula wrote: > Surprisingly many places depend on debugfs.h to be included via > drm_print.h. Fix them. > > v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe > > v2: Also fix ivpu and vmwgfx > > Reviewed-by: Andrzej Hajda > Acked-by: Maxime Ripard > Link: > https://patchwork.freedesktop.org/patch/msgid/20240410141434.157908-1-jani.nik...@intel.com > Signed-off-by: Jani Nikula > > --- > > Cc: Jacek Lawrynowicz > Cc: Stanislaw Gruszka > Cc: Oded Gabbay > Cc: Russell King > Cc: David Airlie > Cc: Daniel Vetter > Cc: Andrzej Hajda > Cc: Neil Armstrong > Cc: Robert Foss > Cc: Laurent Pinchart > Cc: Jonas Karlman > Cc: Jernej Skrabec > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Thomas Zimmermann > Cc: Jani Nikula > Cc: Rodrigo Vivi > Cc: Joonas Lahtinen > Cc: Tvrtko Ursulin > Cc: Frank Binns > Cc: Matt Coster > Cc: Rob Clark > Cc: Abhinav Kumar > Cc: Dmitry Baryshkov > Cc: Sean Paul > Cc: Marijn Suijten > Cc: Karol Herbst > Cc: Lyude Paul > Cc: Danilo Krummrich > Cc: Alex Deucher > Cc: "Christian König" > Cc: "Pan, Xinhui" > Cc: Alain Volmat > Cc: Huang Rui > Cc: Zack Rusin > Cc: Broadcom internal kernel review list > > Cc: Lucas De Marchi > Cc: "Thomas Hellström" > Cc: dri-de...@lists.freedesktop.org > Cc: intel-...@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org > Cc: linux-arm-...@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Cc: nouv...@lists.freedesktop.org > Cc: amd-...@lists.freedesktop.org > --- > drivers/accel/ivpu/ivpu_debugfs.c | 2 ++ > drivers/gpu/drm/armada/armada_debugfs.c | 1 + > drivers/gpu/drm/bridge/ite-it6505.c | 1 + > drivers/gpu/drm/bridge/panel.c | 2 ++ > drivers/gpu/drm/drm_print.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_dmc.c| 1 + > drivers/gpu/drm/imagination/pvr_fw_trace.c | 1 + Acked-by: Matt Coster # drm/imagination Cheers, Matt > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 ++ > drivers/gpu/drm/nouveau/dispnv50/crc.c | 2 ++ > drivers/gpu/drm/radeon/r100.c | 1 + > drivers/gpu/drm/radeon/r300.c | 1 + > drivers/gpu/drm/radeon/r420.c | 1 + > drivers/gpu/drm/radeon/r600.c | 3 ++- > drivers/gpu/drm/radeon/radeon_fence.c | 1 + > drivers/gpu/drm/radeon/radeon_gem.c | 1 + > drivers/gpu/drm/radeon/radeon_ib.c | 2 ++ > drivers/gpu/drm/radeon/radeon_pm.c | 1 + > drivers/gpu/drm/radeon/radeon_ring.c| 2 ++ > drivers/gpu/drm/radeon/radeon_ttm.c | 1 + > drivers/gpu/drm/radeon/rs400.c | 1 + > drivers/gpu/drm/radeon/rv515.c | 1 + > drivers/gpu/drm/sti/sti_drv.c | 1 + > drivers/gpu/drm/ttm/ttm_device.c| 1 + > drivers/gpu/drm/ttm/ttm_resource.c | 3 ++- > drivers/gpu/drm/ttm/ttm_tt.c| 5 +++-- > drivers/gpu/drm/vc4/vc4_drv.h | 1 + > drivers/gpu/drm/vmwgfx/vmwgfx_gem.c | 2 ++ > drivers/gpu/drm/xe/xe_debugfs.c | 1 + > drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 ++ > drivers/gpu/drm/xe/xe_uc_debugfs.c | 2 ++ > include/drm/drm_print.h | 2 +- > 31 files changed, 46 insertions(+), 8 deletions(-) > > diff --git a/drivers/accel/ivpu/ivpu_debugfs.c > b/drivers/accel/ivpu/ivpu_debugfs.c > index d09d29775b3f..e07e447d08d1 100644 > --- a/drivers/accel/ivpu/ivpu_debugfs.c > +++ b/drivers/accel/ivpu/ivpu_debugfs.c > @@ -3,6 +3,8 @@ > * Copyright (C) 2020-2023 Intel Corporation > */ > > +#include > + > #include > #include > #include > diff --git a/drivers/gpu/drm/armada/armada_debugfs.c > b/drivers/gpu/drm/armada/armada_debugfs.c > index 29f4b52e3c8d..a763349dd89f 100644 > --- a/drivers/gpu/drm/armada/armada_debugfs.c > +++ b/drivers/gpu/drm/armada/armada_debugfs.c > @@ -5,6 +5,7 @@ > */ > > #include > +#include > #include > #include > #include > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c > b/drivers/gpu/drm/bridge/ite-it6505.c > index 27334173e911..3f68c82888c2 100644 > --- a/drivers/gpu/drm/bridge/ite-it6505.c > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, The Linux Foundation. All rights reserved. > */ > #include > +#include > #include > #include > #include > diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c > index 7f41525f7a6e..32506524d9a2 100644 > --- a/drivers/gpu/drm/bridge/panel.c > +++ b/drivers/gpu/drm/bridge/panel.c > @@ -4,6 +4,8 @@ > * Copyright (C) 2017 Broadcom > */ > > +#include > + > #include > #include > #include > diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c > index 699b7dbffd7b..cf2efb44722c 100644 > --- a/drivers/gpu/drm/drm_print.c > +++ b/drivers/gpu/drm/drm_print.c > @@ -23,13 +23,13 @@ > * Rob Clark > */ > > -#include > - > +#include > +#include > #include > #incl
[PATCH v2 0/6] drm/msm: Support a750 "software fuse" for raytracing
On a750, Qualcomm decided to gate support for certain features behind a
"software fuse." This consists of a register in the cx_mem zone, which
is normally only writeable by the TrustZone firmware. On bootup it is
0, and we must call an SCM method to initialize it. Then we communicate
its value to userspace. This implements all of this, copying the SCM
call from the downstream kernel and kgsl.
So far the only optional feature we use is ray tracing (i.e. the
"ray_intersection" instruction) in a pending Mesa MR [1], so that's what
we expose to userspace. There's one extra patch to write some missing
registers, which depends on the register XML bump but is otherwise
unrelated, I just included it to make things easier on myself.
Note, 'drm/msm/a7xx: Initialize a750 "software fuse"' has a compile-time
dependency on 'firmware: qcom_scm: Add gpu_init_regs call' and it
depends on 'arm64: dts: qcom: sm8650: Fix GPU cx_mem size' to avoid a
boot-time hang. The commit the latter fixes, db33633b05c0 ("arm64: dts:
qcom: sm8650: add GPU nodes"), hasn't landed upstream yet, so we can
avoid regressions by merging it first. I think the rest of the series
can go through drm/msm for 6.10 after we land the first commit in the
same tree as db33633b05c0 to make sure linux-next is never broken,
although we'll need Bjorn's ack to land 'firmware: qcom_scm: Add
gpu_init_regs call' through drm/msm.
v2: - Refactor a7xx_init_cx_mem() into a750-specific and a740/a730 paths.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28447
Connor Abbott (6):
arm64: dts: qcom: sm8650: Fix GPU cx_mem size
firmware: qcom_scm: Add gpu_init_regs call
drm/msm: Update a6xx registers
drm/msm/a7xx: Initialize a750 "software fuse"
drm/msm: Add MSM_PARAM_RAYTRACING uapi
drm/msm/a7xx: Add missing register writes from downstream
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
drivers/firmware/qcom/qcom_scm.c | 14 +++
drivers/firmware/qcom/qcom_scm.h | 3 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 97 ++-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28 +-
include/linux/firmware/qcom/qcom_scm.h| 23 +
include/uapi/drm/msm_drm.h| 1 +
9 files changed, 168 insertions(+), 5 deletions(-)
--
2.31.1
---
Connor Abbott (6):
arm64: dts: qcom: sm8650: Fix GPU cx_mem size
firmware: qcom_scm: Add gpu_init_regs call
drm/msm: Update a6xx registers
drm/msm/a7xx: Initialize a750 "software fuse"
drm/msm: Add MSM_PARAM_RAYTRACING uapi
drm/msm/a7xx: Add missing register writes from downstream
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
drivers/firmware/qcom/qcom_scm.c | 14
drivers/firmware/qcom/qcom_scm.h | 3 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 96 ++-
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28 +++-
include/linux/firmware/qcom/qcom_scm.h| 23 +++
include/uapi/drm/msm_drm.h| 1 +
9 files changed, 167 insertions(+), 5 deletions(-)
---
base-commit: 7e6b8924568d1aa476b77323df8d2bdd31bd7257
change-id: 20240426-a750-raytracing-dee7a526513b
Best regards,
--
Connor Abbott
[PATCH v2 1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size
This is doubled compared to previous GPUs. We can't access the new
SW_FUSE_VALUE register without this.
Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes")
Signed-off-by: Connor Abbott
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi
b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 658ad2b41c5a..78b8944eaab2 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2607,7 +2607,7 @@ tcsr: clock-controller@1fc {
gpu: gpu@3d0 {
compatible = "qcom,adreno-43051401", "qcom,adreno";
reg = <0x0 0x03d0 0x0 0x4>,
- <0x0 0x03d9e000 0x0 0x1000>,
+ <0x0 0x03d9e000 0x0 0x2000>,
<0x0 0x03d61000 0x0 0x800>;
reg-names = "kgsl_3d0_reg_memory",
"cx_mem",
--
2.31.1
[PATCH v2 2/6] firmware: qcom_scm: Add gpu_init_regs call
This will used by drm/msm.
Signed-off-by: Connor Abbott
---
drivers/firmware/qcom/qcom_scm.c | 14 ++
drivers/firmware/qcom/qcom_scm.h | 3 +++
include/linux/firmware/qcom/qcom_scm.h | 23 +++
3 files changed, 40 insertions(+)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 06e46267161b..f8623ad0987c 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -1394,6 +1394,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg,
u32 payload_val,
}
EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh);
+int qcom_scm_gpu_init_regs(u32 gpu_req)
+{
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_GPU,
+ .cmd = QCOM_SCM_SVC_GPU_INIT_REGS,
+ .arginfo = QCOM_SCM_ARGS(1),
+ .args[0] = gpu_req,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+ return qcom_scm_call(__scm->dev, &desc, NULL);
+}
+EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs);
+
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
{
struct device_node *tcsr;
diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h
index 4532907e8489..484e030bcac9 100644
--- a/drivers/firmware/qcom/qcom_scm.h
+++ b/drivers/firmware/qcom/qcom_scm.h
@@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct
qcom_scm_desc *desc,
#define QCOM_SCM_WAITQ_RESUME 0x02
#define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03
+#define QCOM_SCM_SVC_GPU 0x28
+#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01
+
/* common error codes */
#define QCOM_SCM_V2_EBUSY -12
#define QCOM_SCM_ENOMEM-5
diff --git a/include/linux/firmware/qcom/qcom_scm.h
b/include/linux/firmware/qcom/qcom_scm.h
index aaa19f93ac43..2c444c98682e 100644
--- a/include/linux/firmware/qcom/qcom_scm.h
+++ b/include/linux/firmware/qcom/qcom_scm.h
@@ -115,6 +115,29 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg,
u32 payload_val,
int qcom_scm_lmh_profile_change(u32 profile_id);
bool qcom_scm_lmh_dcvsh_available(void);
+/**
+ * Request TZ to program set of access controlled registers necessary
+ * irrespective of any features
+ */
+#define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0)
+/**
+ * Request TZ to program BCL id to access controlled register when BCL is
+ * enabled
+ */
+#define QCOM_SCM_GPU_BCL_EN_REQ BIT(1)
+/**
+ * Request TZ to program set of access controlled register for CLX feature
+ * when enabled
+ */
+#define QCOM_SCM_GPU_CLX_EN_REQ BIT(2)
+/**
+ * Request TZ to program tsense ids to access controlled registers for reading
+ * gpu temperature sensors
+ */
+#define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3)
+
+int qcom_scm_gpu_init_regs(u32 gpu_req);
+
#ifdef CONFIG_QCOM_QSEECOM
int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
--
2.31.1
[PATCH v2 3/6] drm/msm: Update a6xx registers
Update to mesa commit ff155f46a33 ("freedreno/a7xx: Register updates
from kgsl").
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28 ---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index 78524aaab9d4..43fe90c12679 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -1227,6 +1227,7 @@ to upconvert to 32b float internally?
+
@@ -1503,6 +1504,9 @@ to upconvert to 32b float internally?
+
+
+
@@ -2842,7 +2846,11 @@ to upconvert to 32b float internally?
-
+
+ RB_SAMPLE_COUNT_ADDR register is used up to (and including)
a730. After that
+ the address is specified through
CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT.
+
+
@@ -2950,7 +2958,7 @@ to upconvert to 32b float internally?
-
+
@@ -3306,6 +3314,15 @@ to upconvert to 32b float internally?
+
+
+
+
+
@@ -4293,7 +4310,7 @@ to upconvert to 32b float internally?
-
+
@@ -4965,6 +4982,11 @@ to upconvert to 32b float internally?
+
+
+
+
+
--
2.31.1
[PATCH v2 6/6] drm/msm/a7xx: Add missing register writes from downstream
This isn't known to fix anything yet, but it's a good idea to add it.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 4a3b12b20802..d88ec857f1cb 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1953,6 +1953,14 @@ static int hw_init(struct msm_gpu *gpu)
BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1));
}
+ if (adreno_is_a750(adreno_gpu)) {
+ gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19));
+
+ gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700);
+ } else if (adreno_is_a7xx(adreno_gpu)) {
+ gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19));
+ }
+
/* Enable interrupts */
gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK,
adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK);
--
2.31.1
[PATCH v2 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to
initialize cx_mem. Copy this from downstream (minus BCL which we
currently don't support). On a750, this includes a new "fuse" register
which can be used by qcom_scm to fuse off certain features like
raytracing in software. The fuse is default off, and is initialized by
calling the method. Afterwards we have to read it to find out which
features were enabled.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 88 -
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index cf0b1de1c071..4a3b12b20802 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -10,6 +10,7 @@
#include
#include
+#include
#include
#include
@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
- A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+ A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+ A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
#define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
A6XX_CP_APRIV_CNTL_RBFETCH | \
@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
kthread_queue_work(gpu->worker, &gpu->recover_work);
}
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+ u32 status;
+
+ status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+ gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+ dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation
status=%8.8x\n", status);
+
+ /* Ignore FASTBLEND violations, because the HW will silently fall back
+* to legacy blending.
+*/
+ if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+ A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+ del_timer(&gpu->hangcheck_timer);
+
+ kthread_queue_work(gpu->worker, &gpu->recover_work);
+ }
+}
+
static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
{
struct msm_drm_private *priv = gpu->dev->dev_private;
@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds
access\n");
+ if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+ a7xx_sw_fuse_violation_irq(gpu);
+
if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
msm_gpu_retire(gpu);
@@ -2525,6 +2550,59 @@ static void a6xx_llc_slices_init(struct platform_device
*pdev,
a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
}
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+ struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+ struct msm_gpu *gpu = &adreno_gpu->base;
+ u32 fuse_val;
+ int ret = 0;
+
+ if (adreno_is_a750(adreno_gpu)) {
+ /* Assume that if qcom scm isn't available, that whatever
+* replacement allows writing the fuse register ourselves.
+* Users of alternative firmware need to make sure this
+* register is writeable or indicate that it's not somehow.
+* Print a warning because if you mess this up you're about to
+* crash horribly.
+*/
+ if (!qcom_scm_is_available()) {
+ dev_warn_once(gpu->dev->dev,
+ "SCM is not available, poking fuse register\n");
+ a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+ A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+ A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+ A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+ adreno_gpu->has_ray_tracing = true;
+ return 0;
+ }
+
+ ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ |
+QCOM_SCM_GPU_TSENSE_EN_REQ);
+ if (ret)
+ return ret;
+
+ /* On a750 raytracing may be disabled by the firmware, find out
whether
+* that's the case. The scm call above sets the fuse register.
+*/
+ fuse_val = a6xx_llc_read(a6xx_gpu,
REG_A7XX_CX_MISC_SW_FUSE_VALUE);
+ adreno_gpu->has_ray_tracing =
+ !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
+ } else {
+ if (adreno_is_a740(adreno_gpu)) {
+ /*
[PATCH v2 5/6] drm/msm: Add MSM_PARAM_RAYTRACING uapi
Expose the value of the software fuse to userspace.
Signed-off-by: Connor Abbott
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
include/uapi/drm/msm_drm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 074fb498706f..99ad651857b2 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -376,6 +376,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct
msm_file_private *ctx,
case MSM_PARAM_HIGHEST_BANK_BIT:
*value = adreno_gpu->ubwc_config.highest_bank_bit;
return 0;
+ case MSM_PARAM_RAYTRACING:
+ *value = adreno_gpu->has_ray_tracing;
+ return 0;
default:
DBG("%s: invalid param: %u", gpu->name, param);
return -EINVAL;
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index d8a6b3472760..3fca72f73861 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -87,6 +87,7 @@ struct drm_msm_timespec {
#define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */
#define MSM_PARAM_VA_SIZE0x0f /* RO: size of valid GPU iova range (bytes)
*/
#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */
+#define MSM_PARAM_RAYTRACING 0x11 /* RO */
/* For backwards compat. The original support for preemption was based on
* a single ring per priority level so # of priority levels equals the #
--
2.31.1
Re: [PATCH v2 1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote:
>
> This is doubled compared to previous GPUs. We can't access the new
> SW_FUSE_VALUE register without this.
>
> Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes")
> Signed-off-by: Connor Abbott
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH v2 2/6] firmware: qcom_scm: Add gpu_init_regs call
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote: > > This will used by drm/msm. Can we have some description please? > > Signed-off-by: Connor Abbott > --- > drivers/firmware/qcom/qcom_scm.c | 14 ++ > drivers/firmware/qcom/qcom_scm.h | 3 +++ > include/linux/firmware/qcom/qcom_scm.h | 23 +++ > 3 files changed, 40 insertions(+) > With the commit message improved: Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v2 3/6] drm/msm: Update a6xx registers
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote:
>
> Update to mesa commit ff155f46a33 ("freedreno/a7xx: Register updates
> from kgsl").
>
> Signed-off-by: Connor Abbott
> ---
> drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28
> ---
> 1 file changed, 25 insertions(+), 3 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH v2 4/6] drm/msm/a7xx: Initialize a750 "software fuse"
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote: > > On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to > initialize cx_mem. Copy this from downstream (minus BCL which we > currently don't support). On a750, this includes a new "fuse" register > which can be used by qcom_scm to fuse off certain features like > raytracing in software. The fuse is default off, and is initialized by > calling the method. Afterwards we have to read it to find out which > features were enabled. > > Signed-off-by: Connor Abbott > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 88 > - > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 + > 2 files changed, 89 insertions(+), 1 deletion(-) > I didn't check the register bits, but the rest looks fine Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v2 5/6] drm/msm: Add MSM_PARAM_RAYTRACING uapi
On Fri, 26 Apr 2024 at 21:34, Connor Abbott wrote: > > Expose the value of the software fuse to userspace. > > Signed-off-by: Connor Abbott > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ > include/uapi/drm/msm_drm.h | 1 + > 2 files changed, 4 insertions(+) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
