Re: [PATCH 1/7] dt-bindings: display/msm/dsi: allow specifying TE source
On Thu, 23 May 2024 at 02:57, Abhinav Kumar wrote:
>
>
>
> On 5/22/2024 1:05 PM, Dmitry Baryshkov wrote:
> > On Wed, 22 May 2024 at 21:38, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
> >>> Command mode panels provide TE signal back to the DSI host to signal
> >>> that the frame display has completed and update of the image will not
> >>> cause tearing. Usually it is connected to the first GPIO with the
> >>> mdp_vsync function, which is the default. In such case the property can
> >>> be skipped.
> >>>
> >>
> >> This is a good addition overall. Some comments below.
> >>
> >>> Signed-off-by: Dmitry Baryshkov
> >>> ---
> >>>.../bindings/display/msm/dsi-controller-main.yaml| 16
> >>>
> >>>1 file changed, 16 insertions(+)
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> index 1fa28e976559..c1771c69b247 100644
> >>> ---
> >>> a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> +++
> >>> b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> >>> @@ -162,6 +162,21 @@ properties:
> >>>items:
> >>> enum: [ 0, 1, 2, 3 ]
> >>>
> >>> + qcom,te-source:
> >>> +$ref: /schemas/types.yaml#/definitions/string
> >>> +description:
> >>> + Specifies the source of vsync signal from the panel
> >>> used for
> >>> + tearing elimination. The default is mdp_gpio0.
> >>
> >> panel --> command mode panel?
> >>
> >>> +enum:
> >>> + - mdp_gpio0
> >>> + - mdp_gpio1
> >>> + - mdp_gpio2
> >>
> >> are gpio0, gpio1 and gpio2 referring to the vsync_p, vsync_s and vsync_e
> >> sources?
> >
> > No idea, unfortunately. They are gpioN or just mdp_vsync all over the
> > place. For the reference, in case of the SDM845 and Pixel3 the signal
> > is routed through SoC GPIO12.
> >
>
> GPIO12 on sdm845 is mdp_vsync_e.
>
> Thats why I think its better we use mdp_vsync_p/s/e instead of mdp_gpio0/1/2
Sure. This matches pins description. Are you fine with changing
defines in DPU driver to VSYNC_P / _S / _E too ?
>
> >> In that case wouldnt it be better to name it like that?
> >>
> >>> + - timer0
> >>> + - timer1
> >>> + - timer2
> >>> + - timer3
> >>> + - timer4
> >>> +
> >>
> >> These are indicating watchdog timer sources right?
> >
> > Yes.
> >
> >>
> >>>required:
> >>> - port@0
> >>> - port@1
> >>> @@ -452,6 +467,7 @@ examples:
> >>> dsi0_out: endpoint {
> >>> remote-endpoint = <&sn65dsi86_in>;
> >>> data-lanes = <0 1 2 3>;
> >>> + qcom,te-source = "mdp_gpio2";
> >>
> >> I have a basic doubt on this. Should te-source should be in the input
> >> port or the output one for the controller? Because TE is an input to the
> >> DSI. And if the source is watchdog timer then it aligns even more as a
> >> property of the input endpoint.
> >
> > I don't really want to split this. Both data-lanes and te-source are
> > properties of the link between the DSI and panel. You can not really
> > say which side has which property.
> >
>
> TE is an input to the DSI from the panel. Between input and output port,
> I think it belongs more to the input port.
Technically we don't have in/out ports. There are two ports which
define a link between two instances. For example, if the panel
supports getting information through DCS commands, then "panel input"
also becomes "panel output".
>
> I didnt follow why this is a link property. Sorry , I didnt follow the
> split part.
There is a link between the DSI host and the panel. I don't want to
end up in a situation when the properties of the link are split
between two different nodes.
>
> If we are unsure about input vs output port, do you think its better we
> make it a property of the main dsi node instead?
No, it's not a property of the DSI node at all. If the vendor rewires
the panel GPIOs or (just for example regulators), it has nothing to do
with the DSI host.
--
With best wishes
Dmitry
Re: [PATCH v2 5/7] drm/msm/adreno: Add A702 support
On Fri, Feb 23, 2024 at 9:28 PM Konrad Dybcio wrote:
>
> The A702 is a weird mix of 600 and 700 series.. Perhaps even a
> testing ground for some A7xx features with good ol' A6xx silicon.
> It's basically A610 that's been beefed up with some new registers
> and hw features (like APRIV!), that was then cut back in size,
> memory bus and some other ways.
>
> Add support for it, tested with QCM2290 / RB1.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 92
> +++---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 18 ++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h| 16 +-
> 3 files changed, 117 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index c9c55e2ea584..2a491a486ca1 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -837,6 +837,65 @@ const struct adreno_reglist a690_hwcg[] = {
> {}
> };
>
> +const struct adreno_reglist a702_hwcg[] = {
> + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0220 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x0081 },
> + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0xf3cf },
> + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x0002 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x0001 },
> + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x0007 },
> + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x0120 },
> + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x2220 },
> + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
> + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
> + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x },
> + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x0011 },
> + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
> + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422 },
> + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x },
> + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x0222 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x0002 },
> + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x },
> + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x },
> + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x0200 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
> + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x0004 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x0002 },
> + { REG_A6XX_RBBM_ISDB_CNT, 0x0182 },
> + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x },
> + { REG_A6XX_RBBM_SP_HYST_CNT, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x0222 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x0111 },
> + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x0555 },
> + { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x0222 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x0022 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x },
> + { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x0002 },
> + { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x },
> + { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x },
> + {}
> +};
> +
> const struct adreno_reglist a730_hwcg[] = {
> { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x0222 },
> { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x0202 },
> @@ -968,6 +1027,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool
> state)
> clock_cntl_on = 0x8aa8aa02;
> else if (adreno_is_a610(adreno_gpu))
> clock_cntl_on = 0xaaa8aa82;
> + else if (adreno_is_a702(adreno_gpu))
> + clock_cntl_on = 0xaa82;
> else
> clock_cntl_on = 0x8aa8aa82;
>
> @@ -989,14 +1050,14 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool
> state)
> return;
>
> /* Disable SP clock before programming HWCG registers */
> - if (!adreno_is_a6
[PATCH v4 0/2] io-pgtable-arm + drm/msm: Extend iova fault debugging
From: Rob Clark This series extends io-pgtable-arm with a method to retrieve the page table entries traversed in the process of address translation, and then beefs up drm/msm gpu devcore dump to include this (and additional info) in the devcore dump. This is a respin of https://patchwork.freedesktop.org/series/94968/ (minus a patch that was already merged) v2: Fix an armv7/32b build error in the last patch v3: Incorperate Will Deacon's suggestion to make the interface callback based. v4: Actually wire up the callback Rob Clark (2): iommu/io-pgtable-arm: Add way to debug pgtable walk drm/msm: Extend gpu devcore dumps with pgtbl info drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 + drivers/gpu/drm/msm/msm_gpu.c | 22 +++ drivers/gpu/drm/msm/msm_gpu.h | 8 drivers/gpu/drm/msm/msm_iommu.c | 18 + drivers/gpu/drm/msm/msm_mmu.h | 5 ++- drivers/iommu/io-pgtable-arm.c | 51 - include/linux/io-pgtable.h | 4 ++ 7 files changed, 108 insertions(+), 10 deletions(-) -- 2.45.1
[PATCH v4 1/2] iommu/io-pgtable-arm: Add way to debug pgtable walk
From: Rob Clark
Add an io-pgtable method to walk the pgtable returning the raw PTEs that
would be traversed for a given iova access.
Signed-off-by: Rob Clark
---
drivers/iommu/io-pgtable-arm.c | 51 --
include/linux/io-pgtable.h | 4 +++
2 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index f7828a7aad41..f47a0e64bb35 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -693,17 +693,19 @@ static size_t arm_lpae_unmap_pages(struct io_pgtable_ops
*ops, unsigned long iov
data->start_level, ptep);
}
-static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
-unsigned long iova)
+static int arm_lpae_pgtable_walk(struct io_pgtable_ops *ops, unsigned long
iova,
+ int (*cb)(void *cb_data, void *pte, int level),
+ void *cb_data)
{
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
arm_lpae_iopte pte, *ptep = data->pgd;
int lvl = data->start_level;
+ int ret;
do {
/* Valid IOPTE pointer? */
if (!ptep)
- return 0;
+ return -EFAULT;
/* Grab the IOPTE we're interested in */
ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
@@ -711,22 +713,52 @@ static phys_addr_t arm_lpae_iova_to_phys(struct
io_pgtable_ops *ops,
/* Valid entry? */
if (!pte)
- return 0;
+ return -EFAULT;
+
+ ret = cb(cb_data, &pte, lvl);
+ if (ret)
+ return ret;
- /* Leaf entry? */
+ /* Leaf entry? If so, we've found the translation */
if (iopte_leaf(pte, lvl, data->iop.fmt))
- goto found_translation;
+ return 0;
/* Take it to the next level */
ptep = iopte_deref(pte, data);
} while (++lvl < ARM_LPAE_MAX_LEVELS);
/* Ran out of page tables to walk */
+ return -EFAULT;
+}
+
+struct iova_to_phys_walk_data {
+ arm_lpae_iopte pte;
+ int level;
+};
+
+static int iova_to_phys_walk_cb(void *cb_data, void *pte, int level)
+{
+ struct iova_to_phys_walk_data *d = cb_data;
+
+ d->pte = *(arm_lpae_iopte *)pte;
+ d->level = level;
+
return 0;
+}
+
+static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
+unsigned long iova)
+{
+ struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
+ struct iova_to_phys_walk_data d;
+ int ret;
+
+ ret = arm_lpae_pgtable_walk(ops, iova, iova_to_phys_walk_cb, &d);
+ if (ret)
+ return 0;
-found_translation:
- iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
- return iopte_to_paddr(pte, data) | iova;
+ iova &= (ARM_LPAE_BLOCK_SIZE(d.level, data) - 1);
+ return iopte_to_paddr(d.pte, data) | iova;
}
static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
@@ -807,6 +839,7 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
.map_pages = arm_lpae_map_pages,
.unmap_pages= arm_lpae_unmap_pages,
.iova_to_phys = arm_lpae_iova_to_phys,
+ .pgtable_walk = arm_lpae_pgtable_walk,
};
return data;
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index 86cf1f7ae389..261b48af068a 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -177,6 +177,7 @@ struct io_pgtable_cfg {
* @map_pages:Map a physically contiguous range of pages of the same size.
* @unmap_pages: Unmap a range of virtually contiguous pages of the same size.
* @iova_to_phys: Translate iova to physical address.
+ * @pgtable_walk: (optional) Perform a page table walk for a given iova.
*
* These functions map directly onto the iommu_ops member functions with
* the same names.
@@ -190,6 +191,9 @@ struct io_pgtable_ops {
struct iommu_iotlb_gather *gather);
phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops,
unsigned long iova);
+ int (*pgtable_walk)(struct io_pgtable_ops *ops, unsigned long iova,
+ int (*cb)(void *cb_data, void *pte, int level),
+ void *cb_data);
int (*read_and_clear_dirty)(struct io_pgtable_ops *ops,
unsigned long iova, size_t size,
unsigned long flags,
--
2.45.1
[PATCH v4 2/2] drm/msm: Extend gpu devcore dumps with pgtbl info
From: Rob Clark
In the case of iova fault triggered devcore dumps, include additional
debug information based on what we think is the current page tables,
including the TTBR0 value (which should match what we have in
adreno_smmu_fault_info unless things have gone horribly wrong), and
the pagetable entries traversed in the process of resolving the
faulting iova.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 10 ++
drivers/gpu/drm/msm/msm_gpu.c | 22 ++
drivers/gpu/drm/msm/msm_gpu.h | 8
drivers/gpu/drm/msm/msm_iommu.c | 18 ++
drivers/gpu/drm/msm/msm_mmu.h | 5 -
5 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index a00241e3373b..3b4c75df0a5f 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -861,6 +861,16 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state
*state,
drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ?
"WRITE" : "READ");
drm_printf(p, " - type=%s\n", info->type);
drm_printf(p, " - source=%s\n", info->block);
+
+ /* Information extracted from what we think are the current
+* pgtables. Hopefully the TTBR0 matches what we've extracted
+* from the SMMU registers in smmu_info!
+*/
+ drm_puts(p, "pgtable-fault-info:\n");
+ drm_printf(p, " - ttbr0: %.16llx\n", (u64)info->pgtbl_ttbr0);
+ drm_printf(p, " - asid: %d\n", info->asid);
+ drm_printf(p, " - ptes: %.16llx %.16llx %.16llx %.16llx\n",
+ info->ptes[0], info->ptes[1], info->ptes[2],
info->ptes[3]);
}
drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 43cde0590250..647bddc897f2 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -256,6 +256,18 @@ static void msm_gpu_crashstate_get_bo(struct msm_gpu_state
*state,
state->nr_bos++;
}
+static int pgtable_walk_cb(void *cb_data, void *pte, int level)
+{
+ struct msm_gpu_fault_info *info = cb_data;
+
+ if (level > ARRAY_SIZE(info->ptes))
+ return -EINVAL;
+
+ info->ptes[level] = *(u64 *)pte;
+
+ return 0;
+}
+
static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
struct msm_gem_submit *submit, char *comm, char *cmd)
{
@@ -281,6 +293,16 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
if (submit) {
int i;
+ if (state->fault_info.ttbr0) {
+ struct msm_gpu_fault_info *info = &state->fault_info;
+ struct msm_mmu *mmu = submit->aspace->mmu;
+
+ msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0,
+ &info->asid);
+ msm_iommu_pagetable_walk(mmu, info->iova,
+pgtable_walk_cb, info);
+ }
+
state->bos = kcalloc(submit->nr_bos,
sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 04a696ac4626..82fbb626461a 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -101,6 +101,14 @@ struct msm_gpu_fault_info {
int flags;
const char *type;
const char *block;
+
+ /* Information about what we think/expect is the current SMMU state,
+* for example expected_ttbr0 should match smmu_info.ttbr0 which
+* was read back from SMMU registers.
+*/
+ phys_addr_t pgtbl_ttbr0;
+ u64 ptes[4];
+ int asid;
};
/**
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index d5512037c38b..f46ed4667475 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -195,6 +195,24 @@ struct iommu_domain_geometry
*msm_iommu_get_geometry(struct msm_mmu *mmu)
return &iommu->domain->geometry;
}
+int msm_iommu_pagetable_walk(struct msm_mmu *mmu, unsigned long iova,
+int (*cb)(void *cb_data, void *pte, int level),
+void *cb_data)
+{
+ struct msm_iommu_pagetable *pagetable;
+
+ if (mmu->type != MSM_MMU_IOMMU_PAGETABLE)
+ return -EINVAL;
+
+ pagetable = to_pagetable(mmu);
+
+ if (!pagetable->pgtbl_ops->pgtable_walk)
+ return -EINVAL;
+
+ return pagetable->pgtbl_ops->pgtable_walk(pagetable->pgtbl_ops, iova,
+ cb, cb_data);
+}
+
static const struct msm_mmu_funcs pagetable_funcs
