Re: [PATCH v2] arm64: dts: qcom: msm8998: enable adreno_smmu by default
On Wed, 15 May 2024 16:27:44 +0200, Marc Gonzalez wrote: > 15 qcom platform DTSI files define an adreno_smmu node. > msm8998 is the only one with adreno_smmu disabled by default. > > There's no reason why this SMMU should be disabled by default, > it doesn't need any further configuration. > > Bring msm8998 in line with the 14 other platforms. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: msm8998: enable adreno_smmu by default commit: 98a0c4f2278b4d6c1c7722735c20b2247de6293f Best regards, -- Bjorn Andersson
Re: (subset) [PATCH 0/8] MSM8976 MDSS/GPU/WCNSS support
On Sun, 21 Jan 2024 20:40:58 +0100, Adam Skladowski wrote: > This patch series provide support for display subsystem, gpu > and also adds wireless connectivity subsystem support. > > Adam Skladowski (8): > arm64: dts: qcom: msm8976: Add IOMMU nodes > dt-bindings: dsi-controller-main: Document missing msm8976 compatible > dt-bindings: msm: qcom,mdss: Include ommited fam-b compatible > arm64: dts: qcom: msm8976: Add MDSS nodes > dt-bindings: drm/msm/gpu: Document AON clock for A506/A510 > arm64: dts: qcom: msm8976: Add Adreno GPU > arm64: dts: qcom: msm8976: Declare and wire SDC pins > arm64: dts: qcom: msm8976: Add WCNSS node > > [...] Applied, thanks! [1/8] arm64: dts: qcom: msm8976: Add IOMMU nodes commit: 418c2ffd7df9bfc25c21172bd881b78d7569fb4d Best regards, -- Bjorn Andersson
Re: [PATCH v5 3/6] drm/msm/dpu: enable compression bit in cfg2 for DSC
On Mon, May 27, 2024 at 10:21:49PM +0800, Jun Nie wrote: > Enable compression bit in cfg2 register for DSC in the DSI case > > Signed-off-by: Jun Nie > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 > 1 file changed, 4 insertions(+) > Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [PATCH v5 2/6] drm/msm/dpu: adjust data width for widen bus case
On Mon, May 27, 2024 at 10:21:48PM +0800, Jun Nie wrote: > data is valid for only half the active window if widebus > is enabled > > Signed-off-by: Jun Nie > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 225c1c7768ff..f97221423249 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -168,6 +168,15 @@ static void dpu_hw_intf_setup_timing_engine(struct > dpu_hw_intf *intf, > > data_width = p->width; > > + /* > + * If widebus is enabled, data is valid for only half the active window > + * since the data rate is doubled in this mode. But for the compression > + * mode in DP case, the p->width is already adjusted in > + * drm_mode_to_intf_timing_params() Is there any reason for divergence here? > + */ > + if (p->wide_bus_en && !dp_intf) > + data_width = p->width >> 1; > + > hsync_data_start_x = hsync_start_x; > hsync_data_end_x = hsync_start_x + data_width - 1; > > > -- > 2.34.1 > -- With best wishes Dmitry
Re: [PATCH v5 1/6] drm/msm/dpu: fix video mode DSC for DSI
On Mon, May 27, 2024 at 10:21:47PM +0800, Jun Nie wrote: > From: Jonathan Marek > > Add width change in DPU timing for DSC compression case to work with > DSI video mode. > > Signed-off-by: Jonathan Marek > Signed-off-by: Jun Nie > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++ > 3 files changed, 27 insertions(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry
Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On Mon, May 27, 2024 at 02:39:35PM +0200, Arnaud Vrac wrote:
> On 27/05/2024 14:11, Dmitry Baryshkov wrote:
> > On Thu, 23 May 2024 at 18:14, Marc Gonzalez wrote:
> > >
> > > From: Arnaud Vrac
> > >
> > > Ported from the downstream driver.
> > >
> > > Signed-off-by: Arnaud Vrac
> > > Signed-off-by: Marc Gonzalez
> > > ---
> > > drivers/gpu/drm/msm/Makefile | 1 +
> > > drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
> > > drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
> > > drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
> > > drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
> > > drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
> > > 6 files changed, 1118 insertions(+)
> > > create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
> > >
> > > diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> > > index b21ae2880c715..5b5d6aded5233 100644
> > > --- a/drivers/gpu/drm/msm/Makefile
> > > +++ b/drivers/gpu/drm/msm/Makefile
> > > @@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
> > > hdmi/hdmi_phy.o \
> > > hdmi/hdmi_phy_8960.o \
> > > hdmi/hdmi_phy_8996.o \
> > > + hdmi/hdmi_phy_8998.o \
> > > hdmi/hdmi_phy_8x60.o \
> > > hdmi/hdmi_phy_8x74.o \
> > > hdmi/hdmi_pll_8960.o \
> > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > b/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > index c8ebd75176bba..2a2ce49ef5aa3 100644
> > > --- a/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > @@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct
> > > platform_device *pdev)
> > > }
> > >
> > > static const struct of_device_id msm_hdmi_dt_match[] = {
> > > + { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config
> > > },
> >
> > Missing DT bindings.
> >
> > > { .compatible = "qcom,hdmi-tx-8996", .data =
> > > _tx_8974_config },
> > > { .compatible = "qcom,hdmi-tx-8994", .data =
> > > _tx_8974_config },
> > > { .compatible = "qcom,hdmi-tx-8084", .data =
> > > _tx_8974_config },
> > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > b/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > index ec57864403915..cad0d50c82fbc 100644
> > > --- a/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > @@ -137,6 +137,7 @@ enum hdmi_phy_type {
> > > MSM_HDMI_PHY_8960,
> > > MSM_HDMI_PHY_8x74,
> > > MSM_HDMI_PHY_8996,
> > > + MSM_HDMI_PHY_8998,
> > > MSM_HDMI_PHY_MAX,
> > > };
> > >
> > > @@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg
> > > msm_hdmi_phy_8x60_cfg;
> > > extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
> > > extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
> > > extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
> > > +extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
> > >
> > > struct hdmi_phy {
> > > struct platform_device *pdev;
> > > @@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
> > > #ifdef CONFIG_COMMON_CLK
> > > int msm_hdmi_pll_8960_init(struct platform_device *pdev);
> > > int msm_hdmi_pll_8996_init(struct platform_device *pdev);
> > > +int msm_hdmi_pll_8998_init(struct platform_device *pdev);
> > > #else
> > > static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
> > > {
> > > @@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
> > > platform_device *pdev)
> > > {
> > > return -ENODEV;
> > > }
> > > +
> > > +static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
> > > +{
> > > + return -ENODEV;
> > > +}
> > > #endif
> > >
> > > /*
> > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > index 973b460486a5a..c9ca1101b5ad4 100644
> > > --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > @@ -1396,4 +1396,166 @@ static inline uint32_t
> > > HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
> > > #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV
> > > 0x0110
> > >
> > >
> > > +#define REG_HDMI_8998_PHY_CFG 0x
> > > +
> > > +#define REG_HDMI_8998_PHY_PD_CTL 0x0004
> > > +
> > > +#define REG_HDMI_8998_PHY_MODE 0x0010
> > > +
> > > +#define REG_HDMI_8998_PHY_CLOCK
> > > 0x005c
> > > +
> > > +#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
> > > +
> > > +#define REG_HDMI_8998_PHY_STATUS 0x00b4
> > > +
> > > +
> > > +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
> > > +
> > > +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
> > > +
> > > +#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE
[PATCH v5 6/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding
From: Jonathan Marek Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/dsi/dsi_host.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 7252d36687e6..4768cff08381 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -885,7 +885,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_ for setting bits +* +* pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ + if (pkt_per_line > 4) + drm_warn_once(msm_host->dev, "pkt_per_line too big"); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; -- 2.34.1
[PATCH v5 5/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC
From: Jonathan Marek
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 47f5858334f6..7252d36687e6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -857,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
u32 slice_per_intf, total_bytes_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
+ u32 bytes_per_pkt;
/* first calculate dsc parameters and then program
* compress mode registers
@@ -864,6 +865,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
eol_byte_num = total_bytes_per_intf % 3;
@@ -901,6 +903,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL,
reg_ctrl);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2,
reg_ctrl2);
} else {
+ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt);
dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
}
}
--
2.34.1
[PATCH v5 4/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
From: Jonathan Marek
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
driver is doing in video mode. Fix that by actually enabling widebus for
video mode.
Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Reviewed-by: Jessica Zhang
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a50f4dda5941..47f5858334f6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -754,6 +754,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
+ if (msm_dsi_host_is_wide_bus_enabled(_host->base))
+ data |= DSI_VID_CFG0_DATABUS_WIDEN;
dsi_write(msm_host, REG_DSI_VID_CFG0, data);
/* Do not swap RGB colors */
@@ -778,7 +780,6 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3)
data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE;
- /* TODO: Allow for video-mode support once tested/fixed
*/
if (msm_dsi_host_is_wide_bus_enabled(_host->base))
data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
--
2.34.1
[PATCH v5 3/6] drm/msm/dpu: enable compression bit in cfg2 for DSC
Enable compression bit in cfg2 register for DSC in the DSI case Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index f97221423249..34bfcfba3df2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -177,6 +177,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, if (p->wide_bus_en && !dp_intf) data_width = p->width >> 1; + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ + if (p->compression_en && !dp_intf) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; -- 2.34.1
[PATCH v5 2/6] drm/msm/dpu: adjust data width for widen bus case
data is valid for only half the active window if widebus is enabled Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 225c1c7768ff..f97221423249 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -168,6 +168,15 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, data_width = p->width; + /* +* If widebus is enabled, data is valid for only half the active window +* since the data rate is doubled in this mode. But for the compression +* mode in DP case, the p->width is already adjusted in +* drm_mode_to_intf_timing_params() +*/ + if (p->wide_bus_en && !dp_intf) + data_width = p->width >> 1; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; -- 2.34.1
[PATCH v5 1/6] drm/msm/dpu: fix video mode DSC for DSI
From: Jonathan Marek
Add width change in DPU timing for DSC compression case to work with
DSI video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..48cef6e79c70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
return (num_dsc > 0) && (num_dsc > intf_count);
}
-static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
*drm_enc)
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
{
struct msm_drm_private *priv = drm_enc->dev->dev_private;
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 002e89cc1705..2167c46c1a45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
*/
unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+/**
+ * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
+ * This helper function is used by physical encoder to get DSC config
+ * used for this encoder.
+ * @drm_enc: Pointer to encoder structure
+ */
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc);
+
/**
* dpu_encoder_get_drm_fmt - return DRM fourcc format
* @phys_enc: Pointer to physical encoder structure
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ef69c2f408c3..925ec6ada0e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -11,6 +11,7 @@
#include "dpu_trace.h"
#include "disp/msm_disp_snapshot.h"
+#include
#include
#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
@@ -115,6 +116,23 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
}
+
+ /*
+* for DSI, if compression is enabled, then divide the horizonal active
+* timing parameters by compression ratio. bits of 3 components(R/G/B)
+* is compressed into bits of 1 pixel.
+*/
+ if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
+ struct drm_dsc_config *dsc =
+ dpu_encoder_get_dsc_config(phys_enc->parent);
+ /*
+* TODO: replace drm_dsc_get_bpp_int with logic to handle
+* fractional part if there is fraction
+*/
+ timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
+ (dsc->bits_per_component * 3);
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
--
2.34.1
[PATCH v5 0/6] Add DSC support to DSI video panel
This is follow up update to Jonathan's patch set. Changes vs V4: - Polish width calculation with helper function - Split cfg2 compression bit into another patch Changes vs V3: - Rebase to latest msm-next-lumag branch. - Drop the slice_per_pkt change as it does impact basic DSC feature. - Remove change in generated dsi header - update DSC compressed width calculation with bpp and bpc - split wide bus impact on width into another patch - rename patch tile of VIDEO_COMPRESSION_MODE_CTRL_WC change - Polish warning usage - Add tags from reviewers Changes vs V2: - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in latest mainline code. - Drop the bonded DSI patch as I do not have device to test it. - Address comments from version 2. Signed-off-by: Jun Nie --- Changes in v5: - Link to v4: https://lore.kernel.org/r/20240524-msm-drm-dsc-dsi-video-upstream-4-v4-0-e61c05b40...@linaro.org --- Jonathan Marek (4): drm/msm/dpu: fix video mode DSC for DSI drm/msm/dsi: set video mode widebus enable bit when widebus is enabled drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC drm/msm/dsi: add a comment to explain pkt_per_line encoding Jun Nie (2): drm/msm/dpu: adjust data width for widen bus case drm/msm/dpu: enable compression bit in cfg2 for DSC drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 + drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +- 5 files changed, 49 insertions(+), 2 deletions(-) --- base-commit: e6428bcb611f6c164856a41fc5a1ae8471a9b5a9 change-id: 20240524-msm-drm-dsc-dsi-video-upstream-4-22e2266fbe89 Best regards, -- Jun Nie
Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On 27/05/2024 14:11, Dmitry Baryshkov wrote:
On Thu, 23 May 2024 at 18:14, Marc Gonzalez wrote:
From: Arnaud Vrac
Ported from the downstream driver.
Signed-off-by: Arnaud Vrac
Signed-off-by: Marc Gonzalez
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
6 files changed, 1118 insertions(+)
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index b21ae2880c715..5b5d6aded5233 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi_phy.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8996.o \
+ hdmi/hdmi_phy_8998.o \
hdmi/hdmi_phy_8x60.o \
hdmi/hdmi_phy_8x74.o \
hdmi/hdmi_pll_8960.o \
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c8ebd75176bba..2a2ce49ef5aa3 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct platform_device
*pdev)
}
static const struct of_device_id msm_hdmi_dt_match[] = {
+ { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config },
Missing DT bindings.
{ .compatible = "qcom,hdmi-tx-8996", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8994", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = _tx_8974_config },
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index ec57864403915..cad0d50c82fbc 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -137,6 +137,7 @@ enum hdmi_phy_type {
MSM_HDMI_PHY_8960,
MSM_HDMI_PHY_8x74,
MSM_HDMI_PHY_8996,
+ MSM_HDMI_PHY_8998,
MSM_HDMI_PHY_MAX,
};
@@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
+extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
struct hdmi_phy {
struct platform_device *pdev;
@@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
#ifdef CONFIG_COMMON_CLK
int msm_hdmi_pll_8960_init(struct platform_device *pdev);
int msm_hdmi_pll_8996_init(struct platform_device *pdev);
+int msm_hdmi_pll_8998_init(struct platform_device *pdev);
#else
static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
{
@@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
platform_device *pdev)
{
return -ENODEV;
}
+
+static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
+{
+ return -ENODEV;
+}
#endif
/*
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 973b460486a5a..c9ca1101b5ad4 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -1396,4 +1396,166 @@ static inline uint32_t
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x0110
+#define REG_HDMI_8998_PHY_CFG 0x
+
+#define REG_HDMI_8998_PHY_PD_CTL 0x0004
+
+#define REG_HDMI_8998_PHY_MODE 0x0010
+
+#define REG_HDMI_8998_PHY_CLOCK
0x005c
+
+#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
+
+#define REG_HDMI_8998_PHY_STATUS 0x00b4
+
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE 0x0008
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_BG_TIMER 0x000c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_EN_CENTER0x0010
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER1 0x001c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER2 0x0020
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_DIV 0x002c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_DIV_MUX 0x0030
+
+#define
Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On Thu, 23 May 2024 at 18:14, Marc Gonzalez wrote:
>
> From: Arnaud Vrac
>
> Ported from the downstream driver.
>
> Signed-off-by: Arnaud Vrac
> Signed-off-by: Marc Gonzalez
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
> drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
> drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
> drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
> drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
> 6 files changed, 1118 insertions(+)
> create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index b21ae2880c715..5b5d6aded5233 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
> hdmi/hdmi_phy.o \
> hdmi/hdmi_phy_8960.o \
> hdmi/hdmi_phy_8996.o \
> + hdmi/hdmi_phy_8998.o \
> hdmi/hdmi_phy_8x60.o \
> hdmi/hdmi_phy_8x74.o \
> hdmi/hdmi_pll_8960.o \
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
> index c8ebd75176bba..2a2ce49ef5aa3 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi.c
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
> @@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct platform_device
> *pdev)
> }
>
> static const struct of_device_id msm_hdmi_dt_match[] = {
> + { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config },
Missing DT bindings.
> { .compatible = "qcom,hdmi-tx-8996", .data = _tx_8974_config },
> { .compatible = "qcom,hdmi-tx-8994", .data = _tx_8974_config },
> { .compatible = "qcom,hdmi-tx-8084", .data = _tx_8974_config },
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
> index ec57864403915..cad0d50c82fbc 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi.h
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
> @@ -137,6 +137,7 @@ enum hdmi_phy_type {
> MSM_HDMI_PHY_8960,
> MSM_HDMI_PHY_8x74,
> MSM_HDMI_PHY_8996,
> + MSM_HDMI_PHY_8998,
> MSM_HDMI_PHY_MAX,
> };
>
> @@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
> extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
> extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
> extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
> +extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
>
> struct hdmi_phy {
> struct platform_device *pdev;
> @@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
> #ifdef CONFIG_COMMON_CLK
> int msm_hdmi_pll_8960_init(struct platform_device *pdev);
> int msm_hdmi_pll_8996_init(struct platform_device *pdev);
> +int msm_hdmi_pll_8998_init(struct platform_device *pdev);
> #else
> static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
> {
> @@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
> platform_device *pdev)
> {
> return -ENODEV;
> }
> +
> +static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
> +{
> + return -ENODEV;
> +}
> #endif
>
> /*
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> index 973b460486a5a..c9ca1101b5ad4 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> @@ -1396,4 +1396,166 @@ static inline uint32_t
> HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
> #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x0110
>
>
> +#define REG_HDMI_8998_PHY_CFG 0x
> +
> +#define REG_HDMI_8998_PHY_PD_CTL 0x0004
> +
> +#define REG_HDMI_8998_PHY_MODE 0x0010
> +
> +#define REG_HDMI_8998_PHY_CLOCK
> 0x005c
> +
> +#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
> +
> +#define REG_HDMI_8998_PHY_STATUS 0x00b4
> +
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE 0x0008
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_BG_TIMER 0x000c
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_EN_CENTER0x0010
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER1 0x001c
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER2 0x0020
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
> +
> +#define
Re: Build regressions/improvements in v6.10-rc1
On Mon, 27 May 2024, Geert Uytterhoeven wrote:
Below is the list of build error/warning regressions/improvements in
v6.10-rc1[1] compared to v6.9[2].
Summarized:
- build errors: +27/-20
- build warnings: +3/-1601
Happy fixing! ;-)
Thanks to the linux-next team for providing the build service.
[1]
http://kisskb.ellerman.id.au/kisskb/branch/linus/head/1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0/
(all 138 configs)
[2]
http://kisskb.ellerman.id.au/kisskb/branch/linus/head/a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6/
(all 138 configs)
*** ERRORS ***
27 error regressions:
+ /kisskb/src/arch/sparc/prom/p1275.c: error: no previous prototype for
'prom_cif_init' [-Werror=missing-prototypes]: => 52:6
sparc64-gcc13/sparc64-allmodconfig (seen before)
+
/kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c:
error: the frame size of 2192 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]: => 5118:1
+
/kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.c:
error: the frame size of 2280 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]: => 5234:1
+
/kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:
error: the frame size of 2096 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]: => 5188:1
+
/kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:
error: the frame size of 2184 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]: => 3049:1
+
/kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:
error: the frame size of 2264 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]: => 3274:1
+
/kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.c:
error: the frame size of 2232 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]: => 3296:1
+
/kisskb/src/drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.c:
error: the frame size of 2080 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]: => 1646:1
powerpc-gcc5/ppc32_allmodconfig
+ /kisskb/src/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c: error: unknown option
after '#pragma GCC diagnostic' kind [-Werror=pragmas]: => 16:9
+ /kisskb/src/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h: error:
'gen7_9_0_external_core_regs' defined but not used [-Werror=unused-variable]:
=> 1438:19
+ /kisskb/src/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h: error:
'gen7_9_0_sptp_clusters' defined but not used [-Werror=unused-variable]: =>
1188:43
arm64-gcc5/arm64-allmodconfig
powerpc-gcc5/powerpc-all{mod,yes}config
powerpc-gcc5/ppc32_allmodconfig
powerpc-gcc5/ppc64_book3e_allmodconfig
powerpc-gcc5/ppc64le_allmodconfig
sparc64-gcc5/sparc64-allmodconfig
Looks like #pragma "-Wunused-const-variable" is not supported by gcc-5
+ /kisskb/src/drivers/gpu/drm/nouveau/nvif/object.c: error: 'memcpy' accessing
4294967240 or more bytes at offsets 0 and 56 overlaps 6442450833 bytes at offset
-2147483593 [-Werror=restrict]: => 298:17
+ /kisskb/src/drivers/gpu/drm/nouveau/nvif/object.c: error: 'memcpy' accessing
4294967264 or more bytes at offsets 0 and 32 overlaps 6442450881 bytes at offset
-2147483617 [-Werror=restrict]: => 161:9
parisc-gcc13/generic-32bit_defconfig
parisc-gcc13/parisc-{def,allmod}config
+ /kisskb/src/include/linux/kern_levels.h: error: format '%lu' expects argument
of type 'long unsigned int', but argument 4 has type 'unsigned int'
[-Werror=format=]: => 5:18, 5:25
mips-gcc{8,13}/mips-allmodconfig
parisc-gcc13/parisc-allmodconfig
powerpc-gcc{5,13}/ppc32_allmodconfig
sparc64-gcc{5,13}/sparc-allmodconfig
xtensa-gcc13/xtensa-allmodconfig
drivers/scsi/mpi3mr/mpi3mr_transport.c: In function 'mpi3mr_sas_port_add':
drivers/scsi/mpi3mr/mpi3mr_transport.c:1367:62: note: format string is defined
here
ioc_warn(mrioc, "skipping port %u, max allowed value is %lu\n",
~~^
%u
+ /kisskb/src/kernel/bpf/verifier.c: error: ‘pcpu_hot’ undeclared (first use in
this function): => 20317:85
+ /kisskb/src/lib/iomap.c: error: no previous prototype for ‘ioread64_hi_lo’
[-Werror=missing-prototypes]: => 163:5
+ /kisskb/src/lib/iomap.c: error: no previous prototype for ‘ioread64_lo_hi’
[-Werror=missing-prototypes]: => 156:5
+ /kisskb/src/lib/iomap.c: error: no previous prototype for ‘ioread64be_hi_lo’
[-Werror=missing-prototypes]: => 178:5
+ /kisskb/src/lib/iomap.c: error: no previous prototype for ‘ioread64be_lo_hi’
[-Werror=missing-prototypes]: => 170:5
+ /kisskb/src/lib/iomap.c: error: no previous prototype for ‘iowrite64_hi_lo’
[-Werror=missing-prototypes]: => 272:6
+ /kisskb/src/lib/iomap.c: error: no previous prototype for ‘iowrite64_lo_hi’
[-Werror=missing-prototypes]: => 264:6
+
