Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On 27/05/2024 14:11, Dmitry Baryshkov wrote:
On Thu, 23 May 2024 at 18:14, Marc Gonzalez wrote:
From: Arnaud Vrac
Ported from the downstream driver.
Signed-off-by: Arnaud Vrac
Signed-off-by: Marc Gonzalez
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
6 files changed, 1118 insertions(+)
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index b21ae2880c715..5b5d6aded5233 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi_phy.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8996.o \
+ hdmi/hdmi_phy_8998.o \
hdmi/hdmi_phy_8x60.o \
hdmi/hdmi_phy_8x74.o \
hdmi/hdmi_pll_8960.o \
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c8ebd75176bba..2a2ce49ef5aa3 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct platform_device
*pdev)
}
static const struct of_device_id msm_hdmi_dt_match[] = {
+ { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config },
Missing DT bindings.
{ .compatible = "qcom,hdmi-tx-8996", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8994", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = _tx_8974_config },
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index ec57864403915..cad0d50c82fbc 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -137,6 +137,7 @@ enum hdmi_phy_type {
MSM_HDMI_PHY_8960,
MSM_HDMI_PHY_8x74,
MSM_HDMI_PHY_8996,
+ MSM_HDMI_PHY_8998,
MSM_HDMI_PHY_MAX,
};
@@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
+extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
struct hdmi_phy {
struct platform_device *pdev;
@@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
#ifdef CONFIG_COMMON_CLK
int msm_hdmi_pll_8960_init(struct platform_device *pdev);
int msm_hdmi_pll_8996_init(struct platform_device *pdev);
+int msm_hdmi_pll_8998_init(struct platform_device *pdev);
#else
static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
{
@@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
platform_device *pdev)
{
return -ENODEV;
}
+
+static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
+{
+ return -ENODEV;
+}
#endif
/*
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 973b460486a5a..c9ca1101b5ad4 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -1396,4 +1396,166 @@ static inline uint32_t
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x0110
+#define REG_HDMI_8998_PHY_CFG 0x
+
+#define REG_HDMI_8998_PHY_PD_CTL 0x0004
+
+#define REG_HDMI_8998_PHY_MODE 0x0010
+
+#define REG_HDMI_8998_PHY_CLOCK
0x005c
+
+#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
+
+#define REG_HDMI_8998_PHY_STATUS 0x00b4
+
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE 0x0008
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_BG_TIMER 0x000c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_EN_CENTER0x0010
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER1 0x001c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER2 0x0020
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_DIV 0x002c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_D
Re: [Freedreno] [PATCH 02/11] drm/msm/dpu: use the actual lm maximum width instead of a hardcoded value
Le sam. 20 mai 2023 à 22:49, Dmitry Baryshkov a écrit : > > On 20/04/2023 20:47, Jeykumar Sankaran wrote: > > > > > > On 4/19/2023 3:23 PM, Dmitry Baryshkov wrote: > >> On 19/04/2023 17:41, Arnaud Vrac wrote: > >>> This avoids using two LMs instead of one when the display width is lower > >>> than the maximum supported value. For example on MSM8996/MSM8998, the > >>> actual maxwidth is 2560, so we would use two LMs for 1280x720 or > >>> 1920x1080 resolutions, while one is enough. > >>> > >>> Signed-off-by: Arnaud Vrac > >> > >> While this looks correct (and following what we have in 4.4), later > >> vendor kernels specify the topology explicitly. Probably we should > >> check this with the hw guys, because it might be the following case: > >> even though a single LM can supply the mode, it will spend more power > >> compared to two LMs. > >> > >> > > Yes. 2 LM split will allow the HW to run in lower mdp core clock. Can > > you maintain the split_threshold in the hw catalog until per mode > > topology is available? > > I don't think it warrants the trouble, unless we have a real usecase > when the device is short of LMs. > > Arnaud, I'll mark this patch as Rejected for now, unless it fixes an LM > shortage for your platform. It's fine, if I remember correctly I wrote this patch because display wouldn't work before I fixed the LM pairings on msm8998, but now it's not a requirement anymore. > > > > > Jeykumar S > >>> --- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 +- > >>> 1 file changed, 5 insertions(+), 5 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > >>> index 1dc5dbe585723..dd2914726c4f6 100644 > >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > >>> @@ -53,8 +53,6 @@ > >>> #define IDLE_SHORT_TIMEOUT1 > >>> -#define MAX_HDISPLAY_SPLIT 1080 > >>> - > >>> /* timeout in frames waiting for frame done */ > >>> #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 > >>> @@ -568,10 +566,12 @@ static struct msm_display_topology > >>> dpu_encoder_get_topology( > >>>*/ > >>> if (intf_count == 2) > >>> topology.num_lm = 2; > >>> -else if (!dpu_kms->catalog->caps->has_3d_merge) > >>> -topology.num_lm = 1; > >>> +else if (dpu_kms->catalog->caps->has_3d_merge && > >>> + dpu_kms->catalog->mixer_count > 0 && > >>> + mode->hdisplay > dpu_kms->catalog->mixer[0].sblk->maxwidth) > >>> +topology.num_lm = 2; > >>> else > >>> -topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 > >>> : 1; > >>> +topology.num_lm = 1; > >>> if (crtc_state->ctm) > >>> topology.num_dspp = topology.num_lm; > >>> > >> > > -- > With best wishes > Dmitry >
Re: [Freedreno] [PATCH 2/4] drm/msm: add hdmi cec support
Le ven. 21 avr. 2023 à 15:27, Hans Verkuil a écrit : > > Hi Arnaud, > > Some review comments below... Hi Hans, For context, I first based my work on the fbdev driver from Qualcomm a few years ago, on our own CEC framework which does not implement any CEC protocol logic (as android does). At the time I verified that the messages were matching the electrical and protocol spec, using manual tests and a QD882EA analyzer. I also passed HDMI and CEC certs. I simply ported this work more recently to a newer kernel and the media-cec framework, also checking the port that Qualcomm did later on. > On 4/18/23 20:10, Arnaud Vrac wrote: > > Some Qualcomm SoCs that support HDMI also support CEC, including MSM8996 > > and MSM8998. The hardware block can handle a single CEC logical address > > and broadcast messages. > > > > Port the CEC driver from downstream msm-4.4 kernel. It has been tested > > on MSM8998 and passes the cec-compliance tool tests. > > Just to verify: did you run the cec-compliance --test-adapter test? That's > the important one to verify your own driver. Yes, and I also ran the cec-compliance -r 0 with a pulse8 emulating a tv on the bus. Here's the result of cec-compliance --test-adapter: Find remote devices: Polling: OK CEC API: CEC_ADAP_G_CAPS: OK Invalid ioctls: OK CEC_DQEVENT: OK CEC_ADAP_G/S_PHYS_ADDR: OK CEC_ADAP_G/S_LOG_ADDRS: OK CEC_TRANSMIT: OK CEC_RECEIVE: OK CEC_TRANSMIT/RECEIVE (non-blocking): OK (Presumed) CEC_G/S_MODE: OK warn: cec-test-adapter.cpp(1189): Too many transmits (3) without receives SFTs for repeating messages (>= 7): 7: 38, 8: 2 SFTs for newly transmitted messages (>= 5): 6: 2, 7: 17 SFTs for newly transmitted remote messages (>= 5): 6: 20 CEC_EVENT_LOST_MSGS: OK Network topology: [...] Total for hdmi_msm device /dev/cec0: 11, Succeeded: 11, Failed: 0, Warnings: 1 > > > > > Signed-off-by: Arnaud Vrac > > --- > > drivers/gpu/drm/msm/Kconfig | 8 ++ > > drivers/gpu/drm/msm/Makefile| 1 + > > drivers/gpu/drm/msm/hdmi/hdmi.c | 15 ++ > > drivers/gpu/drm/msm/hdmi/hdmi.h | 18 +++ > > drivers/gpu/drm/msm/hdmi/hdmi_cec.c | 280 > > > > 5 files changed, 322 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > > index 85f5ab1d552c4..2a02c74207935 100644 > > --- a/drivers/gpu/drm/msm/Kconfig > > +++ b/drivers/gpu/drm/msm/Kconfig > > @@ -165,3 +165,11 @@ config DRM_MSM_HDMI_HDCP > > default y > > help > > Choose this option to enable HDCP state machine > > + > > +config DRM_MSM_HDMI_CEC > > + bool "Enable HDMI CEC support in MSM DRM driver" > > + depends on DRM_MSM && DRM_MSM_HDMI > > + select CEC_CORE > > + default y > > + help > > + Choose this option to enable CEC support > > diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile > > index 7274c41228ed9..0237a2f219ac2 100644 > > --- a/drivers/gpu/drm/msm/Makefile > > +++ b/drivers/gpu/drm/msm/Makefile > > @@ -131,6 +131,7 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ > > > > msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o > > > > +msm-$(CONFIG_DRM_MSM_HDMI_CEC) += hdmi/hdmi_cec.o > > msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o > > > > msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c > > b/drivers/gpu/drm/msm/hdmi/hdmi.c > > index 3132105a2a433..1dde3890e25c0 100644 > > --- a/drivers/gpu/drm/msm/hdmi/hdmi.c > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c > > @@ -11,6 +11,8 @@ > > #include > > #include > > > > +#include > > + > > #include > > #include "hdmi.h" > > > > @@ -53,6 +55,9 @@ static irqreturn_t msm_hdmi_irq(int irq, void *dev_id) > > if (hdmi->hdcp_ctrl) > > msm_hdmi_hdcp_irq(hdmi->hdcp_ctrl); > > > > + /* Process CEC: */ > > + msm_hdmi_cec_irq(hdmi); > > + > > /* TODO audio.. */ > > > > return IRQ_HANDLED; > > @@ -66,6 +71,8 @@ static void msm_hdmi_destroy(struct hdmi *hdmi) > >*/ > > if (hdmi->workq) > > destroy_workqueue(hdmi->workq); > > + > > + msm_hdmi_cec_exit(hdmi); > > msm_hdmi_hdcp_destroy(hdmi); > > > > if (hdmi->i2c) > > @@ -139,6 +146,8 @@ static int msm_hdmi_init(struct hdmi *hdmi) > >
Re: [Freedreno] [PATCH 04/11] drm/msm/dpu: allow using lm mixer base stage
Le jeu. 20 avr. 2023 à 00:43, Dmitry Baryshkov
a écrit :
>
> On 19/04/2023 17:41, Arnaud Vrac wrote:
> > The dpu backend already handles applying alpha to the base stage, so we
> > can use it to render the bottom plane in all cases. This allows mixing
> > one additional plane with the hardware mixer.
> >
> > Signed-off-by: Arnaud Vrac
>
> This might require additional changes. First, for the STAGE_BASE pipe
> in the source split mode (iow using two LMs) should programmed with
> respect to the right LM's x offset (rather than usual left top-left LM).
> See mdss_mdp_pipe_position_update().
Ok, I did test with 2 LMs and it seems to be working, I'll investigate.
>
> Also this might need some interaction with CTL_MIXER_BORDER_OUT being
> set or not. If I remember correctly, if there bottom plane is not
> fullscreen or if there are no planes at all, we should set
> CTL_MIXER_BORDER_OUT (which takes STAGE_BASE) and start assigning them
> from STAGE0. If not, we can use STAGE_BASE.
I also tested with both fullscreen and non-fullscreen primary plane,
and no plane. I'll check this.
>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index 14b5cfe306113..148921ed62f85 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -881,7 +881,7 @@ static int dpu_plane_atomic_check(struct drm_plane
> > *plane,
> > r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > r_pipe->sspp = NULL;
> >
> > - pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
> > + pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos;
> > if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
> > DPU_ERROR("> %d plane stages assigned\n",
> > pdpu->catalog->caps->max_mixer_blendstages -
> > DPU_STAGE_0);
> >
>
> --
> With best wishes
> Dmitry
>
Re: [Freedreno] [PATCH 2/4] drm/msm: add hdmi cec support
Le jeu. 20 avr. 2023 à 02:20, Dmitry Baryshkov
a écrit :
>
> On 18/04/2023 21:10, Arnaud Vrac wrote:
> > Some Qualcomm SoCs that support HDMI also support CEC, including MSM8996
> > and MSM8998. The hardware block can handle a single CEC logical address
> > and broadcast messages.
> >
> > Port the CEC driver from downstream msm-4.4 kernel. It has been tested
> > on MSM8998 and passes the cec-compliance tool tests.
> >
> > Signed-off-by: Arnaud Vrac
> > ---
> > drivers/gpu/drm/msm/Kconfig | 8 ++
> > drivers/gpu/drm/msm/Makefile| 1 +
> > drivers/gpu/drm/msm/hdmi/hdmi.c | 15 ++
> > drivers/gpu/drm/msm/hdmi/hdmi.h | 18 +++
> > drivers/gpu/drm/msm/hdmi/hdmi_cec.c | 280
> >
> > 5 files changed, 322 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> > index 85f5ab1d552c4..2a02c74207935 100644
> > --- a/drivers/gpu/drm/msm/Kconfig
> > +++ b/drivers/gpu/drm/msm/Kconfig
> > @@ -165,3 +165,11 @@ config DRM_MSM_HDMI_HDCP
> > default y
> > help
> > Choose this option to enable HDCP state machine
> > +
> > +config DRM_MSM_HDMI_CEC
> > + bool "Enable HDMI CEC support in MSM DRM driver"
> > + depends on DRM_MSM && DRM_MSM_HDMI
> > + select CEC_CORE
> > + default y
> > + help
> > + Choose this option to enable CEC support
> > diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> > index 7274c41228ed9..0237a2f219ac2 100644
> > --- a/drivers/gpu/drm/msm/Makefile
> > +++ b/drivers/gpu/drm/msm/Makefile
> > @@ -131,6 +131,7 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
> >
> > msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
> >
> > +msm-$(CONFIG_DRM_MSM_HDMI_CEC) += hdmi/hdmi_cec.o
> > msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
> >
> > msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
> > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c
> > b/drivers/gpu/drm/msm/hdmi/hdmi.c
> > index 3132105a2a433..1dde3890e25c0 100644
> > --- a/drivers/gpu/drm/msm/hdmi/hdmi.c
> > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
> > @@ -11,6 +11,8 @@
> > #include
> > #include
> >
> > +#include
> > +
> > #include
> > #include "hdmi.h"
> >
> > @@ -53,6 +55,9 @@ static irqreturn_t msm_hdmi_irq(int irq, void *dev_id)
> > if (hdmi->hdcp_ctrl)
> > msm_hdmi_hdcp_irq(hdmi->hdcp_ctrl);
> >
> > + /* Process CEC: */
> > + msm_hdmi_cec_irq(hdmi);
> > +
> > /* TODO audio.. */
> >
> > return IRQ_HANDLED;
> > @@ -66,6 +71,8 @@ static void msm_hdmi_destroy(struct hdmi *hdmi)
> >*/
> > if (hdmi->workq)
> > destroy_workqueue(hdmi->workq);
> > +
> > + msm_hdmi_cec_exit(hdmi);
> > msm_hdmi_hdcp_destroy(hdmi);
> >
> > if (hdmi->i2c)
> > @@ -139,6 +146,8 @@ static int msm_hdmi_init(struct hdmi *hdmi)
> > hdmi->hdcp_ctrl = NULL;
> > }
> >
> > + msm_hdmi_cec_init(hdmi);
> > +
> > return 0;
> >
> > fail:
> > @@ -198,6 +207,12 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
> >
> > drm_connector_attach_encoder(hdmi->connector, hdmi->encoder);
> >
> > + if (hdmi->cec_adap) {
> > + struct cec_connector_info conn_info;
> > + cec_fill_conn_info_from_drm(_info, hdmi->connector);
> > + cec_s_conn_info(hdmi->cec_adap, _info);
> > + }
> > +
> > ret = devm_request_irq(dev->dev, hdmi->irq,
> > msm_hdmi_irq, IRQF_TRIGGER_HIGH,
> > "hdmi_isr", hdmi);
> > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h
> > b/drivers/gpu/drm/msm/hdmi/hdmi.h
> > index e8dbee50637fa..c639bd87f4b8f 100644
> > --- a/drivers/gpu/drm/msm/hdmi/hdmi.h
> > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
> > @@ -29,6 +29,7 @@ struct hdmi_audio {
> > };
> >
> > struct hdmi_hdcp_ctrl;
> > +struct cec_adapter;
> >
> > struct hdmi {
> > struct drm_device *dev;
> > @@ -73,6 +74,7 @@ struct hdmi {
> > struct workqueue_struct *workq;
> >
> > struct hdmi_hdcp_ctrl *hdcp_ctrl;
> > + struct cec_adapter *cec_adap;
> >
> > /*
> > * spinlock to protect registers shared by different execution
&g
Re: [Freedreno] [PATCH 11/11] drm/msm/dpu: do not use mixer that supports dspp when not required
Le jeu. 20 avr. 2023 à 01:18, Dmitry Baryshkov
a écrit :
>
> On 19/04/2023 17:41, Arnaud Vrac wrote:
> > This avoids using lm blocks that support DSPP when not needed, to
> > keep those resources available.
>
> This will break some of the platforms. Consider qcm2290 which has a
> single LM with DSPP. So, _dpu_rm_check_lm_and_get_connected_blks should
> be performed in two steps: first skip non-DSPP-enabled LMs when DSPP is
> not required. Then, if the LM (pair) is not found, look for any suitable
> LM(pair).
Good point, I'll add the change.
>
> >
> > Signed-off-by: Arnaud Vrac
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > index f4dda88a73f7d..4b393d46c743f 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > @@ -362,7 +362,7 @@ static bool
> > _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm,
> > *pp_idx = idx;
> >
> > if (!reqs->topology.num_dspp)
> > - return true;
> > + return !lm_cfg->dspp;
> >
> > idx = lm_cfg->dspp - DSPP_0;
> > if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
> >
>
> --
> With best wishes
> Dmitry
>
Re: [Freedreno] [PATCH 07/11] drm/msm/dpu: add sspp cursor blocks to msm8998 hw catalog
Le jeu. 20 avr. 2023 à 01:10, Dmitry Baryshkov
a écrit :
>
> On 19/04/2023 17:41, Arnaud Vrac wrote:
> > Now that cursor sspp blocks can be used for cursor planes, enable them
> > on msm8998. The dma sspp blocks that were assigned to cursor planes can
> > now be used for overlay planes instead.
>
> While the change is correct, there is more about it. Composers, using
> universal planes, will see this plane too. They have no obligations to
> use it only for the cursor. At the minimum could you please extend the
> plane_atomic_check to check for the plane dimensions for the CURSOR pipes?
Hum, I had assumed the generic atomic checks would already do this,
but it's not the case. I'll add the check when the pipe is of type
SSPP_CURSOR in another patch coming before, thanks.
>
> For this change:
>
> Reviewed-by: Dmitry Baryshkov
>
> >
> > Signed-off-by: Arnaud Vrac
> > ---
> > .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8 +++--
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 34
> > ++
> > 2 files changed, 40 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> > index b07e8a9941f79..7de393b0f91d7 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> > @@ -90,10 +90,14 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
> > sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
> > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> > - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac,
> > DMA_CURSOR_MSM8998_MASK,
> > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_MSM8998_MASK,
> > sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> > - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac,
> > DMA_CURSOR_MSM8998_MASK,
> > + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_MSM8998_MASK,
> > sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> > + SSPP_BLK("sspp_12", SSPP_CURSOR0, 0x34000, 0x1ac,
> > DMA_CURSOR_MSM8998_MASK,
> > + msm8998_cursor_sblk_0, 2, SSPP_TYPE_CURSOR,
> > DPU_CLK_CTRL_CURSOR0),
> > + SSPP_BLK("sspp_13", SSPP_CURSOR1, 0x36000, 0x1ac,
> > DMA_CURSOR_MSM8998_MASK,
> > + msm8998_cursor_sblk_1, 10, SSPP_TYPE_CURSOR,
> > DPU_CLK_CTRL_CURSOR1),
> > };
> >
> > static const struct dpu_lm_cfg msm8998_lm[] = {
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index 8d5d782a43398..f34fa704936bc 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -242,6 +242,22 @@ static const uint32_t wb2_formats[] = {
> > DRM_FORMAT_XBGR,
> > };
> >
> > +static const uint32_t cursor_formats[] = {
> > + DRM_FORMAT_ARGB,
> > + DRM_FORMAT_ABGR,
> > + DRM_FORMAT_RGBA,
> > + DRM_FORMAT_BGRA,
> > + DRM_FORMAT_XRGB,
> > + DRM_FORMAT_ARGB1555,
> > + DRM_FORMAT_ABGR1555,
> > + DRM_FORMAT_RGBA5551,
> > + DRM_FORMAT_BGRA5551,
> > + DRM_FORMAT_ARGB,
> > + DRM_FORMAT_ABGR,
> > + DRM_FORMAT_RGBA,
> > + DRM_FORMAT_BGRA,
> > +};
> > +
> > /*
> >* SSPP sub blocks config
> >*/
> > @@ -300,6 +316,19 @@ static const uint32_t wb2_formats[] = {
> > .virt_num_formats = ARRAY_SIZE(plane_formats), \
> > }
> >
> > +#define _CURSOR_SBLK(num) \
> > + { \
> > + .maxdwnscale = SSPP_UNITY_SCALE, \
> > + .maxupscale = SSPP_UNITY_SCALE, \
> > + .smart_dma_priority = 0, \
> > + .src_blk = {.name = STRCAT("sspp_src_", num), \
> > + .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
> > + .format_list = cursor_formats, \
> > + .num_formats = ARRAY_SIZE(cursor_formats), \
> > + .virt_format_list = cursor_formats, \
> > + .virt_num_formats = ARRAY_SIZE(cursor_formats), \
> > + }
> > +
> > static const struct dpu_sspp_sub_blks msm8998_vi
Re: [Freedreno] [PATCH 1/4] drm/msm: add some cec register bitfield details
Le jeu. 20 avr. 2023 à 02:30, Dmitry Baryshkov
a écrit :
>
> On 20/04/2023 03:27, Abhinav Kumar wrote:
> >
> >
> > On 4/19/2023 5:21 PM, Dmitry Baryshkov wrote:
> >> On 20/04/2023 03:17, Abhinav Kumar wrote:
> >>>
> >>>
> >>> On 4/19/2023 5:11 PM, Dmitry Baryshkov wrote:
> >>>> On 20/04/2023 03:10, Abhinav Kumar wrote:
> >>>>>
> >>>>>
> >>>>> On 4/19/2023 4:53 PM, Dmitry Baryshkov wrote:
> >>>>>> On 18/04/2023 21:10, Arnaud Vrac wrote:
> >>>>>>> The register names and bitfields were determined from the downstream
> >>>>>>> msm-4.4 driver.
> >>>>>>>
> >>>>>>> Signed-off-by: Arnaud Vrac
> >>>>>>> ---
> >>>>>>> drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 62
> >>>>>>> -
> >>>>>>> 1 file changed, 61 insertions(+), 1 deletion(-)
> >>>>>>
> >>>>>> I have opened MR against Mesa at
> >>>>>> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22588.
> >>>>>>
> >>>>>> The patch is:
> >>>>>>
> >>>>>> Reviewed-by: Dmitry Baryshkov
> >>>>>>
> >>>>>> Minor nit below
> >>>>>>
> >>>>>
> >>>>> Also, shouldnt the register updates be done using rnn tool instead
> >>>>> of manual edits?
> >>>>
> >>>> We usually update the rnn and ask Rob to pull it at the beginning of
> >>>> the cycle.
> >>>>
> >>>
> >>> Sorry, I didnt get this. So you are saying, we will accept manual
> >>> edits and then replace it with the tool generated xml later? I was
> >>> not aware of that, because previously I was always asked by Rob to
> >>> use the tool to generate the xml and push that.
> >>
> >> We accept manual edits for the patchset (so that one can test it), but
> >> before merging the patchset we ask Rob to pull the xml.
> >>
> >
> > Interesting, and Rob generates the xml that time or who does that?
> >
> > The MR you have created updates the freedreno/registers which is just to
> > keep the XML in the driver and mesa in sync.
> >
> > But I am trying to understand who generates the updated xml to merge it
> > with the patchset if its not the developer who does that anymore.
>
> In this case I went on and created the MR as Arnaud didn't create one.
> Yes, usually we do this on our own when updating the register file (in
> other words: I usually edit the xml, then regen the xml.h, then add it
> to the patchset).
Ok thanks, I wasn't sure in which order to do this, thanks for posting
the MR on mesa. The changes in hdmi.xml.h I posted are not manually
edited, they were generated using the gen_header.py script in mesa (I
omitted the top comments changes about envytools which are not present
anymore though).
>
> >
> >>>
> >>>>>
> >>>>>>>
> >>>>>>> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> >>>>>>> b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> >>>>>>> index 973b460486a5a..b4dd6e8cba6b7 100644
> >>>>>>> --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> >>>>>>> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> >>>>>>> @@ -76,6 +76,13 @@ enum hdmi_acr_cts {
> >>>>>>> ACR_48 = 3,
> >>>>>>> };
> >>>>>>> +enum hdmi_cec_tx_status {
> >>>>>>> +CEC_TX_OK = 0,
> >>>>>>> +CEC_TX_NACK = 1,
> >>>>>>> +CEC_TX_ARB_LOSS = 2,
> >>>>>>> +CEC_TX_MAX_RETRIES = 3,
> >>>>>>> +};
> >>>>>>> +
> >>>>>>> #define REG_HDMI_CTRL0x
> >>>>>>> #define HDMI_CTRL_ENABLE0x0001
> >>>>>>> #define HDMI_CTRL_HDMI0x0002
> >>>>>>> @@ -476,20 +483,73 @@ static inline uint32_t
> >>>>>>> HDMI_DDC_REF_REFTIMER(uint32_t val)
> >>>>>>> #define REG_HDMI_HDCP_SW_LOWER_AKSV0x0288
> >>>>>>> #define REG_HDMI_CEC_CTRL
[Freedreno] [PATCH 11/11] drm/msm/dpu: do not use mixer that supports dspp when not required
This avoids using lm blocks that support DSPP when not needed, to
keep those resources available.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f4dda88a73f7d..4b393d46c743f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -362,7 +362,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct
dpu_rm *rm,
*pp_idx = idx;
if (!reqs->topology.num_dspp)
- return true;
+ return !lm_cfg->dspp;
idx = lm_cfg->dspp - DSPP_0;
if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
--
2.40.0
[Freedreno] [PATCH 10/11] drm/msm/dpu: tweak lm pairings in msm8998 hw catalog
Change lm blocks pairs so that lm blocks with the same features are
paired together:
LM_0 and LM_1 with PP and DSPP
LM_2 and LM_5 with PP
LM_3 and LM_4
This matches the sdm845 configuration and allows using pp or dspp when 2
lm blocks are needed in the topology. In the previous config the
reservation code could never find an lm pair without a matching feature
set.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 5ae1d41e3fa92..90db622eff4fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -102,17 +102,17 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
static const struct dpu_lm_cfg msm8998_lm[] = {
LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
- _lm_sblk, PINGPONG_0, LM_2, DSPP_0),
+ _lm_sblk, PINGPONG_0, LM_1, DSPP_0),
LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
- _lm_sblk, PINGPONG_1, LM_5, DSPP_1),
+ _lm_sblk, PINGPONG_1, LM_0, DSPP_1),
LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
- _lm_sblk, PINGPONG_2, LM_0, 0),
+ _lm_sblk, PINGPONG_2, LM_5, 0),
LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
- _lm_sblk, PINGPONG_3, LM_1, 0),
+ _lm_sblk, PINGPONG_3, LM_2, 0),
};
static const struct dpu_pingpong_cfg msm8998_pp[] = {
--
2.40.0
[Freedreno] [PATCH 06/11] drm/msm/dpu: support cursor sspp hw blocks
Cursor SSPP must be assigned to the last mixer stage, so we assign an
immutable zpos property with a value higher than primary/overlay planes,
to ensure it will always be on top.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 26 +++---
2 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0e7a68714e9e1..6cce0f6cfcb01 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -738,13 +738,22 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
for (i = 0; i < catalog->sspp_count; i++) {
enum drm_plane_type type;
- if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
- && cursor_planes_idx < max_crtc_count)
- type = DRM_PLANE_TYPE_CURSOR;
- else if (primary_planes_idx < max_crtc_count)
+ if (catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) {
+ if (cursor_planes_idx < max_crtc_count) {
+ type = DRM_PLANE_TYPE_CURSOR;
+ } else if (catalog->sspp[i].type == SSPP_TYPE_CURSOR) {
+ /* Cursor SSPP can only be used in the last
+* mixer stage, so it doesn't make sense to
+* assign two of those to the same CRTC */
+ continue;
+ } else {
+ type = DRM_PLANE_TYPE_OVERLAY;
+ }
+ } else if (primary_planes_idx < max_crtc_count) {
type = DRM_PLANE_TYPE_PRIMARY;
- else
+ } else {
type = DRM_PLANE_TYPE_OVERLAY;
+ }
DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
type, catalog->sspp[i].features,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 128ecdc145260..5a7bb8543866c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -881,7 +881,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
r_pipe->sspp = NULL;
- pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos;
+ if (pipe_hw_caps->type == SSPP_TYPE_CURSOR) {
+ /* enforce cursor sspp to use the last mixer stage */
+ pstate->stage = DPU_STAGE_BASE +
+ pdpu->catalog->caps->max_mixer_blendstages;
+ } else {
+ pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos;
+ }
+
if (pstate->stage > DPU_STAGE_BASE +
pdpu->catalog->caps->max_mixer_blendstages) {
DPU_ERROR("> %d plane mixer stages assigned\n",
pdpu->catalog->caps->max_mixer_blendstages);
@@ -1463,6 +1470,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
struct msm_drm_private *priv = dev->dev_private;
struct dpu_kms *kms = to_dpu_kms(priv->kms);
struct dpu_hw_sspp *pipe_hw;
+ const uint64_t *format_modifiers;
uint32_t num_formats;
uint32_t supported_rotations;
int ret = -EINVAL;
@@ -1489,15 +1497,27 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
format_list = pipe_hw->cap->sblk->format_list;
num_formats = pipe_hw->cap->sblk->num_formats;
+ if (pipe_hw->cap->type == SSPP_TYPE_CURSOR)
+ format_modifiers = NULL;
+ else
+ format_modifiers = supported_format_modifiers;
+
ret = drm_universal_plane_init(dev, plane, 0xff, _plane_funcs,
format_list, num_formats,
- supported_format_modifiers, type, NULL);
+ format_modifiers, type, NULL);
if (ret)
goto clean_plane;
pdpu->catalog = kms->catalog;
- ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX);
+ if (pipe_hw->cap->type == SSPP_TYPE_CURSOR) {
+ /* cursor SSPP can only be used in the last mixer stage,
+* enforce it by maxing out the cursor plane zpos */
+ ret = drm_plane_create_zpos_immutable_property(plane,
DPU_ZPOS_MAX);
+ } else {
+ ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX
- 1);
+ }
+
if (ret)
DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
--
2.40.0
[Freedreno] [PATCH 04/11] drm/msm/dpu: allow using lm mixer base stage
The dpu backend already handles applying alpha to the base stage, so we
can use it to render the bottom plane in all cases. This allows mixing
one additional plane with the hardware mixer.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 14b5cfe306113..148921ed62f85 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -881,7 +881,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
r_pipe->sspp = NULL;
- pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
+ pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos;
if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
DPU_ERROR("> %d plane stages assigned\n",
pdpu->catalog->caps->max_mixer_blendstages -
DPU_STAGE_0);
--
2.40.0
[Freedreno] [PATCH 03/11] drm/msm/dpu: use hsync/vsync polarity set by the encoder
Do not override the hsync/vsync polarity passed by the encoder when
setting up intf timings. The same logic was used in both the encoder and
intf code to set the DP and DSI polarities, so those interfaces are not
impacted. However for HDMI, the polarities were overriden to static
values based on the vertical resolution, instead of using the actual
mode polarities.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 84ee2efa9c664..9f05417eb1213 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -104,7 +104,7 @@ static void dpu_hw_intf_setup_timing_engine(struct
dpu_hw_intf *ctx,
u32 active_h_start, active_h_end;
u32 active_v_start, active_v_end;
u32 active_hctl, display_hctl, hsync_ctl;
- u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
+ u32 polarity_ctl, den_polarity;
u32 panel_format;
u32 intf_cfg, intf_cfg2 = 0;
u32 display_data_hctl = 0, active_data_hctl = 0;
@@ -191,19 +191,9 @@ static void dpu_hw_intf_setup_timing_engine(struct
dpu_hw_intf *ctx,
}
den_polarity = 0;
- if (ctx->cap->type == INTF_HDMI) {
- hsync_polarity = p->yres >= 720 ? 0 : 1;
- vsync_polarity = p->yres >= 720 ? 0 : 1;
- } else if (ctx->cap->type == INTF_DP) {
- hsync_polarity = p->hsync_polarity;
- vsync_polarity = p->vsync_polarity;
- } else {
- hsync_polarity = 0;
- vsync_polarity = 0;
- }
polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
- (vsync_polarity << 1) | /* VSYNC Polarity */
- (hsync_polarity << 0); /* HSYNC Polarity */
+ (p->vsync_polarity << 1) | /* VSYNC Polarity */
+ (p->hsync_polarity << 0); /* HSYNC Polarity */
if (!DPU_FORMAT_IS_YUV(fmt))
panel_format = (fmt->bits[C0_G_Y] |
--
2.40.0
[Freedreno] [PATCH 09/11] drm/msm/dpu: set max cursor width to 512x512
Override the default max cursor size reported to userspace of 64x64. MSM8998 hw cursor planes support 512x512 size, and other chips use DMA SSPPs. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 6cce0f6cfcb01..2dd19b7aca0f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1014,6 +1014,9 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms = to_dpu_kms(kms); dev = dpu_kms->dev; + dev->mode_config.cursor_width = 512; + dev->mode_config.cursor_height = 512; + rc = dpu_kms_global_obj_init(dpu_kms); if (rc) return rc; -- 2.40.0
[Freedreno] [PATCH 08/11] drm/msm/dpu: fix cursor block register bit offset in msm8998 hw catalog
This matches the value for both fbdev and sde implementations in the
downstream msm-4.4 repository.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 7de393b0f91d7..5ae1d41e3fa92 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -39,8 +39,8 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = {
.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
- .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 15 },
- .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 15 },
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
},
};
--
2.40.0
[Freedreno] [PATCH 05/11] drm/msm/dpu: allow using all lm mixer stages
The max_mixer_blendstages hw catalog property represents the number of
planes that can be blended by the lm mixer, excluding the base stage, so
adjust the check for the number of currently assigned planes accordingly.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 148921ed62f85..128ecdc145260 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -882,9 +882,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
r_pipe->sspp = NULL;
pstate->stage = DPU_STAGE_BASE + pstate->base.normalized_zpos;
- if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
- DPU_ERROR("> %d plane stages assigned\n",
- pdpu->catalog->caps->max_mixer_blendstages -
DPU_STAGE_0);
+ if (pstate->stage > DPU_STAGE_BASE +
pdpu->catalog->caps->max_mixer_blendstages) {
+ DPU_ERROR("> %d plane mixer stages assigned\n",
+ pdpu->catalog->caps->max_mixer_blendstages);
return -EINVAL;
}
--
2.40.0
[Freedreno] [PATCH 01/11] drm/msm/dpu: tweak msm8998 hw catalog values
Match the values found in the downstream msm-4.4 kernel sde driver.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 +--
2 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 2b3ae84057dfe..b07e8a9941f79 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -134,10 +134,10 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
};
static const struct dpu_intf_cfg msm8998_intf[] = {
- INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
- INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
- INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
- INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+ INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21,
INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_perf_cfg msm8998_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 03f162af1a50b..8d5d782a43398 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -587,12 +587,12 @@ static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3,
3, 3, 3};
static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
{
- .pps = 1088 * 1920 * 30,
+ .pps = 1920 * 1080 * 30,
.ot_limit = 2,
},
{
- .pps = 1088 * 1920 * 60,
- .ot_limit = 6,
+ .pps = 1920 * 1080 * 60,
+ .ot_limit = 4,
},
{
.pps = 3840 * 2160 * 30,
@@ -705,10 +705,7 @@ static const struct dpu_qos_lut_entry msm8998_qos_linear[]
= {
{.fl = 10, .lut = 0x1555b},
{.fl = 11, .lut = 0xb},
{.fl = 12, .lut = 0x1b},
- {.fl = 13, .lut = 0x5b},
- {.fl = 14, .lut = 0},
- {.fl = 1, .lut = 0x1b},
- {.fl = 0, .lut = 0}
+ {.fl = 0, .lut = 0x5b}
};
static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
@@ -730,9 +727,7 @@ static const struct dpu_qos_lut_entry
msm8998_qos_macrotile[] = {
{.fl = 10, .lut = 0x1aaff},
{.fl = 11, .lut = 0x5aaff},
{.fl = 12, .lut = 0x15aaff},
- {.fl = 13, .lut = 0x55aaff},
- {.fl = 1, .lut = 0x1aaff},
- {.fl = 0, .lut = 0},
+ {.fl = 0, .lut = 0x55aaff},
};
static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
--
2.40.0
[Freedreno] [PATCH 07/11] drm/msm/dpu: add sspp cursor blocks to msm8998 hw catalog
Now that cursor sspp blocks can be used for cursor planes, enable them
on msm8998. The dma sspp blocks that were assigned to cursor planes can
now be used for overlay planes instead.
Signed-off-by: Arnaud Vrac
---
.../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 8 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 34 ++
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index b07e8a9941f79..7de393b0f91d7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -90,10 +90,14 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
- SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_MSM8998_MASK,
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
- SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
+ SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_MSM8998_MASK,
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+ SSPP_BLK("sspp_12", SSPP_CURSOR0, 0x34000, 0x1ac,
DMA_CURSOR_MSM8998_MASK,
+ msm8998_cursor_sblk_0, 2, SSPP_TYPE_CURSOR,
DPU_CLK_CTRL_CURSOR0),
+ SSPP_BLK("sspp_13", SSPP_CURSOR1, 0x36000, 0x1ac,
DMA_CURSOR_MSM8998_MASK,
+ msm8998_cursor_sblk_1, 10, SSPP_TYPE_CURSOR,
DPU_CLK_CTRL_CURSOR1),
};
static const struct dpu_lm_cfg msm8998_lm[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8d5d782a43398..f34fa704936bc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -242,6 +242,22 @@ static const uint32_t wb2_formats[] = {
DRM_FORMAT_XBGR,
};
+static const uint32_t cursor_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_RGBA5551,
+ DRM_FORMAT_BGRA5551,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+};
+
/*
* SSPP sub blocks config
*/
@@ -300,6 +316,19 @@ static const uint32_t wb2_formats[] = {
.virt_num_formats = ARRAY_SIZE(plane_formats), \
}
+#define _CURSOR_SBLK(num) \
+ { \
+ .maxdwnscale = SSPP_UNITY_SCALE, \
+ .maxupscale = SSPP_UNITY_SCALE, \
+ .smart_dma_priority = 0, \
+ .src_blk = {.name = STRCAT("sspp_src_", num), \
+ .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
+ .format_list = cursor_formats, \
+ .num_formats = ARRAY_SIZE(cursor_formats), \
+ .virt_format_list = cursor_formats, \
+ .virt_num_formats = ARRAY_SIZE(cursor_formats), \
+ }
+
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
_VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3);
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
@@ -309,6 +338,11 @@ static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
_VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3);
+static const struct dpu_sspp_sub_blks msm8998_cursor_sblk_0 =
+ _CURSOR_SBLK("12");
+static const struct dpu_sspp_sub_blks msm8998_cursor_sblk_1 =
+ _CURSOR_SBLK("13");
+
static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
.rot_maxheight = 1088,
.rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
--
2.40.0
[Freedreno] [PATCH 02/11] drm/msm/dpu: use the actual lm maximum width instead of a hardcoded value
This avoids using two LMs instead of one when the display width is lower than the maximum supported value. For example on MSM8996/MSM8998, the actual maxwidth is 2560, so we would use two LMs for 1280x720 or 1920x1080 resolutions, while one is enough. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1dc5dbe585723..dd2914726c4f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -53,8 +53,6 @@ #define IDLE_SHORT_TIMEOUT 1 -#define MAX_HDISPLAY_SPLIT 1080 - /* timeout in frames waiting for frame done */ #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 @@ -568,10 +566,12 @@ static struct msm_display_topology dpu_encoder_get_topology( */ if (intf_count == 2) topology.num_lm = 2; - else if (!dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm = 1; + else if (dpu_kms->catalog->caps->has_3d_merge && +dpu_kms->catalog->mixer_count > 0 && +mode->hdisplay > dpu_kms->catalog->mixer[0].sblk->maxwidth) + topology.num_lm = 2; else - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + topology.num_lm = 1; if (crtc_state->ctm) topology.num_dspp = topology.num_lm; -- 2.40.0
[Freedreno] [PATCH 00/11] drm/msm/dpu: tweaks for better hardware resources allocation
This series include misc fixes related to hardware resource allocations in the msm dpu driver, some specifically for msm8998 (including hw catalog fixes and cursor sspp support for cursor planes, instead of using Smart DMA pipes). This series has been tested on msm8998 with additional patches to enable hdmi support. The following modetest example command works now; 8 planes can be displayed simultaneously on msm8998 in 1080p, including a cursor plane, using a single LM: modetest -Mmsm -a \ -s 32:1920x1080-60 \ -P 33@87:1920x1080+0+0@XR24 \ -P 39@87:200x200+100+600@AR24 \ -P 45@87:200x200+200+500@AR24 \ -P 51@87:200x200+300+400@AR24 \ -P 57@87:200x200+400+300@AR24 \ -P 63@87:200x200+500+200@AR24 \ -P 69@87:200x200+600+100@AR24 \ -P 81@87:200x200+700+000@AR24 Signed-off-by: Arnaud Vrac --- Arnaud Vrac (11): drm/msm/dpu: tweak msm8998 hw catalog values drm/msm/dpu: use the actual lm maximum width instead of a hardcoded value drm/msm/dpu: use hsync/vsync polarity set by the encoder drm/msm/dpu: allow using lm mixer base stage drm/msm/dpu: allow using all lm mixer stages drm/msm/dpu: support cursor sspp hw blocks drm/msm/dpu: add sspp cursor blocks to msm8998 hw catalog drm/msm/dpu: fix cursor block register bit offset in msm8998 hw catalog drm/msm/dpu: set max cursor width to 512x512 drm/msm/dpu: tweak lm pairings in msm8998 hw catalog drm/msm/dpu: do not use mixer that supports dspp when not required .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h| 28 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 10 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 49 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 16 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 22 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 32 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 7 files changed, 107 insertions(+), 52 deletions(-) --- base-commit: e3342532ecd39bbd9c2ab5b9001cec1589bc37e9 change-id: 20230419-dpu-tweaks-5475305621d9 Best regards, -- Arnaud Vrac
[Freedreno] [PATCH 1/4] drm/msm: add some cec register bitfield details
The register names and bitfields were determined from the downstream
msm-4.4 driver.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 62 -
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 973b460486a5a..b4dd6e8cba6b7 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -76,6 +76,13 @@ enum hdmi_acr_cts {
ACR_48 = 3,
};
+enum hdmi_cec_tx_status {
+ CEC_TX_OK = 0,
+ CEC_TX_NACK = 1,
+ CEC_TX_ARB_LOSS = 2,
+ CEC_TX_MAX_RETRIES = 3,
+};
+
#define REG_HDMI_CTRL 0x
#define HDMI_CTRL_ENABLE 0x0001
#define HDMI_CTRL_HDMI 0x0002
@@ -476,20 +483,73 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
#define REG_HDMI_HDCP_SW_LOWER_AKSV0x0288
#define REG_HDMI_CEC_CTRL 0x028c
+#define HDMI_CEC_CTRL_ENABLE 0x0001
+#define HDMI_CEC_CTRL_SEND_TRIGGER 0x0002
+#define HDMI_CEC_CTRL_FRAME_SIZE__MASK 0x01f0
+#define HDMI_CEC_CTRL_FRAME_SIZE__SHIFT4
+static inline uint32_t HDMI_CEC_CTRL_FRAME_SIZE(uint32_t val)
+{
+ return ((val) << HDMI_CEC_CTRL_FRAME_SIZE__SHIFT) &
HDMI_CEC_CTRL_FRAME_SIZE__MASK;
+}
+#define HDMI_CEC_CTRL_LINE_OE 0x0200
#define REG_HDMI_CEC_WR_DATA 0x0290
+#define HDMI_CEC_WR_DATA_BROADCAST 0x0001
+#define HDMI_CEC_WR_DATA_DATA__MASK0xff00
+#define HDMI_CEC_WR_DATA_DATA__SHIFT 8
+static inline uint32_t HDMI_CEC_WR_DATA_DATA(uint32_t val)
+{
+ return ((val) << HDMI_CEC_WR_DATA_DATA__SHIFT) &
HDMI_CEC_WR_DATA_DATA__MASK;
+}
-#define REG_HDMI_CEC_CEC_RETRANSMIT0x0294
+#define REG_HDMI_CEC_RETRANSMIT
0x0294
+#define HDMI_CEC_RETRANSMIT_ENABLE 0x0001
+#define HDMI_CEC_RETRANSMIT_COUNT__MASK
0x00fe
+#define HDMI_CEC_RETRANSMIT_COUNT__SHIFT 1
+static inline uint32_t HDMI_CEC_RETRANSMIT_COUNT(uint32_t val)
+{
+ return ((val) << HDMI_CEC_RETRANSMIT_COUNT__SHIFT) &
HDMI_CEC_RETRANSMIT_COUNT__MASK;
+}
#define REG_HDMI_CEC_STATUS0x0298
+#define HDMI_CEC_STATUS_BUSY 0x0001
+#define HDMI_CEC_STATUS_TX_FRAME_DONE 0x0008
+#define HDMI_CEC_STATUS_TX_STATUS__MASK
0x00f0
+#define HDMI_CEC_STATUS_TX_STATUS__SHIFT 4
+static inline uint32_t HDMI_CEC_STATUS_TX_STATUS(enum hdmi_cec_tx_status val)
+{
+ return ((val) << HDMI_CEC_STATUS_TX_STATUS__SHIFT) &
HDMI_CEC_STATUS_TX_STATUS__MASK;
+}
#define REG_HDMI_CEC_INT 0x029c
+#define HDMI_CEC_INT_TX_DONE 0x0001
+#define HDMI_CEC_INT_TX_DONE_MASK 0x0002
+#define HDMI_CEC_INT_TX_ERROR 0x0004
+#define HDMI_CEC_INT_TX_ERROR_MASK 0x0008
+#define HDMI_CEC_INT_MONITOR 0x0010
+#define HDMI_CEC_INT_MONITOR_MASK 0x0020
+#define HDMI_CEC_INT_RX_DONE 0x0040
+#define HDMI_CEC_INT_RX_DONE_MASK 0x0080
#define REG_HDMI_CEC_ADDR 0x02a0
#define REG_HDMI_CEC_TIME 0x02a4
+#define HDMI_CEC_TIME_ENABLE 0x0001
+#define HDMI_CEC_TIME_SIGNAL_FREE_TIME__MASK 0xff80
+#define HDMI_CEC_TIME_SIGNAL_FREE_TIME__SHIFT 7
+static inline uint32_t HDMI_CEC_TIME_SIGNAL_FREE_TIME(uint32_t val)
+{
+ return ((val) << HDMI_CEC_TIME_SIGNAL_FREE_TIME__SHIFT) &
HDMI_CEC_TIME_SIGNAL_FREE_TIME__MASK;
+}
#define REG_HDMI_CEC_REFTIMER 0x02a8
+#define HDMI_CEC_REFTIMER_ENABLE 0x0001
+#define HDMI_CEC_REFTIMER_REFTIMER__MASK 0x
+#define HDMI_CEC_REFTIMER_REFTIMER__SHIFT 0
+static inline uint32_t HDMI_CEC_REFTIMER_REFTIMER(uint32_t val)
+{
+ return ((val) << HDMI_CEC_REFTIMER_REFTIMER__SHIFT) &
HDMI_CEC_REFTIMER_REFTIMER__MASK;
+}
#define REG_HDMI_CEC_RD_DATA 0x02ac
--
2.40.0
[Freedreno] [PATCH 2/4] drm/msm: add hdmi cec support
Some Qualcomm SoCs that support HDMI also support CEC, including MSM8996
and MSM8998. The hardware block can handle a single CEC logical address
and broadcast messages.
Port the CEC driver from downstream msm-4.4 kernel. It has been tested
on MSM8998 and passes the cec-compliance tool tests.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/Kconfig | 8 ++
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c | 15 ++
drivers/gpu/drm/msm/hdmi/hdmi.h | 18 +++
drivers/gpu/drm/msm/hdmi/hdmi_cec.c | 280
5 files changed, 322 insertions(+)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 85f5ab1d552c4..2a02c74207935 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -165,3 +165,11 @@ config DRM_MSM_HDMI_HDCP
default y
help
Choose this option to enable HDCP state machine
+
+config DRM_MSM_HDMI_CEC
+ bool "Enable HDMI CEC support in MSM DRM driver"
+ depends on DRM_MSM && DRM_MSM_HDMI
+ select CEC_CORE
+ default y
+ help
+ Choose this option to enable CEC support
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 7274c41228ed9..0237a2f219ac2 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -131,6 +131,7 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
+msm-$(CONFIG_DRM_MSM_HDMI_CEC) += hdmi/hdmi_cec.o
msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 3132105a2a433..1dde3890e25c0 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -11,6 +11,8 @@
#include
#include
+#include
+
#include
#include "hdmi.h"
@@ -53,6 +55,9 @@ static irqreturn_t msm_hdmi_irq(int irq, void *dev_id)
if (hdmi->hdcp_ctrl)
msm_hdmi_hdcp_irq(hdmi->hdcp_ctrl);
+ /* Process CEC: */
+ msm_hdmi_cec_irq(hdmi);
+
/* TODO audio.. */
return IRQ_HANDLED;
@@ -66,6 +71,8 @@ static void msm_hdmi_destroy(struct hdmi *hdmi)
*/
if (hdmi->workq)
destroy_workqueue(hdmi->workq);
+
+ msm_hdmi_cec_exit(hdmi);
msm_hdmi_hdcp_destroy(hdmi);
if (hdmi->i2c)
@@ -139,6 +146,8 @@ static int msm_hdmi_init(struct hdmi *hdmi)
hdmi->hdcp_ctrl = NULL;
}
+ msm_hdmi_cec_init(hdmi);
+
return 0;
fail:
@@ -198,6 +207,12 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi,
drm_connector_attach_encoder(hdmi->connector, hdmi->encoder);
+ if (hdmi->cec_adap) {
+ struct cec_connector_info conn_info;
+ cec_fill_conn_info_from_drm(_info, hdmi->connector);
+ cec_s_conn_info(hdmi->cec_adap, _info);
+ }
+
ret = devm_request_irq(dev->dev, hdmi->irq,
msm_hdmi_irq, IRQF_TRIGGER_HIGH,
"hdmi_isr", hdmi);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index e8dbee50637fa..c639bd87f4b8f 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -29,6 +29,7 @@ struct hdmi_audio {
};
struct hdmi_hdcp_ctrl;
+struct cec_adapter;
struct hdmi {
struct drm_device *dev;
@@ -73,6 +74,7 @@ struct hdmi {
struct workqueue_struct *workq;
struct hdmi_hdcp_ctrl *hdcp_ctrl;
+ struct cec_adapter *cec_adap;
/*
* spinlock to protect registers shared by different execution
@@ -261,4 +263,20 @@ static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl
*hdcp_ctrl) {}
static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
#endif
+/*
+ * cec
+ */
+#ifdef CONFIG_DRM_MSM_HDMI_CEC
+int msm_hdmi_cec_init(struct hdmi *hdmi);
+void msm_hdmi_cec_exit(struct hdmi *hdmi);
+void msm_hdmi_cec_irq(struct hdmi *hdmi);
+#else
+static inline int msm_hdmi_cec_init(struct hdmi *hdmi)
+{
+ return -ENXIO;
+}
+static inline void msm_hdmi_cec_exit(struct hdmi *hdmi) {}
+static inline void msm_hdmi_cec_irq(struct hdmi *hdmi) {}
+#endif
+
#endif /* __HDMI_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_cec.c
b/drivers/gpu/drm/msm/hdmi/hdmi_cec.c
new file mode 100644
index 0..51326e493e5da
--- /dev/null
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_cec.c
@@ -0,0 +1,280 @@
+#include
+#include
+
+#include "hdmi.h"
+
+#define HDMI_CEC_INT_MASK ( \
+ HDMI_CEC_INT_TX_DONE_MASK | \
+ HDMI_CEC_INT_TX_ERROR_MASK | \
+ HDMI_CEC_INT_RX_DONE_MASK)
+
+struct hdmi_cec_ctrl {
+ struct hdmi *hdmi;
+ struct work_struct work;
+ spinlock_t lock;
+ u32 irq_status;
+ u32 tx_status;
+ u32 tx_retran
[Freedreno] [PATCH 3/4] drm/msm: expose edid to hdmi cec adapter
When edid has been read after hpd, pass it to the cec adapter so that it
can extract the physical address of the device on the cec bus.
Invalidate the physical address when hpd is low.
Signed-off-by: Arnaud Vrac
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 ++
drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 17 +
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 9b1391d27ed39..efc3bd4908e83 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include "msm_kms.h"
#include "hdmi.h"
@@ -256,6 +257,7 @@ static struct edid *msm_hdmi_bridge_get_edid(struct
drm_bridge *bridge,
hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE);
edid = drm_get_edid(connector, hdmi->i2c);
+ cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
index bfa827b479897..cb3eb2625ff63 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include "msm_kms.h"
#include "hdmi.h"
@@ -230,15 +231,17 @@ enum drm_connector_status msm_hdmi_bridge_detect(
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;
- enum drm_connector_status stat_gpio, stat_reg;
+ enum drm_connector_status status, stat_gpio, stat_reg;
int retry = 20;
/*
* some platforms may not have hpd gpio. Rely only on the status
* provided by REG_HDMI_HPD_INT_STATUS in this case.
*/
- if (!hdmi->hpd_gpiod)
- return detect_reg(hdmi);
+ if (!hdmi->hpd_gpiod) {
+ status = detect_reg(hdmi);
+ goto out;
+ }
do {
stat_gpio = detect_gpio(hdmi);
@@ -259,5 +262,11 @@ enum drm_connector_status msm_hdmi_bridge_detect(
DBG("hpd gpio tells us: %d", stat_gpio);
}
- return stat_gpio;
+ status = stat_gpio;
+
+out:
+ if (!status)
+ cec_phys_addr_invalidate(hdmi->cec_adap);
+
+ return status;
}
--
2.40.0
[Freedreno] [PATCH 4/4] arm64: dts: qcom: msm8998: add hdmi cec pinctrl nodes
HDMI is not enabled yet on msm8998 so the pinctrl nodes are not
used.
Signed-off-by: Arnaud Vrac
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi
b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index b150437a83558..fb4aa376ef117 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -1312,6 +1312,20 @@ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
drive-strength = <2>;
bias-pull-up;
};
+
+ hdmi_cec_default: hdmi-cec-default-state {
+ pins = "gpio31";
+ function = "hdmi_cec";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hdmi_cec_sleep: hdmi-cec-sleep-state {
+ pins = "gpio31";
+ function = "hdmi_cec";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
remoteproc_mss: remoteproc@408 {
--
2.40.0
[Freedreno] [PATCH 0/4] Support HDMI CEC on Qualcomm SoCs
Some Qualcomm SoCs that support HDMI also support CEC, including MSM8996 and MSM8998. The hardware block can handle a single CEC logical address and broadcast messages. Port the CEC driver from downstream msm-4.4 kernel. It has been tested on MSM8998 and passes the cec-compliance tool tests. The equivalent downstream driver also passed CEC CTS tests using a Quantum Data QD882E analyzer. Some registers bitfield definitions were added to make the code clearer, and those will also be proposed for upstream in the original xml file from which the header was generated, in the mesa project. Note HDMI support is not yet included upstream for MSM8998, I would appreciate if someone can verify this driver at least works on MSM8996, for which adding the pinctrl nodes for CEC should be sufficient. Signed-off-by: Arnaud Vrac --- Arnaud Vrac (4): drm/msm: add some cec register bitfield details drm/msm: add hdmi cec support drm/msm: expose edid to hdmi cec adapter arm64: dts: qcom: msm8998: add hdmi cec pinctrl nodes arch/arm64/boot/dts/qcom/msm8998.dtsi | 14 ++ drivers/gpu/drm/msm/Kconfig| 8 + drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/hdmi/hdmi.c| 15 ++ drivers/gpu/drm/msm/hdmi/hdmi.h| 18 +++ drivers/gpu/drm/msm/hdmi/hdmi.xml.h| 62 +++- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 + drivers/gpu/drm/msm/hdmi/hdmi_cec.c| 280 + drivers/gpu/drm/msm/hdmi/hdmi_hpd.c| 17 +- 9 files changed, 412 insertions(+), 5 deletions(-) --- base-commit: e3342532ecd39bbd9c2ab5b9001cec1589bc37e9 change-id: 20230418-msm8998-hdmi-cec-08b5890bf41e Best regards, -- Arnaud Vrac
Re: [Freedreno] [PATCH 2/2] drm/msm/dpu: add HDMI output support
On Apr 15 20:19, Dmitry Baryshkov wrote:
MSM8998 and the older Qualcomm platforms support HDMI outputs. Now as
DPU encoder is ready, add support for using INTF_HDMI.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e85e3721d2c7..65cce59163a4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -617,6 +617,45 @@ static int _dpu_kms_initialize_displayport(struct
drm_device *dev,
return 0;
}
+static int _dpu_kms_initialize_hdmi(struct drm_device *dev,
+ struct msm_drm_private *priv,
+ struct dpu_kms *dpu_kms)
+{
+ struct drm_encoder *encoder = NULL;
+ struct msm_display_info info;
+ int rc;
+ int i;
+
+ if (!priv->hdmi)
+ return 0;
+
+ encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
+ if (IS_ERR(encoder)) {
+ DPU_ERROR("encoder init failed for HDMI display\n");
+ return PTR_ERR(encoder);
+ }
+
+ memset(, 0, sizeof(info));
Move this where fields are initialized ?
+ rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
+ if (rc) {
+ DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
+ drm_encoder_cleanup(encoder);
+ return rc;
+ }
+
+ info.num_of_h_tiles = 1;
+ info.h_tile_instance[0] = i;
i is uninitialized here, the line can be removed.
With the above changes:
Reviewed-by: Arnaud Vrac
Tested-by: Arnaud Vrac # on msm8998
-Arnaud
+ info.intf_type = INTF_HDMI;
+ rc = dpu_encoder_setup(dev, encoder, );
+ if (rc) {
+ DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
+ encoder->base.id, rc);
+ return rc;
+ }
+
+ return 0;
+}
+
static int _dpu_kms_initialize_writeback(struct drm_device *dev,
struct msm_drm_private *priv, struct dpu_kms *dpu_kms,
const u32 *wb_formats, int n_formats)
@@ -683,6 +722,12 @@ static int _dpu_kms_setup_displays(struct drm_device *dev,
return rc;
}
+ rc = _dpu_kms_initialize_hdmi(dev, priv, dpu_kms);
+ if (rc) {
+ DPU_ERROR("initialize HDMI failed, rc = %d\n", rc);
+ return rc;
+ }
+
/* Since WB isn't a driver check the catalog before initializing */
if (dpu_kms->catalog->wb_count) {
for (i = 0; i < dpu_kms->catalog->wb_count; i++) {
--
2.30.2
Re: [Freedreno] [PATCH 1/2] drm/msm/dpu: simplify intf allocation code
On Apr 15 20:19, Dmitry Baryshkov wrote:
Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess,
which intf type we mean, pass INTF_DSI/INTF_DP directly. This is
required to support HDMI output in DPU, as both DP and HDMI encoders are
DRM_MODE_ENCODER_TMDS. Thus dpu_encoder code can not make a difference
between HDMI and DP outputs.
Reviewed-by: Bjorn Andersson
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Arnaud Vrac
Tested-by: Arnaud Vrac
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 39 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 ++--
3 files changed, 18 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1dc5dbe58572..b34416cbd0f5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -495,7 +495,7 @@ void dpu_encoder_helper_split_config(
hw_mdptop = phys_enc->hw_mdptop;
disp_info = _enc->disp_info;
- if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
+ if (disp_info->intf_type != INTF_DSI)
return;
/**
@@ -1127,7 +1127,7 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
}
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
+ if (dpu_enc->disp_info.intf_type == INTF_DP &&
dpu_enc->cur_master->hw_mdptop &&
dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
@@ -1135,7 +1135,7 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
_dpu_encoder_update_vsync_source(dpu_enc, _enc->disp_info);
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
+ if (dpu_enc->disp_info.intf_type == INTF_DSI &&
!WARN_ON(dpu_enc->num_phys_encs == 0)) {
unsigned bpc = dpu_enc->connector->display_info.bpc;
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
@@ -1977,7 +1977,7 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
phys->ops.handle_post_kickoff(phys);
}
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
+ if (dpu_enc->disp_info.intf_type == INTF_DSI &&
!dpu_encoder_vsync_time(drm_enc, _time)) {
trace_dpu_enc_early_kickoff(DRMID(drm_enc),
ktime_to_ms(wakeup_time));
@@ -2182,7 +2182,7 @@ static int dpu_encoder_virt_add_phys_encs(
}
- if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
+ if (disp_info->intf_type == INTF_WB) {
enc = dpu_encoder_phys_wb_init(params);
if (IS_ERR(enc)) {
@@ -2231,7 +2231,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
{
int ret = 0;
int i = 0;
- enum dpu_intf_type intf_type = INTF_NONE;
struct dpu_enc_phys_init_params phys_params;
if (!dpu_enc) {
@@ -2246,23 +2245,11 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
phys_params.parent = _enc->base;
phys_params.enc_spinlock = _enc->enc_spinlock;
- switch (disp_info->intf_type) {
- case DRM_MODE_ENCODER_DSI:
- intf_type = INTF_DSI;
- break;
- case DRM_MODE_ENCODER_TMDS:
- intf_type = INTF_DP;
- break;
- case DRM_MODE_ENCODER_VIRTUAL:
- intf_type = INTF_WB;
- break;
- }
-
WARN_ON(disp_info->num_of_h_tiles < 1);
DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
- if (disp_info->intf_type != DRM_MODE_ENCODER_VIRTUAL)
+ if (disp_info->intf_type != INTF_WB)
dpu_enc->idle_pc_supported =
dpu_kms->catalog->caps->has_idle_pc;
@@ -2290,11 +2277,11 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
i, controller_id, phys_params.split_role);
phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
-
intf_type,
-
controller_id);
+
disp_info->intf_type,
+ controller_id);
phys_params.wb_idx = dpu_encoder_get_wb(dpu_kms->catalog,
- in
Re: [Freedreno] [PATCH v2 5/6] drm/msm/dpu: drop unused lm_max_width from RM
Hi Dmitry,
Le dim. 16 mai 2021 à 00:58, Dmitry Baryshkov
a écrit :
>
> No code uses lm_max_width from resource manager, so drop it.
I have a pending patch which uses this value to properly determine the
number of LMs to use in the topology. Currently the code uses a
hardcoded value of MAX_HDISPLAY_SPLIT (1080), but in reality I believe
it should be the lm max width (typically 2560). This will avoid using
two LMs to render resolutions like 1280x720 or 1920x1080.
I haven't managed to make hdmi work yet on DPU (testing on MSM8998) so
I'm not ready to send the patch yet, but it doesn't seem to trigger
any error.
-Arnaud
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 4
> 2 files changed, 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index c36700a06ff2..ec4387ad1182 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -88,18 +88,6 @@ int dpu_rm_init(struct dpu_rm *rm,
> goto fail;
> }
> rm->mixer_blks[lm->id - LM_0] = >base;
> -
> - if (!rm->lm_max_width) {
> - rm->lm_max_width = lm->sblk->maxwidth;
> - } else if (rm->lm_max_width != lm->sblk->maxwidth) {
> - /*
> -* Don't expect to have hw where lm max widths differ.
> -* If found, take the min.
> -*/
> - DPU_ERROR("unsupported: lm maxwidth differs\n");
> - if (rm->lm_max_width > lm->sblk->maxwidth)
> - rm->lm_max_width = lm->sblk->maxwidth;
> - }
> }
>
> for (i = 0; i < cat->ctl_count; i++) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index ee90b1233430..0c9113581d71 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -17,14 +17,10 @@ struct dpu_global_state;
> * struct dpu_rm - DPU dynamic hardware resource manager
> * @mixer_blks: array of layer mixer hardware resources
> * @ctl_blks: array of ctl hardware resources
> - * @lm_max_width: cached layer mixer maximum width
> - * @rm_lock: resource manager mutex
> */
> struct dpu_rm {
> struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
> struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
> -
> - uint32_t lm_max_width;
> };
>
> struct dpu_kms;
> --
> 2.30.2
>
> ___
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
___
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