[PATCH v6 6/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding
From: Jonathan Marek Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Signed-off-by: Jun Nie Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8650-HDK Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi_host.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 7252d36687e6..4768cff08381 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -885,7 +885,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_ for setting bits +* +* pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ + if (pkt_per_line > 4) + drm_warn_once(msm_host->dev, "pkt_per_line too big"); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; -- 2.34.1
[PATCH v6 5/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC
From: Jonathan Marek
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 47f5858334f6..7252d36687e6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -857,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
u32 slice_per_intf, total_bytes_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
+ u32 bytes_per_pkt;
/* first calculate dsc parameters and then program
* compress mode registers
@@ -864,6 +865,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
eol_byte_num = total_bytes_per_intf % 3;
@@ -901,6 +903,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL,
reg_ctrl);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2,
reg_ctrl2);
} else {
+ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt);
dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
}
}
--
2.34.1
[PATCH v6 4/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
From: Jonathan Marek
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
driver is doing in video mode. Fix that by actually enabling widebus for
video mode.
Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Reviewed-by: Jessica Zhang
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a50f4dda5941..47f5858334f6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -754,6 +754,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
+ if (msm_dsi_host_is_wide_bus_enabled(_host->base))
+ data |= DSI_VID_CFG0_DATABUS_WIDEN;
dsi_write(msm_host, REG_DSI_VID_CFG0, data);
/* Do not swap RGB colors */
@@ -778,7 +780,6 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3)
data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE;
- /* TODO: Allow for video-mode support once tested/fixed
*/
if (msm_dsi_host_is_wide_bus_enabled(_host->base))
data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
--
2.34.1
[PATCH v6 3/6] drm/msm/dpu: enable compression bit in cfg2 for DSC
Enable compression bit in cfg2 register for DSC in the DSI case
per hardware version.
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 ++-
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 925ec6ada0e1..f2aab3e7c783 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -307,7 +307,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
- _params, fmt);
+ _params, fmt,
+ phys_enc->dpu_kms->catalog->mdss_ver);
phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, _cfg);
/* setup which pp blk will connect to this intf */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index f97221423249..fa6debda0774 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -98,7 +98,8 @@
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct msm_format *fmt)
+ const struct msm_format *fmt,
+ const struct dpu_mdss_version *mdss_ver)
{
struct dpu_hw_blk_reg_map *c = >hw;
u32 hsync_period, vsync_period;
@@ -177,6 +178,11 @@ static void dpu_hw_intf_setup_timing_engine(struct
dpu_hw_intf *intf,
if (p->wide_bus_en && !dp_intf)
data_width = p->width >> 1;
+ /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
+ if (p->compression_en && !dp_intf &&
+ mdss_ver->core_major_ver >= 7)
+ intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
+
hsync_data_start_x = hsync_start_x;
hsync_data_end_x = hsync_start_x + data_width - 1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index f9015c67a574..ef947bf77693 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -81,7 +81,8 @@ struct dpu_hw_intf_cmd_mode_cfg {
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct msm_format *fmt);
+ const struct msm_format *fmt,
+ const struct dpu_mdss_version *mdss_ver);
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_prog_fetch *fetch);
--
2.34.1
[PATCH v6 2/6] drm/msm/dpu: adjust data width for widen bus case
data is valid for only half the active window if widebus is enabled Signed-off-by: Jun Nie Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8650-HDK Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 225c1c7768ff..f97221423249 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -168,6 +168,15 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, data_width = p->width; + /* +* If widebus is enabled, data is valid for only half the active window +* since the data rate is doubled in this mode. But for the compression +* mode in DP case, the p->width is already adjusted in +* drm_mode_to_intf_timing_params() +*/ + if (p->wide_bus_en && !dp_intf) + data_width = p->width >> 1; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; -- 2.34.1
[PATCH v6 1/6] drm/msm/dpu: fix video mode DSC for DSI
From: Jonathan Marek
Add width change in DPU timing for DSC compression case to work with
DSI video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Neil Armstrong # on SM8650-QRD
Tested-by: Neil Armstrong # on SM8650-HDK
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..48cef6e79c70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
return (num_dsc > 0) && (num_dsc > intf_count);
}
-static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
*drm_enc)
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
{
struct msm_drm_private *priv = drm_enc->dev->dev_private;
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 002e89cc1705..2167c46c1a45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
*/
unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+/**
+ * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
+ * This helper function is used by physical encoder to get DSC config
+ * used for this encoder.
+ * @drm_enc: Pointer to encoder structure
+ */
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc);
+
/**
* dpu_encoder_get_drm_fmt - return DRM fourcc format
* @phys_enc: Pointer to physical encoder structure
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ef69c2f408c3..925ec6ada0e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -11,6 +11,7 @@
#include "dpu_trace.h"
#include "disp/msm_disp_snapshot.h"
+#include
#include
#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
@@ -115,6 +116,23 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
}
+
+ /*
+* for DSI, if compression is enabled, then divide the horizonal active
+* timing parameters by compression ratio. bits of 3 components(R/G/B)
+* is compressed into bits of 1 pixel.
+*/
+ if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
+ struct drm_dsc_config *dsc =
+ dpu_encoder_get_dsc_config(phys_enc->parent);
+ /*
+* TODO: replace drm_dsc_get_bpp_int with logic to handle
+* fractional part if there is fraction
+*/
+ timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
+ (dsc->bits_per_component * 3);
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
--
2.34.1
[PATCH v6 0/6] Add DSC support to DSI video panel
This is follow up update to Jonathan's patch set. Changes vs V5: - Add hardware version check for compression bit change in cfg2 register Changes vs V4: - Polish width calculation with helper function - Split cfg2 compression bit into another patch Changes vs V3: - Rebase to latest msm-next-lumag branch. - Drop the slice_per_pkt change as it does impact basic DSC feature. - Remove change in generated dsi header - update DSC compressed width calculation with bpp and bpc - split wide bus impact on width into another patch - rename patch tile of VIDEO_COMPRESSION_MODE_CTRL_WC change - Polish warning usage - Add tags from reviewers Changes vs V2: - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in latest mainline code. - Drop the bonded DSI patch as I do not have device to test it. - Address comments from version 2. Signed-off-by: Jun Nie --- Changes in v6: - Link to v5: https://lore.kernel.org/r/20240527-msm-drm-dsc-dsi-video-upstream-4-v5-0-f797ffba4...@linaro.org Changes in v5: - Link to v4: https://lore.kernel.org/r/20240524-msm-drm-dsc-dsi-video-upstream-4-v4-0-e61c05b40...@linaro.org --- Jonathan Marek (4): drm/msm/dpu: fix video mode DSC for DSI drm/msm/dsi: set video mode widebus enable bit when widebus is enabled drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC drm/msm/dsi: add a comment to explain pkt_per_line encoding Jun Nie (2): drm/msm/dpu: adjust data width for widen bus case drm/msm/dpu: enable compression bit in cfg2 for DSC drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h| 8 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c| 21 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 17 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 ++- drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +- 6 files changed, 56 insertions(+), 5 deletions(-) --- base-commit: e6428bcb611f6c164856a41fc5a1ae8471a9b5a9 change-id: 20240524-msm-drm-dsc-dsi-video-upstream-4-22e2266fbe89 Best regards, -- Jun Nie
Re: [PATCH v5 2/6] drm/msm/dpu: adjust data width for widen bus case
Dmitry Baryshkov 于2024年5月28日周二 08:48写道： > > On Mon, May 27, 2024 at 10:21:48PM +0800, Jun Nie wrote: > > data is valid for only half the active window if widebus > > is enabled > > > > Signed-off-by: Jun Nie > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > index 225c1c7768ff..f97221423249 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > @@ -168,6 +168,15 @@ static void dpu_hw_intf_setup_timing_engine(struct > > dpu_hw_intf *intf, > > > > data_width = p->width; > > > > + /* > > + * If widebus is enabled, data is valid for only half the active > > window > > + * since the data rate is doubled in this mode. But for the > > compression > > + * mode in DP case, the p->width is already adjusted in > > + * drm_mode_to_intf_timing_params() > > Is there any reason for divergence here? Lots of parameters in dpu_hw_intf_setup_timing_engine() is calculated from timing->width, such as hsync_period and display_v_start. So the width cannot be adjusted beforehand in drm_mode_to_intf_timing_params(). Otherwise, we get below error. I guess the interface timing configuration differ in silicon, thus the software shall handle the difference. If we adjust the width beforehand for DSI, we get below error. [6.625446] [drm:dpu_encoder_frame_done_timeout:2469] [dpu error]enc31 frame done timeout [6.642369] [drm:dpu_encoder_phys_vid_wait_for_commit_done:525] [dpu error]vblank timeout: 4200c1 [6.642395] [drm:dpu_kms_wait_for_commit_done:493] [dpu error]wait for commit done returned -110 > > > + */ > > + if (p->wide_bus_en && !dp_intf) > > + data_width = p->width >> 1; > > + > > hsync_data_start_x = hsync_start_x; > > hsync_data_end_x = hsync_start_x + data_width - 1; > > > > > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry
[PATCH v5 6/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding
From: Jonathan Marek Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/dsi/dsi_host.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 7252d36687e6..4768cff08381 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -885,7 +885,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_ for setting bits +* +* pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ + if (pkt_per_line > 4) + drm_warn_once(msm_host->dev, "pkt_per_line too big"); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; -- 2.34.1
[PATCH v5 5/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC
From: Jonathan Marek
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 47f5858334f6..7252d36687e6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -857,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
u32 slice_per_intf, total_bytes_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
+ u32 bytes_per_pkt;
/* first calculate dsc parameters and then program
* compress mode registers
@@ -864,6 +865,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
eol_byte_num = total_bytes_per_intf % 3;
@@ -901,6 +903,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL,
reg_ctrl);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2,
reg_ctrl2);
} else {
+ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt);
dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
}
}
--
2.34.1
[PATCH v5 4/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
From: Jonathan Marek
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
driver is doing in video mode. Fix that by actually enabling widebus for
video mode.
Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Reviewed-by: Jessica Zhang
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a50f4dda5941..47f5858334f6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -754,6 +754,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
+ if (msm_dsi_host_is_wide_bus_enabled(_host->base))
+ data |= DSI_VID_CFG0_DATABUS_WIDEN;
dsi_write(msm_host, REG_DSI_VID_CFG0, data);
/* Do not swap RGB colors */
@@ -778,7 +780,6 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3)
data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE;
- /* TODO: Allow for video-mode support once tested/fixed
*/
if (msm_dsi_host_is_wide_bus_enabled(_host->base))
data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
--
2.34.1
[PATCH v5 3/6] drm/msm/dpu: enable compression bit in cfg2 for DSC
Enable compression bit in cfg2 register for DSC in the DSI case Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index f97221423249..34bfcfba3df2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -177,6 +177,10 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, if (p->wide_bus_en && !dp_intf) data_width = p->width >> 1; + /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ + if (p->compression_en && !dp_intf) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; -- 2.34.1
[PATCH v5 2/6] drm/msm/dpu: adjust data width for widen bus case
data is valid for only half the active window if widebus is enabled Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 225c1c7768ff..f97221423249 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -168,6 +168,15 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, data_width = p->width; + /* +* If widebus is enabled, data is valid for only half the active window +* since the data rate is doubled in this mode. But for the compression +* mode in DP case, the p->width is already adjusted in +* drm_mode_to_intf_timing_params() +*/ + if (p->wide_bus_en && !dp_intf) + data_width = p->width >> 1; + hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; -- 2.34.1
[PATCH v5 1/6] drm/msm/dpu: fix video mode DSC for DSI
From: Jonathan Marek
Add width change in DPU timing for DSC compression case to work with
DSI video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..48cef6e79c70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
return (num_dsc > 0) && (num_dsc > intf_count);
}
-static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
*drm_enc)
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
{
struct msm_drm_private *priv = drm_enc->dev->dev_private;
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 002e89cc1705..2167c46c1a45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
*/
unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+/**
+ * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
+ * This helper function is used by physical encoder to get DSC config
+ * used for this encoder.
+ * @drm_enc: Pointer to encoder structure
+ */
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc);
+
/**
* dpu_encoder_get_drm_fmt - return DRM fourcc format
* @phys_enc: Pointer to physical encoder structure
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ef69c2f408c3..925ec6ada0e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -11,6 +11,7 @@
#include "dpu_trace.h"
#include "disp/msm_disp_snapshot.h"
+#include
#include
#define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \
@@ -115,6 +116,23 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
}
+
+ /*
+* for DSI, if compression is enabled, then divide the horizonal active
+* timing parameters by compression ratio. bits of 3 components(R/G/B)
+* is compressed into bits of 1 pixel.
+*/
+ if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
+ struct drm_dsc_config *dsc =
+ dpu_encoder_get_dsc_config(phys_enc->parent);
+ /*
+* TODO: replace drm_dsc_get_bpp_int with logic to handle
+* fractional part if there is fraction
+*/
+ timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
+ (dsc->bits_per_component * 3);
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
--
2.34.1
[PATCH v5 0/6] Add DSC support to DSI video panel
This is follow up update to Jonathan's patch set. Changes vs V4: - Polish width calculation with helper function - Split cfg2 compression bit into another patch Changes vs V3: - Rebase to latest msm-next-lumag branch. - Drop the slice_per_pkt change as it does impact basic DSC feature. - Remove change in generated dsi header - update DSC compressed width calculation with bpp and bpc - split wide bus impact on width into another patch - rename patch tile of VIDEO_COMPRESSION_MODE_CTRL_WC change - Polish warning usage - Add tags from reviewers Changes vs V2: - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in latest mainline code. - Drop the bonded DSI patch as I do not have device to test it. - Address comments from version 2. Signed-off-by: Jun Nie --- Changes in v5: - Link to v4: https://lore.kernel.org/r/20240524-msm-drm-dsc-dsi-video-upstream-4-v4-0-e61c05b40...@linaro.org --- Jonathan Marek (4): drm/msm/dpu: fix video mode DSC for DSI drm/msm/dsi: set video mode widebus enable bit when widebus is enabled drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC drm/msm/dsi: add a comment to explain pkt_per_line encoding Jun Nie (2): drm/msm/dpu: adjust data width for widen bus case drm/msm/dpu: enable compression bit in cfg2 for DSC drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 + drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +- 5 files changed, 49 insertions(+), 2 deletions(-) --- base-commit: e6428bcb611f6c164856a41fc5a1ae8471a9b5a9 change-id: 20240524-msm-drm-dsc-dsi-video-upstream-4-22e2266fbe89 Best regards, -- Jun Nie
[PATCH v4 5/5] drm/msm/dsi: add a comment to explain pkt_per_line encoding
From: Jonathan Marek Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/dsi/dsi_host.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 7252d36687e6..4768cff08381 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -885,7 +885,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_ for setting bits +* +* pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ + if (pkt_per_line > 4) + drm_warn_once(msm_host->dev, "pkt_per_line too big"); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; -- 2.34.1
[PATCH v4 4/5] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC
From: Jonathan Marek
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 47f5858334f6..7252d36687e6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -857,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
u32 slice_per_intf, total_bytes_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
+ u32 bytes_per_pkt;
/* first calculate dsc parameters and then program
* compress mode registers
@@ -864,6 +865,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
eol_byte_num = total_bytes_per_intf % 3;
@@ -901,6 +903,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL,
reg_ctrl);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2,
reg_ctrl2);
} else {
+ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt);
dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
}
}
--
2.34.1
[PATCH v4 3/5] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
From: Jonathan Marek
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
driver is doing in video mode. Fix that by actually enabling widebus for
video mode.
Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Reviewed-by: Jessica Zhang
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a50f4dda5941..47f5858334f6 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -754,6 +754,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
+ if (msm_dsi_host_is_wide_bus_enabled(_host->base))
+ data |= DSI_VID_CFG0_DATABUS_WIDEN;
dsi_write(msm_host, REG_DSI_VID_CFG0, data);
/* Do not swap RGB colors */
@@ -778,7 +780,6 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3)
data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE;
- /* TODO: Allow for video-mode support once tested/fixed
*/
if (msm_dsi_host_is_wide_bus_enabled(_host->base))
data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
--
2.34.1
[PATCH v4 2/5] drm: adjust data width for widen bus case
data is valid for only half the active window if widebus is enabled Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 2cf1f8c116b5..3d1bc8fa4ca2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -167,6 +167,14 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; data_width = p->width; + /* +* If widebus is enabled, data is valid for only half the active window +* since the data rate is doubled in this mode. But for the compression +* mode in DP case, the p->width is already adjusted in +* drm_mode_to_intf_timing_params() +*/ + if (p->wide_bus_en && !dp_intf) + data_width = p->width >> 1; /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ if (p->compression_en && !dp_intf) -- 2.34.1
[PATCH v4 1/5] drm/msm/dpu: fix video mode DSC for DSI
From: Jonathan Marek
Add necessary DPU timing and control changes for DSC to work with DSI
video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4
4 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..48cef6e79c70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
return (num_dsc > 0) && (num_dsc > intf_count);
}
-static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
*drm_enc)
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
{
struct msm_drm_private *priv = drm_enc->dev->dev_private;
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 002e89cc1705..2167c46c1a45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
*/
unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+/**
+ * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
+ * This helper function is used by physical encoder to get DSC config
+ * used for this encoder.
+ * @drm_enc: Pointer to encoder structure
+ */
+struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc);
+
/**
* dpu_encoder_get_drm_fmt - return DRM fourcc format
* @phys_enc: Pointer to physical encoder structure
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ef69c2f408c3..7047b607ca91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -115,6 +115,19 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
}
+
+ /*
+* for DSI, if compression is enabled, then divide the horizonal active
+* timing parameters by compression ratio. bits of 3 components(R/G/B)
+* is compressed into bits of 1 pixel.
+*/
+ if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
+ struct drm_dsc_config *dsc =
+ dpu_encoder_get_dsc_config(phys_enc->parent);
+ timing->width = timing->width * (dsc->bits_per_pixel >> 4) /
+ (dsc->bits_per_component * 3);
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 225c1c7768ff..2cf1f8c116b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -168,6 +168,10 @@ static void dpu_hw_intf_setup_timing_engine(struct
dpu_hw_intf *intf,
data_width = p->width;
+ /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
+ if (p->compression_en && !dp_intf)
+ intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
+
hsync_data_start_x = hsync_start_x;
hsync_data_end_x = hsync_start_x + data_width - 1;
--
2.34.1
[PATCH v4 0/5] Add DSC support to DSI video panel
This is follow up update to Jonathan's patch set. Changes vs V3: - Rebase to latest msm-next-lumag branch. - Drop the slice_per_pkt change as it does impact basic DSC feature. - Remove change in generated dsi header - update DSC compressed width calculation with bpp and bpc - split wide bus impact on width into another patch - rename patch tile of VIDEO_COMPRESSION_MODE_CTRL_WC change - Polish warning usage - Add tags from reviewers Changes vs V2: - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in latest mainline code. - Drop the bonded DSI patch as I do not have device to test it. - Address comments from version 2. Signed-off-by: Jun Nie --- Jonathan Marek (4): drm/msm/dpu: fix video mode DSC for DSI drm/msm/dsi: set video mode widebus enable bit when widebus is enabled drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC drm/msm/dsi: add a comment to explain pkt_per_line encoding Jun Nie (1): drm: adjust data width for widen bus case drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 13 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +- 5 files changed, 43 insertions(+), 2 deletions(-) --- base-commit: e6428bcb611f6c164856a41fc5a1ae8471a9b5a9 change-id: 20240524-msm-drm-dsc-dsi-video-upstream-4-22e2266fbe89 Best regards, -- Jun Nie
Re: [PATCH v3 3/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC)
Marijn Suijten 于2024年4月9日周二 00:45写道： > > Can we drop (fix video mode DSC) from this patch title? It looks like more > patches are required to get this done, such a mention is more something for > the > cover letter. > > We could also clarify further to "set Word Count for video-mode DSC". > Accepted. video-mode DSC is achieved with the patch set, not this specific patch.
Re: [PATCH v3 6/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1
Dmitry Baryshkov 于2024年4月3日周三 18:51写道： > > On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote: > > > > From: Jonathan Marek > > > > Support slice_per_pkt in msm driver. > > > > Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt" > > comment is incorrect. > > > > Also trim the code to simplify the dsc reference. > > > > Signed-off-by: Jonathan Marek > > Signed-off-by: Jun Nie > > --- > > drivers/gpu/drm/msm/dsi/dsi_host.c | 35 ++- > > 1 file changed, 14 insertions(+), 21 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c > > b/drivers/gpu/drm/msm/dsi/dsi_host.c > > index b0507a42ee6a..0c6f40dbd25c 100644 > > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > > @@ -866,17 +866,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host > > *msm_host, bool is_cmd_mod > > slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); > > > > total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; > > - bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ > > - > > + bytes_per_pkt = dsc->slice_chunk_size * dsc->slice_per_pkt; > > Please don't mix cleanup and functional changes. OK. Will fix this.
Re: [PATCH v3 5/6] drm/display: Add slice_per_pkt for dsc
Dmitry Baryshkov 于2024年4月3日周三 17:41写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > Add variable for slice number of a DSC compression bit stream packet.
> > Its value shall be specified in panel driver, or default value can be set
> > in display controller driver if panel driver does not set it.
>
> This is not a part of the standard. Please justify it.
Right, I read the standard but did not find any details of packet description.
Looks like msm silicon support tuning of number of slice packing per downstream
code.
The slice_per_pkt can be set in the downstream msm device tree. And I test the
values 1 and 2 on vtdr6130 panel and both work. So I guess this is related to
performance or something like that. I will have more test with different panel
to check the impact.
drivers/gpu/drm/panel/panel-raydium-rm692e5.c also mentions to pass new value
to slice_per_pkt.
Hi Konrad,
Do you remember why value 2 is TODO for slice_per_pkt for panel rm692e5?
>
> >
> > Signed-off-by: Jun Nie
> > ---
> > include/drm/display/drm_dsc.h | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/include/drm/display/drm_dsc.h b/include/drm/display/drm_dsc.h
> > index bc90273d06a6..4fac0a2746ae 100644
> > --- a/include/drm/display/drm_dsc.h
> > +++ b/include/drm/display/drm_dsc.h
> > @@ -82,6 +82,10 @@ struct drm_dsc_config {
> > * @bits_per_component: Bits per component to code (8/10/12)
> > */
> > u8 bits_per_component;
> > + /**
> > +* @slice_per_pkt: slice number per DSC bit stream packet
> > +*/
> > + u8 slice_per_pkt;
> > /**
> > * @convert_rgb:
> > * Flag to indicate if RGB - YCoCg conversion is needed
> >
> > --
> > 2.34.1
> >
>
>
> --
> With best wishes
> Dmitry
Re: [PATCH v3 2/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
Dmitry Baryshkov 于2024年4月3日周三 18:10写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > From: Jonathan Marek
> >
> > The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
> > driver is doing in video mode. Fix that by actually enabling widebus for
> > video mode.
> >
> > Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
> > Signed-off-by: Jonathan Marek
> > Signed-off-by: Jun Nie
>
> You have ignored all the review comments that were provided for v1.
> None of the tags were picked up either.
Just find that It was an accident that I cherry-picked wrong patch.
>
> Have you posted this for internal review like I have explicitly asked you?
Sorry, I guess I skipped your word in depression when I read the email.
>
> > ---
> > drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
> > drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
> > 2 files changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > index 2a7d980e12c3..f0b3cdc020a1 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > @@ -231,6 +231,7 @@ static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum
> > dsi_traffic_mode val)
> > #define DSI_VID_CFG0_HSA_POWER_STOP0x0001
> > #define DSI_VID_CFG0_HBP_POWER_STOP0x0010
> > #define DSI_VID_CFG0_HFP_POWER_STOP0x0100
> > +#define DSI_VID_CFG0_DATABUS_WIDEN 0x0200
> > #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x1000
>
> From the top of the file:
>
> /* Autogenerated file, DO NOT EDIT manually!
This is my fault, I did not notice the top of this file totally. Will
fix it in next version.
>
> >
> > #define REG_DSI_VID_CFG1 0x001c
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > index 9d86a6aca6f2..2a0422cad6de 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -754,6 +754,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host
> > *msm_host,
> > data |=
> > DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
> > data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
> > data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
> > + if (msm_dsi_host_is_wide_bus_enabled(_host->base))
> > + data |= DSI_VID_CFG0_DATABUS_WIDEN;
> > dsi_write(msm_host, REG_DSI_VID_CFG0, data);
> >
> > /* Do not swap RGB colors */
> >
> > --
> > 2.34.1
> >
>
>
> --
> With best wishes
> Dmitry
Re: [PATCH v3 1/6] drm/msm/dpu: fix video mode DSC for DSI
Dmitry Baryshkov 于2024年4月3日周三 17:57写道：
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> >
> > From: Jonathan Marek
> >
> > Add necessary DPU timing and control changes for DSC to work with DSI
> > video mode.
> >
> > Signed-off-by: Jonathan Marek
> > Signed-off-by: Jun Nie
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > index d9e7dbf0499c..c7b009a60b63 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > @@ -115,6 +115,15 @@ static void drm_mode_to_intf_timing_params(
> > timing->h_front_porch = timing->h_front_porch >> 1;
> > timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
> > }
> > +
> > + /*
> > +* for DSI, if compression is enabled, then divide the horizonal
> > active
> > +* timing parameters by compression ratio.
> > +*/
> > + if (phys_enc->hw_intf->cap->type != INTF_DP &&
> > timing->compression_en) {
> > + timing->width = timing->width / 3; /* XXX: don't assume 3:1
> > compression ratio */
> > + timing->xres = timing->width;
> > + }
> > }
> >
> > static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params
> > *timing)
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > index 965692ef7892..079efb48db05 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > @@ -167,6 +167,14 @@ static void dpu_hw_intf_setup_timing_engine(struct
> > dpu_hw_intf *ctx,
> > intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
> >
> > data_width = p->width;
> > + if (p->wide_bus_en && !dp_intf)
> > + data_width = p->width >> 1;
>
> How is wide_bus relevant to the DSC case?
> Is there a need for the Fixes tag?
48bit bus width should be used when DSC is enabled. Without the
widebus configuration,
a lot dsi error happens as below in DSC case.
[ 206.275992] dsi_err_worker: status=4
For the Fixes tag, the previous patch mentioned to enable the widebus
mode for any DSC case. So it is fair to add the tag.
>
> > +
> > + if (p->compression_en)
> > + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
> > +
> > + if (p->compression_en && dp_intf)
> > + DPU_ERROR("missing adjustments for DSC+DP\n");
> >
> > hsync_data_start_x = hsync_start_x;
> > hsync_data_end_x = hsync_start_x + data_width - 1;
> >
> > --
> > 2.34.1
> >
>
>
> --
> With best wishes
> Dmitry
Re: [PATCH v3 0/6] Add DSC support to DSI video panel
Dmitry Baryshkov 于2024年4月3日周三 17:49写道： > > On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote: > > > > This is follow up update to Jonathan's patch set. > > > > Changes vs V2: > > - Rebase to latest mainline. > > - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in > > latest mainline code. > > - Drop the bonded DSI patch as I do not have device to test it. > > - Address comments from version 2. > > Which comments? "Adress comments" is the worst case of changelog. Adopted. Will add more details in next version. > > Also, what do you consider as version 2? Jonathan Marek has only sent v1. It's wired. I see v2 in patch title of below link. Just notice that there is v1 in the link address. https://patchwork.freedesktop.org/patch/567518/?series=126430=1 > > > > > Signed-off-by: Jun Nie > > --- > > Jonathan Marek (5): > > drm/msm/dpu: fix video mode DSC for DSI > > drm/msm/dsi: set video mode widebus enable bit when widebus is enabled > > drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC) > > drm/msm/dsi: add a comment to explain pkt_per_line encoding > > drm/msm/dsi: support DSC configurations with slice_per_pkt > 1 > > > > Jun Nie (1): > > drm/display: Add slice_per_pkt for dsc > > > > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 8 + > > drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + > > drivers/gpu/drm/msm/dsi/dsi_host.c | 42 > > +++--- > > include/drm/display/drm_dsc.h | 4 +++ > > 5 files changed, 44 insertions(+), 20 deletions(-) > > --- > > base-commit: b1e6ec0a0fd0252af046e542f91234cd6c30b2cb > > change-id: 20240403-msm-drm-dsc-dsi-video-upstream-1156d110a53d > > > > Best regards, > > -- > > Jun Nie > > > > > -- > With best wishes > Dmitry
[PATCH v3 6/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1
From: Jonathan Marek
Support slice_per_pkt in msm driver.
Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
comment is incorrect.
Also trim the code to simplify the dsc reference.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 35 ++-
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b0507a42ee6a..0c6f40dbd25c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -866,17 +866,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
- bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
-
+ bytes_per_pkt = dsc->slice_chunk_size * dsc->slice_per_pkt;
eol_byte_num = total_bytes_per_intf % 3;
- /*
-* Typically, pkt_per_line = slice_per_intf * slice_per_pkt.
-*
-* Since the current driver only supports slice_per_pkt = 1,
-* pkt_per_line will be equal to slice per intf for now.
-*/
- pkt_per_line = slice_per_intf;
+ pkt_per_line = slice_per_intf / dsc->slice_per_pkt;
if (is_cmd_mode) /* packet data type */
reg =
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -916,6 +909,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
struct drm_display_mode *mode = msm_host->mode;
+ struct drm_dsc_config *dsc = msm_host->dsc;
u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
u32 h_total = mode->htotal;
u32 v_total = mode->vtotal;
@@ -947,8 +941,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
hdisplay /= 2;
}
- if (msm_host->dsc) {
- struct drm_dsc_config *dsc = msm_host->dsc;
+ if (dsc) {
u32 bytes_per_pclk;
/* update dsc params with timing params */
@@ -988,14 +981,14 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
else
bytes_per_pclk = 3;
- hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk);
+ hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(dsc),
bytes_per_pclk);
h_total += hdisplay;
ha_end = ha_start + hdisplay;
}
if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
- if (msm_host->dsc)
+ if (dsc)
dsi_update_dsc_timing(msm_host, false, mode->hdisplay);
dsi_write(msm_host, REG_DSI_ACTIVE_H,
@@ -1016,21 +1009,17 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
} else {/* command mode */
- if (msm_host->dsc)
+ if (dsc)
dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
/* image data and 1 byte write_memory_start cmd */
- if (!msm_host->dsc)
+ if (!dsc)
wc = hdisplay *
mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1;
else
/*
* When DSC is enabled, WC = slice_chunk_size *
slice_per_pkt + 1.
-* Currently, the driver only supports default value of
slice_per_pkt = 1
-*
-* TODO: Expand mipi_dsi_device struct to hold
slice_per_pkt info
-* and adjust DSC math to account for
slice_per_pkt.
*/
- wc = msm_host->dsc->slice_chunk_size + 1;
+ wc = dsc->slice_chunk_size * dsc->slice_per_pkt + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
@@ -1657,8 +1646,12 @@ static int dsi_host_attach(struct mipi_dsi_host *host,
msm_host->lanes = dsi->lanes;
msm_host->format = dsi->format;
msm_host->mode_flags = dsi->mode_flags;
- if (dsi->dsc)
+ if (dsi->dsc) {
msm_host->dsc = dsi->dsc;
+ /* for backwards compatibility, assume 1 if not set */
+ if (!dsi->dsc->slice_per_pkt)
+ dsi->
[PATCH v3 5/6] drm/display: Add slice_per_pkt for dsc
Add variable for slice number of a DSC compression bit stream packet.
Its value shall be specified in panel driver, or default value can be set
in display controller driver if panel driver does not set it.
Signed-off-by: Jun Nie
---
include/drm/display/drm_dsc.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/drm/display/drm_dsc.h b/include/drm/display/drm_dsc.h
index bc90273d06a6..4fac0a2746ae 100644
--- a/include/drm/display/drm_dsc.h
+++ b/include/drm/display/drm_dsc.h
@@ -82,6 +82,10 @@ struct drm_dsc_config {
* @bits_per_component: Bits per component to code (8/10/12)
*/
u8 bits_per_component;
+ /**
+* @slice_per_pkt: slice number per DSC bit stream packet
+*/
+ u8 slice_per_pkt;
/**
* @convert_rgb:
* Flag to indicate if RGB - YCoCg conversion is needed
--
2.34.1
[PATCH v3 4/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding
From: Jonathan Marek Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/dsi/dsi_host.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 80ea4f1d8274..b0507a42ee6a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -886,7 +886,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_ for setting bits +* +* pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ + if (pkt_per_line > 4) + drm_warn(msm_host->dev, "pkt_per_line too big"); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; -- 2.34.1
[PATCH v3 3/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC)
From: Jonathan Marek
Video mode DSC won't work if this field is not set correctly. Set it to fix
video mode DSC (for slice_per_pkt==1 cases at least).
Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration")
Signed-off-by: Jonathan Marek
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 2a0422cad6de..80ea4f1d8274 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -858,6 +858,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
u32 slice_per_intf, total_bytes_per_intf;
u32 pkt_per_line;
u32 eol_byte_num;
+ u32 bytes_per_pkt;
/* first calculate dsc parameters and then program
* compress mode registers
@@ -865,6 +866,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
+ bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
eol_byte_num = total_bytes_per_intf % 3;
@@ -902,6 +904,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host
*msm_host, bool is_cmd_mod
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL,
reg_ctrl);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2,
reg_ctrl2);
} else {
+ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt);
dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
}
}
--
2.34.1
[PATCH v3 2/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled
From: Jonathan Marek
The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
driver is doing in video mode. Fix that by actually enabling widebus for
video mode.
Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI")
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 2a7d980e12c3..f0b3cdc020a1 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -231,6 +231,7 @@ static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum
dsi_traffic_mode val)
#define DSI_VID_CFG0_HSA_POWER_STOP0x0001
#define DSI_VID_CFG0_HBP_POWER_STOP0x0010
#define DSI_VID_CFG0_HFP_POWER_STOP0x0100
+#define DSI_VID_CFG0_DATABUS_WIDEN 0x0200
#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x1000
#define REG_DSI_VID_CFG1 0x001c
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 9d86a6aca6f2..2a0422cad6de 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -754,6 +754,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
+ if (msm_dsi_host_is_wide_bus_enabled(_host->base))
+ data |= DSI_VID_CFG0_DATABUS_WIDEN;
dsi_write(msm_host, REG_DSI_VID_CFG0, data);
/* Do not swap RGB colors */
--
2.34.1
[PATCH v3 1/6] drm/msm/dpu: fix video mode DSC for DSI
From: Jonathan Marek
Add necessary DPU timing and control changes for DSC to work with DSI
video mode.
Signed-off-by: Jonathan Marek
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d9e7dbf0499c..c7b009a60b63 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -115,6 +115,15 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
}
+
+ /*
+* for DSI, if compression is enabled, then divide the horizonal active
+* timing parameters by compression ratio.
+*/
+ if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) {
+ timing->width = timing->width / 3; /* XXX: don't assume 3:1
compression ratio */
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 965692ef7892..079efb48db05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -167,6 +167,14 @@ static void dpu_hw_intf_setup_timing_engine(struct
dpu_hw_intf *ctx,
intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
data_width = p->width;
+ if (p->wide_bus_en && !dp_intf)
+ data_width = p->width >> 1;
+
+ if (p->compression_en)
+ intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
+
+ if (p->compression_en && dp_intf)
+ DPU_ERROR("missing adjustments for DSC+DP\n");
hsync_data_start_x = hsync_start_x;
hsync_data_end_x = hsync_start_x + data_width - 1;
--
2.34.1
[PATCH v3 0/6] Add DSC support to DSI video panel
This is follow up update to Jonathan's patch set. Changes vs V2: - Rebase to latest mainline. - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in latest mainline code. - Drop the bonded DSI patch as I do not have device to test it. - Address comments from version 2. Signed-off-by: Jun Nie --- Jonathan Marek (5): drm/msm/dpu: fix video mode DSC for DSI drm/msm/dsi: set video mode widebus enable bit when widebus is enabled drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC) drm/msm/dsi: add a comment to explain pkt_per_line encoding drm/msm/dsi: support DSC configurations with slice_per_pkt > 1 Jun Nie (1): drm/display: Add slice_per_pkt for dsc .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 8 + drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 42 +++--- include/drm/display/drm_dsc.h | 4 +++ 5 files changed, 44 insertions(+), 20 deletions(-) --- base-commit: b1e6ec0a0fd0252af046e542f91234cd6c30b2cb change-id: 20240403-msm-drm-dsc-dsi-video-upstream-1156d110a53d Best regards, -- Jun Nie
Re: [PATCH 1/3] drm/msm/dpu: fix DSC for DSI video mode
Dmitry Baryshkov 于2024年3月28日周四 23:05写道： > > On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote: > > > > Fix DSC timing and control configurations in DPU for DSI video mode. > > Only compression ratio 3:1 is handled and tested. > > > > This patch is modified from patchs of Jonathan Marek. > > > > Signed-off-by: Jun Nie > > This almost looks like a joke, except it isn't the 1st of April yet. > The patch lacks proper Author / Sign-off tags from Jonathan. > This is pretty close to copyright infringement. I'm sorry, but I'd > have to ask you to abstain from sending patches w/o prior internal > review. Thanks for pointing me the previous version. I am not aware of it actually. The only version I knew is from internal repo. It is my fault. I see the slides says that Jonathan does not want to disturbed, so only his name is mentioned in the commit message. What's the patch set status? I do not see it in mainline yet. If it is in pipeline, I can just forget the DPU side change. Thanks! Jun > > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- > > .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +++- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + > > drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + > > drivers/gpu/drm/msm/dsi/dsi_host.c| 48 +++ > > include/drm/display/drm_dsc.h | 4 ++ > > Ok. The feedback for the original patchset [1] was that it should be > split logically. Instead you pile everything together into a single > patch. This is a complete no-go. > > Also, this patchset lacks changelog in comparison to the previous > patchseris. I don't think I'll continue the review of this patch. > Please rework it properly and add corresponding changelog. > > [1] https://patchwork.freedesktop.org/patch/567518/?series=126430=1 > > > 8 files changed, 56 insertions(+), 24 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > > index 6a4b489d44e5..c1b9da06dde2 100644 > > -- > With best wishes > Dmitry
[PATCH 3/3] drm/panel: Enable DSC for Visionox VTDR6130 panel
Enable display compression (DSC v1.2) for 1080x2400 Visionox
VTDR6130 AMOLED DSI panel. DTS property is needed to enable DSC.
Default configuration is video mode + non-DSC for any back
compatibility.
Below modes works on SM8650. While cmd mode does not work yet.
- video mode + DSC
- video mode
- cmd mode + DSC
Signed-off-by: Jun Nie
---
.../gpu/drm/panel/panel-visionox-vtdr6130.c | 58 ++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c
b/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c
index 540099253e1b..d6c44816cdd0 100644
--- a/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c
+++ b/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c
@@ -9,6 +9,7 @@
#include
#include
+#include
#include
#include
#include
@@ -17,9 +18,12 @@
struct visionox_vtdr6130 {
struct drm_panel panel;
+ struct drm_dsc_config dsc;
struct mipi_dsi_device *dsi;
struct gpio_desc *reset_gpio;
struct regulator_bulk_data supplies[3];
+ bool cmd_mode;
+ bool dsc_enable;
};
static inline struct visionox_vtdr6130 *to_visionox_vtdr6130(struct drm_panel
*panel)
@@ -49,12 +53,20 @@ static int visionox_vtdr6130_on(struct visionox_vtdr6130
*ctx)
if (ret)
return ret;
+ if (ctx->dsc_enable)
+ mipi_dsi_dcs_write_seq(dsi, 0x03, 0x01);
+
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0x00,
0x00);
mipi_dsi_dcs_write_seq(dsi, 0x59, 0x09);
mipi_dsi_dcs_write_seq(dsi, 0x6c, 0x01);
mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x00);
- mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x01);
+
+ if (ctx->cmd_mode)
+ mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x02);
+ else
+ mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x01);
+
mipi_dsi_dcs_write_seq(dsi, 0x70,
0x12, 0x00, 0x00, 0xab, 0x30, 0x80, 0x09, 0x60,
0x04,
0x38, 0x00, 0x28, 0x02, 0x1c, 0x02, 0x1c, 0x02,
0x00,
@@ -205,6 +217,26 @@ static const struct drm_display_mode
visionox_vtdr6130_mode = {
.height_mm = 157,
};
+static int visionox_vtdr6130_enable(struct drm_panel *panel)
+{
+ struct visionox_vtdr6130 *ctx = to_visionox_vtdr6130(panel);
+ struct mipi_dsi_device *dsi = ctx->dsi;
+ struct drm_dsc_picture_parameter_set pps;
+ int ret;
+
+ if (!dsi->dsc)
+ return 0;
+
+ drm_dsc_pps_payload_pack(, dsi->dsc);
+ ret = mipi_dsi_picture_parameter_set(dsi, );
+ if (ret) {
+ dev_err(>dev, "Failed to set PPS\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int visionox_vtdr6130_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
@@ -228,6 +260,7 @@ static const struct drm_panel_funcs
visionox_vtdr6130_panel_funcs = {
.prepare = visionox_vtdr6130_prepare,
.unprepare = visionox_vtdr6130_unprepare,
.get_modes = visionox_vtdr6130_get_modes,
+ .enable = visionox_vtdr6130_enable,
};
static int visionox_vtdr6130_bl_update_status(struct backlight_device *bl)
@@ -260,12 +293,32 @@ static int visionox_vtdr6130_probe(struct mipi_dsi_device
*dsi)
{
struct device *dev = >dev;
struct visionox_vtdr6130 *ctx;
+ struct drm_dsc_config *dsc;
int ret;
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
+ ctx->cmd_mode = of_property_read_bool(dev->of_node, "enforce-cmd-mode");
+ ctx->dsc_enable = of_property_read_bool(dev->of_node, "enable-dsc");
+
+ /* Set DSC params */
+ if (ctx->dsc_enable) {
+ dsc = >dsc;
+ dsc->dsc_version_major = 0x1;
+ dsc->dsc_version_minor = 0x2;
+ dsc->slice_height = 40;
+ dsc->slice_width = 540;
+ dsc->slice_count = 2;
+ dsc->slice_per_pkt = 1;
+ dsc->bits_per_component = 8;
+ dsc->bits_per_pixel = 8 << 4;
+ dsc->block_pred_enable = true;
+
+ dsi->dsc = dsc;
+ }
+
ctx->supplies[0].supply = "vddio";
ctx->supplies[1].supply = "vci";
ctx->supplies[2].supply = "vdd";
@@ -306,6 +359,9 @@ static int visionox_vtdr6130_probe(struct mipi_dsi_device
*dsi)
return ret;
}
+ dev_err(>dev, "discovered with %s mode %s\n",
+ ctx->cmd_mode ? "cmd" : "video",
+ ctx->dsc_enable ? "and DSC enabled" : "");
return 0;
}
--
2.34.1
[PATCH 2/3] dt-bindings: display: panel: visionox, vtdr6130: Add mode property
Add DSI mode property and compression mode property Signed-off-by: Jun Nie --- .../bindings/display/panel/visionox,vtdr6130.yaml | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml b/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml index d5a8295106c1..36ae94fa96ec 100644 --- a/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml +++ b/Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml @@ -26,6 +26,14 @@ properties: port: true reset-gpios: true + enforce-cmd-mode: +type: boolean +description: Set DSI as command mode. Video mode by default. + + enable-dsc: +type: boolean +description: Enable display stream compression + additionalProperties: false required: -- 2.34.1
[PATCH 1/3] drm/msm/dpu: fix DSC for DSI video mode
Fix DSC timing and control configurations in DPU for DSI video mode.
Only compression ratio 3:1 is handled and tested.
This patch is modified from patchs of Jonathan Marek.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c| 48 +++
include/drm/display/drm_dsc.h | 4 ++
8 files changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6a4b489d44e5..c1b9da06dde2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2440,7 +2440,7 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct
drm_encoder *encoder)
return INTF_MODE_NONE;
}
-unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
+unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys
*phys_enc)
{
struct drm_encoder *encoder = phys_enc->parent;
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 993f26343331..5000fa22ad40 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -339,7 +339,7 @@ static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
* used for this encoder.
* @phys_enc: Pointer to physical encoder structure
*/
-unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys
*phys_enc);
/**
* dpu_encoder_helper_split_config - split display configuration helper
function
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d0f56c5c4cce..c0ff39450e66 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -102,6 +102,8 @@ static void drm_mode_to_intf_timing_params(
}
timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+ if (dpu_encoder_helper_get_dsc(phys_enc))
+ timing->dsc_en = true;
/*
* for DP, divide the horizonal parameters by 2 when
@@ -114,6 +116,16 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
}
+
+ /*
+* for DSI, if compression is enabled, then divide the horizonal active
+* timing parameters by compression ratio.
+*/
+ if (phys_enc->hw_intf->cap->type != INTF_DP && timing->dsc_en) {
+ /* TODO: handle non 3:1 compression ratio, such as 30bpp case */
+ timing->width = timing->width / 3;
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 6bba531d6dc4..e2f6fa542883 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -168,10 +168,18 @@ static void dpu_hw_intf_setup_timing_engine(struct
dpu_hw_intf *ctx,
* video timing. It is recommended to enable it for all cases, except
* if compression is enabled in 1 pixel per clock mode
*/
+ if (!p->dsc_en || p->wide_bus_en)
+ intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN;
+
if (p->wide_bus_en)
- intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN;
+ intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
+
+ if (p->dsc_en)
+ intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
data_width = p->width;
+ if (p->wide_bus_en && !dp_intf)
+ data_width = p->width >> 1;
hsync_data_start_x = hsync_start_x;
hsync_data_end_x = hsync_start_x + data_width - 1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 0bd57a32144a..b452e3557d10 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params {
u32 hsync_skew;
bool wide_bus_en;
+ bool dsc_en;
};
struct dpu_hw_intf_prog_fetch {
diff --git a/drivers
