Re: [PATCH 1/2] drm/print: drop include debugfs.h and include where needed
On Mon, Apr 22, 2024 at 2:10 PM Jani Nikula wrote: > > Surprisingly many places depend on debugfs.h to be included via > drm_print.h. Fix them. > > v3: Also fix armada, ite-it6505, imagination, msm, sti, vc4, and xe > > v2: Also fix ivpu and vmwgfx > > Reviewed-by: Andrzej Hajda > Acked-by: Maxime Ripard > Link: > https://patchwork.freedesktop.org/patch/msgid/20240410141434.157908-1-jani.nik...@intel.com > Signed-off-by: Jani Nikula > > --- > > Cc: Jacek Lawrynowicz > Cc: Stanislaw Gruszka > Cc: Oded Gabbay > Cc: Russell King > Cc: David Airlie > Cc: Daniel Vetter > Cc: Andrzej Hajda > Cc: Neil Armstrong > Cc: Robert Foss > Cc: Laurent Pinchart > Cc: Jonas Karlman > Cc: Jernej Skrabec > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Thomas Zimmermann > Cc: Jani Nikula > Cc: Rodrigo Vivi > Cc: Joonas Lahtinen > Cc: Tvrtko Ursulin > Cc: Frank Binns > Cc: Matt Coster > Cc: Rob Clark > Cc: Abhinav Kumar > Cc: Dmitry Baryshkov > Cc: Sean Paul > Cc: Marijn Suijten > Cc: Karol Herbst > Cc: Lyude Paul > Cc: Danilo Krummrich > Cc: Alex Deucher > Cc: "Christian König" > Cc: "Pan, Xinhui" > Cc: Alain Volmat > Cc: Huang Rui > Cc: Zack Rusin > Cc: Broadcom internal kernel review list > > Cc: Lucas De Marchi > Cc: "Thomas Hellström" > Cc: dri-de...@lists.freedesktop.org > Cc: intel-...@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org > Cc: linux-arm-...@vger.kernel.org > Cc: freedreno@lists.freedesktop.org > Cc: nouv...@lists.freedesktop.org > Cc: amd-...@lists.freedesktop.org > --- > drivers/accel/ivpu/ivpu_debugfs.c | 2 ++ > drivers/gpu/drm/armada/armada_debugfs.c | 1 + > drivers/gpu/drm/bridge/ite-it6505.c | 1 + > drivers/gpu/drm/bridge/panel.c | 2 ++ > drivers/gpu/drm/drm_print.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_dmc.c| 1 + > drivers/gpu/drm/imagination/pvr_fw_trace.c | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 ++ > drivers/gpu/drm/nouveau/dispnv50/crc.c | 2 ++ > drivers/gpu/drm/radeon/r100.c | 1 + > drivers/gpu/drm/radeon/r300.c | 1 + > drivers/gpu/drm/radeon/r420.c | 1 + > drivers/gpu/drm/radeon/r600.c | 3 ++- > drivers/gpu/drm/radeon/radeon_fence.c | 1 + > drivers/gpu/drm/radeon/radeon_gem.c | 1 + > drivers/gpu/drm/radeon/radeon_ib.c | 2 ++ > drivers/gpu/drm/radeon/radeon_pm.c | 1 + > drivers/gpu/drm/radeon/radeon_ring.c| 2 ++ > drivers/gpu/drm/radeon/radeon_ttm.c | 1 + > drivers/gpu/drm/radeon/rs400.c | 1 + > drivers/gpu/drm/radeon/rv515.c | 1 + > drivers/gpu/drm/sti/sti_drv.c | 1 + > drivers/gpu/drm/ttm/ttm_device.c| 1 + > drivers/gpu/drm/ttm/ttm_resource.c | 3 ++- > drivers/gpu/drm/ttm/ttm_tt.c| 5 +++-- > drivers/gpu/drm/vc4/vc4_drv.h | 1 + > drivers/gpu/drm/vmwgfx/vmwgfx_gem.c | 2 ++ > drivers/gpu/drm/xe/xe_debugfs.c | 1 + > drivers/gpu/drm/xe/xe_gt_debugfs.c | 2 ++ > drivers/gpu/drm/xe/xe_uc_debugfs.c | 2 ++ > include/drm/drm_print.h | 2 +- > 31 files changed, 46 insertions(+), 8 deletions(-) > > diff --git a/drivers/accel/ivpu/ivpu_debugfs.c > b/drivers/accel/ivpu/ivpu_debugfs.c > index d09d29775b3f..e07e447d08d1 100644 > --- a/drivers/accel/ivpu/ivpu_debugfs.c > +++ b/drivers/accel/ivpu/ivpu_debugfs.c > @@ -3,6 +3,8 @@ > * Copyright (C) 2020-2023 Intel Corporation > */ > > +#include > + > #include > #include > #include > diff --git a/drivers/gpu/drm/armada/armada_debugfs.c > b/drivers/gpu/drm/armada/armada_debugfs.c > index 29f4b52e3c8d..a763349dd89f 100644 > --- a/drivers/gpu/drm/armada/armada_debugfs.c > +++ b/drivers/gpu/drm/armada/armada_debugfs.c > @@ -5,6 +5,7 @@ > */ > > #include > +#include > #include > #include > #include > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c > b/drivers/gpu/drm/bridge/ite-it6505.c > index 27334173e911..3f68c82888c2 100644 > --- a/drivers/gpu/drm/bridge/ite-it6505.c > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2020, The Linux Foundation. All rights reserved. > */ > #include > +#include > #include > #include > #include > diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c > index 7f41525f7a6e..32506524d9a2 100644 > --- a/drivers/gpu/drm/bridge/panel.c > +++ b/drivers/gpu/drm/bridge/panel.c > @@ -4,6 +4,8 @@
Re: [Freedreno] [PATCH] drm/bridge: lt9611uxc: fix the race in the error path
On Thu, 12 Oct 2023 01:00:02 +0300, Dmitry Baryshkov wrote: > If DSI host attachment fails, the LT9611UXC driver will remove the > bridge without ensuring that there is no outstanding HPD work being > done. In rare cases this can result in the warnings regarding the mutex > being incorrect. Fix this by forcebly freing IRQ and flushing the work. > > DEBUG_LOCKS_WARN_ON(lock->magic != lock) > WARNING: CPU: 0 PID: 10 at kernel/locking/mutex.c:582 __mutex_lock+0x468/0x77c > Modules linked in: > CPU: 0 PID: 10 Comm: kworker/0:1 Tainted: G U > 6.6.0-rc5-next-20231011-gd81f81c2b682-dirty #1206 > Hardware name: Qualcomm Technologies, Inc. Robotics RB5 (DT) > Workqueue: events lt9611uxc_hpd_work > pstate: 6045 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) > pc : __mutex_lock+0x468/0x77c > lr : __mutex_lock+0x468/0x77c > sp : 8000800a3c70 > x29: 8000800a3c70 x28: x27: d595fe333000 > x26: 7c2f0002c005 x25: d595ff1b3000 x24: d595fccda5a0 > x23: x22: 0002 x21: 7c2f056d91c8 > x20: x19: 7c2f056d91c8 x18: fffe8db0 > x17: 00040044 x16: 005000f2b5503510 x15: > x14: 0006efb8 x13: x12: 0037 > x11: 0001 x10: 1470 x9 : 8000800a3ae0 > x8 : 7c2f0027f8d0 x7 : 7c2f0027e400 x6 : d595fc702b54 > x5 : x4 : 8000800a x3 : > x2 : x1 : x0 : 7c2f0027e400 > Call trace: > __mutex_lock+0x468/0x77c > mutex_lock_nested+0x24/0x30 > drm_bridge_hpd_notify+0x2c/0x5c > lt9611uxc_hpd_work+0x6c/0x80 > process_one_work+0x1ec/0x51c > worker_thread+0x1ec/0x3e4 > kthread+0x120/0x124 > ret_from_fork+0x10/0x20 > irq event stamp: 15799 > hardirqs last enabled at (15799): [] > finish_task_switch.isra.0+0xa8/0x278 > hardirqs last disabled at (15798): [] __schedule+0x7b8/0xbd8 > softirqs last enabled at (15794): [] > __do_softirq+0x498/0x4e0 > softirqs last disabled at (15771): [] > do_softirq+0x10/0x1c > > [...] Applied, thanks! [1/1] drm/bridge: lt9611uxc: fix the race in the error path https://cgit.freedesktop.org/drm/drm-misc/commit/?id=15fe53be46ea Rob
Re: [Freedreno] [PATCH] drm: Explicitly include correct DT includes
On Mon, Jul 17, 2023 at 4:27 PM Rob Herring wrote: > > On Sun, Jul 16, 2023 at 3:26 AM Heiko Stuebner wrote: > > > > Am Freitag, 14. Juli 2023, 19:45:34 CEST schrieb Rob Herring: > > > The DT of_device.h and of_platform.h date back to the separate > > > of_platform_bus_type before it as merged into the regular platform bus. > > > As part of that merge prepping Arm DT support 13 years ago, they > > > "temporarily" include each other. They also include platform_device.h > > > and of.h. As a result, there's a pretty much random mix of those include > > > files used throughout the tree. In order to detangle these headers and > > > replace the implicit includes with struct declarations, users need to > > > explicitly include the correct includes. > > > > > > Signed-off-by: Rob Herring > > > --- > > > > [...] > > > > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > > > b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > > > index 917e79951aac..2744d8f4a6fa 100644 > > > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > > > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c > > > @@ -12,7 +12,9 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include > > > +#include > > > #include > > > #include > > > > I'm not sure if I'm just misreading something, but in all other places > > of_device.h gets removed while here is stays as an include. Is this > > correct this way? > > Yes, because of_match_device() is used. > > Rob > For drivers/gpu/drm/bridge/ Acked-by: Robert Foss
Re: [Freedreno] [PATCH v4 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
On Tue, 3 Jan 2023 at 08:59, Krzysztof Kozlowski wrote: > > On 02/01/2023 18:10, Robert Foss wrote: > > On Fri, 30 Dec 2022 at 17:12, Krzysztof Kozlowski > > wrote: > >> > >> On 30/12/2022 16:35, Robert Foss wrote: > >>> Use two interconnect cells in order to optionally > >>> support a path tag. > >>> > >>> Signed-off-by: Robert Foss > >>> Reviewed-by: Konrad Dybcio > >>> --- > >>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++-- > >>> 1 file changed, 14 insertions(+), 14 deletions(-) > >>> > >> > >> I think you need to rebase to include: > >> https://lore.kernel.org/all/167233461761.1099840.5517525898039031248.b4...@kernel.org/ > > > > Ah, I see. Functionally I seemed to do fine without those commits. > > > >> > >> On which tree/revision did you base this? > > > > msm/drm-msm-display-for-6.2 > > Then it is not a proper base for DTS changes - you will miss quite some > commits. The DTS patches should be based on Bjorn's SoC tree or > linux-next (although the latter sometimes can lead to conflicts). Alright, then in that case this series needs to be split into 3 parts. The dts fixes, remaining dts changes & the remainder of code. Is this what you'd like to see? > > > Best regards, > Krzysztof >
Re: [Freedreno] [PATCH v4 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
On Fri, 30 Dec 2022 at 17:12, Krzysztof Kozlowski wrote: > > On 30/12/2022 16:35, Robert Foss wrote: > > Use two interconnect cells in order to optionally > > support a path tag. > > > > Signed-off-by: Robert Foss > > Reviewed-by: Konrad Dybcio > > --- > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++-- > > 1 file changed, 14 insertions(+), 14 deletions(-) > > > > I think you need to rebase to include: > https://lore.kernel.org/all/167233461761.1099840.5517525898039031248.b4...@kernel.org/ Ah, I see. Functionally I seemed to do fine without those commits. > > On which tree/revision did you base this? msm/drm-msm-display-for-6.2 > > Best regards, > Krzysztof >
[Freedreno] [PATCH v4 09/11] arm64: dts: qcom: sm8350: Add display system nodes
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 297 ++-
1 file changed, 293 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index bdefbbb2e38f..a80c0bf6d7fd 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include
#include
#include
#include
@@ -2535,14 +2536,302 @@ usb_2_dwc3: usb@a80 {
};
};
+ mdss: display-subsystem@ae0 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: opp-2 should work with
+* &rpmhpd_opp_low_svs, but one some of
+* sm8350_hdk boards reboot using this
+* opp.
+*/
+ opp-2 {
+ opp-hz = /bits/ 64 <2>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-34500 {
+ opp-hz = /bits/ 64 <34500>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-46000 {
+ opp-hz = /bits/ 64 <46000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
+
[Freedreno] [PATCH v4 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 1961f941ff83..6b21897c92dc 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ lt9611_1v2: lt9611-1v2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <&vph_pwr>;
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ lt9611_3v3: lt9611-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <&vreg_bob>;
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&adsp {
@@ -220,6 +256,15 @@ &dispcc {
&mdss_dsi0 {
vdda-supply = <&vreg_l6b_1p2>;
status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
};
&mdss_dsi0_phy {
@@ -231,6 +276,46 @@ &gpi_dma1 {
status = "okay";
};
+&i2c15 {
+ clock-frequency = <40>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_state>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
&mdss {
status = "okay";
};
@@ -248,6 +333,10 @@ &qupv3_id_0 {
status = "okay";
};
+&qupv3_id_2 {
+ status = "okay";
+};
+
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+ lt9611_state: lt9611-state {
+ rst {
+ pins = "gpio48";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ };
+
+ irq {
+ pins = "gpio50";
+ function = "gpio";
+ bias-disable;
+ };
+ };
};
--
2.34.1
[Freedreno] [PATCH v4 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..1961f941ff83 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+&dispcc {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l6b_1p2>;
+ status = "okay";
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l5b_0p88>;
+ status = "okay";
+};
+
&gpi_dma1 {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
2.34.1
[Freedreno] [PATCH v4 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 770ea105a565..bdefbbb2e38f 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@158 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@168 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x0168 0 0x1c200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e 0 0x1f180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@170 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x0170 0 0x33000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@174 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x0174 0 0x1f080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3c4 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c4 0 0xf080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@a0c{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c 0 0xa180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
@@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
- interconnects = <&aggre2_noc MASTER_IPA &mc_virt
SLAVE_EBI1>,
- <&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_IPA_CFG>;
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt
SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
&config_noc SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
@@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {
<&rpmhpd SM8350_MSS>;
power-domain-names = "cx", "mss";
- interconnects = <&mc_virt MASTER_LLCC &mc_virt
SLAVE_EBI1>;
+ interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt
SLAVE_EBI1 0>;
memory-region = <&pil_modem_mem>;
@@ -2238,7 +2238,7 @@ cdsp: remoteproc@9890 {
<&rpmhpd SM8350_MXC>;
[Freedreno] [PATCH v4 05/11] drm/msm: Add support for SM8350
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_mdss.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index ef31aad0c2de..34cd3df58aa1 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -297,6 +297,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f);
break;
+ case DPU_HW_VER_700:
+ /* TODO: highest_bank_bit = 2 for LP_DDR4 */
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
+ break;
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -533,6 +537,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sm6115-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
};
--
2.34.1
[Freedreno] [PATCH v4 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).
Signed-off-by: Robert Foss
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a86d9ea93b9d..770ea105a565 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2557,7 +2557,6 @@ dispcc: clock-controller@af0 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
- power-domain-names = "mmcx";
};
adsp: remoteproc@1730 {
--
2.34.1
[Freedreno] [PATCH v4 04/11] drm/msm/dpu: Add support for SM8350
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 987a74fb7fad..165958d47ec6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1302,6 +1302,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sm6115-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8350-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
--
2.34.1
[Freedreno] [PATCH v4 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
Add GPIO line names as described by the sm8350-hdk schematic.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ &slpi {
&tlmm {
gpio-reserved-ranges = <52 8>;
+
+ gpio-line-names =
+ "APPS_I2C_SDA", /* GPIO_0 */
+ "APPS_I2C_SCL",
+ "FSA_INT_N",
+ "USER_LED3_EN",
+ "SMBUS_SDA_1P8",
+ "SMBUS_SCL_1P8",
+ "2M2_3P3_EN",
+ "ALERT_DUAL_M2_N",
+ "EXP_UART_CTS",
+ "EXP_UART_RFR",
+ "EXP_UART_TX", /* GPIO_10 */
+ "EXP_UART_RX",
+ "NC",
+ "NC",
+ "RCM_MARKER1",
+ "WSA0_EN",
+ "CAM1_RESET_N",
+ "CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP0_RESET_N",
+ "DISP1_RESET_N",
+ "ETH_RESET",
+ "RCM_MARKER2",
+ "CAM_DC_MIPI_MUX_EN",
+ "CAM_DC_MIPI_MUX_SEL",
+ "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+ "AFC_PHY_TA_D_MINUS",
+ "PM8008_1_IRQ",
+ "PM8008_1_RESET_N",
+ "PM8008_2_IRQ",
+ "PM8008_2_RESET_N",
+ "CAM_DC_I3C_SDA",
+ "CAM_DC_I3C_SCL",
+ "FP_INT_N",
+ "FP_WUHB_INT_N",
+ "SMB_SPMI_DATA", /* GPIO_40 */
+ "SMB_SPMI_CLK",
+ "USB_HUB_RESET",
+ "FORCE_USB_BOOT",
+ "LRF_IRQ",
+ "NC",
+ "IMU2_INT",
+ "HDMI_3P3_EN",
+ "HDMI_RSTN",
+ "HDMI_1P2_EN",
+ "HDMI_INT", /* GPIO_50 */
+ "USB1_ID",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCLC",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "CAM_DC_SPI0_MISO",
+ "CAM_DC_SPI0_MOSI",
+ "CAM_DC_SPI0_CLK",
+ "CAM_DC_SPI0_CS_N",
+ "CAM_DC_SPI1_MISO",
+ "CAM_DC_SPI1_MOSI",
+ "CAM_DC_SPI1_CLK",
+ "CAM_DC_SPI1_CS_N",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_PHY_PS",
+ "MDP_VSYNC_P",
+ "MDP_VSYNC_S",
+ "ETH_3P3_EN",
+ "RADAR_INT",
+ "NFC_DWL_REQ",
+ "SM_GPIO_87",
+ "WCD_RESET_N",
+ "ALSP_INT_N",
+ "PRESS_INT", /* GPIO_90 */
+ "SAR_INT_N",
+ "SD_CARD_DET_N",
+ "NC",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "PCIE1_RESET_N",
+ "PCIE1_CLK_REQ_N",
+ "PCIE1_WAKE_N",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2&qu
[Freedreno] [PATCH v4 03/11] drm/msm/dpu: Add SM8350 to hw catalog
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss
Reviewed-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 195 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
2 files changed, 196 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2196e205efa5..29181844aa43 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -379,6 +388,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -529,6 +552,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2b4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2bc, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2c4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2ac, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2b4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2bc, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2c4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -687,6 +737,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1213,6 +1302,27 @@ static const struc
[Freedreno] [PATCH v4 02/11] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings
Signed-off-by: Robert Foss
Reviewed-by: Rob Herring
---
.../display/msm/qcom,sm8350-mdss.yaml | 221 ++
1 file changed, 221 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index ..0d452f22f556
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,221 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+ - Robert Foss
+
+description:
+ MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm8350-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sm8350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem";
+
+power-domains = <&dispcc MDSS_GDSC>;
+resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "nrt_bus", "core";
+
+iommus = <&apps_smmu 0x820 0x402>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+
[Freedreno] [PATCH v4 01/11] dt-bindings: display: msm: Add qcom, sm8350-dpu binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Robert Foss
Reviewed-by: Rob Herring
---
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
1 file changed, 120 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index ..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+ - Robert Foss
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz = /bits/ 64 <46000>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+};
+};
+...
--
2.34.1
[Freedreno] [PATCH v4 00/11] Enable Display for SM8350
Dependencies: https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/ Branch: https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v4 This series implements display support for SM8350 and enables HDMI output for the SM8350-HDK platform. Changes from v1: - Added R-b tags from v1 - Added qcom,sm8350-dpu binding patch - Added qcom,sm8350-mdss binding patch - Corrected sm8350.dtsi according to new dpu/mdss bindings - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator - Bjorn: Moved lt9611 pinctl pins into a common node - Bjorn/Krzysztof: Moved status property to last in node - Krzysztof: Changed hdmi-out to hdmi-connector - Krzysztof: Fixed regulator node name - Krzysztof: Changed &mdss to status=disabled as default - Krzysztof: Changed &mdss_mdp node name to display-controller - Krzysztof: Fixed opp-table node name - Krzysztof: Fixed phy node name - Dmitry: Split commit containing dpu & mdss compatibles string - Dmitry: Added msm_mdss_enable case - Dmitry: Fixed dpu ctl features Changes from v2: - Rob: Added r-b - Rob: Improved mdss binding description - Rob: Added interconnect names for mdss-binding - Rob: Removed phy from example - Konrad: Remove sc7280_pp refactor patch - Konrad: Fixed upper case hex in dpu_hw_catalog - Konrad: Fixed various downstream dts based values for dpu_hw_catalog - Konrad: Removed status=disabled from mdss_mdp - Konrad: Removed phy-names from dsi nodes - Konrad/Dmitry: Change mdp_opp_table opp-2 to use &rpmhpd_opp_svs, add comment - Dmitry: Move mdp_opp_table to dsi0 node Changes from v3: - Rebased on drm-msm-display-for-6.2 - Abhinav: Remove dsc_2 block - Bjorn/Dmitry: Add "mdss_" prefix for dsi & dsi_phy nodes - Dmitry: Add r-b - Dmitry: Fixed msm_mdss_setup_ubwc_dec_40 arguments - Dmitry: Changed &mdss to use display-subsystem@ - Dmitry: Moved &mdp_opp_table to &display-subsystem node - Dmitry: Chancged &mdp_opp_table to &dpu_upp_table - Dmitry: Correct opp-table disclaimer & fix opp - Dmitry: Move dsi_opp_table from &mdss_dsi0_phy to &mdss_dsi0 - Dmitry: Add dsi1 - Dmitry: Remove dispcc required opp - Georgi: Add missing interconnect cell - Krzysztof: Fix underscores in sm8350-hdk.dts node names - Krzysztof: Change dsi-opp-table to opp-table - Rob: Add r-b tags Robert Foss (11): dt-bindings: display: msm: Add qcom,sm8350-dpu binding dt-bindings: display: msm: Add qcom,sm8350-mdss binding drm/msm/dpu: Add SM8350 to hw catalog drm/msm/dpu: Add support for SM8350 drm/msm: Add support for SM8350 arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names arm64: dts: qcom: sm8350: Remove mmxc power-domain-name arm64: dts: qcom: sm8350: Use 2 interconnect cells arm64: dts: qcom: sm8350: Add display system nodes arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++ .../display/msm/qcom,sm8350-mdss.yaml | 221 arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 326 - .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 195 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 5 + 8 files changed, 1182 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml -- 2.34.1
Re: [Freedreno] [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
On Thu, 8 Dec 2022 at 00:42, Abhinav Kumar wrote:
>
>
>
> On 12/5/2022 8:37 AM, Robert Foss wrote:
> > Add compatibility for SM8350 display subsystem, including
> > required entries in DPU hw catalog.
> >
> > Signed-off-by: Robert Foss
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
> > 2 files changed, 197 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index 4dac90ee5b8a..ba26af73be53 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -112,6 +112,15 @@
> >BIT(MDP_INTF3_INTR) | \
> >BIT(MDP_INTF4_INTR))
> >
> > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_7xxx_INTR) | \
> > + BIT(MDP_INTF1_7xxx_INTR) | \
> > + BIT(MDP_INTF2_7xxx_INTR) | \
> > + BIT(MDP_INTF3_7xxx_INTR) | \
> > + 0)
> > +
> > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > BIT(MDP_SSPP_TOP0_INTR2) | \
> > BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > };
> >
> > +static const struct dpu_caps sm8350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0xb,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > + .ubwc_version = DPU_HW_UBWC_VER_40,
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .has_3d_merge = true,
> > + .max_linewidth = 4096,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > static const struct dpu_caps sm8450_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0xb,
> > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> > },
> > };
> >
> > +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > + .reg_off = 0x2ac, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > + .reg_off = 0x2b4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > + .reg_off = 0x2bc, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > + .reg_off = 0x2c4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > + .reg_off = 0x2ac, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > + .reg_off = 0x2b4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > + .reg_off = 0x2bc, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> > + .reg_off = 0x2c4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> > + .reg_off = 0x2bc, .bit_off = 20},
> > + },
> > +};
> > +
> > static const struct dpu_mdp_cfg sm8450_mdp[] = {
> > {
> > .name = "top_0", .id = MDP_TOP,
> > @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> > },
> > };
> >
> > +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x15000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> > + },
> > + {
> > + .name = "ctl_1", .id = CTL_1,
> > + .base = 0x16000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> > + },
> &g
Re: [Freedreno] [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
On Mon, 5 Dec 2022 at 17:47, Krzysztof Kozlowski
wrote:
>
> On 05/12/2022 17:37, Robert Foss wrote:
> > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
> >
> > In order to toggle the board to enable the HDMI output,
> > switch #7 & #8 on the rightmost multi-switch package have
> > to be toggled to On.
> >
> > Signed-off-by: Robert Foss
>
> Thank you for your patch. There is something to discuss/improve.
>
> > +
> > &slpi {
> > status = "okay";
> > firmware-name = "qcom/sm8350/slpi.mbn";
> > @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> > drive-strength = <2>;
> > output-low;
> > };
> > +
> > + lt9611_state: lt9611-state {
> > + lt9611_rst_pin {
>
> No underscores in node names.
Ack
>
> > + pins = "gpio48";
> > + function = "normal";
> > +
> > + output-high;
> > + input-disable;
> > + };
> > +
> > + lt9611_irq_pin {
>
> Ditto
Ack
>
> > + pins = "gpio50";
> > + function = "gpio";
> > + bias-disable;
> > + };
> > + };
> > };
>
> Best regards,
> Krzysztof
>
Re: [Freedreno] [PATCH v3 05/11] drm/msm: Add support for SM8350
On Thu, 8 Dec 2022 at 00:50, Dmitry Baryshkov
wrote:
>
> On 05/12/2022 18:37, Robert Foss wrote:
> > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
> > subsystem unit used on Qualcomm SM8350 platform.
> >
> > Signed-off-by: Robert Foss
> > ---
> > drivers/gpu/drm/msm/msm_mdss.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> > index a2264fb517a1..39746b972cdd 100644
> > --- a/drivers/gpu/drm/msm/msm_mdss.c
> > +++ b/drivers/gpu/drm/msm/msm_mdss.c
> > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> > /* UBWC_2_0 */
> > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
> > break;
> > + case DPU_HW_VER_700:
> > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
> > + break;
>
> Judging from the vendor kernel, the highest_rank_bit is 3, with usual
> todo for 2 for LP_DDR4.
Thanks! Will fix.
>
> > case DPU_HW_VER_720:
> > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
> > break;
> > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
> > { .compatible = "qcom,sc8180x-mdss" },
> > { .compatible = "qcom,sm8150-mdss" },
> > { .compatible = "qcom,sm8250-mdss" },
> > + { .compatible = "qcom,sm8350-mdss" },
> > { .compatible = "qcom,sm8450-mdss" },
> > {}
> > };
>
> --
> With best wishes
> Dmitry
>
Re: [Freedreno] [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
On Mon, 5 Dec 2022 at 20:19, Georgi Djakov wrote:
>
> Hi Robert,
>
> On 5.12.22 18:37, Robert Foss wrote:
> > Use two interconnect cells in order to optionally
> > support a path tag.
> >
> > Signed-off-by: Robert Foss
> > Reviewed-by: Konrad Dybcio
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
> > 1 file changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index 805d53d91952..434f8e8b12c1 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
> > config_noc: interconnect@150 {
> > compatible = "qcom,sm8350-config-noc";
> > reg = <0 0x0150 0 0xa580>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > mc_virt: interconnect@158 {
> > compatible = "qcom,sm8350-mc-virt";
> > reg = <0 0x0158 0 0x1000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> [..]
> > @@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {
> > clocks = <&rpmhcc RPMH_IPA_CLK>;
> > clock-names = "core";
> >
> > - interconnects = <&aggre2_noc MASTER_IPA &mc_virt
> > SLAVE_EBI1>,
> > - <&gem_noc MASTER_APPSS_PROC
> > &config_noc SLAVE_IPA_CFG>;
> > + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt
> > SLAVE_EBI1 0>,
> > + <&gem_noc MASTER_APPSS_PROC 0
> > &config_noc SLAVE_IPA_CFG 0>;
> > interconnect-names = "memory",
> >"config";
> >
> > @@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {
> > <&rpmhpd SM8350_MSS>;
> > power-domain-names = "cx", "mss";
> >
> > - interconnects = <&mc_virt MASTER_LLCC &mc_virt
> > SLAVE_EBI1>;
> > + interconnects = <&mc_virt MASTER_LLCC &mc_virt
> > SLAVE_EBI1 0>;
>
> The second cell for the first endpoint is missing, so this should be:
> interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
Nice catch, thanks!
>
> Thanks,
> Georgi
>
> >
> > memory-region = <&pil_modem_mem>;
> >
> > @@ -2239,7 +2239,7 @@ cdsp: remoteproc@9890 {
> > <&rpmhpd SM8350_MXC>;
> > power-domain-names = "cx", "mxc";
> >
> > - interconnects = <&compute_noc MASTER_CDSP_PROC
> > &mc_virt SLAVE_EBI1>;
> > + interconnects = <&compute_noc MASTER_CDSP_PROC 0
> > &mc_virt SLAVE_EBI1 0>;
> >
> > memory-region = <&pil_cdsp_mem>;
> >
> > @@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {
> > dc_noc: interconnect@90c {
> > compatible = "qcom,sm8350-dc-noc";
> > reg = <0 0x090c 0 0x4200>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > gem_noc: interconnect@910 {
> > compatible = "qcom,sm8350-gem-noc";
> > reg = <0 0x0910 0 0xb4000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
>
Re: [Freedreno] [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
On Mon, 5 Dec 2022 at 17:44, Dmitry Baryshkov
wrote:
>
> On 05/12/2022 18:37, Robert Foss wrote:
> > Enable the display subsystem and the dsi0 output for
> > the sm8350-hdk board.
> >
> > Signed-off-by: Robert Foss
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index e6deb08c6da0..39462c659c58 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -213,10 +213,32 @@ &cdsp {
> > firmware-name = "qcom/sm8350/cdsp.mbn";
> > };
> >
> > +&dispcc {
> > + status = "okay";
> > +};
> > +
> > +&dsi0 {
>
> Bjorn suggested using mdss_dsi0 / mdss_dsi0_phy labels for DSI host and
> PHY, as it allows us to group them nicely. WDYT?
Sounds quite reasonable, fixing it in dts/dtsi/binding.
>
> > + vdda-supply = <&vreg_l6b_1p2>;
> > + status = "okay";
> > +};
> > +
> > +&dsi0_phy {
> > + vdds-supply = <&vreg_l5b_0p88>;
> > + status = "okay";
> > +};
> > +
> > &gpi_dma1 {
> > status = "okay";
> > };
> >
> > +&mdss {
> > + status = "okay";
> > +};
> > +
> > +&mdss_mdp {
> > + status = "okay";
> > +};
> > +
> > &mpss {
> > status = "okay";
> > firmware-name = "qcom/sm8350/modem.mbn";
>
> --
> With best wishes
> Dmitry
>
[Freedreno] [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..39462c659c58 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+&dispcc {
+ status = "okay";
+};
+
+&dsi0 {
+ vdda-supply = <&vreg_l6b_1p2>;
+ status = "okay";
+};
+
+&dsi0_phy {
+ vdds-supply = <&vreg_l5b_0p88>;
+ status = "okay";
+};
+
&gpi_dma1 {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
2.34.1
[Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++-
1 file changed, 195 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..fb1c616c5e89 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include
#include
#include
#include
@@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 {
};
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<&dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+
[Freedreno] [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 39462c659c58..3aa4ca8271e5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ lt9611_1v2: lt9611-1v2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <&vph_pwr>;
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ lt9611_3v3: lt9611-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <&vreg_bob>;
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&adsp {
@@ -220,6 +256,15 @@ &dispcc {
&dsi0 {
vdda-supply = <&vreg_l6b_1p2>;
status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
};
&dsi0_phy {
@@ -231,6 +276,46 @@ &gpi_dma1 {
status = "okay";
};
+&i2c15 {
+ clock-frequency = <40>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_state>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
&mdss {
status = "okay";
};
@@ -248,6 +333,10 @@ &qupv3_id_0 {
status = "okay";
};
+&qupv3_id_2 {
+ status = "okay";
+};
+
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+ lt9611_state: lt9611-state {
+ lt9611_rst_pin {
+ pins = "gpio48";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ };
+
+ lt9611_irq_pin {
+ pins = "gpio50";
+ function = "gpio";
+ bias-disable;
+ };
+ };
};
--
2.34.1
[Freedreno] [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 805d53d91952..434f8e8b12c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@158 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@168 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x0168 0 0x1c200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e 0 0x1f180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@170 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x0170 0 0x33000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@174 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x0174 0 0x1f080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3c4 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c4 0 0xf080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@a0c{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c 0 0xa180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
@@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
- interconnects = <&aggre2_noc MASTER_IPA &mc_virt
SLAVE_EBI1>,
- <&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_IPA_CFG>;
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt
SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
&config_noc SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
@@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {
<&rpmhpd SM8350_MSS>;
power-domain-names = "cx", "mss";
- interconnects = <&mc_virt MASTER_LLCC &mc_virt
SLAVE_EBI1>;
+ interconnects = <&mc_virt MASTER_LLCC &mc_virt
SLAVE_EBI1 0>;
memory-region = <&pil_modem_mem>;
@@ -2239,7 +2239,7 @@ cdsp: remoteproc@9890 {
<&rpmhpd SM8350_MXC>;
[Freedreno] [PATCH v3 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
Add GPIO line names as described by the sm8350-hdk schematic.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ &slpi {
&tlmm {
gpio-reserved-ranges = <52 8>;
+
+ gpio-line-names =
+ "APPS_I2C_SDA", /* GPIO_0 */
+ "APPS_I2C_SCL",
+ "FSA_INT_N",
+ "USER_LED3_EN",
+ "SMBUS_SDA_1P8",
+ "SMBUS_SCL_1P8",
+ "2M2_3P3_EN",
+ "ALERT_DUAL_M2_N",
+ "EXP_UART_CTS",
+ "EXP_UART_RFR",
+ "EXP_UART_TX", /* GPIO_10 */
+ "EXP_UART_RX",
+ "NC",
+ "NC",
+ "RCM_MARKER1",
+ "WSA0_EN",
+ "CAM1_RESET_N",
+ "CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP0_RESET_N",
+ "DISP1_RESET_N",
+ "ETH_RESET",
+ "RCM_MARKER2",
+ "CAM_DC_MIPI_MUX_EN",
+ "CAM_DC_MIPI_MUX_SEL",
+ "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+ "AFC_PHY_TA_D_MINUS",
+ "PM8008_1_IRQ",
+ "PM8008_1_RESET_N",
+ "PM8008_2_IRQ",
+ "PM8008_2_RESET_N",
+ "CAM_DC_I3C_SDA",
+ "CAM_DC_I3C_SCL",
+ "FP_INT_N",
+ "FP_WUHB_INT_N",
+ "SMB_SPMI_DATA", /* GPIO_40 */
+ "SMB_SPMI_CLK",
+ "USB_HUB_RESET",
+ "FORCE_USB_BOOT",
+ "LRF_IRQ",
+ "NC",
+ "IMU2_INT",
+ "HDMI_3P3_EN",
+ "HDMI_RSTN",
+ "HDMI_1P2_EN",
+ "HDMI_INT", /* GPIO_50 */
+ "USB1_ID",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCLC",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "CAM_DC_SPI0_MISO",
+ "CAM_DC_SPI0_MOSI",
+ "CAM_DC_SPI0_CLK",
+ "CAM_DC_SPI0_CS_N",
+ "CAM_DC_SPI1_MISO",
+ "CAM_DC_SPI1_MOSI",
+ "CAM_DC_SPI1_CLK",
+ "CAM_DC_SPI1_CS_N",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_PHY_PS",
+ "MDP_VSYNC_P",
+ "MDP_VSYNC_S",
+ "ETH_3P3_EN",
+ "RADAR_INT",
+ "NFC_DWL_REQ",
+ "SM_GPIO_87",
+ "WCD_RESET_N",
+ "ALSP_INT_N",
+ "PRESS_INT", /* GPIO_90 */
+ "SAR_INT_N",
+ "SD_CARD_DET_N",
+ "NC",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "PCIE1_RESET_N",
+ "PCIE1_CLK_REQ_N",
+ "PCIE1_WAKE_N",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2&qu
[Freedreno] [PATCH v3 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).
Signed-off-by: Robert Foss
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index cbd48f248df4..805d53d91952 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2558,7 +2558,6 @@ dispcc: clock-controller@af0 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
- power-domain-names = "mmcx";
};
adsp: remoteproc@1730 {
--
2.34.1
[Freedreno] [PATCH v3 05/11] drm/msm: Add support for SM8350
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/msm_mdss.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index a2264fb517a1..39746b972cdd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
+ case DPU_HW_VER_700:
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
+ break;
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
};
--
2.34.1
[Freedreno] [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9827914dc096..6048bfae0824 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8350-dpu", },
{ .compatible = "qcom,sm8450-dpu", },
{}
};
--
2.34.1
[Freedreno] [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
2 files changed, 197 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..ba26af73be53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2b4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2bc, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2c4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2ac, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2b4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2bc, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2c4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sm8450_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_p
[Freedreno] [PATCH v3 02/11] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings
Signed-off-by: Robert Foss
---
.../display/msm/qcom,sm8350-mdss.yaml | 221 ++
1 file changed, 221 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index ..d9aa6e857d1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,221 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+ - Robert Foss
+
+description:
+ MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm8350-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sm8350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem";
+
+power-domains = <&dispcc MDSS_GDSC>;
+resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "nrt_bus", "core";
+
+iommus = <&apps_smmu 0x820 0x402>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-tabl
[Freedreno] [PATCH v3 01/11] dt-bindings: display: msm: Add qcom, sm8350-dpu binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Robert Foss
Reviewed-by: Rob Herring
---
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
1 file changed, 120 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index ..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+ - Robert Foss
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz = /bits/ 64 <46000>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+};
+};
+...
--
2.34.1
[Freedreno] [PATCH v3 00/11] Enable Display for SM8350
Dependencies: https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/ Branch: https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v3 This series implements display support for SM8350 and enables HDMI output for the SM8350-HDK platform. Changes from v1: - Added R-b tags from v1 - Added qcom,sm8350-dpu binding patch - Added qcom,sm8350-mdss binding patch - Corrected sm8350.dtsi according to new dpu/mdss bindings - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator - Bjorn: Moved lt9611 pinctl pins into a common node - Bjorn/Krzysztof: Moved status property to last in node - Krzysztof: Changed hdmi-out to hdmi-connector - Krzysztof: Fixed regulator node name - Krzysztof: Changed &mdss to status=disabled as default - Krzysztof: Changed &mdss_mdp node name to display-controller - Krzysztof: Fixed opp-table node name - Krzysztof: Fixed phy node name - Dmitry: Split commit containing dpu & mdss compatibles string - Dmitry: Added msm_mdss_enable case - Dmitry: Fixed dpu ctl features Changes from v2: - Rob: Added r-b - Rob: Improved mdss binding description - Rob: Added interconnect names for mdss-binding - Rob: Removed phy from example - Konrad: Remove sc7280_pp refactor patch - Konrad: Fixed upper case hex in dpu_hw_catalog - Konrad: Fixed various downstream dts based values for dpu_hw_catalog - Konrad: Removed status=disabled from mdss_mdp - Konrad: Removed phy-names from dsi nodes - Konrad/Dmitry: Change mdp_opp_table opp-2 to use &rpmhpd_opp_svs, add comment - Dmitry: Move mdp_opp_table to dsi0 node Robert Foss (11): dt-bindings: display: msm: Add qcom,sm8350-dpu binding dt-bindings: display: msm: Add qcom,sm8350-mdss binding drm/msm/dpu: Add SM8350 to hw catalog drm/msm/dpu: Add support for SM8350 drm/msm: Add support for SM8350 arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names arm64: dts: qcom: sm8350: Remove mmxc power-domain-name arm64: dts: qcom: sm8350: Use 2 interconnect cells arm64: dts: qcom: sm8350: Add display system nodes arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++ .../display/msm/qcom,sm8350-mdss.yaml | 221 arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 228 +++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 +++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 4 + 8 files changed, 1084 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml -- 2.34.1
Re: [Freedreno] [PATCH v2 10/12] arm64: dts: qcom: sm8350: Add display system nodes
On Tue, 15 Nov 2022 at 14:47, Konrad Dybcio wrote:
>
>
>
> On 15/11/2022 14:31, Robert Foss wrote:
> > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> > nodes the display subsystem is configured to support
> > one DSI output.
> >
> > Signed-off-by: Robert Foss
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++-
> > 1 file changed, 193 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index 434f8e8b12c1..5c98e5cf5ad0 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -3,6 +3,7 @@
> >* Copyright (c) 2020, Linaro Limited
> >*/
> >
> > +#include
> > #include
> > #include
> > #include
> > @@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a80 {
> > };
> > };
> >
> > + mdss: mdss@ae0 {
> > + compatible = "qcom,sm8350-mdss";
> > + reg = <0 0x0ae0 0 0x1000>;
> > + reg-names = "mdss";
> > +
> > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
> > SLAVE_EBI1 0>,
> > + <&mmss_noc MASTER_MDP1 0 &mc_virt
> > SLAVE_EBI1 0>;
> > + interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > + power-domains = <&dispcc MDSS_GDSC>;
> > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > + clock-names = "iface", "bus", "nrt_bus", "core";
> > +
> > + interrupts = ;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + iommus = <&apps_smmu 0x820 0x402>;
> > +
> > + status = "disabled";
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + mdss_mdp: display-controller@ae01000 {
> > + compatible = "qcom,sm8350-dpu";
> > + reg = <0 0x0ae01000 0 0x8f000>,
> > + <0 0x0aeb 0 0x2008>;
> > + reg-names = "mdp", "vbif";
> > +
> > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + clock-names = "bus",
> > + "nrt_bus",
> > + "iface",
> > + "lut",
> > + "core",
> > + "vsync";
> > +
> > + assigned-clocks = <&dispcc
> > DISP_CC_MDSS_VSYNC_CLK>;
> > + assigned-clock-rates = <1920>;
> > +
> > + operating-points-v2 = <&mdp_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <0>;
> > +
> > + status = "disabled";
> It doesn't make sense to disable mdp separately, as mdss is essentially
> useless without it.
Ac
Re: [Freedreno] [PATCH v2 04/12] drm/msm/dpu: Add SM8350 to hw catalog
On Tue, 15 Nov 2022 at 14:40, Konrad Dybcio wrote:
>
>
>
> On 15/11/2022 14:30, Robert Foss wrote:
> > Add compatibility for SM8350 display subsystem, including
> > required entries in DPU hw catalog.
> >
> > Signed-off-by: Robert Foss
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
> > 2 files changed, 197 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index 8f2d634f7b6b..e21ef7d912a0 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -112,6 +112,15 @@
> >BIT(MDP_INTF3_INTR) | \
> >BIT(MDP_INTF4_INTR))
> >
> > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_7xxx_INTR) | \
> > + BIT(MDP_INTF1_7xxx_INTR) | \
> > + BIT(MDP_INTF2_7xxx_INTR) | \
> > + BIT(MDP_INTF3_7xxx_INTR) | \
> > + 0)
> > +
> > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > BIT(MDP_SSPP_TOP0_INTR2) | \
> > BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > @@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > };
> >
> > +static const struct dpu_caps sm8350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0xb,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > + .ubwc_version = DPU_HW_UBWC_VER_40,
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .has_3d_merge = true,
> > + .max_linewidth = 4096,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > static const struct dpu_caps sm8450_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0xb,
> > @@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> > },
> > };
> >
> > +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > + .reg_off = 0x2AC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > + .reg_off = 0x2B4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > + .reg_off = 0x2BC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > + .reg_off = 0x2C4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > + .reg_off = 0x2AC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > + .reg_off = 0x2B4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > + .reg_off = 0x2BC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> > + .reg_off = 0x2C4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> > + .reg_off = 0x2BC, .bit_off = 20},
> > + },
> Let's try not adding more uppercase hex.
Ack
>
> > +};
> > +
> > static const struct dpu_mdp_cfg sm8450_mdp[] = {
> > {
> > .name = "top_0", .id = MDP_TOP,
> > @@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> > },
> > };
> >
> > +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x15000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> > + },
> > + {
> > + .name = "ctl_1", .id = CTL_1,
> > + .base = 0x16000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
> > + .
Re: [Freedreno] [PATCH v2 06/12] drm/msm: Add support for SM8350
On Tue, 15 Nov 2022 at 14:42, Konrad Dybcio wrote:
>
>
>
> On 15/11/2022 14:30, Robert Foss wrote:
> > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
> > subsystem unit used on Qualcomm SM8350 platform.
> >
> > Signed-off-by: Robert Foss
> > ---
> > drivers/gpu/drm/msm/msm_mdss.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> > index a2264fb517a1..39746b972cdd 100644
> > --- a/drivers/gpu/drm/msm/msm_mdss.c
> > +++ b/drivers/gpu/drm/msm/msm_mdss.c
> > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> > /* UBWC_2_0 */
> > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
> > break;
> > + case DPU_HW_VER_700:
> > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
> > + break;
> Shouldn't the second-last argument be 2 or 3 depending on DDR type?
Dmitry, can I get your input on this? I'm a little bit unsure of which
dts properties some of these
values are derived from.
>
> Konrad
> > case DPU_HW_VER_720:
> > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
> > break;
> > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
> > { .compatible = "qcom,sc8180x-mdss" },
> > { .compatible = "qcom,sm8150-mdss" },
> > { .compatible = "qcom,sm8250-mdss" },
> > + { .compatible = "qcom,sm8350-mdss" },
> > { .compatible = "qcom,sm8450-mdss" },
> > {}
> > };
Re: [Freedreno] [PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
On Tue, 15 Nov 2022 at 17:49, Rob Herring wrote:
>
> On Tue, Nov 15, 2022 at 12:17:11PM +0100, Robert Foss wrote:
> > Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> > like DPU display controller, DSI etc. Add YAML schema for MDSS device
> > tree bindings
> >
> > Signed-off-by: Robert Foss
> > ---
> > .../display/msm/qcom,sm8350-mdss.yaml | 240 ++
> > 1 file changed, 240 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> > b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> > new file mode 100644
> > index ..9a0694853576
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
> > @@ -0,0 +1,240 @@
> > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SM8350 Display MDSS
> > +
> > +maintainers:
> > + - Robert Foss
> > +
> > +description:
> > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that
> > encapsulates
>
> Drop 'Device tree bindings for '. Describe what this h/w is.
Ack
>
> > + sub-blocks like DPU display controller, DSI and DP interfaces etc.
> > Device tree
> > + bindings of MDSS are mentioned for SM8350 target.
> > +
> > +$ref: /schemas/display/msm/mdss-common.yaml#
> > +
> > +properties:
> > + compatible:
> > +items:
> > + - const: qcom,sm8350-mdss
> > +
> > + clocks:
> > +items:
> > + - description: Display AHB clock from gcc
> > + - description: Display hf axi clock
> > + - description: Display sf axi clock
> > + - description: Display core clock
> > +
> > + clock-names:
> > +items:
> > + - const: iface
> > + - const: bus
> > + - const: nrt_bus
> > + - const: core
> > +
> > + iommus:
> > +maxItems: 1
> > +
> > + interconnects:
> > +maxItems: 2
> > +
> > + interconnect-names:
> > +maxItems: 2
>
> Need to define the names.
>
> > +
> > +patternProperties:
> > + "^display-controller@[0-9a-f]+$":
> > +type: object
> > +properties:
> > + compatible:
> > +const: qcom,sm8350-dpu
> > +
> > + "^dsi@[0-9a-f]+$":
> > +type: object
> > +properties:
> > + compatible:
> > +const: qcom,mdss-dsi-ctrl
> > +
> > + "^phy@[0-9a-f]+$":
> > +type: object
> > +properties:
> > + compatible:
> > +const: qcom,dsi-phy-5nm-8350
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +display-subsystem@ae0 {
> > +compatible = "qcom,sm8350-mdss";
> > +reg = <0x0ae0 0x1000>;
> > +reg-names = "mdss";
> > +
> > +interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
> > +<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
> > +interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > +power-domains = <&dispcc MDSS_GDSC>;
> > +resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> > +
> > +clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > +clock-names = "iface", "bus", "nrt_bus", "core";
> > +
> > +iommus = <&apps_smmu 0x820 0x402>;
> > +
> > +interrupts = ;
> > +interrupt-controller;
> > +#interrupt-cells = <1>;
> > +
> > +#address-cells = <1>;
> > +#size-cells = <1>;
> > +ranges;
> > +
> > +display-controller@ae01000 {
> > +compatible = "q
[Freedreno] [PATCH v2 07/12] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
Add GPIO line names as described by the sm8350-hdk schematic.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ &slpi {
&tlmm {
gpio-reserved-ranges = <52 8>;
+
+ gpio-line-names =
+ "APPS_I2C_SDA", /* GPIO_0 */
+ "APPS_I2C_SCL",
+ "FSA_INT_N",
+ "USER_LED3_EN",
+ "SMBUS_SDA_1P8",
+ "SMBUS_SCL_1P8",
+ "2M2_3P3_EN",
+ "ALERT_DUAL_M2_N",
+ "EXP_UART_CTS",
+ "EXP_UART_RFR",
+ "EXP_UART_TX", /* GPIO_10 */
+ "EXP_UART_RX",
+ "NC",
+ "NC",
+ "RCM_MARKER1",
+ "WSA0_EN",
+ "CAM1_RESET_N",
+ "CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP0_RESET_N",
+ "DISP1_RESET_N",
+ "ETH_RESET",
+ "RCM_MARKER2",
+ "CAM_DC_MIPI_MUX_EN",
+ "CAM_DC_MIPI_MUX_SEL",
+ "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+ "AFC_PHY_TA_D_MINUS",
+ "PM8008_1_IRQ",
+ "PM8008_1_RESET_N",
+ "PM8008_2_IRQ",
+ "PM8008_2_RESET_N",
+ "CAM_DC_I3C_SDA",
+ "CAM_DC_I3C_SCL",
+ "FP_INT_N",
+ "FP_WUHB_INT_N",
+ "SMB_SPMI_DATA", /* GPIO_40 */
+ "SMB_SPMI_CLK",
+ "USB_HUB_RESET",
+ "FORCE_USB_BOOT",
+ "LRF_IRQ",
+ "NC",
+ "IMU2_INT",
+ "HDMI_3P3_EN",
+ "HDMI_RSTN",
+ "HDMI_1P2_EN",
+ "HDMI_INT", /* GPIO_50 */
+ "USB1_ID",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCLC",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "CAM_DC_SPI0_MISO",
+ "CAM_DC_SPI0_MOSI",
+ "CAM_DC_SPI0_CLK",
+ "CAM_DC_SPI0_CS_N",
+ "CAM_DC_SPI1_MISO",
+ "CAM_DC_SPI1_MOSI",
+ "CAM_DC_SPI1_CLK",
+ "CAM_DC_SPI1_CS_N",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_PHY_PS",
+ "MDP_VSYNC_P",
+ "MDP_VSYNC_S",
+ "ETH_3P3_EN",
+ "RADAR_INT",
+ "NFC_DWL_REQ",
+ "SM_GPIO_87",
+ "WCD_RESET_N",
+ "ALSP_INT_N",
+ "PRESS_INT", /* GPIO_90 */
+ "SAR_INT_N",
+ "SD_CARD_DET_N",
+ "NC",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "PCIE1_RESET_N",
+ "PCIE1_CLK_REQ_N",
+ "PCIE1_WAKE_N",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2&qu
[Freedreno] [PATCH v2 10/12] arm64: dts: qcom: sm8350: Add display system nodes
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 197 ++-
1 file changed, 193 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..5c98e5cf5ad0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include
#include
#include
#include
@@ -2536,14 +2537,201 @@ usb_2_dwc3: usb@a80 {
};
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-2 {
+ opp-hz = /bits/ 64 <2>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+
[Freedreno] [PATCH v2 09/12] arm64: dts: qcom: sm8350: Use 2 interconnect cells
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 805d53d91952..434f8e8b12c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@158 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@168 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x0168 0 0x1c200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e 0 0x1f180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@170 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x0170 0 0x33000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@174 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x0174 0 0x1f080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3c4 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c4 0 0xf080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@a0c{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c 0 0xa180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
@@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
- interconnects = <&aggre2_noc MASTER_IPA &mc_virt
SLAVE_EBI1>,
- <&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_IPA_CFG>;
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt
SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
&config_noc SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
@@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {
<&rpmhpd SM8350_MSS>;
power-domain-names = "cx", "mss";
- interconnects = <&mc_virt MASTER_LLCC &mc_virt
SLAVE_EBI1>;
+ interconnects = <&mc_virt MASTER_LLCC &mc_virt
SLAVE_EBI1 0>;
memory-region = <&pil_modem_mem>;
@@ -2239,7 +2239,7 @@ cdsp: remoteproc@9890 {
<&rpmhpd SM8350_MXC>;
power-domain-names =
[Freedreno] [PATCH v2 12/12] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 39462c659c58..3aa4ca8271e5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ lt9611_1v2: lt9611-1v2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <&vph_pwr>;
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ lt9611_3v3: lt9611-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <&vreg_bob>;
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&adsp {
@@ -220,6 +256,15 @@ &dispcc {
&dsi0 {
vdda-supply = <&vreg_l6b_1p2>;
status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
};
&dsi0_phy {
@@ -231,6 +276,46 @@ &gpi_dma1 {
status = "okay";
};
+&i2c15 {
+ clock-frequency = <40>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_state>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
&mdss {
status = "okay";
};
@@ -248,6 +333,10 @@ &qupv3_id_0 {
status = "okay";
};
+&qupv3_id_2 {
+ status = "okay";
+};
+
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+ lt9611_state: lt9611-state {
+ lt9611_rst_pin {
+ pins = "gpio48";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ };
+
+ lt9611_irq_pin {
+ pins = "gpio50";
+ function = "gpio";
+ bias-disable;
+ };
+ };
};
--
2.34.1
[Freedreno] [PATCH v2 08/12] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index cbd48f248df4..805d53d91952 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2558,7 +2558,6 @@ dispcc: clock-controller@af0 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
- power-domain-names = "mmcx";
};
adsp: remoteproc@1730 {
--
2.34.1
[Freedreno] [PATCH v2 11/12] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..39462c659c58 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+&dispcc {
+ status = "okay";
+};
+
+&dsi0 {
+ vdda-supply = <&vreg_l6b_1p2>;
+ status = "okay";
+};
+
+&dsi0_phy {
+ vdds-supply = <&vreg_l5b_0p88>;
+ status = "okay";
+};
+
&gpi_dma1 {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
2.34.1
[Freedreno] [PATCH v2 06/12] drm/msm: Add support for SM8350
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/msm_mdss.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index a2264fb517a1..39746b972cdd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
+ case DPU_HW_VER_700:
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
+ break;
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
};
--
2.34.1
[Freedreno] [PATCH v2 04/12] drm/msm/dpu: Add SM8350 to hw catalog
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
2 files changed, 197 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8f2d634f7b6b..e21ef7d912a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2BC, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sm8450_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1301,6 +1390,27 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
[Freedreno] [PATCH v2 05/12] drm/msm/dpu: Add support for SM8350
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9827914dc096..6048bfae0824 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8350-dpu", },
{ .compatible = "qcom,sm8450-dpu", },
{}
};
--
2.34.1
[Freedreno] [PATCH v2 03/12] drm/msm/dpu: Refactor sc7280_pp location
The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.
Signed-off-by: Robert Foss
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..8f2d634f7b6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1294,6 +1294,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sc7280_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1352,13 +1359,6 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] =
{
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
};
-static const struct dpu_pingpong_cfg sc7280_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
/*
* DSC sub blocks config
*/
--
2.34.1
[Freedreno] [PATCH v2 00/12] Enable Display for SM8350
Dependencies: https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/ Branch: https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2 This series implements display support for SM8350 and enables HDMI output for the SM8350-HDK platform. Changes from v1: - Added R-b tags from v1 - Added qcom,sm8350-dpu binding patch - Added qcom,sm8350-mdss binding patch - Corrected sm8350.dtsi according to new dpu/mdss bindings - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator - Bjorn: Moved lt9611 pinctl pins into a common node - Bjorn/Krzysztof: Moved status property to last in node - Krzysztof: Changed hdmi-out to hdmi-connector - Krzysztof: Fixed regulator node name - Krzysztof: Changed &mdss to status=disabled as default - Krzysztof: Changed &mdss_mdp node name to display-controller - Krzysztof: Fixed opp-table node name - Krzysztof: Fixed phy node name - Dmitry: Split commit containing dpu & mdss compatibles string - Dmitry: Added msm_mdss_enable case - Dmitry: Fixed dpu ctl features Robert Foss (12): dt-bindings: display: msm: Add qcom,sm8350-dpu binding dt-bindings: display: msm: Add qcom,sm8350-mdss binding drm/msm/dpu: Refactor sc7280_pp location drm/msm/dpu: Add SM8350 to hw catalog drm/msm/dpu: Add support for SM8350 drm/msm: Add support for SM8350 arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names arm64: dts: qcom: sm8350: Remove mmxc power-domain-name arm64: dts: qcom: sm8350: Use 2 interconnect cells arm64: dts: qcom: sm8350: Add display system nodes arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++ .../display/msm/qcom,sm8350-mdss.yaml | 240 + arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 226 +++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 210 ++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 4 + 8 files changed, 1108 insertions(+), 26 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml -- 2.34.1
[Freedreno] [PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings
Signed-off-by: Robert Foss
---
.../display/msm/qcom,sm8350-mdss.yaml | 240 ++
1 file changed, 240 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index ..9a0694853576
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+ - Robert Foss
+
+description:
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
+ bindings of MDSS are mentioned for SM8350 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm8350-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sm8350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem";
+
+power-domains = <&dispcc MDSS_GDSC>;
+resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "nrt_bus", "core";
+
+iommus = <&apps_smmu 0x820 0x402>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+
[Freedreno] [PATCH v2 01/12] dt-bindings: display: msm: Add qcom, sm8350-dpu binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Robert Foss
---
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
1 file changed, 120 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index ..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+ - Robert Foss
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz = /bits/ 64 <46000>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+};
+};
+...
--
2.34.1
[Freedreno] [PATCH v2 02/12] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings
Signed-off-by: Robert Foss
---
.../display/msm/qcom,sm8350-mdss.yaml | 240 ++
1 file changed, 240 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index ..9a0694853576
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+ - Robert Foss
+
+description:
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device
tree
+ bindings of MDSS are mentioned for SM8350 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm8350-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sm8350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem";
+
+power-domains = <&dispcc MDSS_GDSC>;
+resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "nrt_bus", "core";
+
+iommus = <&apps_smmu 0x820 0x402>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+
[Freedreno] [PATCH v2 03/12] drm/msm/dpu: Refactor sc7280_pp location
The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.
Signed-off-by: Robert Foss
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..8f2d634f7b6b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1294,6 +1294,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sc7280_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1352,13 +1359,6 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] =
{
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
};
-static const struct dpu_pingpong_cfg sc7280_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
/*
* DSC sub blocks config
*/
--
2.34.1
[Freedreno] [PATCH v2 01/12] dt-bindings: display: msm: Add qcom, sm8350-dpu binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Robert Foss
---
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
1 file changed, 120 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index ..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+ - Robert Foss
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd SM8350_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz = /bits/ 64 <46000>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+};
+};
+...
--
2.34.1
[Freedreno] [PATCH v2 00/12] Enable Display for SM8350
Dependencies: https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/ Branch: https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v2 This series implements display support for SM8350 and enables HDMI output for the SM8350-HDK platform. Changes from v1: - Added R-b tags from v1 - Added qcom,sm8350-dpu binding patch - Added qcom,sm8350-mdss binding patch - Corrected sm8350.dtsi according to new dpu/mdss bindings - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator - Bjorn: Moved lt9611 pinctl pins into a common node - Bjorn/Krzysztof: Moved status property to last in node - Krzysztof: Changed hdmi-out to hdmi-connector - Krzysztof: Fixed regulator node name - Krzysztof: Changed &mdss to status=disabled as default - Krzysztof: Changed &mdss_mdp node name to display-controller - Krzysztof: Fixed opp-table node name - Krzysztof: Fixed phy node name - Dmitry: Split commit containing dpu & mdss compatibles string - Dmitry: Added msm_mdss_enable case - Dmitry: Fixed dpu ctl features Robert Foss (12): dt-bindings: display: msm: Add qcom,sm8350-dpu binding dt-bindings: display: msm: Add qcom,sm8350-mdss binding drm/msm/dpu: Refactor sc7280_pp location drm/msm/dpu: Add SM8350 to hw catalog drm/msm/dpu: Add support for SM8350 drm/msm: Add support for SM8350 arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names arm64: dts: qcom: sm8350: Remove mmxc power-domain-name arm64: dts: qcom: sm8350: Use 2 interconnect cells arm64: dts: qcom: sm8350: Add display system nodes arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++ .../display/msm/qcom,sm8350-mdss.yaml | 240 + arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 226 +++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 210 ++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 4 + 8 files changed, 1108 insertions(+), 26 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml -- 2.34.1
Re: [Freedreno] [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
On Sat, 29 Oct 2022 at 00:06, Krzysztof Kozlowski
wrote:
>
> On 28/10/2022 08:08, Robert Foss wrote:
> > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
> >
> > In order to toggle the board to enable the HDMI output,
> > switch #7 & #8 on the rightmost multi-switch package have
> > to be toggled to On.
> >
> > Signed-off-by: Robert Foss
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106
> > 1 file changed, 106 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index 6e07feb4b3b2..b38b58f8 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -20,6 +20,17 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + hdmi-out {
>
> Generic node names, so hdmi-connector or just connector.
Ack.
>
> > + compatible = "hdmi-connector";
> > + type = "a";
> > +
> > + port {
> > + hdmi_con: endpoint {
> > + remote-endpoint = <<9611_out>;
> > + };
> > + };
> > + };
> > +
> > vph_pwr: vph-pwr-regulator {
> > compatible = "regulator-fixed";
> > regulator-name = "vph_pwr";
> > @@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
> > regulator-always-on;
> > regulator-boot-on;
> > };
> > +
> > + lt9611_1v2: lt9611-1v2 {
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Ack.
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_1V2";
> > +
> > + vin-supply = <&vph_pwr>;
> > + regulator-min-microvolt = <120>;
> > + regulator-max-microvolt = <120>;
> > + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + lt9611_3v3: lt9611-3v3 {
>
> Ditto
Ack.
>
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_3V3";
> > +
> > + vin-supply = <&vreg_bob>;
> > + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > };
> >
> > &adsp {
> > @@ -220,6 +257,15 @@ &dispcc {
> > &dsi0 {
> > status = "okay";
> > vdda-supply = <&vreg_l6b_1p2>;
> > +
> > + ports {
> > + port@1 {
> > + endpoint {
> > + remote-endpoint = <<9611_a>;
> > + data-lanes = <0 1 2 3>;
> > + };
> > + };
> > + };
> > };
> >
> > &dsi0_phy {
> > @@ -231,6 +277,48 @@ &gpi_dma1 {
> > status = "okay";
> > };
> >
> > +&i2c15 {
> > + status = "okay";
>
> status is the last property
Ack.
>
> > + clock-frequency = <40>;
> > +
> > + lt9611_codec: hdmi-bridge@2b {
> > + compatible = "lontium,lt9611uxc";
> > + reg = <0x2b>;
> > + status = "okay";
>
> Why status?
It should be removed. Fixing in v2.
>
> > +
> > + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
> > + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
> > +
> > + vdd-supply = <<9611_1v2>;
> > + vcc-supply = <<9611_3v3>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> > +
> > + ports {
> > + #address-cells = <1>;
> >
Re: [Freedreno] [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
On Fri, 28 Oct 2022 at 15:57, Bjorn Andersson wrote:
>
> On Fri, Oct 28, 2022 at 02:08:12PM +0200, Robert Foss wrote:
> > The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
> >
> > In order to toggle the board to enable the HDMI output,
> > switch #7 & #8 on the rightmost multi-switch package have
> > to be toggled to On.
> >
> > Signed-off-by: Robert Foss
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106
> > 1 file changed, 106 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index 6e07feb4b3b2..b38b58f8 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -20,6 +20,17 @@ chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + hdmi-out {
> > + compatible = "hdmi-connector";
> > + type = "a";
> > +
> > + port {
> > + hdmi_con: endpoint {
> > + remote-endpoint = <<9611_out>;
> > + };
> > + };
> > + };
> > +
> > vph_pwr: vph-pwr-regulator {
> > compatible = "regulator-fixed";
> > regulator-name = "vph_pwr";
> > @@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
> > regulator-always-on;
> > regulator-boot-on;
> > };
> > +
> > + lt9611_1v2: lt9611-1v2 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_1V2";
> > +
> > + vin-supply = <&vph_pwr>;
> > + regulator-min-microvolt = <120>;
> > + regulator-max-microvolt = <120>;
> > + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
>
> Why is this always-on?
It shouldn't be. Removing this in v2.
>
> > + };
> > +
> > + lt9611_3v3: lt9611-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "LT9611_3V3";
> > +
> > + vin-supply = <&vreg_bob>;
> > + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + enable-active-high;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > };
> >
> > &adsp {
> > @@ -220,6 +257,15 @@ &dispcc {
> > &dsi0 {
> > status = "okay";
> > vdda-supply = <&vreg_l6b_1p2>;
> > +
> > + ports {
> > + port@1 {
> > + endpoint {
> > + remote-endpoint = <<9611_a>;
> > + data-lanes = <0 1 2 3>;
> > + };
> > + };
> > + };
> > };
> >
> > &dsi0_phy {
> > @@ -231,6 +277,48 @@ &gpi_dma1 {
> > status = "okay";
> > };
> >
> > +&i2c15 {
> > + status = "okay";
>
> Please keep status last. (Yes I see that it goes against the convention
> in this file, so let's update that at some point as well)
Ack.
>
> > + clock-frequency = <40>;
> > +
> > + lt9611_codec: hdmi-bridge@2b {
> > + compatible = "lontium,lt9611uxc";
> > + reg = <0x2b>;
> > + status = "okay";
>
> This is the default, you can omit it.
Ack.
>
> > +
> > + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
> > + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
> > +
> > + vdd-supply = <<9611_1v2>;
> > + vcc-supply = <<9611_3v3>;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
Re: [Freedreno] [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
On Sat, 29 Oct 2022 at 00:03, Krzysztof Kozlowski
wrote:
>
> On 28/10/2022 08:08, Robert Foss wrote:
> > Enable the display subsystem and the dsi0 output for
> > the sm8350-hdk board.
> >
> > Signed-off-by: Robert Foss
> > ---
> > arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > index e6deb08c6da0..6e07feb4b3b2 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> > @@ -213,10 +213,32 @@ &cdsp {
> > firmware-name = "qcom/sm8350/cdsp.mbn";
> > };
> >
> > +&dispcc {
> > + status = "okay";
> > +};
> > +
> > +&dsi0 {
> > + status = "okay";
>
> Status is the last property.
Ack.
>
>
> Best regards,
> Krzysztof
>
Re: [Freedreno] [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes
On Sat, 29 Oct 2022 at 00:01, Krzysztof Kozlowski
wrote:
>
> On 28/10/2022 08:08, Robert Foss wrote:
> > Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> > nodes the display subsystem is configured to support
> > one DSI output.
> >
> > Signed-off-by: Robert Foss
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++-
> > 1 file changed, 192 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index b6e44cd3b394..eaa3cdee1860 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -3,6 +3,7 @@
> > * Copyright (c) 2020, Linaro Limited
> > */
> >
> > +#include
> > #include
> > #include
> > #include
> > @@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a80 {
> > };
> > };
> >
> > + mdss: mdss@ae0 {
> > + compatible = "qcom,sm8350-mdss";
> > + reg = <0 0x0ae0 0 0x1000>;
> > + reg-names = "mdss";
> > +
> > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
> > SLAVE_EBI1 0>,
> > + <&mmss_noc MASTER_MDP1 0 &mc_virt
> > SLAVE_EBI1 0>;
> > + interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > + power-domains = <&dispcc MDSS_GDSC>;
> > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > + clock-names = "iface", "bus", "nrt_bus", "core";
> > +
> > + interrupts = ;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + status = "ok";
>
> No need for this.
Ack, I'll switch to disabled.
>
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + mdss_mdp: mdp@ae01000 {
>
> Node name: display-controller
Ack.
> > + compatible = "qcom,sm8350-dpu";
> > + reg = <0 0x0ae01000 0 0x8f000>,
> > + <0 0x0aeb 0 0x2008>;
> > + reg-names = "mdp", "vbif";
> > + iommus = <&apps_smmu 0x820 0x402>;
> > +
> > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&gcc GCC_DISP_SF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > + clock-names = "bus",
> > + "nrt_bus",
> > + "iface",
> > + "lut",
> > + "core",
> > + "vsync";
> > +
> > + assigned-clocks = <&dispcc
> > DISP_CC_MDSS_VSYNC_CLK>;
> > + assigned-clock-rates = <1920>;
> > +
> > + operating-points-v2 = <&mdp_opp_table>;
> > + power-domains = <&rpmhpd SM8350_MMCX>;
> > +
> > + interrupt-parent = <&mdss>;
> > + interrupts = <0>;
> > +
> > + status = "ok";
> > +
> > + ports {
> >
Re: [Freedreno] [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells
On Fri, 28 Oct 2022 at 15:44, Bjorn Andersson wrote:
>
> On Fri, Oct 28, 2022 at 02:08:09PM +0200, Robert Foss wrote:
> > Use two interconnect cells in order to optionally
> > support a path tag.
> >
> > Signed-off-by: Robert Foss
> > ---
> > arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++--
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > index 606fab087945..b6e44cd3b394 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> > @@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
> > config_noc: interconnect@150 {
> > compatible = "qcom,sm8350-config-noc";
> > reg = <0 0x0150 0 0xa580>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
>
> You also need amend all the interconnects references with the additional
> tag cell.
Ack
>
> Regards,
> Bjorn
>
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > mc_virt: interconnect@158 {
> > compatible = "qcom,sm8350-mc-virt";
> > reg = <0 0x0158 0 0x1000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > system_noc: interconnect@168 {
> > compatible = "qcom,sm8350-system-noc";
> > reg = <0 0x0168 0 0x1c200>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > aggre1_noc: interconnect@16e {
> > compatible = "qcom,sm8350-aggre1-noc";
> > reg = <0 0x016e 0 0x1f180>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > aggre2_noc: interconnect@170 {
> > compatible = "qcom,sm8350-aggre2-noc";
> > reg = <0 0x0170 0 0x33000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > mmss_noc: interconnect@174 {
> > compatible = "qcom,sm8350-mmss-noc";
> > reg = <0 0x0174 0 0x1f080>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > lpass_ag_noc: interconnect@3c4 {
> > compatible = "qcom,sm8350-lpass-ag-noc";
> > reg = <0 0x03c4 0 0xf080>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > compute_noc: interconnect@a0c{
> > compatible = "qcom,sm8350-compute-noc";
> > reg = <0 0x0a0c 0 0xa180>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > @@ -2420,14 +2420,14 @@ usb_2_ssphy: phy@88ebe00 {
> > dc_noc: interconnect@90c {
> > compatible = "qcom,sm8350-dc-noc";
> > reg = <0 0x090c 0 0x4200>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > gem_noc: interconnect@910 {
> > compatible = "qcom,sm8350-gem-noc";
> > reg = <0 0x0910 0 0xb4000>;
> > - #interconnect-cells = <1>;
> > + #interconnect-cells = <2>;
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > --
> > 2.34.1
> >
Re: [Freedreno] [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog
On Fri, 28 Oct 2022 at 14:27, Dmitry Baryshkov
wrote:
>
> On 28/10/2022 15:08, Robert Foss wrote:
> > Add compatibility for SM8350 display subsystem, including
> > required entries in DPU hw catalog.
> > ---
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 217 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
> > 2 files changed, 218 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index d0ce7612fee8..bc829d7bdd6e 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -112,6 +112,15 @@
> >BIT(MDP_INTF3_INTR) | \
> >BIT(MDP_INTF4_INTR))
> >
> > +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_7xxx_INTR) | \
> > + BIT(MDP_INTF1_7xxx_INTR) | \
> > + BIT(MDP_INTF2_7xxx_INTR) | \
> > + BIT(MDP_INTF3_7xxx_INTR) | \
> > + 0)
> > +
> > #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > BIT(MDP_SSPP_TOP0_INTR2) | \
> > BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > @@ -364,6 +373,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
> > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > };
> >
> > +static const struct dpu_caps sm8350_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0xb,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
> > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > + .ubwc_version = DPU_HW_UBWC_VER_40,
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .has_3d_merge = true,
> > + .max_linewidth = 4096,
>
> Is it 4096 or 5120?
4096 is what I'm seeing in the downstream dts, except for the
wb-linewidth-linear property which is 5120.
So I would think 4096 is the correct value, what do you think?
>
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +};
> > +
> > static const struct dpu_caps sc7280_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0x7,
> > @@ -501,6 +524,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
> > },
> > };
> >
> > +static const struct dpu_mdp_cfg sm8350_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x494,
> > + .features = 0,
> > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > + .reg_off = 0x2AC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > + .reg_off = 0x2B4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > + .reg_off = 0x2BC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > + .reg_off = 0x2C4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > + .reg_off = 0x2AC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > + .reg_off = 0x2B4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > + .reg_off = 0x2BC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> > + .reg_off = 0x2C4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> > + .reg_off = 0x2BC, .bit_off = 20},
> > + },
> > +};
> > +
> > static const struct dpu_mdp_cfg sc7280_mdp[] = {
> > {
> > .name = "top_0", .id = MDP_TOP,
> > @@ -659,6 +709,66 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> > },
> > };
> >
> > +static const struct dpu_ctl_cfg sm8350_ctl[] = {
> > + {
> > + .name = "ctl_0", .id = CTL_0,
> > + .base = 0x15000, .len = 0x1e8,
> > + .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
> > + BIT(DPU_CTL_PINGPONG_SPLIT) |
> > + BIT(DPU_CTL_ACTIVE_CFG) |
> > + BIT(DPU_CTL_FETCH_ACTIVE) |
> > + BIT(DPU_CTL_VM_CFG) |
> > +
[Freedreno] [PATCH v1 9/9] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 106
1 file changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 6e07feb4b3b2..b38b58f8 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,32 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ lt9611_1v2: lt9611-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <&vph_pwr>;
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lt9611_3v3: lt9611-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <&vreg_bob>;
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&adsp {
@@ -220,6 +257,15 @@ &dispcc {
&dsi0 {
status = "okay";
vdda-supply = <&vreg_l6b_1p2>;
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
};
&dsi0_phy {
@@ -231,6 +277,48 @@ &gpi_dma1 {
status = "okay";
};
+&i2c15 {
+ status = "okay";
+ clock-frequency = <40>;
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+ status = "okay";
+
+ interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+
+ };
+ };
+};
+
&mdss {
status = "okay";
};
@@ -248,6 +336,10 @@ &qupv3_id_0 {
status = "okay";
};
+&qupv3_id_2 {
+ status = "okay";
+};
+
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +636,18 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio48";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ };
+
+ lt9611_irq_pin: lt9611-irq {
+ pins = "gpio50";
+ function = "gpio";
+ bias-disable;
+ };
};
--
2.34.1
[Freedreno] [PATCH v1 8/9] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..6e07feb4b3b2 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+&dispcc {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+ vdda-supply = <&vreg_l6b_1p2>;
+};
+
+&dsi0_phy {
+ status = "okay";
+ vdds-supply = <&vreg_l5b_0p88>;
+};
+
&gpi_dma1 {
status = "okay";
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
2.34.1
[Freedreno] [PATCH v1 7/9] arm64: dts: qcom: sm8350: Add display system nodes
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++-
1 file changed, 192 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index b6e44cd3b394..eaa3cdee1860 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include
#include
#include
#include
@@ -2535,14 +2536,200 @@ usb_2_dwc3: usb@a80 {
};
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ status = "ok";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+ iommus = <&apps_smmu 0x820 0x402>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ status = "ok";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<&dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: mdp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-2 {
+ opp-hz = /bits/ 64 <2>;
+ required-opps =
<&rpmhpd_opp_low_svs>;
+
[Freedreno] [PATCH v1 6/9] arm64: dts: qcom: sm8350: Use 2 interconnect cells
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 606fab087945..b6e44cd3b394 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@158 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@168 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x0168 0 0x1c200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e 0 0x1f180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@170 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x0170 0 0x33000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@174 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x0174 0 0x1f080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3c4 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c4 0 0xf080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
compute_noc: interconnect@a0c{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c 0 0xa180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
@@ -2420,14 +2420,14 @@ usb_2_ssphy: phy@88ebe00 {
dc_noc: interconnect@90c {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c 0 0x4200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@910 {
compatible = "qcom,sm8350-gem-noc";
reg = <0 0x0910 0 0xb4000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
--
2.34.1
[Freedreno] [PATCH v1 2/9] drm/msm/dpu: Refactor sc7280_pp location
The sc7280_pp declaration is not located by the other _pp
declarations, but rather hidden around the _merge_3d
declarations. Let's fix this to avoid confusion.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0239a811d5ec..d0ce7612fee8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1175,6 +1175,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sc7280_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+ PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
+};
+
static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x7, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1198,13 +1205,6 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] =
{
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
};
-static const struct dpu_pingpong_cfg sc7280_pp[] = {
- PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
- PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
-};
-
/*
* DSC sub blocks config
*/
--
2.34.1
[Freedreno] [PATCH v1 5/9] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e72a04411888..606fab087945 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2557,7 +2557,6 @@ dispcc: clock-controller@af0 {
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8350_MMCX>;
- power-domain-names = "mmcx";
};
adsp: remoteproc@1730 {
--
2.34.1
[Freedreno] [PATCH v1 4/9] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names
Add GPIO line names as described by the sm8350-hdk schematic.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ &slpi {
&tlmm {
gpio-reserved-ranges = <52 8>;
+
+ gpio-line-names =
+ "APPS_I2C_SDA", /* GPIO_0 */
+ "APPS_I2C_SCL",
+ "FSA_INT_N",
+ "USER_LED3_EN",
+ "SMBUS_SDA_1P8",
+ "SMBUS_SCL_1P8",
+ "2M2_3P3_EN",
+ "ALERT_DUAL_M2_N",
+ "EXP_UART_CTS",
+ "EXP_UART_RFR",
+ "EXP_UART_TX", /* GPIO_10 */
+ "EXP_UART_RX",
+ "NC",
+ "NC",
+ "RCM_MARKER1",
+ "WSA0_EN",
+ "CAM1_RESET_N",
+ "CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP0_RESET_N",
+ "DISP1_RESET_N",
+ "ETH_RESET",
+ "RCM_MARKER2",
+ "CAM_DC_MIPI_MUX_EN",
+ "CAM_DC_MIPI_MUX_SEL",
+ "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+ "AFC_PHY_TA_D_MINUS",
+ "PM8008_1_IRQ",
+ "PM8008_1_RESET_N",
+ "PM8008_2_IRQ",
+ "PM8008_2_RESET_N",
+ "CAM_DC_I3C_SDA",
+ "CAM_DC_I3C_SCL",
+ "FP_INT_N",
+ "FP_WUHB_INT_N",
+ "SMB_SPMI_DATA", /* GPIO_40 */
+ "SMB_SPMI_CLK",
+ "USB_HUB_RESET",
+ "FORCE_USB_BOOT",
+ "LRF_IRQ",
+ "NC",
+ "IMU2_INT",
+ "HDMI_3P3_EN",
+ "HDMI_RSTN",
+ "HDMI_1P2_EN",
+ "HDMI_INT", /* GPIO_50 */
+ "USB1_ID",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCLC",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "CAM_DC_SPI0_MISO",
+ "CAM_DC_SPI0_MOSI",
+ "CAM_DC_SPI0_CLK",
+ "CAM_DC_SPI0_CS_N",
+ "CAM_DC_SPI1_MISO",
+ "CAM_DC_SPI1_MOSI",
+ "CAM_DC_SPI1_CLK",
+ "CAM_DC_SPI1_CS_N",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_PHY_PS",
+ "MDP_VSYNC_P",
+ "MDP_VSYNC_S",
+ "ETH_3P3_EN",
+ "RADAR_INT",
+ "NFC_DWL_REQ",
+ "SM_GPIO_87",
+ "WCD_RESET_N",
+ "ALSP_INT_N",
+ "PRESS_INT", /* GPIO_90 */
+ "SAR_INT_N",
+ "SD_CARD_DET_N",
+ "NC",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "PCIE1_RESET_N",
+ "PCIE1_CLK_REQ_N",
+ "PCIE1_WAKE_N",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2&qu
[Freedreno] [PATCH v1 3/9] drm/msm/dpu: Add SM8350 to hw catalog
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 217 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
2 files changed, 218 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d0ce7612fee8..bc829d7bdd6e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -364,6 +373,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sc7280_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x7,
@@ -501,6 +524,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2BC, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sc7280_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -659,6 +709,66 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
+ BIT(DPU_CTL_PINGPONG_SPLIT) |
+ BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) |
+ BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) |
+ BIT(DPU_CTL_FETCH_ACTIVE) |
+ BIT(DPU_CTL_VM_CFG) |
+ BIT(DPU_CTL_UNIFIED_DSPP_FLUSH),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+
[Freedreno] [PATCH v1 1/9] drm/msm: Add compatibles for SM8350 display
Add compatible string for "qcom,sm8350-dpu" and
"qcom,sm8350-mdss".
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 008e1420e6e5..70683dbc6b32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1315,6 +1315,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8350-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e13c5c12b775..fd5a95cace16 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -447,6 +447,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{}
};
MODULE_DEVICE_TABLE(of, mdss_dt_match);
--
2.34.1
[Freedreno] [PATCH v1 0/9] Enable Display for SM8350
This series implements display support for SM8350 and enables HDMI output for the SM8350-HDK platform. Robert Foss (9): drm/msm: Add compatibles for SM8350 display drm/msm/dpu: Refactor sc7280_pp location drm/msm/dpu: Add SM8350 to hw catalog arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names arm64: dts: qcom: sm8350: Remove mmxc power-domain-name arm64: dts: qcom: sm8350: Use 2 interconnect cells arm64: dts: qcom: sm8350: Add display system nodes arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 333 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 217 +++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 227 +++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 1 + 6 files changed, 760 insertions(+), 20 deletions(-) -- 2.34.1
Re: [Freedreno] [PATCH v2] drm/bridge: adv7533: remove dynamic lane switching from adv7533 bridge
On Tue, 11 Oct 2022 at 23:11, Abhinav Kumar wrote:
>
> adv7533 bridge tries to dynamically switch lanes based on the
> mode by detaching and attaching the mipi dsi device.
>
> This approach is incorrect because this method of dynamic switch of
> detaching and attaching the mipi dsi device also results in removing
> and adding the component which is not necessary.
>
> This approach is also prone to deadlocks. So for example, on the
> db410c whenever this path is executed with lockdep enabled,
> this results in a deadlock due to below ordering of locks.
>
> -> #1 (crtc_ww_class_acquire){+.+.}-{0:0}:
> lock_acquire+0x6c/0x90
> drm_modeset_acquire_init+0xf4/0x150
> drmm_mode_config_init+0x220/0x770
> msm_drm_bind+0x13c/0x654
> try_to_bring_up_aggregate_device+0x164/0x1d0
> __component_add+0xa8/0x174
> component_add+0x18/0x2c
> dsi_dev_attach+0x24/0x30
> dsi_host_attach+0x98/0x14c
> devm_mipi_dsi_attach+0x38/0xb0
> adv7533_attach_dsi+0x8c/0x110
> adv7511_probe+0x5a0/0x930
> i2c_device_probe+0x30c/0x350
> really_probe.part.0+0x9c/0x2b0
> __driver_probe_device+0x98/0x144
> driver_probe_device+0xac/0x14c
> __device_attach_driver+0xbc/0x124
> bus_for_each_drv+0x78/0xd0
> __device_attach+0xa8/0x1c0
> device_initial_probe+0x18/0x24
> bus_probe_device+0xa0/0xac
> deferred_probe_work_func+0x90/0xd0
> process_one_work+0x28c/0x6b0
> worker_thread+0x240/0x444
> kthread+0x110/0x114
> ret_from_fork+0x10/0x20
>
> -> #0 (component_mutex){+.+.}-{3:3}:
> __lock_acquire+0x1280/0x20ac
> lock_acquire.part.0+0xe0/0x230
> lock_acquire+0x6c/0x90
> __mutex_lock+0x84/0x400
> mutex_lock_nested+0x3c/0x70
> component_del+0x34/0x170
> dsi_dev_detach+0x24/0x30
> dsi_host_detach+0x20/0x64
> mipi_dsi_detach+0x2c/0x40
> adv7533_mode_set+0x64/0x90
> adv7511_bridge_mode_set+0x210/0x214
> drm_bridge_chain_mode_set+0x5c/0x84
> crtc_set_mode+0x18c/0x1dc
> drm_atomic_helper_commit_modeset_disables+0x40/0x50
> msm_atomic_commit_tail+0x1d0/0x6e0
> commit_tail+0xa4/0x180
> drm_atomic_helper_commit+0x178/0x3b0
> drm_atomic_commit+0xa4/0xe0
> drm_client_modeset_commit_atomic+0x228/0x284
> drm_client_modeset_commit_locked+0x64/0x1d0
> drm_client_modeset_commit+0x34/0x60
> drm_fb_helper_lastclose+0x74/0xcc
> drm_lastclose+0x3c/0x80
> drm_release+0xfc/0x114
> __fput+0x70/0x224
> fput+0x14/0x20
> task_work_run+0x88/0x1a0
> do_exit+0x350/0xa50
> do_group_exit+0x38/0xa4
> __wake_up_parent+0x0/0x34
> invoke_syscall+0x48/0x114
> el0_svc_common.constprop.0+0x60/0x11c
> do_el0_svc+0x30/0xc0
> el0_svc+0x58/0x100
> el0t_64_sync_handler+0x1b0/0x1bc
> el0t_64_sync+0x18c/0x190
>
> Due to above reasons, remove the dynamic lane switching
> code from adv7533 bridge chip and filter out the modes
> which would need different number of lanes as compared
> to the initialization time using the mode_valid callback.
>
> This can be potentially re-introduced by using the pre_enable()
> callback but this needs to be evaluated first whether such an
> approach will work so this will be done with a separate change.
>
> changes since RFC:
> - Fix commit text and add TODO comment
>
> changes in v2:
> - Fix checkpatch formatting errors
>
> Fixes: 62b2f026cd8e ("drm/bridge: adv7533: Change number of DSI lanes
> dynamically")
> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/16
> Suggested-by: Dmitry Baryshkov
> Signed-off-by: Abhinav Kumar
> Reviewed-by: Robert Foss
> Link:
> https://lore.kernel.org/r/1661797363-7564-1-git-send-email-quic_abhin...@quicinc.com
> ---
> drivers/gpu/drm/bridge/adv7511/adv7511.h | 3 ++-
> drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 18 ++
> drivers/gpu/drm/bridge/adv7511/adv7533.c | 25 +
> 3 files changed, 29 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h
> b/drivers/gpu/drm/bridge/adv7511/adv7511.h
> index a031a0cd1f18..1053d185b24c 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
> @@ -405,7 +405,8 @@ static inline int adv7511_cec_init(struct device *dev,
> struct adv7511 *adv7511)
>
> void adv7533_dsi_power_on(
Re: [Freedreno] [PATCH] drm/bridge: adv7533: remove dynamic lane switching from adv7533 bridge
On Thu, 6 Oct 2022 at 17:07, Abhinav Kumar wrote:
>
> Hi Robert
>
> Thanks for the review.
>
> On 10/4/2022 8:55 AM, Robert Foss wrote:
> > On Mon, 29 Aug 2022 at 20:23, Abhinav Kumar
> > wrote:
> >>
> >> adv7533 bridge tries to dynamically switch lanes based on the
> >> mode by detaching and attaching the mipi dsi device.
> >>
> >> This approach is incorrect because this method of dynamic switch of
> >> detaching and attaching the mipi dsi device also results in removing
> >> and adding the component which is not necessary.
> >>
> >> This approach is also prone to deadlocks. So for example, on the
> >> db410c whenever this path is executed with lockdep enabled,
> >> this results in a deadlock due to below ordering of locks.
> >>
> >> -> #1 (crtc_ww_class_acquire){+.+.}-{0:0}:
> >> lock_acquire+0x6c/0x90
> >> drm_modeset_acquire_init+0xf4/0x150
> >> drmm_mode_config_init+0x220/0x770
> >> msm_drm_bind+0x13c/0x654
> >> try_to_bring_up_aggregate_device+0x164/0x1d0
> >> __component_add+0xa8/0x174
> >> component_add+0x18/0x2c
> >> dsi_dev_attach+0x24/0x30
> >> dsi_host_attach+0x98/0x14c
> >> devm_mipi_dsi_attach+0x38/0xb0
> >> adv7533_attach_dsi+0x8c/0x110
> >> adv7511_probe+0x5a0/0x930
> >> i2c_device_probe+0x30c/0x350
> >> really_probe.part.0+0x9c/0x2b0
> >> __driver_probe_device+0x98/0x144
> >> driver_probe_device+0xac/0x14c
> >> __device_attach_driver+0xbc/0x124
> >> bus_for_each_drv+0x78/0xd0
> >> __device_attach+0xa8/0x1c0
> >> device_initial_probe+0x18/0x24
> >> bus_probe_device+0xa0/0xac
> >> deferred_probe_work_func+0x90/0xd0
> >> process_one_work+0x28c/0x6b0
> >> worker_thread+0x240/0x444
> >> kthread+0x110/0x114
> >> ret_from_fork+0x10/0x20
> >>
> >> -> #0 (component_mutex){+.+.}-{3:3}:
> >> __lock_acquire+0x1280/0x20ac
> >> lock_acquire.part.0+0xe0/0x230
> >> lock_acquire+0x6c/0x90
> >> __mutex_lock+0x84/0x400
> >> mutex_lock_nested+0x3c/0x70
> >> component_del+0x34/0x170
> >> dsi_dev_detach+0x24/0x30
> >> dsi_host_detach+0x20/0x64
> >> mipi_dsi_detach+0x2c/0x40
> >> adv7533_mode_set+0x64/0x90
> >> adv7511_bridge_mode_set+0x210/0x214
> >> drm_bridge_chain_mode_set+0x5c/0x84
> >> crtc_set_mode+0x18c/0x1dc
> >> drm_atomic_helper_commit_modeset_disables+0x40/0x50
> >> msm_atomic_commit_tail+0x1d0/0x6e0
> >> commit_tail+0xa4/0x180
> >> drm_atomic_helper_commit+0x178/0x3b0
> >> drm_atomic_commit+0xa4/0xe0
> >> drm_client_modeset_commit_atomic+0x228/0x284
> >> drm_client_modeset_commit_locked+0x64/0x1d0
> >> drm_client_modeset_commit+0x34/0x60
> >> drm_fb_helper_lastclose+0x74/0xcc
> >> drm_lastclose+0x3c/0x80
> >> drm_release+0xfc/0x114
> >> __fput+0x70/0x224
> >> fput+0x14/0x20
> >> task_work_run+0x88/0x1a0
> >> do_exit+0x350/0xa50
> >> do_group_exit+0x38/0xa4
> >> __wake_up_parent+0x0/0x34
> >> invoke_syscall+0x48/0x114
> >> el0_svc_common.constprop.0+0x60/0x11c
> >> do_el0_svc+0x30/0xc0
> >> el0_svc+0x58/0x100
> >> el0t_64_sync_handler+0x1b0/0x1bc
> >> el0t_64_sync+0x18c/0x190
> >>
> >> Due to above reasons, remove the dynamic lane switching
> >> code from adv7533 bridge chip and filter out the modes
> >> which would need different number of lanes as compared
> >> to the initialization time using the mode_valid callback.
> >>
> >> This can be potentially re-introduced by using the pre_enable()
> >> callback but this needs to be evaluated first whether such an
> >> approach will work so this will be done with a separate change.
> >>
> >> changes since RFC:
> >> - Fix commit text and add TODO comment
> >>
> >> Fixes: 62b2f026cd8e ("drm/bridge: adv7533: Change number of DSI lanes
> >>
Re: [Freedreno] [PATCH] drm/bridge: adv7533: remove dynamic lane switching from adv7533 bridge
valid(struct adv7511 *adv,
> + const struct drm_display_mode *mode);
> int adv7533_patch_registers(struct adv7511 *adv);
> int adv7533_patch_cec_registers(struct adv7511 *adv);
> int adv7533_attach_dsi(struct adv7511 *adv);
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> index 5bb9300040dd..1115ef9be83c 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> @@ -697,7 +697,7 @@ adv7511_detect(struct adv7511 *adv7511, struct
> drm_connector *connector)
> }
>
> static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511,
> - struct drm_display_mode *mode)
> + const struct drm_display_mode *mode)
> {
> if (mode->clock > 165000)
> return MODE_CLOCK_HIGH;
> @@ -791,9 +791,6 @@ static void adv7511_mode_set(struct adv7511 *adv7511,
> regmap_update_bits(adv7511->regmap, 0x17,
> 0x60, (vsync_polarity << 6) | (hsync_polarity << 5));
>
> - if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
> - adv7533_mode_set(adv7511, adj_mode);
> -
> drm_mode_copy(&adv7511->curr_mode, adj_mode);
>
> /*
> @@ -913,6 +910,18 @@ static void adv7511_bridge_mode_set(struct drm_bridge
> *bridge,
> adv7511_mode_set(adv, mode, adj_mode);
> }
>
> +static enum drm_mode_status adv7511_bridge_mode_valid(struct drm_bridge
> *bridge,
> + const struct drm_display_info *info,
> + const struct drm_display_mode *mode)
> +{
> + struct adv7511 *adv = bridge_to_adv7511(bridge);
> +
> + if (adv->type == ADV7533 || adv->type == ADV7535)
> + return adv7533_mode_valid(adv, mode);
> + else
> + return adv7511_mode_valid(adv, mode);
> +}
> +
> static int adv7511_bridge_attach(struct drm_bridge *bridge,
> enum drm_bridge_attach_flags flags)
> {
> @@ -960,6 +969,7 @@ static const struct drm_bridge_funcs adv7511_bridge_funcs
> = {
> .enable = adv7511_bridge_enable,
> .disable = adv7511_bridge_disable,
> .mode_set = adv7511_bridge_mode_set,
> + .mode_valid = adv7511_bridge_mode_valid,
> .attach = adv7511_bridge_attach,
> .detect = adv7511_bridge_detect,
> .get_edid = adv7511_bridge_get_edid,
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c
> b/drivers/gpu/drm/bridge/adv7511/adv7533.c
> index ef6270806d1d..5f590abd6403 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7533.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c
> @@ -100,26 +100,27 @@ void adv7533_dsi_power_off(struct adv7511 *adv)
> regmap_write(adv->regmap_cec, 0x27, 0x0b);
> }
>
> -void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode
> *mode)
> +enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,
> + const struct drm_display_mode *mode)
> {
> + int lanes;
> struct mipi_dsi_device *dsi = adv->dsi;
> - int lanes, ret;
> -
> - if (adv->num_dsi_lanes != 4)
> - return;
>
> if (mode->clock > 8)
> lanes = 4;
> else
> lanes = 3;
>
> - if (lanes != dsi->lanes) {
> - mipi_dsi_detach(dsi);
> - dsi->lanes = lanes;
> - ret = mipi_dsi_attach(dsi);
> - if (ret)
> - dev_err(&dsi->dev, "failed to change host lanes\n");
> - }
> + /*
> +* TODO: add support for dynamic switching of lanes
> +* by using the bridge pre_enable() op . Till then filter
> +* out the modes which shall need different number of lanes
> +* than what was configured in the device tree.
> +*/
> + if (lanes != dsi->lanes)
> + return MODE_BAD;
> +
> + return MODE_OK;
> }
>
> int adv7533_patch_registers(struct adv7511 *adv)
> --
> 2.7.4
>
This patch has some checkpatch --style warnings, with those fixed feel
free to add my r-b.
Reviewed-by: Robert Foss
Re: [Freedreno] [PATCH v6 00/10] Add PSR support for eDP
On Fri, 29 Jul 2022 at 02:22, Doug Anderson wrote: > > Hi, > > On Mon, Jul 11, 2022 at 5:57 AM Vinod Polimera > wrote: > > > > Changes in v2: > > - Use dp bridge to set psr entry/exit instead of dpu_enocder. > > - Don't modify whitespaces. > > - Set self refresh aware from atomic_check. > > - Set self refresh aware only if psr is supported. > > - Provide a stub for msm_dp_display_set_psr. > > - Move dp functions to bridge code. > > > > Changes in v3: > > - Change callback names to reflect atomic interfaces. > > - Move bridge callback change to separate patch as suggested by Dmitry. > > - Remove psr function declaration from msm_drv.h. > > - Set self_refresh_aware flag only if psr is supported. > > - Modify the variable names to simpler form. > > - Define bit fields for PSR settings. > > - Add comments explaining the steps to enter/exit psr. > > - Change DRM_INFO to drm_dbg_db. > > > > Changes in v4: > > - Move the get crtc functions to drm_atomic. > > - Add atomic functions for DP bridge too. > > - Add ternary operator to choose eDP or DP ops. > > - Return true/false instead of 1/0. > > - mode_valid missing in the eDP bridge ops. > > - Move the functions to get crtc into drm_atomic.c. > > - Fix compilation issues. > > - Remove dpu_assign_crtc and get crtc from drm_enc instead of dpu_enc. > > - Check for crtc state enable while reserving resources. > > > > Changes in v5: > > - Move the mode_valid changes into a different patch. > > - Complete psr_op_comp only when isr is set. > > - Move the DP atomic callback changes to a different patch. > > - Get crtc from drm connector state crtc. > > - Move to separate patch for check for crtc state enable while > > reserving resources. > > > > Changes in v6: > > - Remove crtc from dpu_encoder_virt struct. > > - fix crtc check during vblank toggle crtc. > > - Misc changes. > > > > Signed-off-by: Sankeerth Billakanti > > Signed-off-by: Kalyan Thota > > Signed-off-by: Vinod Polimera > > > > Vinod Polimera (10): > > drm/msm/disp/dpu: clear dpu_assign_crtc and get crtc from connector > > state instead of dpu_enc > > drm: add helper functions to retrieve old and new crtc > > drm/msm/dp: use atomic callbacks for DP bridge ops > > drm/msm/dp: Add basic PSR support for eDP > > drm/msm/dp: use the eDP bridge ops to validate eDP modes > > drm/bridge: use atomic enable/disable callbacks for panel bridge > > drm/bridge: add psr support for panel bridge callbacks > > drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder > > functions > > drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver > > drm/msm/disp/dpu: check for crtc enable rather than crtc active to > > release shared resources > > > > drivers/gpu/drm/bridge/panel.c | 68 -- > > drivers/gpu/drm/drm_atomic.c| 60 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 17 ++- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 56 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 8 -- > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- > > drivers/gpu/drm/msm/dp/dp_catalog.c | 81 > > drivers/gpu/drm/msm/dp/dp_catalog.h | 4 + > > drivers/gpu/drm/msm/dp/dp_ctrl.c| 73 +++ > > drivers/gpu/drm/msm/dp/dp_ctrl.h| 3 + > > drivers/gpu/drm/msm/dp/dp_display.c | 31 +++-- > > drivers/gpu/drm/msm/dp/dp_display.h | 2 + > > drivers/gpu/drm/msm/dp/dp_drm.c | 184 > > ++-- > > drivers/gpu/drm/msm/dp/dp_drm.h | 9 +- > > drivers/gpu/drm/msm/dp/dp_link.c| 36 ++ > > drivers/gpu/drm/msm/dp/dp_panel.c | 22 > > drivers/gpu/drm/msm/dp/dp_panel.h | 6 + > > drivers/gpu/drm/msm/dp/dp_reg.h | 27 > > include/drm/drm_atomic.h| 7 ++ > > 19 files changed, 631 insertions(+), 65 deletions(-) > Which tree does this series apply to?
Re: [Freedreno] [PATCH] drm/msm/dpu: Add more of the INTF interrupt regions
On Tue, 23 Nov 2021 at 16:39, Bjorn Andersson
wrote:
>
> In addition to the other 7xxx INTF interrupt regions, SM8350 has
> additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
> these. The 7xxx naming scheme of the bits are kept for consistency.
>
> Signed-off-by: Bjorn Andersson
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index d2b6dca487e3..a77a5eaa78ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -30,6 +30,9 @@
> #define MDP_AD4_INTR_STATUS_OFF0x420
> #define MDP_INTF_0_OFF_REV_7xxx 0x34000
> #define MDP_INTF_1_OFF_REV_7xxx 0x35000
> +#define MDP_INTF_2_OFF_REV_7xxx 0x36000
> +#define MDP_INTF_3_OFF_REV_7xxx 0x37000
> +#define MDP_INTF_4_OFF_REV_7xxx 0x38000
> #define MDP_INTF_5_OFF_REV_7xxx 0x39000
>
> /**
> @@ -110,6 +113,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
> MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
> MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
> },
> + {
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> + {
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> + {
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,
> + MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS
> + },
> {
> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
> MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index d50e78c9f148..1ab75cccd145 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -26,6 +26,9 @@ enum dpu_hw_intr_reg {
> MDP_AD4_1_INTR,
> MDP_INTF0_7xxx_INTR,
> MDP_INTF1_7xxx_INTR,
> + MDP_INTF2_7xxx_INTR,
> + MDP_INTF3_7xxx_INTR,
> + MDP_INTF4_7xxx_INTR,
> MDP_INTF5_7xxx_INTR,
> MDP_INTR_MAX,
> };
Reviewed-by: Robert Foss
[Freedreno] [PATCH v1] drm/msm/dpu: Fix address of SM8150 PINGPONG5 IRQ register
Both PINGPONG4 and PINGPONG5 IRQ registers are using the
same address, which is incorrect. PINGPONG4 should use the
register offset 30, and PINGPONG5 should use the register
offset 31 according to the downstream driver.
Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw
catalog")
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2e482cdd7b3c5..420d78cfce8af 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -794,7 +794,7 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
-1),
PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
- DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
-1),
};
--
2.30.2
[Freedreno] [PATCH v1] drm/msm/dpu: Fix sm8250_mdp register length
The downstream dts lists this value as 0x494, and not
0x45c.
Fixes: af776a3e1c30 ("drm/msm/dpu: add SM8250 to hw catalog")
Signed-off-by: Robert Foss
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 189f3533525c..5d30c7f33930 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -244,7 +244,7 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
static const struct dpu_mdp_cfg sm8250_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
- .base = 0x0, .len = 0x45C,
+ .base = 0x0, .len = 0x494,
.features = 0,
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
--
2.30.2
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Re: [Freedreno] [PATCH] drm/dsi: Add _NO_ to MIPI_DSI_* flags disabling features
Hey Nicolas,
Thanks for submitting this, making these flags more intuitive is really nice.
This looks good to me, feel free to add my r-b.
Reviewed-by: Robert Foss
On Thu, 11 Feb 2021 at 04:34, Nicolas Boichat wrote:
>
> Many of the DSI flags have names opposite to their actual effects,
> e.g. MIPI_DSI_MODE_EOT_PACKET means that EoT packets will actually
> be disabled. Fix this by including _NO_ in the flag names, e.g.
> MIPI_DSI_MODE_NO_EOT_PACKET.
>
> Signed-off-by: Nicolas Boichat
> ---
> I considered adding _DISABLE_ instead, but that'd make the
> flag names a big too long.
>
> Generated with:
> flag=MIPI_DSI_MODE_VIDEO_HFP; git grep $flag | cut -f1 -d':' | \
> xargs -I{} sed -i -e "s/$flag/MIPI_DSI_MODE_VIDEO_NO_HFP/" {}
> flag=MIPI_DSI_MODE_VIDEO_HBP; git grep $flag | cut -f1 -d':' | \
> xargs -I{} sed -i -e "s/$flag/MIPI_DSI_MODE_VIDEO_NO_HBP/" {}
> flag=MIPI_DSI_MODE_VIDEO_HSA; git grep $flag | cut -f1 -d':' | \
> xargs -I{} sed -i -e "s/$flag/MIPI_DSI_MODE_VIDEO_NO_HSA/" {}
> flag=MIPI_DSI_MODE_EOT_PACKET; git grep $flag | cut -f1 -d':' | \
> xargs -I{} sed -i -e "s/$flag/MIPI_DSI_MODE_NO_EOT_PACKET/" {}
> (then minor format changes)
>
> drivers/gpu/drm/bridge/adv7511/adv7533.c | 2 +-
> drivers/gpu/drm/bridge/analogix/anx7625.c| 2 +-
> drivers/gpu/drm/bridge/cdns-dsi.c| 4 ++--
> drivers/gpu/drm/bridge/tc358768.c| 2 +-
> drivers/gpu/drm/exynos/exynos_drm_dsi.c | 8
> drivers/gpu/drm/mcde/mcde_dsi.c | 2 +-
> drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +-
> drivers/gpu/drm/msm/dsi/dsi_host.c | 8
> drivers/gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c | 2 +-
> drivers/gpu/drm/panel/panel-dsi-cm.c | 2 +-
> drivers/gpu/drm/panel/panel-elida-kd35t133.c | 2 +-
> drivers/gpu/drm/panel/panel-khadas-ts050.c | 2 +-
> drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c | 2 +-
> drivers/gpu/drm/panel/panel-leadtek-ltk500hd1829.c | 2 +-
> drivers/gpu/drm/panel/panel-novatek-nt35510.c| 2 +-
> drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c | 2 +-
> drivers/gpu/drm/panel/panel-samsung-s6d16d0.c| 2 +-
> drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c | 2 +-
> drivers/gpu/drm/panel/panel-samsung-s6e63m0-dsi.c| 2 +-
> drivers/gpu/drm/panel/panel-samsung-s6e8aa0.c| 4 ++--
> drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c | 2 +-
> drivers/gpu/drm/panel/panel-simple.c | 2 +-
> drivers/gpu/drm/panel/panel-sony-acx424akp.c | 2 +-
> drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c | 2 +-
> include/drm/drm_mipi_dsi.h | 8
> 25 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c
> b/drivers/gpu/drm/bridge/adv7511/adv7533.c
> index aa19d5a40e31..59d718bde8c4 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7533.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c
> @@ -165,7 +165,7 @@ int adv7533_attach_dsi(struct adv7511 *adv)
> dsi->lanes = adv->num_dsi_lanes;
> dsi->format = MIPI_DSI_FMT_RGB888;
> dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
> MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> - MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
> + MIPI_DSI_MODE_NO_EOT_PACKET |
> MIPI_DSI_MODE_VIDEO_HSE;
>
> ret = mipi_dsi_attach(dsi);
> if (ret < 0) {
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c
> b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 65cc05982f82..beecfe6bf359 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1334,7 +1334,7 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
> dsi->format = MIPI_DSI_FMT_RGB888;
> dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
> MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> - MIPI_DSI_MODE_EOT_PACKET|
> + MIPI_DSI_MODE_NO_EOT_PACKET |
> MIPI_DSI_MODE_VIDEO_HSE;
>
> if (mipi_dsi_attach(dsi) < 0) {
> diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c
> b/drivers/gpu/drm/bridge/cdns-dsi.c
> index 76373e31df92..34aa24269a57 100644
> --- a/drivers/gpu/drm/bridge/cdns-dsi.c
> +++ b/drivers/gpu/drm/bridge/cdns-dsi.c
> @@ -829,7 +829,7 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
> *bridge)
> tmp = DIV_ROUND_UP(dsi_cfg.htotal, nlanes) -
> DIV_ROUND_UP(dsi_cfg.hsa, nlanes);
>
&
Re: [Freedreno] [RESEND PATCH v3] drm/msm: Move fence put to where failure occurs
On 2018-12-04 21:21, Rob Clark wrote:
On Tue, Dec 4, 2018 at 11:56 AM Robert Foss wrote:
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
Reviewed-by: Chris Wilson
Cc: sta...@vger.kernel.org
Fyi, this is queued up in msm-next/fixes
Ah!
I had a look for it in drm=misc-next, but didn't find it.
Thanks for the heads up!
BR,
-R
---
drivers/gpu/drm/msm/msm_gem_submit.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..d5e6665a4c8f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,6 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
+ struct dma_fence *in_fence;
+
in_fence = sync_file_get_fence(args->fence_fd);
if (!in_fence)
@@ -453,11 +454,13 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
* Wait if the fence is from a foreign context, or if the fence
* array contains any fence from a foreign context.
*/
- if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
+ ret = 0;
+ if (!dma_fence_match_context(in_fence, ring->fctx->context))
ret = dma_fence_wait(in_fence, true);
- if (ret)
- return ret;
- }
+
+ dma_fence_put(in_fence);
+ if (ret)
+ return ret;
}
ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -583,8 +586,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
out:
- if (in_fence)
- dma_fence_put(in_fence);
submit_cleanup(submit);
if (ret)
msm_gem_submit_free(submit);
--
2.17.1
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[Freedreno] [RESEND PATCH v3] drm/msm: Move fence put to where failure occurs
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
Reviewed-by: Chris Wilson
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/msm/msm_gem_submit.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..d5e6665a4c8f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,6 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
+ struct dma_fence *in_fence;
+
in_fence = sync_file_get_fence(args->fence_fd);
if (!in_fence)
@@ -453,11 +454,13 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
* Wait if the fence is from a foreign context, or if the fence
* array contains any fence from a foreign context.
*/
- if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
+ ret = 0;
+ if (!dma_fence_match_context(in_fence, ring->fctx->context))
ret = dma_fence_wait(in_fence, true);
- if (ret)
- return ret;
- }
+
+ dma_fence_put(in_fence);
+ if (ret)
+ return ret;
}
ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -583,8 +586,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
out:
- if (in_fence)
- dma_fence_put(in_fence);
submit_cleanup(submit);
if (ret)
msm_gem_submit_free(submit);
--
2.17.1
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Re: [Freedreno] [PATCH v3] drm/msm: Move fence put to where failure occurs
Hey,
I think this patch is ready for inclusion.
Rob.
On 2018-11-05 11:13, Robert Foss wrote:
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
Reviewed-by: Chris Wilson
Cc: sta...@vger.kernel.org
---
Changes since v2:
- Chris Wilson: Added r-b and stable kernel tag
Changes since v1:
- Chris Wilson: Make sure that dma_fence_put() is always executed
drivers/gpu/drm/msm/msm_gem_submit.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..d5e6665a4c8f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,6 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
+ struct dma_fence *in_fence;
+
in_fence = sync_file_get_fence(args->fence_fd);
if (!in_fence)
@@ -453,11 +454,13 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
* Wait if the fence is from a foreign context, or if the fence
* array contains any fence from a foreign context.
*/
- if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
+ ret = 0;
+ if (!dma_fence_match_context(in_fence, ring->fctx->context))
ret = dma_fence_wait(in_fence, true);
- if (ret)
- return ret;
- }
+
+ dma_fence_put(in_fence);
+ if (ret)
+ return ret;
}
ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -583,8 +586,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
out:
- if (in_fence)
- dma_fence_put(in_fence);
submit_cleanup(submit);
if (ret)
msm_gem_submit_free(submit);
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[Freedreno] [PATCH v3] drm/msm: Move fence put to where failure occurs
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
Reviewed-by: Chris Wilson
Cc: sta...@vger.kernel.org
---
Changes since v2:
- Chris Wilson: Added r-b and stable kernel tag
Changes since v1:
- Chris Wilson: Make sure that dma_fence_put() is always executed
drivers/gpu/drm/msm/msm_gem_submit.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..d5e6665a4c8f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,6 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
+ struct dma_fence *in_fence;
+
in_fence = sync_file_get_fence(args->fence_fd);
if (!in_fence)
@@ -453,11 +454,13 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
* Wait if the fence is from a foreign context, or if the fence
* array contains any fence from a foreign context.
*/
- if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
+ ret = 0;
+ if (!dma_fence_match_context(in_fence, ring->fctx->context))
ret = dma_fence_wait(in_fence, true);
- if (ret)
- return ret;
- }
+
+ dma_fence_put(in_fence);
+ if (ret)
+ return ret;
}
ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -583,8 +586,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
out:
- if (in_fence)
- dma_fence_put(in_fence);
submit_cleanup(submit);
if (ret)
msm_gem_submit_free(submit);
--
2.17.1
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Re: [Freedreno] [PATCH v2] drm/msm: Move fence put to where failure occurs
Hey Chris, On 2018-11-02 13:16, Chris Wilson wrote: Quoting Robert Foss (2018-11-02 12:13:13) If dma_fence_wait fails to wait for a supplied in-fence in msm_ioctl_gem_submit, make sure we release that in-fence. Also remove this dma_fence_put() from the 'out' label. Signed-off-by: Robert Foss Reviewed-by: Chris Wilson Danke! Rob, this probably merits a cc:stable tag -- if the wait was interrupted by a signal, the fence would be leaked. Ack, CC-ed the v2 submission. Rob. ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v2] drm/msm: Move fence put to where failure occurs
+stable
On 2018-11-02 13:13, Robert Foss wrote:
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
---
Changes since v1:
- Chris Wilson: Make sure that dma_fence_put() is always executed
drivers/gpu/drm/msm/msm_gem_submit.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..d5e6665a4c8f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,6 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
+ struct dma_fence *in_fence;
+
in_fence = sync_file_get_fence(args->fence_fd);
if (!in_fence)
@@ -453,11 +454,13 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
* Wait if the fence is from a foreign context, or if the fence
* array contains any fence from a foreign context.
*/
- if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
+ ret = 0;
+ if (!dma_fence_match_context(in_fence, ring->fctx->context))
ret = dma_fence_wait(in_fence, true);
- if (ret)
- return ret;
- }
+
+ dma_fence_put(in_fence);
+ if (ret)
+ return ret;
}
ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -583,8 +586,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
out:
- if (in_fence)
- dma_fence_put(in_fence);
submit_cleanup(submit);
if (ret)
msm_gem_submit_free(submit);
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[Freedreno] [PATCH v2] drm/msm: Move fence put to where failure occurs
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
---
Changes since v1:
- Chris Wilson: Make sure that dma_fence_put() is always executed
drivers/gpu/drm/msm/msm_gem_submit.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..d5e6665a4c8f 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,6 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
+ struct dma_fence *in_fence;
+
in_fence = sync_file_get_fence(args->fence_fd);
if (!in_fence)
@@ -453,11 +454,13 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
* Wait if the fence is from a foreign context, or if the fence
* array contains any fence from a foreign context.
*/
- if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
+ ret = 0;
+ if (!dma_fence_match_context(in_fence, ring->fctx->context))
ret = dma_fence_wait(in_fence, true);
- if (ret)
- return ret;
- }
+
+ dma_fence_put(in_fence);
+ if (ret)
+ return ret;
}
ret = mutex_lock_interruptible(&dev->struct_mutex);
@@ -583,8 +586,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
out:
- if (in_fence)
- dma_fence_put(in_fence);
submit_cleanup(submit);
if (ret)
msm_gem_submit_free(submit);
--
2.17.1
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Re: [Freedreno] [PATCH v1] drm/msm: Move fence put to where failure occurs
Hey Chris,
On 2018-11-01 17:26, Chris Wilson wrote:
Quoting Robert Foss (2018-11-01 16:12:28)
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..3e7704af5b24 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,7 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
- in_fence = sync_file_get_fence(args->fence_fd);
+ struct dma_fence *in_fence = sync_file_get_fence(
+ args->fence_fd);
if (!in_fence)
return -EINVAL;
@@ -455,8 +455,10 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
*/
if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
ret = dma_fence_wait(in_fence, true);
- if (ret)
+ if (ret) {
+ dma_fence_put(in_fence);
return ret;
+ }
}
Careful, we need to keep the put for the normal path. Maybe,
Good catch, I'll send out a fixed version tomorrow.
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
struct dma_fence *in_fence;
in_fence = sync_file_get_fence(args->fence_fd); // keep line breaks
natural
if (!in_fence)
return -EINVAL;
ret = 0;
if (!dma_fence_match_match_context(in_fence, ring->fctx->context)
ret = dma_fence_wait(in_fence, true);
dma_fence_put(in_fence);
if (ret)
return ret;
}
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[Freedreno] [PATCH v1] drm/msm: Move fence put to where failure occurs
If dma_fence_wait fails to wait for a supplied in-fence in
msm_ioctl_gem_submit, make sure we release that in-fence.
Also remove this dma_fence_put() from the 'out' label.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
b/drivers/gpu/drm/msm/msm_gem_submit.c
index a90aedd6883a..3e7704af5b24 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -411,7 +411,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu = priv->gpu;
- struct dma_fence *in_fence = NULL;
struct sync_file *sync_file = NULL;
struct msm_gpu_submitqueue *queue;
struct msm_ringbuffer *ring;
@@ -444,7 +443,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
ring = gpu->rb[queue->prio];
if (args->flags & MSM_SUBMIT_FENCE_FD_IN) {
- in_fence = sync_file_get_fence(args->fence_fd);
+ struct dma_fence *in_fence = sync_file_get_fence(
+ args->fence_fd);
if (!in_fence)
return -EINVAL;
@@ -455,8 +455,10 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void
*data,
*/
if (!dma_fence_match_context(in_fence, ring->fctx->context)) {
ret = dma_fence_wait(in_fence, true);
- if (ret)
+ if (ret) {
+ dma_fence_put(in_fence);
return ret;
+ }
}
}
@@ -583,8 +585,6 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
out:
- if (in_fence)
- dma_fence_put(in_fence);
submit_cleanup(submit);
if (ret)
msm_gem_submit_free(submit);
--
2.17.1
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[Freedreno] [PATCH v4 1/2] drm/blend: Fix comment typ-o
Fix DRM_REFELCT_Y -> DRM_REFLECT_Y. Signed-off-by: Robert Foss --- drivers/gpu/drm/drm_blend.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c index a0d0d6843288..dee67ef6c670 100644 --- a/drivers/gpu/drm/drm_blend.c +++ b/drivers/gpu/drm/drm_blend.c @@ -129,7 +129,7 @@ * "rotate-270" * DRM_REFLECT_X: * "reflect-x" - * DRM_REFELCT_Y: + * DRM_REFLECT_Y: * "reflect-y" * * Rotation is the specified amount in degrees in counter clockwise direction, -- 2.11.0.453.g787f75f05 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v4 2/2] drm: Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ to UAPI
Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ defines to the UAPI
as a convenience.
Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
through the atomic API, but realizing that userspace is likely to take
shortcuts and assume that the enum values are what is sent over the
wire.
As a result these defines are provided purely as a convenience to
userspace applications.
Signed-off-by: Robert Foss
Reviewed-by: Emil Velikov
Reviewed-by: Sinclair Yeh
Acked-by: Liviu Dudau
---
Changes since v3:
- Switched away from past tense in comments
- Add define name change to previously mis-spelled DRM_REFLECT_X comment
- Improved the comment for the DRM_MODE_REFLECT_ comment
Changes since v2:
- Changed define prefix from DRM_MODE_PROP_ to DRM_MODE_
- Fix compilation errors
- Changed comment formatting
- Deduplicated comment lines
- Clarified DRM_MODE_PROP_REFLECT_ comment
Changes since v1:
- Moved defines from drm.h to drm_mode.h
- Changed define prefix from DRM_ to DRM_MODE_PROP_
- Updated uses of the defines to the new prefix
- Removed include from drm_rect.c
- Stopped using the BIT() macro
drivers/gpu/drm/arm/malidp_drv.h| 2 +-
drivers/gpu/drm/arm/malidp_planes.c | 18 -
drivers/gpu/drm/armada/armada_overlay.c | 2 +-
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 20 +-
drivers/gpu/drm/drm_atomic.c| 2 +-
drivers/gpu/drm/drm_atomic_helper.c | 2 +-
drivers/gpu/drm/drm_blend.c | 45 +++---
drivers/gpu/drm/drm_fb_helper.c | 4 +-
drivers/gpu/drm/drm_plane_helper.c | 2 +-
drivers/gpu/drm/drm_rect.c | 36 +-
drivers/gpu/drm/i915/i915_debugfs.c | 14 +++
drivers/gpu/drm/i915/intel_atomic_plane.c | 6 +--
drivers/gpu/drm/i915/intel_display.c| 50 -
drivers/gpu/drm/i915/intel_fbc.c| 2 +-
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 20 +-
drivers/gpu/drm/imx/ipuv3-plane.c | 2 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 30 +++
drivers/gpu/drm/nouveau/nv50_display.c | 2 +-
drivers/gpu/drm/omapdrm/omap_drv.c | 4 +-
drivers/gpu/drm/omapdrm/omap_fb.c | 18 -
drivers/gpu/drm/omapdrm/omap_plane.c| 16
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 4 +-
include/drm/drm_blend.h | 21 +--
include/uapi/drm/drm_mode.h | 49 +++-
25 files changed, 202 insertions(+), 171 deletions(-)
diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h
index 040311ffcaec..2e2033140efc 100644
--- a/drivers/gpu/drm/arm/malidp_drv.h
+++ b/drivers/gpu/drm/arm/malidp_drv.h
@@ -65,6 +65,6 @@ void malidp_de_planes_destroy(struct drm_device *drm);
int malidp_crtc_init(struct drm_device *drm);
/* often used combination of rotational bits */
-#define MALIDP_ROTATED_MASK(DRM_ROTATE_90 | DRM_ROTATE_270)
+#define MALIDP_ROTATED_MASK(DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)
#endif /* __MALIDP_DRV_H__ */
diff --git a/drivers/gpu/drm/arm/malidp_planes.c
b/drivers/gpu/drm/arm/malidp_planes.c
index 814fda23cead..063a8d2b0be3 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -80,7 +80,7 @@ static void malidp_plane_reset(struct drm_plane *plane)
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (state) {
state->base.plane = plane;
- state->base.rotation = DRM_ROTATE_0;
+ state->base.rotation = DRM_MODE_ROTATE_0;
plane->state = &state->base;
}
}
@@ -221,7 +221,7 @@ static int malidp_de_plane_check(struct drm_plane *plane,
return ret;
/* packed RGB888 / BGR888 can't be rotated or flipped */
- if (state->rotation != DRM_ROTATE_0 &&
+ if (state->rotation != DRM_MODE_ROTATE_0 &&
(fb->format->format == DRM_FORMAT_RGB888 ||
fb->format->format == DRM_FORMAT_BGR888))
return -EINVAL;
@@ -315,12 +315,12 @@ static void malidp_de_plane_update(struct drm_plane
*plane,
val &= ~LAYER_ROT_MASK;
/* setup the rotation and axis flip bits */
- if (plane->state->rotation & DRM_ROTATE_MASK)
- val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) <<
+ if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
+ val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
LAYER_ROT_OFFSET;
- if (plane->state->rotation & DRM_REFLECT_X)
+ if (plane->state->rotation & DRM_MODE_
Re: [Freedreno] [PATCH v3] drm: Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ to UAPI
On 2017-05-18 05:49 AM, Ville Syrjälä wrote:
On Wed, May 17, 2017 at 09:39:11PM -0400, Robert Foss wrote:
+/*
+ * DRM_MODE_REFLECT_
+ *
+ * Signals that the contents of a drm plane has been reflected in
+ * the axis.
Still vague.
Ack, I'll add some verbiage.
Also you didn't respond to my comment about the use of past tense.
Fixed in v4.
Rob.
+ *
+ * This define is provided as a convenience, looking up the property id
+ * using the name->prop id lookup is the preferred method.
+ */
+#define DRM_MODE_REFLECT_X (1<<4)
+#define DRM_MODE_REFLECT_Y (1<<5)
+
+/*
+ * DRM_MODE_REFLECT_MASK
+ *
+ * Bitmask used to look for drm plane reflections.
+ */
+#define DRM_MODE_REFLECT_MASK (\
+ DRM_MODE_REFLECT_X | \
+ DRM_MODE_REFLECT_Y)
+
+
struct drm_mode_modeinfo {
__u32 clock;
__u16 hdisplay;
--
2.11.0.453.g787f75f05
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[Freedreno] [PATCH v3] drm: Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ to UAPI
Add DRM_MODE_ROTATE_ and DRM_MODE_REFLECT_ defines to the UAPI
as a convenience.
Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
through the atomic API, but realizing that userspace is likely to take
shortcuts and assume that the enum values are what is sent over the
wire.
As a result these defines are provided purely as a convenience to
userspace applications.
Signed-off-by: Robert Foss
---
Changes since v2:
- Changed define prefix from DRM_MODE_PROP_ to DRM_MODE_
- Fix compilation errors
- Changed comment formatting
- Deduplicated comment lines
- Clarified DRM_MODE_PROP_REFLECT_ comment
Changes since v1:
- Moved defines from drm.h to drm_mode.h
- Changed define prefix from DRM_ to DRM_MODE_PROP_
- Updated uses of the defines to the new prefix
- Removed include from drm_rect.c
- Stopped using the BIT() macro
drivers/gpu/drm/arm/malidp_drv.h| 2 +-
drivers/gpu/drm/arm/malidp_planes.c | 18 -
drivers/gpu/drm/armada/armada_overlay.c | 2 +-
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 20 +-
drivers/gpu/drm/drm_atomic.c| 2 +-
drivers/gpu/drm/drm_atomic_helper.c | 2 +-
drivers/gpu/drm/drm_blend.c | 43 ++---
drivers/gpu/drm/drm_fb_helper.c | 4 +-
drivers/gpu/drm/drm_plane_helper.c | 2 +-
drivers/gpu/drm/drm_rect.c | 36 +-
drivers/gpu/drm/i915/i915_debugfs.c | 14 +++
drivers/gpu/drm/i915/intel_atomic_plane.c | 6 +--
drivers/gpu/drm/i915/intel_display.c| 50 -
drivers/gpu/drm/i915/intel_fbc.c| 2 +-
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 20 +-
drivers/gpu/drm/imx/ipuv3-plane.c | 2 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 30 +++
drivers/gpu/drm/nouveau/nv50_display.c | 2 +-
drivers/gpu/drm/omapdrm/omap_drv.c | 4 +-
drivers/gpu/drm/omapdrm/omap_fb.c | 18 -
drivers/gpu/drm/omapdrm/omap_plane.c| 16
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 4 +-
include/drm/drm_blend.h | 21 +--
include/uapi/drm/drm_mode.h | 49 +++-
25 files changed, 201 insertions(+), 170 deletions(-)
diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h
index 040311ffcaec..2e2033140efc 100644
--- a/drivers/gpu/drm/arm/malidp_drv.h
+++ b/drivers/gpu/drm/arm/malidp_drv.h
@@ -65,6 +65,6 @@ void malidp_de_planes_destroy(struct drm_device *drm);
int malidp_crtc_init(struct drm_device *drm);
/* often used combination of rotational bits */
-#define MALIDP_ROTATED_MASK(DRM_ROTATE_90 | DRM_ROTATE_270)
+#define MALIDP_ROTATED_MASK(DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)
#endif /* __MALIDP_DRV_H__ */
diff --git a/drivers/gpu/drm/arm/malidp_planes.c
b/drivers/gpu/drm/arm/malidp_planes.c
index 814fda23cead..063a8d2b0be3 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -80,7 +80,7 @@ static void malidp_plane_reset(struct drm_plane *plane)
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (state) {
state->base.plane = plane;
- state->base.rotation = DRM_ROTATE_0;
+ state->base.rotation = DRM_MODE_ROTATE_0;
plane->state = &state->base;
}
}
@@ -221,7 +221,7 @@ static int malidp_de_plane_check(struct drm_plane *plane,
return ret;
/* packed RGB888 / BGR888 can't be rotated or flipped */
- if (state->rotation != DRM_ROTATE_0 &&
+ if (state->rotation != DRM_MODE_ROTATE_0 &&
(fb->format->format == DRM_FORMAT_RGB888 ||
fb->format->format == DRM_FORMAT_BGR888))
return -EINVAL;
@@ -315,12 +315,12 @@ static void malidp_de_plane_update(struct drm_plane
*plane,
val &= ~LAYER_ROT_MASK;
/* setup the rotation and axis flip bits */
- if (plane->state->rotation & DRM_ROTATE_MASK)
- val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) <<
+ if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
+ val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
LAYER_ROT_OFFSET;
- if (plane->state->rotation & DRM_REFLECT_X)
+ if (plane->state->rotation & DRM_MODE_REFLECT_X)
val |= LAYER_H_FLIP;
- if (plane->state->rotation & DRM_REFLECT_Y)
+ if (plane->state->rotation & DRM_MODE_REFLECT_Y)
val |= LAYER_V_FLIP;
/*
@@ -370,8 +370,8 @@ int malidp_de_pla
