Re: [Freedreno] [PATCH][drm-next] drm/msm/disp/dpu: fix two spelling mistakes
On Mon, Jul 30, 2018 at 02:44:46PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in error messages
> "diable" -> "disable"
> "cliend" -> "client"
>
> Signed-off-by: Colin Ian King
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 0bd3eda93e22..0922d3536412 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -421,7 +421,7 @@ int dpu_encoder_helper_unregister_irq(struct
> dpu_encoder_phys *phys_enc,
>
> ret = dpu_core_irq_disable(phys_enc->dpu_kms, >irq_idx, 1);
> if (ret) {
> - DRM_ERROR("diable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
> + DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
> DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> irq->irq_idx, ret);
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
> index a68f1249388c..a75eebca2f37 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
> @@ -121,7 +121,7 @@ void dpu_power_resource_deinit(struct platform_device
> *pdev,
> mutex_lock(>phandle_lock);
> list_for_each_entry_safe(curr_client, next_client,
> >power_client_clist, list) {
> - pr_err("cliend:%s-%d still registered with refcount:%d\n",
> + pr_err("client:%s-%d still registered with refcount:%d\n",
> curr_client->name, curr_client->id,
> curr_client->refcount);
> curr_client->active = false;
> --
> 2.17.1
>
> --
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--
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[Freedreno] [PATCH v4 03/19] drm: add msm compressed format modifiers
From: Jeykumar Sankaran
Qualcomm Snapdragon chipsets uses compressed format
to optimize BW across multiple IP's. This change adds
needed modifier support in drm for a simple 4x4 tile
based compressed variants of base formats.
Changes in v3:
- Removed duplicate entry for DRM_FORMAT_MOD_QCOM_COMPRESSED (Rob Clark)
Changes in v4:
- Remove all modifiers aside from COMPRESSED, this includes tiled and
10-bit
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sean Paul
Signed-off-by: Rob Clark
---
include/uapi/drm/drm_fourcc.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index d43949b5bb3e..721ab7e54d96 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -299,6 +299,19 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
+/*
+ * Qualcomm Compressed Format
+ *
+ * Refers to a compressed variant of the base format that is compressed.
+ * Implementation may be platform and base-format specific.
+ *
+ * Each macrotile consists of m x n (mostly 4 x 4) tiles.
+ * Pixel data pitch/stride is aligned with macrotile width.
+ * Pixel data height is aligned with macrotile height.
+ * Entire pixel data buffer is aligned with 4k(bytes).
+ */
+#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
+
/* Vivante framebuffer modifiers */
/*
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH 1/3] drm/msm: dpu: Use 'vsync' instead of 'vsync_clk' in cmdmode encoder
Should work with the legacy handling in of, but we shouldn't rely on
that.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 035a5fbe1435..e6d02c6947b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -424,7 +424,7 @@ static void dpu_encoder_phys_cmd_tearcheck_config(
* vsync_count is ratio of MDP VSYNC clock frequency to LCD panel
* frequency divided by the no. of rows (lines) in the LCDpanel.
*/
- vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync_clk");
+ vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync");
if (vsync_hz <= 0) {
DPU_DEBUG_CMDENC(cmd_enc, "invalid - vsync_hz %u\n",
vsync_hz);
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH v3 16/19] drm/msm: Add .commit() callback to msm_kms functions
From: Jeykumar Sankaran
Called right before wait_for_commit_done() to perform kickoff for
active crtcs.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran
[seanpaul split this out of the megapatch]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_atomic.c | 5 +
drivers/gpu/drm/msm/msm_kms.h| 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index e6f1e25c60af..c1f1779c980f 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -71,6 +71,11 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state)
drm_atomic_helper_commit_modeset_enables(dev, state);
+ if (kms->funcs->commit) {
+ DRM_DEBUG_ATOMIC("triggering commit\n");
+ kms->funcs->commit(kms, state);
+ }
+
msm_atomic_wait_for_commit_done(dev, state);
kms->funcs->complete_commit(kms, state);
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 76c14221ffdf..761bb07cd7bf 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -42,6 +42,7 @@ struct msm_kms_funcs {
void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
/* modeset, bracketing atomic_commit(): */
void (*prepare_commit)(struct msm_kms *kms, struct drm_atomic_state
*state);
+ void (*commit)(struct msm_kms *kms, struct drm_atomic_state *state);
void (*complete_commit)(struct msm_kms *kms, struct drm_atomic_state
*state);
/* functions to wait for atomic commit completed on each CRTC */
void (*wait_for_crtc_commit_done)(struct msm_kms *kms,
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH v3 19/19] drm/msm: Add SDM845 DPU support
From: Jeykumar Sankaran SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +-+ | +-+ | | | DPU | | | | ++ ++ | | | | | SSPP | | SSPP | | | | | ++---+ ++---+ | | | | | | | | | | +v---v---+ | | | | | Layer Mixer (LM) | | | | | ++ | | | | ++ | | | | |PingPong (PP) | | | | | ++ | | | | ++ | | | | | INTERFACE (VIDEO) | | | | | +---++ | | | +--|--+ | ||| | +--|-+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-+ | | | | | DSI | | DP | | | | | +-+ +-+ | | | ++ | +-+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: -- PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar Signed-off-by: Archit Taneja Signed-off-by: Chandan Uddaraju Signed-off-by: Jeykumar Sankaran Signed-off-by: Jordan Crouse Signed-off-by: Rajesh Yadav Signed-off-by: Sravanthi Kollukuduru Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/Makefile | 32 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 479 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 153 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 637 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 133 + drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2504 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 484 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 2393 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 103 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2575 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 191 ++ .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 453 +++ .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 905 ++ .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 922 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 1276 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 136 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c| 155 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h| 53 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 511 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 804 + .../drm/msm/disp/dpu1/dpu_hw_catalog_format.h | 182 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c| 323 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h| 139 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 540 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
[Freedreno] [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU
From: Jeykumar Sankaran
Adds bindings for Snapdragon 845 display processing unit
Changes in v2:
- Use SoC specific compatibles for mdss and dpu (Rob Herring)
- Use assigned-clocks to set initial clock frequency (Rob Herring)
Changes in v3 (all suggested by Rob Herring):
- Rename mdss_phys to mdss
- Correct description for clocks/assigned-clocks
- Rename mdp_phys to mdp
- Rename vbif_phys to vbif
- Remove redundant interrupt-parent from mdss_mdp
- Fully specify 'ranges' and use relative reg address in mdss_mdp
Cc: Rob Herring
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Rajesh Yadav
Signed-off-by: Sean Paul
---
.../devicetree/bindings/display/msm/dpu.txt | 131 ++
1 file changed, 131 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
new file mode 100644
index ..ad2e8830324e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -0,0 +1,131 @@
+Qualcomm Technologies, Inc. DPU KMS
+
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,sdm845-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+ * "mdss"
+- power-domains: a power domain consumer specifier according to
+ Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required:
+ * "iface"
+ * "bus"
+ * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,sdm845-dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+ * "mdp"
+ * "vbif"
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required.
+ * "bus"
+ * "iface"
+ * "core"
+ * "vsync"
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+ to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+ Each output port contains an endpoint that describes how it is connected to
an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ Port 0 -> DPU_INTF1 (DSI1)
+ Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+Example:
+
+ mdss: mdss@ae0 {
+ compatible = "qcom,sdm845-mdss";
+ reg = <0xae0 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <_dispcc 0>;
+
+ clocks = < GCC_DISP_AHB_CLK>, < GCC_DISP_AXI_CLK>,
+<_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ assigned-clocks = <_dispcc DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <3>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_iommu 0>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xae0 0xb2008>;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0
[Freedreno] [PATCH v3 17/19] drm/msm: Add pm_suspend/resume callbacks to msm_kms
From: Jeykumar Sankaran
Used by the dpu driver for custom suspend/resume.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran
[seanpaul split this out of the megapatch]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 10 ++
drivers/gpu/drm/msm/msm_kms.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 8bd9fe831968..e79ad74ca98c 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -903,6 +903,11 @@ static int msm_pm_suspend(struct device *dev)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ /* TODO: Use atomic helper suspend/resume */
+ if (kms && kms->funcs && kms->funcs->pm_suspend)
+ return kms->funcs->pm_suspend(dev);
drm_kms_helper_poll_disable(ddev);
@@ -919,6 +924,11 @@ static int msm_pm_resume(struct device *dev)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ /* TODO: Use atomic helper suspend/resume */
+ if (kms && kms->funcs && kms->funcs->pm_resume)
+ return kms->funcs->pm_resume(dev);
drm_atomic_helper_resume(ddev, priv->pm_state);
drm_kms_helper_poll_enable(ddev);
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 761bb07cd7bf..c15de28ae2dd 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -61,6 +61,9 @@ struct msm_kms_funcs {
void (*set_encoder_mode)(struct msm_kms *kms,
struct drm_encoder *encoder,
bool cmd_mode);
+ /* pm suspend/resume hooks */
+ int (*pm_suspend)(struct device *dev);
+ int (*pm_resume)(struct device *dev);
/* cleanup: */
void (*destroy)(struct msm_kms *kms);
#ifdef CONFIG_DEBUG_FS
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH v3 15/19] drm/msm: #define MAX_ in msm_drv.h
From: Jeykumar Sankaran
dpu uses these elsewhere in the driver (in addition to increasing
MAX_PLANES, that'll come later), so pull them out into #define.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran
[seanpaul pulled this out of the dpu megapatch]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.h | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index fa0376b0f42b..3b206ae6423f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -54,6 +54,12 @@ struct msm_fence_context;
struct msm_gem_address_space;
struct msm_gem_vma;
+#define MAX_CRTCS 8
+#define MAX_PLANES 16
+#define MAX_ENCODERS 8
+#define MAX_BRIDGES8
+#define MAX_CONNECTORS 8
+
struct msm_file_private {
rwlock_t queuelock;
struct list_head submitqueues;
@@ -117,19 +123,19 @@ struct msm_drm_private {
struct workqueue_struct *wq;
unsigned int num_planes;
- struct drm_plane *planes[16];
+ struct drm_plane *planes[MAX_PLANES];
unsigned int num_crtcs;
- struct drm_crtc *crtcs[8];
+ struct drm_crtc *crtcs[MAX_CRTCS];
unsigned int num_encoders;
- struct drm_encoder *encoders[8];
+ struct drm_encoder *encoders[MAX_ENCODERS];
unsigned int num_bridges;
- struct drm_bridge *bridges[8];
+ struct drm_bridge *bridges[MAX_BRIDGES];
unsigned int num_connectors;
- struct drm_connector *connectors[8];
+ struct drm_connector *connectors[MAX_CONNECTORS];
/* Properties */
struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH v3 12/19] drm/msm: Clean up dangling atomic_wq
I missed this during the atomic conversion
Changes in v3:
- None
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 4
drivers/gpu/drm/msm/msm_drv.h | 1 -
2 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 9c760cee5156..b73acdd52931 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -244,9 +244,6 @@ static int msm_drm_uninit(struct device *dev)
flush_workqueue(priv->wq);
destroy_workqueue(priv->wq);
- flush_workqueue(priv->atomic_wq);
- destroy_workqueue(priv->atomic_wq);
-
if (kms && kms->funcs)
kms->funcs->destroy(kms);
@@ -389,7 +386,6 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
mdss = priv->mdss;
priv->wq = alloc_ordered_workqueue("msm", 0);
- priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0);
INIT_LIST_HEAD(>inactive_list);
INIT_LIST_HEAD(>vblank_ctrl.event_list);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 17cefca1d566..fa0376b0f42b 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -115,7 +115,6 @@ struct msm_drm_private {
struct list_head inactive_list;
struct workqueue_struct *wq;
- struct workqueue_struct *atomic_wq;
unsigned int num_planes;
struct drm_plane *planes[16];
--
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[Freedreno] [PATCH v3 13/19] drm/msm: #define MDP version numbers
From: Jeykumar Sankaran
Useful for incoming DPU support
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran
[seanpaul split this from the dpu megapatch]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index b73acdd52931..67816543a0d7 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -267,6 +267,9 @@ static int msm_drm_uninit(struct device *dev)
return 0;
}
+#define KMS_MDP4 4
+#define KMS_MDP5 5
+
static int get_mdp_ver(struct platform_device *pdev)
{
struct device *dev = >dev;
@@ -411,11 +414,11 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
msm_gem_shrinker_init(ddev);
switch (get_mdp_ver(pdev)) {
- case 4:
+ case KMS_MDP4:
kms = mdp4_kms_init(ddev);
priv->kms = kms;
break;
- case 5:
+ case KMS_MDP5:
kms = mdp5_kms_init(ddev);
break;
default:
@@ -1162,8 +1165,8 @@ static int msm_pdev_remove(struct platform_device *pdev)
}
static const struct of_device_id dt_match[] = {
- { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */
- { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */
+ { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
+ { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
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[Freedreno] [PATCH v3 14/19] drm/msm: Use labels for unwinding in the error path
From: Jeykumar Sankaran
This simplifies cleanup, to make sure nothing drops out in case of
error.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran
[seanpaul split out of dpu megapatch and renamed labels]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 44 +--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 67816543a0d7..8bd9fe831968 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -372,19 +372,16 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv) {
- drm_dev_unref(ddev);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto err_unref_drm_dev;
}
ddev->dev_private = priv;
priv->dev = ddev;
ret = mdp5_mdss_init(ddev);
- if (ret) {
- kfree(priv);
- drm_dev_unref(ddev);
- return ret;
- }
+ if (ret)
+ goto err_free_priv;
mdss = priv->mdss;
@@ -399,17 +396,12 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
/* Bind all our sub-components: */
ret = component_bind_all(dev, ddev);
- if (ret) {
- if (mdss && mdss->funcs)
- mdss->funcs->destroy(ddev);
- kfree(priv);
- drm_dev_unref(ddev);
- return ret;
- }
+ if (ret)
+ goto err_destroy_mdss;
ret = msm_init_vram(ddev);
if (ret)
- goto fail;
+ goto err_msm_uninit;
msm_gem_shrinker_init(ddev);
@@ -435,7 +427,7 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
*/
dev_err(dev, "failed to load kms\n");
ret = PTR_ERR(kms);
- goto fail;
+ goto err_msm_uninit;
}
/* Enable normalization of plane zpos */
@@ -445,7 +437,7 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
ret = kms->funcs->hw_init(kms);
if (ret) {
dev_err(dev, "kms hw init failed: %d\n", ret);
- goto fail;
+ goto err_msm_uninit;
}
}
@@ -455,7 +447,7 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
ret = drm_vblank_init(ddev, priv->num_crtcs);
if (ret < 0) {
dev_err(dev, "failed to initialize vblank\n");
- goto fail;
+ goto err_msm_uninit;
}
if (kms) {
@@ -464,13 +456,13 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
pm_runtime_put_sync(dev);
if (ret < 0) {
dev_err(dev, "failed to install IRQ handler\n");
- goto fail;
+ goto err_msm_uninit;
}
}
ret = drm_dev_register(ddev, 0);
if (ret)
- goto fail;
+ goto err_msm_uninit;
drm_mode_config_reset(ddev);
@@ -481,15 +473,23 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
ret = msm_debugfs_late_init(ddev);
if (ret)
- goto fail;
+ goto err_msm_uninit;
drm_kms_helper_poll_init(ddev);
return 0;
-fail:
+err_msm_uninit:
msm_drm_uninit(dev);
return ret;
+err_destroy_mdss:
+ if (mdss && mdss->funcs)
+ mdss->funcs->destroy(ddev);
+err_free_priv:
+ kfree(priv);
+err_unref_drm_dev:
+ drm_dev_unref(ddev);
+ return ret;
}
/*
--
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[Freedreno] [PATCH v3 11/19] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor
From: Abhinav Kumar
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Changes in v3:
- Converted pclk_rate to u32 (Archit)
- Rebase on dsi cleanup set in msm-next
Cc: Sibi Sankar
Cc: Archit Taneja
Signed-off-by: Abhinav Kumar
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index f6c6eddbcec7..dff8e88efb66 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -702,6 +702,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host,
bool is_dual_dsi)
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
u32 pclk_rate;
+ u64 pclk_bpp;
unsigned int esc_mhz, esc_div;
unsigned long byte_mhz;
@@ -716,13 +717,15 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host,
bool is_dual_dsi)
if (is_dual_dsi)
pclk_rate /= 2;
+ pclk_bpp = pclk_rate * bpp;
if (lanes > 0) {
- msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+ do_div(pclk_bpp, (8 * lanes));
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
- msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+ do_div(pclk_bpp, 8);
}
msm_host->pixel_clk_rate = pclk_rate;
+ msm_host->byte_clk_rate = pclk_bpp;
DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
msm_host->byte_clk_rate);
--
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[Freedreno] [PATCH v3 08/19] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks
DPU doesn't use this, so push it into the mdp drivers. Changes in v3: - None Signed-off-by: Sean Paul Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 ++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 ++ drivers/gpu/drm/msm/msm_atomic.c | 2 -- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index 4b646bf9c214..44d1cda56974 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -125,6 +125,8 @@ static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; + drm_atomic_helper_wait_for_vblanks(mdp4_kms->dev, state); + /* see 119ecb7fd */ for_each_new_crtc_in_state(state, crtc, crtc_state, i) drm_crtc_vblank_put(crtc); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 6e12e275deba..bddd625ab91b 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -170,6 +170,8 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s struct device *dev = _kms->pdev->dev; struct mdp5_global_state *global_state; + drm_atomic_helper_wait_for_vblanks(mdp5_kms->dev, state); + global_state = mdp5_get_existing_global_state(mdp5_kms); if (mdp5_kms->smp) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index f0635c3da7f4..e6f1e25c60af 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -75,8 +75,6 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state) kms->funcs->complete_commit(kms, state); - drm_atomic_helper_wait_for_vblanks(dev, state); - drm_atomic_helper_commit_hw_done(state); drm_atomic_helper_cleanup_planes(dev, state); -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 07/19] drm/msm/dsi: set encoder mode for DRM bridge explicitly
From: Abhinav Kumar Currently, DRM bridge for DPU relies on the default video mode setting to set the encoder mode. Add an explicit call to set the encoder mode for bridges. Changes in v3: - None Reviewed-by: Archit Taneja Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/dsi/dsi_manager.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 000721fe5ab4..29025d9b7c62 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -777,6 +777,7 @@ void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags) struct msm_drm_private *priv; struct msm_kms *kms; struct drm_encoder *encoder; + bool cmd_mode; /* * drm_device pointer is assigned to msm_dsi only in the modeset_init @@ -791,10 +792,11 @@ void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags) priv = dev->dev_private; kms = priv->kms; encoder = msm_dsi_get_encoder(msm_dsi); + cmd_mode = !(device_flags & +MIPI_DSI_MODE_VIDEO); if (encoder && kms->funcs->set_encoder_mode) - if (!(device_flags & MIPI_DSI_MODE_VIDEO)) - kms->funcs->set_encoder_mode(kms, encoder, true); + kms->funcs->set_encoder_mode(kms, encoder, cmd_mode); } int msm_dsi_manager_register(struct msm_dsi *msm_dsi) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 09/19] drm/msm/mdp5: subclass msm_mdss for mdp5
From: Rajesh Yadav
SoCs having mdp5 or dpu have identical tree like
device hierarchy where MDSS top level wrapper manages
common power resources for all child devices.
Subclass msm_mdss so that msm_mdss includes common defines
and mdp5/dpu mdss derivations to include any extensions.
Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.
This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.
Changes in v3:
- Added Archit's R-b
Reviewed-by: Archit Taneja
Reviewed-by: Sean Paul
Signed-off-by: Rajesh Yadav
[seanpaul rebased on msm-next and resolved conflicts]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 --
drivers/gpu/drm/msm/msm_drv.c | 22 +++-
drivers/gpu/drm/msm/msm_kms.h | 17 ++-
3 files changed, 109 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
index f2a0db7a8a03..1cc4e57f0226 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
@@ -20,12 +20,10 @@
#include "msm_drv.h"
#include "mdp5_kms.h"
-/*
- * If needed, this can become more specific: something like struct mdp5_mdss,
- * which contains a 'struct msm_mdss base' member.
- */
-struct msm_mdss {
- struct drm_device *dev;
+#define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
+
+struct mdp5_mdss {
+ struct msm_mdss base;
void __iomem *mmio, *vbif;
@@ -41,22 +39,22 @@ struct msm_mdss {
} irqcontroller;
};
-static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
+static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
{
- msm_writel(data, mdss->mmio + reg);
+ msm_writel(data, mdp5_mdss->mmio + reg);
}
-static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
+static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
{
- return msm_readl(mdss->mmio + reg);
+ return msm_readl(mdp5_mdss->mmio + reg);
}
static irqreturn_t mdss_irq(int irq, void *arg)
{
- struct msm_mdss *mdss = arg;
+ struct mdp5_mdss *mdp5_mdss = arg;
u32 intr;
- intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
+ intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
VERB("intr=%08x", intr);
@@ -64,7 +62,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)
irq_hw_number_t hwirq = fls(intr) - 1;
generic_handle_irq(irq_find_mapping(
- mdss->irqcontroller.domain, hwirq));
+ mdp5_mdss->irqcontroller.domain, hwirq));
intr &= ~(1 << hwirq);
}
@@ -84,19 +82,19 @@ static irqreturn_t mdss_irq(int irq, void *arg)
static void mdss_hw_mask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- clear_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ clear_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
static void mdss_hw_unmask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- set_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ set_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
@@ -109,13 +107,13 @@ static struct irq_chip mdss_hw_irq_chip = {
static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
- struct msm_mdss *mdss = d->host_data;
+ struct mdp5_mdss *mdp5_mdss = d->host_data;
if (!(VALID_IRQS & (1 << hwirq)))
return -EPERM;
irq_set_chip_and_handler(irq, _hw_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, mdss);
+ irq_set_chip_data(irq, mdp5_mdss);
return 0;
}
@@ -126,90 +124,99 @@ static const struct irq_domain_ops mdss_hw_irqdomain_ops
= {
};
-static int mdss_irq_domain_init(struct msm_mdss *mdss)
+static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
{
- struct device *dev = mdss->dev->dev;
+ struct device *dev = mdp5_mdss->base.dev->dev;
struct irq_domain *d;
d = irq_domain_add_linear(dev->of_node, 32, _hw_irqdomain_ops,
- mdss);
+ mdp5_mdss);
if (!d) {
dev_err(dev, "mdss irq domain add failed\n");
return -ENXIO;
}
- mdss->irqcontroller.
[Freedreno] [PATCH v3 10/19] drm/msm: enable zpos normalization
From: Jeykumar Sankaran
Enable drm core zpos normalization for planes.
Changes in v3:
- None
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 2608d3f77956..9c760cee5156 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -439,6 +439,9 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
goto fail;
}
+ /* Enable normalization of plane zpos */
+ ddev->mode_config.normalize_zpos = true;
+
if (kms) {
ret = kms->funcs->hw_init(kms);
if (ret) {
--
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[Freedreno] [PATCH v3 04/19] drm/msm/dsi: adjust dsi timing for dual dsi mode
From: Chandan Uddaraju
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Changes in v3:
- Added Archit's R-b
- Rebase on dsi cleanup set in msm-next
Cc: Sibi Sankar
Reviewed-by: Archit Taneja
Signed-off-by: Chandan Uddaraju
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi.h | 10 +++--
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_host.c| 65 ++-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 7 +--
4 files changed, 64 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index dfa049d876bd..d3f613c76ffa 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -163,7 +163,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host
*host,
int msm_dsi_host_enable(struct mipi_dsi_host *host);
int msm_dsi_host_disable(struct mipi_dsi_host *host);
int msm_dsi_host_power_on(struct mipi_dsi_host *host,
- struct msm_dsi_phy_shared_timings *phy_shared_timings);
+ struct msm_dsi_phy_shared_timings *phy_shared_timings,
+ bool is_dual_dsi);
int msm_dsi_host_power_off(struct mipi_dsi_host *host);
int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
struct drm_display_mode *mode);
@@ -176,7 +177,8 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll);
void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
- struct msm_dsi_phy_clk_request *clk_req);
+ struct msm_dsi_phy_clk_request *clk_req,
+ bool is_dual_dsi);
void msm_dsi_host_destroy(struct mipi_dsi_host *host);
int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
@@ -196,8 +198,8 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host,
uint64_t *iova);
int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova);
int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
+int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi);
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi);
/* dsi phy */
struct msm_dsi_phy;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index a795a062b779..16c50790 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -48,7 +48,7 @@ struct msm_dsi_host_cfg_ops {
void* (*tx_buf_get)(struct msm_dsi_host *msm_host);
void (*tx_buf_put)(struct msm_dsi_host *msm_host);
int (*dma_base_get)(struct msm_dsi_host *msm_host, uint64_t *iova);
- int (*calc_clk_rate)(struct msm_dsi_host *msm_host);
+ int (*calc_clk_rate)(struct msm_dsi_host *msm_host, bool is_dual_dsi);
};
struct msm_dsi_cfg_handler {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index bb00e0f150cb..f6c6eddbcec7 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -118,6 +118,7 @@ struct msm_dsi_host {
struct clk *byte_intf_clk;
u32 byte_clk_rate;
+ u32 pixel_clk_rate;
u32 esc_clk_rate;
/* DSI v2 specific clocks */
@@ -523,7 +524,7 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
goto error;
}
- ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+ ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -604,7 +605,7 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
goto error;
}
- ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+ ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -663,7 +664,7 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
clk_disable_unprepare(msm_host->byte_clk);
}
-int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
+int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi)
{
struct drm_display_mode *mode = msm_host->mode;
u8 lanes = msm_host->lanes;
@@ -671,6 +672,16 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
u32 pclk_rate;
pclk_rate
[Freedreno] [PATCH v3 05/19] drm/msm/dsi: Use one connector for dual DSI mode
From: Chandan Uddaraju
Current DSI driver uses two connectors for dual DSI case even
though we only have one panel. Fix this by implementing one
connector/bridge for dual DSI use case. Use master DSI
controllers to register one connector/bridge.
Changes in v3:
- None
Reviewed-by: Archit Taneja
Signed-off-by: Chandan Uddaraju
[seanpaul removed unused local var causing a build warning]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi.c | 3 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_manager.c | 112 ++
3 files changed, 30 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index b744bcc7d8ad..ff8164cc6738 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -208,6 +208,9 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct
drm_device *dev,
goto fail;
}
+ if (!msm_dsi_manager_validate_current_config(msm_dsi->id))
+ goto fail;
+
msm_dsi->encoder = encoder;
msm_dsi->bridge = msm_dsi_manager_bridge_init(msm_dsi->id);
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index d3f613c76ffa..08f3fc6771b7 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -100,6 +100,7 @@ bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base,
u32 len);
void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
+bool msm_dsi_manager_validate_current_config(u8 id);
/* msm dsi */
static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 3bb506b44a4b..000721fe5ab4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -306,102 +306,25 @@ static void dsi_mgr_connector_destroy(struct
drm_connector *connector)
kfree(dsi_connector);
}
-static void dsi_dual_connector_fix_modes(struct drm_connector *connector)
-{
- struct drm_display_mode *mode, *m;
-
- /* Only support left-right mode */
- list_for_each_entry_safe(mode, m, >probed_modes, head) {
- mode->clock >>= 1;
- mode->hdisplay >>= 1;
- mode->hsync_start >>= 1;
- mode->hsync_end >>= 1;
- mode->htotal >>= 1;
- drm_mode_set_name(mode);
- }
-}
-
-static int dsi_dual_connector_tile_init(
- struct drm_connector *connector, int id)
-{
- struct drm_display_mode *mode;
- /* Fake topology id */
- char topo_id[8] = {'M', 'S', 'M', 'D', 'U', 'D', 'S', 'I'};
-
- if (connector->tile_group) {
- DBG("Tile property has been initialized");
- return 0;
- }
-
- /* Use the first mode only for now */
- mode = list_first_entry(>probed_modes,
- struct drm_display_mode,
- head);
- if (!mode)
- return -EINVAL;
-
- connector->tile_group = drm_mode_get_tile_group(
- connector->dev, topo_id);
- if (!connector->tile_group)
- connector->tile_group = drm_mode_create_tile_group(
- connector->dev, topo_id);
- if (!connector->tile_group) {
- pr_err("%s: failed to create tile group\n", __func__);
- return -ENOMEM;
- }
-
- connector->has_tile = true;
- connector->tile_is_single_monitor = true;
-
- /* mode has been fixed */
- connector->tile_h_size = mode->hdisplay;
- connector->tile_v_size = mode->vdisplay;
-
- /* Only support left-right mode */
- connector->num_h_tile = 2;
- connector->num_v_tile = 1;
-
- connector->tile_v_loc = 0;
- connector->tile_h_loc = (id == DSI_RIGHT) ? 1 : 0;
-
- return 0;
-}
-
static int dsi_mgr_connector_get_modes(struct drm_connector *connector)
{
int id = dsi_mgr_connector_get_id(connector);
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct drm_panel *panel = msm_dsi->panel;
- int ret, num;
+ int num;
if (!panel)
return 0;
- /* Since we have 2 connectors, but only 1 drm_panel in dual DSI mode,
-* panel should not attach to any connector.
-* Only temporarily attach panel to the current connector here,
-* to let panel set mode to this connector.
+ /*
+* In dual DSI mode, we have one connector that can be
+* attached to the drm_panel.
*/
drm_panel_attach
[Freedreno] [PATCH v3 06/19] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll
From: Rajesh Yadav postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja Signed-off-by: Rajesh Yadav Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index c4c37a7df637..4c03f0b7343e 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -798,6 +798,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) return ERR_PTR(-ENOMEM); } + spin_lock_init(_10nm->postdiv_lock); + pll = _10nm->base; pll->min_rate = 10UL; pll->max_rate = 350000UL; -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 00/19] drm/msm: Add support for SDM845 Display Processing Unit (DPU)
Hello! Here's v3 (well, kind of v2/v3) I revved the dt-bindings in the meantime. Refer to [1] for all of the gory details on the driver. It's been baking in linux-next for ~week now and the outstanding dt-bindings changes are sorted, so I figured it's time for another try. Note that I've removed both the dispcc and dts patches from v1. I'll wait for dispcc to land elsewhere and then add the dpu/mdss nodes to dts. For now, the dt-bindings will hopefully suffice. Thanks, Sean [1]- https://lists.freedesktop.org/archives/dri-devel/2018-July/182681.html Abhinav Kumar (2): drm/msm/dsi: set encoder mode for DRM bridge explicitly drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Chandan Uddaraju (2): drm/msm/dsi: adjust dsi timing for dual dsi mode drm/msm/dsi: Use one connector for dual DSI mode Jeykumar Sankaran (10): dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding drm: add msm compressed format modifiers drm/msm: enable zpos normalization drm/msm: #define MDP version numbers drm/msm: Use labels for unwinding in the error path drm/msm: #define MAX_ in msm_drv.h drm/msm: Add .commit() callback to msm_kms functions drm/msm: Add pm_suspend/resume callbacks to msm_kms dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU drm/msm: Add SDM845 DPU support Rajesh Yadav (2): drm/msm/dsi: initialize postdiv_lock before use for 10nm pll drm/msm/mdp5: subclass msm_mdss for mdp5 Sean Paul (2): drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks drm/msm: Clean up dangling atomic_wq vkorjani (1): drm: Add support for pps and compression mode command packet .../devicetree/bindings/display/msm/dpu.txt | 131 + .../devicetree/bindings/display/msm/dsi.txt | 16 + drivers/gpu/drm/drm_mipi_dsi.c|2 + drivers/gpu/drm/msm/Makefile | 32 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 479 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 153 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 637 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 133 + drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2504 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 484 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 2393 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 103 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2575 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 191 ++ .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 453 +++ .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 905 ++ .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 922 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 1276 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 136 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c| 155 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h| 53 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 511 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 804 + .../drm/msm/disp/dpu1/dpu_hw_catalog_format.h | 182 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c| 323 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h| 139 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 540 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h| 218 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1183 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 257 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 349 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 128 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 261 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 122 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 465 +++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 250 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 136 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 753 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 424 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 398 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h| 202 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 452 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 358 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 275 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h | 128 + drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 56 + drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 204 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h | 57 + drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 66 + drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h | 59 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1345 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 402 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c | 153 + drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 245 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1963 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 175 ++ .../gpu/drm/msm/disp/dpu1/dpu_power_handle.c
[Freedreno] [PATCH v3 02/19] drm: Add support for pps and compression mode command packet
From: vkorjani
After enabling DSC we need to send compression mode command packet
and pps data packet, for which 2 new data types are added
07h Compression Mode Data Type Write , short write, 2 parameters
0Ah PPS Long Write (word count determines number of bytes)
This patch adds support to send these packets.
Cc: David Airlie
Cc: Jean-Christophe Plagniol-Villard
Cc: Tomi Valkeinen
Cc: dri-de...@lists.freedesktop.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-fb...@vger.kernel.org
Changes in v3:
- None
Signed-off-by: vkorjani
[seanpaul removed pps_write_buffer fn, added types to packet_format helpers]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
include/video/mipi_display.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index bc73b7f5b9fc..80b75501f5c6 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -392,6 +392,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
+ case MIPI_DSI_DCS_COMPRESSION_MODE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -410,6 +411,7 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
bool mipi_dsi_packet_format_is_long(u8 type)
{
switch (type) {
+ case MIPI_DSI_PPS_LONG_WRITE:
case MIPI_DSI_NULL_PACKET:
case MIPI_DSI_BLANKING_PACKET:
case MIPI_DSI_GENERIC_LONG_WRITE:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 19aa65a35546..49a53ef8da96 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -38,6 +38,9 @@ enum {
MIPI_DSI_DCS_READ = 0x06,
+ MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
+ MIPI_DSI_PPS_LONG_WRITE = 0x0A,
+
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
MIPI_DSI_END_OF_TRANSMISSION= 0x08,
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH v3 01/19] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding
From: Jeykumar Sankaran Adds mdp transfer time to msm dsi binding Changes in v3: - Added Rob's R-b Reviewed-by: Rob Herring Signed-off-by: Jeykumar Sankaran Signed-off-by: Rajesh Yadav Signed-off-by: Sean Paul --- .../devicetree/bindings/display/msm/dsi.txt | 16 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 518e9cdf0d4b..d22237a88eae 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -121,6 +121,20 @@ Required properties: Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY regulator is wanted. +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/graph.txt @@ -171,6 +185,8 @@ Example: qcom,master-dsi; qcom,sync-dual-dsi; + qcom,mdss-mdp-transfer-time-us = <12000>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <_active>; pinctrl-1 = <_suspend>; -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 03/19] drm: add msm compressed format modifiers
From: Jeykumar Sankaran
Qualcomm Snapdragon chipsets uses compressed format
to optimize BW across multiple IP's. This change adds
needed modifier support in drm for a simple 4x4 tile
based compressed variants of base formats.
Changes in v3:
- Removed duplicate entry for DRM_FORMAT_MOD_QCOM_COMPRESSED (Rob Clark)
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sean Paul
---
include/uapi/drm/drm_fourcc.h | 37 +++
1 file changed, 37 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index e04613d30a13..1c9a6bf8c81e 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -298,6 +298,43 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
+/*
+ * Qualcomm Compressed Format
+ *
+ * Refers to a compressed variant of the base format that is compressed.
+ * Implementation may be platform and base-format specific.
+ *
+ * Each macrotile consists of m x n (mostly 4 x 4) tiles.
+ * Pixel data pitch/stride is aligned with macrotile width.
+ * Pixel data height is aligned with macrotile height.
+ * Entire pixel data buffer is aligned with 4k(bytes).
+ */
+#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
+
+/*
+ * QTI DX Format
+ *
+ * Refers to a DX variant of the base format.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_DX fourcc_mod_code(QCOM, 0x2)
+
+/*
+ * QTI Tight Format
+ *
+ * Refers to a tightly packed variant of the base format.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_TIGHT fourcc_mod_code(QCOM, 0x4)
+
+/*
+ * QTI Tile Format
+ *
+ * Refers to a tile variant of the base format.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_TILE fourcc_mod_code(QCOM, 0x8)
+
/* Vivante framebuffer modifiers */
/*
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [PATCH] drm/msm: rework vblank event handling in dpu_crtc
On Fri, Jul 13, 2018 at 06:27:23PM +0530, Rajesh Yadav wrote:
> The vblank on/off calls were missing in dpu_crtc
> leading to "driver forgot to call drm_crtc_vblank_off()"
> warning while entering suspend state.
> Also handle the state update completion event for
> a crtc being disabled in current atomic commit.
>
> This patch depends on https://www.spinics.net/lists/dri-devel/msg182402.html
>
> Signed-off-by: Rajesh Yadav
Applied to dpu-staging/for-next.
Thanks!
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index d171282..24715e4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -1617,6 +1617,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
> struct drm_encoder *encoder;
> struct msm_drm_private *priv;
> int ret;
> + unsigned long flags;
>
> if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
> DPU_ERROR("invalid crtc\n");
> @@ -1632,6 +1633,9 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
> if (dpu_kms_is_suspend_state(crtc->dev))
> _dpu_crtc_set_suspend(crtc, true);
>
> + /* Disable/save vblank irq handling */
> + drm_crtc_vblank_off(crtc);
> +
> mutex_lock(_crtc->crtc_lock);
>
> /* wait for frame_event_done completion */
> @@ -1669,7 +1673,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
> dpu_power_handle_unregister_event(dpu_crtc->phandle,
> dpu_crtc->power_event);
>
> -
> memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
> dpu_crtc->num_mixers = 0;
> dpu_crtc->mixers_swapped = false;
> @@ -1679,6 +1682,13 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
> cstate->bw_split_vote = false;
>
> mutex_unlock(_crtc->crtc_lock);
> +
> + if (crtc->state->event && !crtc->state->active) {
> + spin_lock_irqsave(>dev->event_lock, flags);
> + drm_crtc_send_vblank_event(crtc, crtc->state->event);
> + crtc->state->event = NULL;
> + spin_unlock_irqrestore(>dev->event_lock, flags);
> + }
> }
>
> static void dpu_crtc_enable(struct drm_crtc *crtc,
> @@ -1718,6 +1728,9 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
>
> mutex_unlock(_crtc->crtc_lock);
>
> + /* Enable/restore vblank irq handling */
> + drm_crtc_vblank_on(crtc);
> +
> dpu_crtc->power_event = dpu_power_handle_register_event(
> dpu_crtc->phandle,
> DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE |
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH v2 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file
DPU is short for the Display Processing Unit. It is the display
controller on Qualcomm SDM845 chips.
While the dts is pretty sparse for sdm845 atm, the only piece
we're missing is the iommu. It's commented out for now, and should be
uncommented once support is provided.
Changes in v2:
- Beefed up commit message
- Use SoC specific compatibles for mdss and dpu
- Use assigned-clocks to set initial clock frequency
Signed-off-by: Sean Paul
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 200 +++
1 file changed, 200 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cdaabeb3c995..f1f4cdc9cb63 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5,6 +5,8 @@
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
+#include
+#include
#include
/ {
@@ -221,6 +223,204 @@
#interrupt-cells = <2>;
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sdm845-mdss";
+ reg = <0xae0 0x1000>;
+ reg-names = "mdss_phys";
+
+ power-domains = < 0>;
+
+ clocks = < GCC_DISP_AHB_CLK>,
+< GCC_DISP_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ assigned-clocks = < DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <3>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ /* iommus = <_iommu 0>; */
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+ reg-names = "mdp_phys", "vbif_phys";
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_MDP_CLK>,
+ <
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <3>,
+ <1920>;
+
+ interrupt-parent = <>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0xae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4 0>;
+
+ clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+< DISP_CC_MDSS_BYTE0_INTF_CLK>,
+< DISP_CC_MDSS_PCLK0_CLK>,
+< DISP_CC_MDSS_ESC0_CLK>,
+< DISP_CC_MDSS_AHB_C
[Freedreno] [PATCH v2 19/21] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU
From: Jeykumar Sankaran
Adds bindings for Snapdragon 845 display processing unit
Changes in v2:
- Use SoC specific compatibles for mdss and dpu
- Use assigned-clocks to set initial clock frequency
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Rajesh Yadav
Signed-off-by: Sean Paul
---
.../devicetree/bindings/display/msm/dpu.txt | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
new file mode 100644
index ..a998028896ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -0,0 +1,136 @@
+Qualcomm Technologies, Inc. DPU KMS
+
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,sdm845-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+ * "mdss_phys"
+- power-domains: a power domain consumer specifier according to
+ Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required:
+ * "iface"
+ * "bus"
+ * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- assigned-clocks: list of phandles for clock device nodes needing rate
+ assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,sdm845-dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+ * "mdp_phys"
+ * "vbif_phys"
+- clocks: list of phandles for clock device nodes needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required.
+ * "bus"
+ * "iface"
+ * "core"
+ * "vsync"
+- interrupt-parent: phandle to MDSS block.
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+ to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+ Each output port contains an endpoint that describes how it is connected to
an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ Port 0 -> DPU_INTF1 (DSI1)
+ Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- assigned-clocks: list of phandles for clock device nodes needing rate
+ assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+Example:
+
+ mdss: mdss@ae0 {
+ compatible = "qcom,sdm845-mdss";
+ reg = <0xae0 0x1000>;
+ reg-names = "mdss_phys";
+
+ power-domains = <_dispcc 0>;
+
+ clocks = < GCC_DISP_AHB_CLK>, < GCC_DISP_AXI_CLK>,
+<_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ assigned-clocks = <_dispcc DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <3>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_iommu 0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+ reg-names = "mdp_phys", "vbif_phys";
+
+ clocks = <_dispcc DISP_CC_MDSS_AHB_CLK>,
+
Re: [Freedreno] [PATCH] drm/msm: avoid using 'timespec'
On Tue, Jul 10, 2018 at 11:27:00PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 10, 2018 at 10:47 PM, Sean Paul wrote:
> > On Mon, Jun 18, 2018 at 05:39:42PM +0200, Arnd Bergmann wrote:
> >> The timespec structure and associated interfaces are deprecated and will
> >> be removed in the future because of the y2038 overflow.
> >>
> >> The use of ktime_to_timespec() in timeout_to_jiffies() does not
> >> suffer from that overflow, but is easy to avoid by just converting
> >> the ktime_t into jiffies directly.
> >>
> >> Signed-off-by: Arnd Bergmann
> >> ---
> >> drivers/gpu/drm/msm/msm_drv.h | 3 +--
> >> 1 file changed, 1 insertion(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> >> index b2da1fbf81e0..cc8977476a41 100644
> >> --- a/drivers/gpu/drm/msm/msm_drv.h
> >> +++ b/drivers/gpu/drm/msm/msm_drv.h
> >> @@ -353,8 +353,7 @@ static inline unsigned long timeout_to_jiffies(const
> >> ktime_t *timeout)
> >> remaining_jiffies = 0;
> >> } else {
> >> ktime_t rem = ktime_sub(*timeout, now);
> >> - struct timespec ts = ktime_to_timespec(rem);
> >> - remaining_jiffies = timespec_to_jiffies();
> >> + remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
> >
> > Do you need to wrap rem in ktime_to_ns() just to be safe?
>
> The ktime_t interfaces are still defined to use an opaque type,
> as previously it was a union that could be a seconds/nanoseconds
> pair depending on the architecture. These days, ktime_t is just
> a 64-bit integer, so div_u64() would work just as well as ktime_divns(),
> but this is the documented way to do it.
Hey Arnd,
Ahh, ok, I think I realize my confusion now. If ktime_t was not ns,
ktime_divns() would do the conversion for us. Since it is ns, the conversion
is a no-op (which is why I didn't see ktime_to_ns() in ktime_divns()).
Thanks for breaking that down for me,
Reviewed-by: Sean Paul
>
> Arnd
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Re: [Freedreno] [PATCH] drm/msm: avoid using 'timespec'
On Mon, Jun 18, 2018 at 05:39:42PM +0200, Arnd Bergmann wrote:
> The timespec structure and associated interfaces are deprecated and will
> be removed in the future because of the y2038 overflow.
>
> The use of ktime_to_timespec() in timeout_to_jiffies() does not
> suffer from that overflow, but is easy to avoid by just converting
> the ktime_t into jiffies directly.
>
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/msm/msm_drv.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index b2da1fbf81e0..cc8977476a41 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -353,8 +353,7 @@ static inline unsigned long timeout_to_jiffies(const
> ktime_t *timeout)
> remaining_jiffies = 0;
> } else {
> ktime_t rem = ktime_sub(*timeout, now);
> - struct timespec ts = ktime_to_timespec(rem);
> - remaining_jiffies = timespec_to_jiffies();
> + remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
Do you need to wrap rem in ktime_to_ns() just to be safe?
Sean
> }
>
> return remaining_jiffies;
> --
> 2.9.0
>
--
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Re: [Freedreno] [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file
On Mon, Jul 09, 2018 at 12:07:11PM -0600, Rob Herring wrote:
> On Mon, Jul 9, 2018 at 11:40 AM Sean Paul wrote:
> >
> > Signed-off-by: Sean Paul
> > ---
> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++
> > 1 file changed, 194 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index cdaabeb3c995..339afed856de 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -5,6 +5,8 @@
> > * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> > */
> >
> > +#include
> > +#include
> > #include
> >
> > / {
> > @@ -221,6 +223,198 @@
> > #interrupt-cells = <2>;
> > };
> >
> > + mdss: mdss@ae0 {
> > + compatible = "qcom,dpu-mdss";
> > + reg = <0xae0 0x1000>;
> > + reg-names = "mdss_phys";
> > +
> > + power-domains = < 0>;
> > +
> > + clocks = < GCC_DISP_AHB_CLK>,
> > +< GCC_DISP_AXI_CLK>,
> > +< DISP_CC_MDSS_MDP_CLK>;
> > + clock-names = "iface", "bus", "core";
> > + clock-frequency = <0 0 3>;
> > +
> > + interrupts = ;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > +
> > + /* iommus = <_iommu 0>; */
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + mdss_mdp: mdp@ae01000 {
> > + compatible = "qcom,dpu";
>
Hi Rob,
Thanks for the quick turnaround! In addition to below, I'll also beef up the
commit message, since I forgot to add any description of the change.
> Needs an SoC specific compatible. Did this binding get reviewed?
>
No, it's part of this set ([PATCH 19/21] dt-bindings: msm/disp: Add bindings for
Snapdragon 845 DPU).
> > + reg = <0x0ae01000 0x8f000>,
> > + <0x0aeb 0x2008>;
> > + reg-names = "mdp_phys", "vbif_phys";
> > +
> > + clocks = < DISP_CC_MDSS_AHB_CLK>,
> > +< DISP_CC_MDSS_AXI_CLK>,
> > +< DISP_CC_MDSS_MDP_CLK>,
> > +< DISP_CC_MDSS_VSYNC_CLK>;
> > + clock-names = "iface", "bus", "core",
> > "vsync";
> > + clock-frequency = <0 0 3 1920>;
>
> That's abusing clock-frequency which is generally 1 value. Use
> assigned-clock-rates instead.
>
Thanks, will change.
> > +
> > + interrupt-parent = <>;
> > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dpu_intf1_out: endpoint {
> > + remote-endpoint =
> > <_in>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + dpu_intf2_out: endpoint {
> > + remote-endpoint =
> > <_in>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + dsi0: dsi
[Freedreno] [PATCH 21/21] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file
Signed-off-by: Sean Paul
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 194 +++
1 file changed, 194 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cdaabeb3c995..339afed856de 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5,6 +5,8 @@
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
+#include
+#include
#include
/ {
@@ -221,6 +223,198 @@
#interrupt-cells = <2>;
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,dpu-mdss";
+ reg = <0xae0 0x1000>;
+ reg-names = "mdss_phys";
+
+ power-domains = < 0>;
+
+ clocks = < GCC_DISP_AHB_CLK>,
+< GCC_DISP_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+ clock-frequency = <0 0 3>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ /* iommus = <_iommu 0>; */
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+ reg-names = "mdp_phys", "vbif_phys";
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+ clock-frequency = <0 0 3 1920>;
+
+ interrupt-parent = <>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0xae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4 0>;
+
+ clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+< DISP_CC_MDSS_BYTE0_INTF_CLK>,
+< DISP_CC_MDSS_PCLK0_CLK>,
+< DISP_CC_MDSS_ESC0_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte_clk",
+ "byte_intf_clk",
+ "pixel_clk",
+ "core_clk",
+ "iface_clk",
+ "bus_clk";
+
+ phys = <_phy>;
+ phy-names = "dsi-phy";
+
+ #address-cells = <1>;
+ #size-cells =
[Freedreno] [PATCH 18/21] drm/msm: Add pm_suspend/resume callbacks to msm_kms
From: Jeykumar Sankaran
Used by the dpu driver for custom suspend/resume.
Signed-off-by: Jeykumar Sankaran
[seanpaul split this out of the megapatch]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 10 ++
drivers/gpu/drm/msm/msm_kms.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index ed6efebabc38..cd0959783203 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -912,6 +912,11 @@ static int msm_pm_suspend(struct device *dev)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ /* TODO: Use atomic helper suspend/resume */
+ if (kms && kms->funcs && kms->funcs->pm_suspend)
+ return kms->funcs->pm_suspend(dev);
drm_kms_helper_poll_disable(ddev);
@@ -928,6 +933,11 @@ static int msm_pm_resume(struct device *dev)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+ struct msm_kms *kms = priv->kms;
+
+ /* TODO: Use atomic helper suspend/resume */
+ if (kms && kms->funcs && kms->funcs->pm_resume)
+ return kms->funcs->pm_resume(dev);
drm_atomic_helper_resume(ddev, priv->pm_state);
drm_kms_helper_poll_enable(ddev);
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 9cd7223febcf..36201f43fa31 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -62,6 +62,9 @@ struct msm_kms_funcs {
void (*set_encoder_mode)(struct msm_kms *kms,
struct drm_encoder *encoder,
bool cmd_mode);
+ /* pm suspend/resume hooks */
+ int (*pm_suspend)(struct device *dev);
+ int (*pm_resume)(struct device *dev);
/* cleanup: */
void (*destroy)(struct msm_kms *kms);
#ifdef CONFIG_DEBUG_FS
--
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[Freedreno] [PATCH 15/21] drm/msm: #define MAX_ in msm_drv.h
From: Jeykumar Sankaran
dpu uses these elsewhere in the driver (in addition to increasing
MAX_PLANES, that'll come later), so pull them out into #define.
Signed-off-by: Jeykumar Sankaran
[seanpaul pulled this out of the dpu megapatch]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.h | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index fa0376b0f42b..3b206ae6423f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -54,6 +54,12 @@ struct msm_fence_context;
struct msm_gem_address_space;
struct msm_gem_vma;
+#define MAX_CRTCS 8
+#define MAX_PLANES 16
+#define MAX_ENCODERS 8
+#define MAX_BRIDGES8
+#define MAX_CONNECTORS 8
+
struct msm_file_private {
rwlock_t queuelock;
struct list_head submitqueues;
@@ -117,19 +123,19 @@ struct msm_drm_private {
struct workqueue_struct *wq;
unsigned int num_planes;
- struct drm_plane *planes[16];
+ struct drm_plane *planes[MAX_PLANES];
unsigned int num_crtcs;
- struct drm_crtc *crtcs[8];
+ struct drm_crtc *crtcs[MAX_CRTCS];
unsigned int num_encoders;
- struct drm_encoder *encoders[8];
+ struct drm_encoder *encoders[MAX_ENCODERS];
unsigned int num_bridges;
- struct drm_bridge *bridges[8];
+ struct drm_bridge *bridges[MAX_BRIDGES];
unsigned int num_connectors;
- struct drm_connector *connectors[8];
+ struct drm_connector *connectors[MAX_CONNECTORS];
/* Properties */
struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
--
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[Freedreno] [PATCH 14/21] drm/msm: Use labels for unwinding in the error path
From: Jeykumar Sankaran
This simplifies cleanup, to make sure nothing drops out in case of
error.
Signed-off-by: Jeykumar Sankaran
[seanpaul split out of dpu megapatch and renamed labels]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 44 +--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 67816543a0d7..8bd9fe831968 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -372,19 +372,16 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv) {
- drm_dev_unref(ddev);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto err_unref_drm_dev;
}
ddev->dev_private = priv;
priv->dev = ddev;
ret = mdp5_mdss_init(ddev);
- if (ret) {
- kfree(priv);
- drm_dev_unref(ddev);
- return ret;
- }
+ if (ret)
+ goto err_free_priv;
mdss = priv->mdss;
@@ -399,17 +396,12 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
/* Bind all our sub-components: */
ret = component_bind_all(dev, ddev);
- if (ret) {
- if (mdss && mdss->funcs)
- mdss->funcs->destroy(ddev);
- kfree(priv);
- drm_dev_unref(ddev);
- return ret;
- }
+ if (ret)
+ goto err_destroy_mdss;
ret = msm_init_vram(ddev);
if (ret)
- goto fail;
+ goto err_msm_uninit;
msm_gem_shrinker_init(ddev);
@@ -435,7 +427,7 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
*/
dev_err(dev, "failed to load kms\n");
ret = PTR_ERR(kms);
- goto fail;
+ goto err_msm_uninit;
}
/* Enable normalization of plane zpos */
@@ -445,7 +437,7 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
ret = kms->funcs->hw_init(kms);
if (ret) {
dev_err(dev, "kms hw init failed: %d\n", ret);
- goto fail;
+ goto err_msm_uninit;
}
}
@@ -455,7 +447,7 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
ret = drm_vblank_init(ddev, priv->num_crtcs);
if (ret < 0) {
dev_err(dev, "failed to initialize vblank\n");
- goto fail;
+ goto err_msm_uninit;
}
if (kms) {
@@ -464,13 +456,13 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
pm_runtime_put_sync(dev);
if (ret < 0) {
dev_err(dev, "failed to install IRQ handler\n");
- goto fail;
+ goto err_msm_uninit;
}
}
ret = drm_dev_register(ddev, 0);
if (ret)
- goto fail;
+ goto err_msm_uninit;
drm_mode_config_reset(ddev);
@@ -481,15 +473,23 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
ret = msm_debugfs_late_init(ddev);
if (ret)
- goto fail;
+ goto err_msm_uninit;
drm_kms_helper_poll_init(ddev);
return 0;
-fail:
+err_msm_uninit:
msm_drm_uninit(dev);
return ret;
+err_destroy_mdss:
+ if (mdss && mdss->funcs)
+ mdss->funcs->destroy(ddev);
+err_free_priv:
+ kfree(priv);
+err_unref_drm_dev:
+ drm_dev_unref(ddev);
+ return ret;
}
/*
--
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[Freedreno] [PATCH 11/21] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor
From: Abhinav Kumar
Make the pclk_rate u64 to accommodate higher pixel clock
rates.
Changes in v4:
- fixed commit message
Signed-off-by: Abhinav Kumar
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 671039b7b75b..73587e731a23 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host,
bool is_dual_dsi)
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
u8 lanes = msm_host->lanes;
u32 bpp = dsi_get_bpp(msm_host->format);
- u32 pclk_rate;
+ u64 pclk_rate;
+ u64 pclk_bpp;
if (!mode) {
pr_err("%s: mode not set\n", __func__);
@@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host
*msm_host, bool is_dual_dsi)
if (is_dual_dsi)
pclk_rate /= 2;
+ pclk_bpp = pclk_rate * bpp;
if (lanes > 0) {
- msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+ do_div(pclk_bpp, (8 * lanes));
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
- msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+ do_div(pclk_bpp, 8);
}
msm_host->pixel_clk_rate = pclk_rate;
+ msm_host->byte_clk_rate = pclk_bpp;
DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
msm_host->byte_clk_rate);
--
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[Freedreno] [PATCH 12/21] drm/msm: Clean up dangling atomic_wq
I missed this during the atomic conversion
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 4
drivers/gpu/drm/msm/msm_drv.h | 1 -
2 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 9c760cee5156..b73acdd52931 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -244,9 +244,6 @@ static int msm_drm_uninit(struct device *dev)
flush_workqueue(priv->wq);
destroy_workqueue(priv->wq);
- flush_workqueue(priv->atomic_wq);
- destroy_workqueue(priv->atomic_wq);
-
if (kms && kms->funcs)
kms->funcs->destroy(kms);
@@ -389,7 +386,6 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
mdss = priv->mdss;
priv->wq = alloc_ordered_workqueue("msm", 0);
- priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0);
INIT_LIST_HEAD(>inactive_list);
INIT_LIST_HEAD(>vblank_ctrl.event_list);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 17cefca1d566..fa0376b0f42b 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -115,7 +115,6 @@ struct msm_drm_private {
struct list_head inactive_list;
struct workqueue_struct *wq;
- struct workqueue_struct *atomic_wq;
unsigned int num_planes;
struct drm_plane *planes[16];
--
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[Freedreno] [PATCH 10/21] drm/msm: enable zpos normalization
From: Jeykumar Sankaran
Enable drm core zpos normalization for planes.
changes in v2:
- none
changes in v3:
- rebased on https://gitlab.freedesktop.org/seanpaul/
dpu-staging/commit/481d29d31cd629fd216381b53de5695f645465d5
Signed-off-by: Jeykumar Sankaran
Reviewed-by: Sean Paul
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 2608d3f77956..9c760cee5156 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -439,6 +439,9 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
goto fail;
}
+ /* Enable normalization of plane zpos */
+ ddev->mode_config.normalize_zpos = true;
+
if (kms) {
ret = kms->funcs->hw_init(kms);
if (ret) {
--
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[Freedreno] [PATCH 09/21] drm/msm/mdp5: subclass msm_mdss for mdp5
From: Rajesh Yadav
SoCs having mdp5 or dpu have identical tree like
device hierarchy where MDSS top level wrapper manages
common power resources for all child devices.
Subclass msm_mdss so that msm_mdss includes common defines
and mdp5/dpu mdss derivations to include any extensions.
Add mdss helper interface (msm_mdss_funcs) to msm_mdss
base for mdp5/dpu mdss specific implementation calls.
This change subclasses msm_mdss for mdp5, dpu specific
changes will be done separately.
Changes in v3:
- none
Changes in v2:
- fixed indentation for irq_domain_add_linear call (Sean Paul)
Signed-off-by: Rajesh Yadav
Reviewed-by: Sean Paul
[seanpaul rebased on msm-next and resolved conflicts]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c | 154 --
drivers/gpu/drm/msm/msm_drv.c | 22 +++-
drivers/gpu/drm/msm/msm_kms.h | 17 ++-
3 files changed, 109 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
index f2a0db7a8a03..1cc4e57f0226 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c
@@ -20,12 +20,10 @@
#include "msm_drv.h"
#include "mdp5_kms.h"
-/*
- * If needed, this can become more specific: something like struct mdp5_mdss,
- * which contains a 'struct msm_mdss base' member.
- */
-struct msm_mdss {
- struct drm_device *dev;
+#define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
+
+struct mdp5_mdss {
+ struct msm_mdss base;
void __iomem *mmio, *vbif;
@@ -41,22 +39,22 @@ struct msm_mdss {
} irqcontroller;
};
-static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
+static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
{
- msm_writel(data, mdss->mmio + reg);
+ msm_writel(data, mdp5_mdss->mmio + reg);
}
-static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
+static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
{
- return msm_readl(mdss->mmio + reg);
+ return msm_readl(mdp5_mdss->mmio + reg);
}
static irqreturn_t mdss_irq(int irq, void *arg)
{
- struct msm_mdss *mdss = arg;
+ struct mdp5_mdss *mdp5_mdss = arg;
u32 intr;
- intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
+ intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
VERB("intr=%08x", intr);
@@ -64,7 +62,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)
irq_hw_number_t hwirq = fls(intr) - 1;
generic_handle_irq(irq_find_mapping(
- mdss->irqcontroller.domain, hwirq));
+ mdp5_mdss->irqcontroller.domain, hwirq));
intr &= ~(1 << hwirq);
}
@@ -84,19 +82,19 @@ static irqreturn_t mdss_irq(int irq, void *arg)
static void mdss_hw_mask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- clear_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ clear_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
static void mdss_hw_unmask_irq(struct irq_data *irqd)
{
- struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
+ struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
smp_mb__before_atomic();
- set_bit(irqd->hwirq, >irqcontroller.enabled_mask);
+ set_bit(irqd->hwirq, _mdss->irqcontroller.enabled_mask);
smp_mb__after_atomic();
}
@@ -109,13 +107,13 @@ static struct irq_chip mdss_hw_irq_chip = {
static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
- struct msm_mdss *mdss = d->host_data;
+ struct mdp5_mdss *mdp5_mdss = d->host_data;
if (!(VALID_IRQS & (1 << hwirq)))
return -EPERM;
irq_set_chip_and_handler(irq, _hw_irq_chip, handle_level_irq);
- irq_set_chip_data(irq, mdss);
+ irq_set_chip_data(irq, mdp5_mdss);
return 0;
}
@@ -126,90 +124,99 @@ static const struct irq_domain_ops mdss_hw_irqdomain_ops
= {
};
-static int mdss_irq_domain_init(struct msm_mdss *mdss)
+static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
{
- struct device *dev = mdss->dev->dev;
+ struct device *dev = mdp5_mdss->base.dev->dev;
struct irq_domain *d;
d = irq_domain_add_linear(dev->of_node, 32, _hw_irqdomain_ops,
- mdss);
+ mdp5_mdss);
if (!d) {
dev_err(dev, "mdss irq domain add failed\n");
return
[Freedreno] [PATCH 08/21] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks
DPU doesn't use this, so push it into the mdp drivers. Signed-off-by: Sean Paul Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 ++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 ++ drivers/gpu/drm/msm/msm_atomic.c | 2 -- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index 4b646bf9c214..44d1cda56974 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -125,6 +125,8 @@ static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; + drm_atomic_helper_wait_for_vblanks(mdp4_kms->dev, state); + /* see 119ecb7fd */ for_each_new_crtc_in_state(state, crtc, crtc_state, i) drm_crtc_vblank_put(crtc); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 6e12e275deba..bddd625ab91b 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -170,6 +170,8 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s struct device *dev = _kms->pdev->dev; struct mdp5_global_state *global_state; + drm_atomic_helper_wait_for_vblanks(mdp5_kms->dev, state); + global_state = mdp5_get_existing_global_state(mdp5_kms); if (mdp5_kms->smp) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index f0635c3da7f4..e6f1e25c60af 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -75,8 +75,6 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state) kms->funcs->complete_commit(kms, state); - drm_atomic_helper_wait_for_vblanks(dev, state); - drm_atomic_helper_commit_hw_done(state); drm_atomic_helper_cleanup_planes(dev, state); -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 07/21] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll
From: Rajesh Yadav postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Signed-off-by: Rajesh Yadav Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index c4c37a7df637..4c03f0b7343e 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -798,6 +798,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) return ERR_PTR(-ENOMEM); } + spin_lock_init(_10nm->postdiv_lock); + pll = _10nm->base; pll->min_rate = 10UL; pll->max_rate = 350000UL; -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 06/21] drm/msm/dsi: Use one connector for dual DSI mode
From: Chandan Uddaraju
Current DSI driver uses two connectors for dual DSI case even
though we only have one panel. Fix this by implementing one
connector/bridge for dual DSI use case. Use master DSI
controllers to register one connector/bridge.
Changes in V2:
-Removed Change-Id from the commit text tags.
-Remove extra parentheses
Changes in V3:
-None
Reviewed-by: Archit Taneja
Signed-off-by: Chandan Uddaraju
[seanpaul removed unused local var causing a build warning]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi.c | 3 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_manager.c | 112 ++
3 files changed, 30 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index b744bcc7d8ad..ff8164cc6738 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -208,6 +208,9 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct
drm_device *dev,
goto fail;
}
+ if (!msm_dsi_manager_validate_current_config(msm_dsi->id))
+ goto fail;
+
msm_dsi->encoder = encoder;
msm_dsi->bridge = msm_dsi_manager_bridge_init(msm_dsi->id);
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 01c38f67d699..c858e8e1a5bd 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -100,6 +100,7 @@ bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base,
u32 len);
void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
+bool msm_dsi_manager_validate_current_config(u8 id);
/* msm dsi */
static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index 3bb506b44a4b..000721fe5ab4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -306,102 +306,25 @@ static void dsi_mgr_connector_destroy(struct
drm_connector *connector)
kfree(dsi_connector);
}
-static void dsi_dual_connector_fix_modes(struct drm_connector *connector)
-{
- struct drm_display_mode *mode, *m;
-
- /* Only support left-right mode */
- list_for_each_entry_safe(mode, m, >probed_modes, head) {
- mode->clock >>= 1;
- mode->hdisplay >>= 1;
- mode->hsync_start >>= 1;
- mode->hsync_end >>= 1;
- mode->htotal >>= 1;
- drm_mode_set_name(mode);
- }
-}
-
-static int dsi_dual_connector_tile_init(
- struct drm_connector *connector, int id)
-{
- struct drm_display_mode *mode;
- /* Fake topology id */
- char topo_id[8] = {'M', 'S', 'M', 'D', 'U', 'D', 'S', 'I'};
-
- if (connector->tile_group) {
- DBG("Tile property has been initialized");
- return 0;
- }
-
- /* Use the first mode only for now */
- mode = list_first_entry(>probed_modes,
- struct drm_display_mode,
- head);
- if (!mode)
- return -EINVAL;
-
- connector->tile_group = drm_mode_get_tile_group(
- connector->dev, topo_id);
- if (!connector->tile_group)
- connector->tile_group = drm_mode_create_tile_group(
- connector->dev, topo_id);
- if (!connector->tile_group) {
- pr_err("%s: failed to create tile group\n", __func__);
- return -ENOMEM;
- }
-
- connector->has_tile = true;
- connector->tile_is_single_monitor = true;
-
- /* mode has been fixed */
- connector->tile_h_size = mode->hdisplay;
- connector->tile_v_size = mode->vdisplay;
-
- /* Only support left-right mode */
- connector->num_h_tile = 2;
- connector->num_v_tile = 1;
-
- connector->tile_v_loc = 0;
- connector->tile_h_loc = (id == DSI_RIGHT) ? 1 : 0;
-
- return 0;
-}
-
static int dsi_mgr_connector_get_modes(struct drm_connector *connector)
{
int id = dsi_mgr_connector_get_id(connector);
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct drm_panel *panel = msm_dsi->panel;
- int ret, num;
+ int num;
if (!panel)
return 0;
- /* Since we have 2 connectors, but only 1 drm_panel in dual DSI mode,
-* panel should not attach to any connector.
-* Only temporarily attach panel to the current connector here,
-* to let panel set mode to this connector.
+ /*
+* In dual DSI mode, we
[Freedreno] [PATCH 05/21] drm/msm/dsi: adjust dsi timing for dual dsi mode
From: Chandan Uddaraju
For dual dsi mode, the horizontal timing needs
to be divided by half since both the dsi controllers
will be driving this panel. Adjust the pixel clock and
DSI timing accordingly.
Changes in V2:
--Removed Change-Id from the commit text tags.
Changes in V3:
--Instead of adjusting the DRM mode structure, divide
the clocks and horizontal timings in DSI host just
before configuring the values.
Signed-off-by: Chandan Uddaraju
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dsi/dsi.h | 6 ++-
drivers/gpu/drm/msm/dsi/dsi_host.c| 55 +--
drivers/gpu/drm/msm/dsi/dsi_manager.c | 7 ++--
3 files changed, 52 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 70d9a9a47acd..01c38f67d699 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -162,7 +162,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host
*host,
int msm_dsi_host_enable(struct mipi_dsi_host *host);
int msm_dsi_host_disable(struct mipi_dsi_host *host);
int msm_dsi_host_power_on(struct mipi_dsi_host *host,
- struct msm_dsi_phy_shared_timings *phy_shared_timings);
+ struct msm_dsi_phy_shared_timings *phy_shared_timings,
+ bool is_dual_dsi);
int msm_dsi_host_power_off(struct mipi_dsi_host *host);
int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
struct drm_display_mode *mode);
@@ -175,7 +176,8 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll);
void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
- struct msm_dsi_phy_clk_request *clk_req);
+ struct msm_dsi_phy_clk_request *clk_req,
+ bool is_dual_dsi);
void msm_dsi_host_destroy(struct mipi_dsi_host *host);
int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 2f1a2780658a..671039b7b75b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -118,6 +118,7 @@ struct msm_dsi_host {
struct clk *byte_intf_clk;
u32 byte_clk_rate;
+ u32 pixel_clk_rate;
u32 esc_clk_rate;
/* DSI v2 specific clocks */
@@ -511,7 +512,7 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host
*msm_host)
goto error;
}
- ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+ ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -592,7 +593,7 @@ static int dsi_link_clk_enable_v2(struct msm_dsi_host
*msm_host)
goto error;
}
- ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
+ ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
if (ret) {
pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
goto error;
@@ -662,7 +663,7 @@ static void dsi_link_clk_disable(struct msm_dsi_host
*msm_host)
}
}
-static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
+static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
{
struct drm_display_mode *mode = msm_host->mode;
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
@@ -676,14 +677,28 @@ static int dsi_calc_clk_rate(struct msm_dsi_host
*msm_host)
}
pclk_rate = mode->clock * 1000;
+
+ /*
+* For dual DSI mode, the current DRM mode has
+* the complete width of the panel. Since, the complete
+* panel is driven by two DSI controllers, the
+* the clock rates have to be split between
+* the two dsi controllers. Adjust the byte and
+* pixel clock rates for each dsi host accordingly.
+*/
+ if (is_dual_dsi)
+ pclk_rate /= 2;
+
if (lanes > 0) {
msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
} else {
pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
}
+ msm_host->pixel_clk_rate = pclk_rate;
- DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
+ DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
+ msm_host->byte_clk_rate);
msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
@@ -885,7 +900,7 @@ static void dsi_ctrl_config(struct msm_dsi_host
[Freedreno] [PATCH 04/21] drm: add msm compressed format modifiers
From: Jeykumar Sankaran
Qualcomm Snapdragon chipsets uses compressed format
to optimize BW across multiple IP's. This change adds
needed modifier support in drm for a simple 4x4 tile
based compressed variants of base formats.
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sean Paul
---
include/uapi/drm/drm_fourcc.h | 45 +++
1 file changed, 45 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index e04613d30a13..9a97405a3d2a 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -298,6 +298,38 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
+/*
+ * Qualcomm Compressed Format
+ *
+ * Refers to a compressed variant of the base format that is compressed.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
+
+/*
+ * QTI DX Format
+ *
+ * Refers to a DX variant of the base format.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_DX fourcc_mod_code(QCOM, 0x2)
+
+/*
+ * QTI Tight Format
+ *
+ * Refers to a tightly packed variant of the base format.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_TIGHT fourcc_mod_code(QCOM, 0x4)
+
+/*
+ * QTI Tile Format
+ *
+ * Refers to a tile variant of the base format.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_TILE fourcc_mod_code(QCOM, 0x8)
+
/* Vivante framebuffer modifiers */
/*
@@ -405,6 +437,19 @@ extern "C" {
*/
#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
+/*
+ * MSM compressed format
+ *
+ * Refers to the compressed variant of a base format.
+ * Implementation may be platform and base-format specific.
+ *
+ * Each macrotile consists of m x n (mostly 4 x 4) tiles.
+ * Pixel data pitch/stride is aligned with macrotile width.
+ * Pixel data height is aligned with macrotile height.
+ * Entire pixel data buffer is aligned with 4k(bytes).
+ */
+#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
+
#if defined(__cplusplus)
}
#endif
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH 02/21] dt-bindings: clock: Introduce QCOM Display clock bindings
From: Taniya Das
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
Reviewed-by: Rob Herring
Signed-off-by: Sean Paul
---
.../devicetree/bindings/clock/qcom,dispcc.txt | 19
.../dt-bindings/clock/qcom,dispcc-sdm845.h| 45 +++
2 files changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc.txt
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sdm845.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
new file mode 100644
index ..d639e18d0b85
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt
@@ -0,0 +1,19 @@
+Qualcomm Technologies, Inc. Display Clock Controller Binding
+
+
+Required properties :
+
+- compatible : shall contain "qcom,sdm845-dispcc"
+- reg : shall contain base register location and length.
+- #clock-cells : from common clock binding, shall contain 1.
+- #reset-cells : from common reset binding, shall contain 1.
+- #power-domain-cells : from generic power domain binding, shall contain 1.
+
+Example:
+ dispcc: clock-controller@af0 {
+ compatible = "qcom,sdm845-dispcc";
+ reg = <0xaf0 0x10>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h
b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
new file mode 100644
index ..11eed4bc9646
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AXI_CLK 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_INTF_CLK4
+#define DISP_CC_MDSS_BYTE1_CLK 5
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 6
+#define DISP_CC_MDSS_BYTE1_INTF_CLK7
+#define DISP_CC_MDSS_ESC0_CLK 8
+#define DISP_CC_MDSS_ESC0_CLK_SRC 9
+#define DISP_CC_MDSS_ESC1_CLK 10
+#define DISP_CC_MDSS_ESC1_CLK_SRC 11
+#define DISP_CC_MDSS_MDP_CLK 12
+#define DISP_CC_MDSS_MDP_CLK_SRC 13
+#define DISP_CC_MDSS_MDP_LUT_CLK 14
+#define DISP_CC_MDSS_PCLK0_CLK 15
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
+#define DISP_CC_MDSS_PCLK1_CLK 17
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 18
+#define DISP_CC_MDSS_ROT_CLK 19
+#define DISP_CC_MDSS_ROT_CLK_SRC 20
+#define DISP_CC_MDSS_RSCC_AHB_CLK 21
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK22
+#define DISP_CC_MDSS_VSYNC_CLK 23
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
+#define DISP_CC_PLL0 25
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_RSCC_BCR 0
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH 03/21] drm: Add support for pps and compression mode command packet
From: vkorjani
After enabling DSC we need to send compression mode command packet
and pps data packet, for which 2 new data types are added
07h Compression Mode Data Type Write , short write, 2 parameters
0Ah PPS Long Write (word count determines number of bytes)
This patch adds support to send these packets.
Cc: David Airlie
Cc: Jean-Christophe Plagniol-Villard
Cc: Tomi Valkeinen
Cc: dri-de...@lists.freedesktop.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-fb...@vger.kernel.org
Signed-off-by: vkorjani
[seanpaul removed pps_write_buffer fn, added types to packet_format helpers]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
include/video/mipi_display.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index bc73b7f5b9fc..80b75501f5c6 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -392,6 +392,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
+ case MIPI_DSI_DCS_COMPRESSION_MODE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -410,6 +411,7 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
bool mipi_dsi_packet_format_is_long(u8 type)
{
switch (type) {
+ case MIPI_DSI_PPS_LONG_WRITE:
case MIPI_DSI_NULL_PACKET:
case MIPI_DSI_BLANKING_PACKET:
case MIPI_DSI_GENERIC_LONG_WRITE:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 19aa65a35546..49a53ef8da96 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -38,6 +38,9 @@ enum {
MIPI_DSI_DCS_READ = 0x06,
+ MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
+ MIPI_DSI_PPS_LONG_WRITE = 0x0A,
+
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
MIPI_DSI_END_OF_TRANSMISSION= 0x08,
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH 01/21] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding
From: Jeykumar Sankaran Adds mdp transfer time to msm dsi binding Signed-off-by: Jeykumar Sankaran Signed-off-by: Rajesh Yadav Signed-off-by: Sean Paul --- .../devicetree/bindings/display/msm/dsi.txt | 16 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 518e9cdf0d4b..d22237a88eae 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -121,6 +121,20 @@ Required properties: Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY regulator is wanted. +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt [2] Documentation/devicetree/bindings/graph.txt @@ -171,6 +185,8 @@ Example: qcom,master-dsi; qcom,sync-dual-dsi; + qcom,mdss-mdp-transfer-time-us = <12000>; + pinctrl-names = "default", "sleep"; pinctrl-0 = <_active>; pinctrl-1 = <_suspend>; -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 00/21] drm/msm: Add support for SDM845 Display Processing Unit (DPU)
u: use kms stored hw mdp block drm/msm/dpu: use private obj to track hw resources drm/msm/dsi-staging: compile out partial update path drm/msm/dsi-staging: remove support for partial update drm/msm: enable zpos normalization drm/msm: hook up DPU with upstream DSI drm/msm: populate aspace in msm_kms drm/msm: remove connector custom properties drm/msm: remove display stream compression(DSC) support for SM845 drm/msm: remove dpu specific uapi header drm/msm: remove dsi-staging driver drm/msm: remove hw rotation support drm/msm: remove msm_prop files drm/msm: remove panel autorefresh support for SDM845 drm/msm: remove partial update support drm/msm: remove support for ping pong split topology drm/msm: strip down custom event ioctl's Jordan Crouse (1): drm/msm/dpu: Remove unused code and move the header Rajesh Yadav (29): Revert "drm/msm: Add DisplayPort support" drm/msm/dp: remove dpu_power_handle calls from dp driver drm/msm/dpu: add MDSS top level driver for dpu drm/msm/dpu: add error handling in dpu_core_perf_crtc_update drm/msm/dpu: correct dpu_io_util.h include path drm/msm/dpu: create new platform driver for dpu device drm/msm/dpu: move dpu_io_util to dpu folder drm/msm/dpu: move dpu_power_handle to dpu folder drm/msm/dpu: remove clock management code from dpu_power_handle drm/msm/dpu: remove dt parsing logic for bus_scale config drm/msm/dpu: remove hdcp support drm/msm/dpu: remove msm_prop entry from Makefile drm/msm/dpu: remove power management code from dpu_power_handle drm/msm/dpu: remove writeback support drm/msm/dpu: update dpu sub-block offsets wrt dpu base address drm/msm/dpu: use runtime_pm calls in dpu_dbg drm/msm/dpu: use runtime_pm calls on dpu device drm/msm/dsi-staging: Gate bus scale code drm/msm/dsi: initialize postdiv_lock before use for 10nm pll drm/msm/mdp5: subclass msm_mdss for mdp5 drm/msm: Fix return type mismatch for dpu_kms_init drm/msm: Remove RSC support from DPU driver drm/msm: Remove unused variables drm/msm: remove redundant pm_runtime_enable call from msm_drv dt-bindings: msm/disp: Remove DPU RSC device bindings dt-bindings: msm/disp: cleanup bindings for Snapdragon 845 DPU dt-bindings: msm/disp: remove unused display port bindings dt-bindings: msm/disp: remove unused dsi & panel bindings dt-bindings: msm/disp: remove unused writeback bindings Sean Paul (85): arm64: dts: qcom: Remove obsolete dpu dts files arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file drm/bridge: adv7511: Reset registers on hotplug drm/mipi: Remove Qualcomm-specific dsi packet header format drm/mipi: Remove unused mipi/dsi packet types drm/msm: Add displayport files to Makefile drm/msm: Add pm_runtime_get/put calls to dpu drm/msm: Alphabetize dpu files in Makefile drm/msm: Change driver name back to msm drm/msm: Defer probe if display component not found drm/msm: Disable mdp5 crtc when there are no active planes drm/msm: Don't duplicate modeset_enables atomic helper drm/msm: Fix NULL deref on bind/probe deferral drm/msm: Fix deadlock calling msm_gem_new() drm/msm: Fix dpu build warnings drm/msm: Fix dpu compile when CONFIG_DEBUG_FS !defined drm/msm: Fix uninitialized use of prefill_lines drm/msm: Include the dpu_dbg header in msm_drv.c drm/msm: Issue queued events when disabling crtc drm/msm: Mark the crtc->state->event consumed drm/msm: More cleanup in msm_drv drm/msm: Move debugfs root tracking to dpu drm/msm: Move dpu_dbg init/destroy into dpu_kms drm/msm: Move implicit sync fence handling to prepare_fb drm/msm: Move implicit sync handling to prepare_fb drm/msm: Populate kms->irq for dpu drm/msm: Properly cast return with ERR_PTR drm/msm: Reduce dpu_crtc_atomic_check frame size drm/msm: Refactor complete_commit() to look more the helpers drm/msm: Remove DPU_DBG->pr_err ifdef gate drm/msm: Remove _dpu_format_calc_offset_linear() drm/msm: Remove atomic_check() from msm_kms drm/msm: Remove dpu bus scaling code drm/msm: Remove dpu input fences drm/msm: Remove dpu module parameters drm/msm: Remove dpu_edid_parser drm/msm: Remove dpu_kms_fbo and associated functions drm/msm: Remove dpu_plane_state->defer_prepare_fb drm/msm: Remove get_address_space msm_kms hook drm/msm: Remove hand-rolled out fences drm/msm: Remove ion from dpu drm/msm: Remove more dpu changes from msm core drm/msm: Remove more dpu-related code from msm_drv drm/msm: Remove msm_commit/kthread, use atomic helper commit drm/msm: Remove msm_commit/worker, use atomic helpe
[Freedreno] [DPU PATCH] drm/msm: Remove msm_hdcp devicetree bindings
hdcp support was (temporarily) removed from msm.
Signed-off-by: Sean Paul
---
.../devicetree/bindings/msm_hdcp/msm_hdcp.txt | 14 --
1 file changed, 14 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/msm_hdcp/msm_hdcp.txt
diff --git a/Documentation/devicetree/bindings/msm_hdcp/msm_hdcp.txt
b/Documentation/devicetree/bindings/msm_hdcp/msm_hdcp.txt
deleted file mode 100644
index 8d5f55d7a8ca..
--- a/Documentation/devicetree/bindings/msm_hdcp/msm_hdcp.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-MSM HDCP driver
-
-Standalone driver managing HDCP related communications
-between TZ and HLOS for MSM chipset.
-
-Required properties:
-
-compatible = "qcom,msm-hdcp";
-
-Example:
-
-qcom_msmhdcp: qcom,msm_hdcp {
- compatible = "qcom,msm-hdcp";
-};
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 2/3] dt-bindings: dpu: Fixup dt-bindings discrepencies
Signed-off-by: Sean Paul
---
.../devicetree/bindings/display/msm/dpu.txt | 22 +++
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index a4407b848faf..d3b13a517579 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -39,6 +39,7 @@ Required properties:
- reg: physical base address and length of controller's registers.
- reg-names : register region names. The following region is required:
* "mdp_phys"
+ * "vbif_phys"
- clocks: list of phandles for clock device nodes needed by the device.
- clock-names: device clock names, must be in same order as clocks property.
The following clocks are required.
@@ -74,15 +75,16 @@ Example:
power-domains = <_dispcc 0>;
clocks = < GCC_DISP_AHB_CLK>,
-< GCC_DISP_AXI_CLK>,
-<_dispcc DISP_CC_MDSS_MDP_CLK>;
- clock-names = "gcc_iface", "gcc_bus", "core_clk";
+< GCC_DISP_AXI_CLK>,
+<_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface_clk", "bus_clk", "core_clk";
+ clock-frequency = <0 0 3>;
interrupts = ;
interrupt-controller;
#interrupt-cells = <1>;
- iommus = <_smmu 0>;
+ iommus = <_iommu 0>;
#address-cells = <1>;
#size-cells = <1>;
@@ -90,14 +92,16 @@ Example:
mdss_mdp: mdp@ae01000 {
compatible = "qcom,dpu";
- reg = <0x0ae01000 0x8f000>;
- reg-names = "mdp_phys";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+ reg-names = "mdp_phys", "vbif_phys";
clocks = <_dispcc DISP_CC_MDSS_AHB_CLK>,
-<_dispcc DISP_CC_MDSS_AXI_CLK>,
-<_dispcc DISP_CC_MDSS_MDP_CLK>,
-<_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+<_dispcc DISP_CC_MDSS_AXI_CLK>,
+<_dispcc DISP_CC_MDSS_MDP_CLK>,
+<_dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface_clk", "bus_clk", "core_clk",
"vsync_clk";
+ clock-frequency = <0 0 3 1920>;
interrupt-parent = <>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 1/3] arm64: dts: qcom: Remove obsolete dpu dts files
Signed-off-by: Sean Paul
---
.../boot/dts/qcom/sdm845-dpu-display.dtsi | 248 --
arch/arm64/boot/dts/qcom/sdm845-dpu.dtsi | 323 --
2 files changed, 571 deletions(-)
delete mode 100644 arch/arm64/boot/dts/qcom/sdm845-dpu-display.dtsi
delete mode 100644 arch/arm64/boot/dts/qcom/sdm845-dpu.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sdm845-dpu-display.dtsi
b/arch/arm64/boot/dts/qcom/sdm845-dpu-display.dtsi
deleted file mode 100644
index 294efaee9a19..
--- a/arch/arm64/boot/dts/qcom/sdm845-dpu-display.dtsi
+++ /dev/null
@@ -1,248 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
-#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
-#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
-#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
-#include
-
- {
- dsi_panel_pwr_supply: dsi_panel_pwr_supply {
- #address-cells = <1>;
- #size-cells = <0>;
-
- qcom,panel-supply-entry@0 {
- reg = <0>;
- qcom,supply-name = "vddio";
- qcom,supply-min-voltage = <180>;
- qcom,supply-max-voltage = <180>;
- qcom,supply-enable-load = <62000>;
- qcom,supply-disable-load = <80>;
- qcom,supply-post-on-sleep = <20>;
- };
-
- qcom,panel-supply-entry@1 {
- reg = <1>;
- qcom,supply-name = "lab";
- qcom,supply-min-voltage = <460>;
- qcom,supply-max-voltage = <600>;
- qcom,supply-enable-load = <10>;
- qcom,supply-disable-load = <100>;
- };
-
- qcom,panel-supply-entry@2 {
- reg = <2>;
- qcom,supply-name = "ibb";
- qcom,supply-min-voltage = <460>;
- qcom,supply-max-voltage = <600>;
- qcom,supply-enable-load = <10>;
- qcom,supply-disable-load = <100>;
- qcom,supply-post-on-sleep = <20>;
- };
- };
-
- dsi_dual_nt35597_truly_video_display: qcom,dsi-display@4 {
- compatible = "qcom,dsi-display";
- label = "dsi_dual_nt35597_truly_video_display";
- qcom,display-type = "primary";
-
- qcom,dsi-ctrl = <_dsi0 _dsi1>;
- qcom,dsi-phy = <_dsi_phy0 _dsi_phy1>;
- clocks = <_dsi0_pll BYTECLK_MUX_0_CLK>,
- <_dsi0_pll PCLK_MUX_0_CLK>;
- clock-names = "src_byte_clk", "src_pixel_clk";
-
- pinctrl-names = "panel_active", "panel_suspend";
- pinctrl-0 = <_dsi_active _te_active>;
- pinctrl-1 = <_dsi_suspend _te_suspend>;
- qcom,platform-reset-gpio = < 6 0>;
- qcom,panel-mode-gpio = < 52 0>;
-
- qcom,dsi-panel = <_dual_nt35597_truly_video>;
- vddio-supply = <_l14>;
- lab-supply = <_regulator>;
- ibb-supply = <_regulator>;
- };
-
- dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@5 {
- compatible = "qcom,dsi-display";
- label = "dsi_dual_nt35597_truly_cmd_display";
- qcom,display-type = "primary";
-
- qcom,dsi-ctrl = <_dsi0 _dsi1>;
- qcom,dsi-phy = <_dsi_phy0 _dsi_phy1>;
- clocks = <_dsi0_pll BYTECLK_MUX_0_CLK>,
- <_dsi0_pll PCLK_MUX_0_CLK>;
- clock-names = "src_byte_clk", "src_pixel_clk";
-
- pinctrl-names = "panel_active", "panel_suspend";
- pinctrl-0 = <_dsi_active _te_active>;
- pinctrl-1 = <_dsi_suspend _te_suspend>;
- qcom,platform-te-gpio = < 10 0>;
- qcom,platform-re
[Freedreno] [DPU PATCH 3/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file
Signed-off-by: Sean Paul
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 182 +++
1 file changed, 182 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cdaabeb3c995..537269636b43 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -221,6 +221,188 @@
#interrupt-cells = <2>;
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,dpu-mdss";
+ reg = <0xae0 0x1000>;
+ reg-names = "mdss_phys";
+
+ power-domains = <_dispcc 0>;
+
+ clocks = < GCC_DISP_AHB_CLK>,
+< GCC_DISP_AXI_CLK>,
+<_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface_clk", "bus_clk", "core_clk";
+ clock-frequency = <0 0 3>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_iommu 0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+ reg-names = "mdp_phys", "vbif_phys";
+
+ clocks = <_dispcc DISP_CC_MDSS_AHB_CLK>,
+<_dispcc DISP_CC_MDSS_AXI_CLK>,
+<_dispcc DISP_CC_MDSS_MDP_CLK>,
+<_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface_clk", "bus_clk",
"core_clk", "vsync_clk";
+ clock-frequency = <0 0 3 1920>;
+
+ interrupt-parent = <>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0xae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4 0>;
+
+ clocks = <_dispcc DISP_CC_MDSS_BYTE0_CLK>,
+<_dispcc
DISP_CC_MDSS_BYTE0_INTF_CLK>,
+<_dispcc DISP_CC_MDSS_PCLK0_CLK>,
+<_dispcc DISP_CC_MDSS_ESC0_CLK>,
+<_dispcc DISP_CC_MDSS_AHB_CLK>,
+<_dispcc DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte_clk",
+ "byte_intf_clk",
+ "pixel_clk",
+ "core_clk",
+ "iface_clk",
+ "bus_clk";
+
+ phys = <_phy>;
+ phy-names = "dsi-phy";
+
+ #address-cells = <1>;
+ #size-cells =
Re: [Freedreno] [PATCH] drm/msm/mdp5: fix missing CTL flush
On Tue, Jul 03, 2018 at 12:43:50PM -0400, Rob Clark wrote: > f9cb8d8d836e fixed various race conditions with CTL flush, in particular > flushing and sending the START signal before encoder state was updated. > But it did this a little too well in some cases that don't trigger > encoder->enable(), and CTL[n].FLUSH would never be set. When page flips > happen it would paper over the bug, since the first plag flip would > flush out the state to the hardware. > > The issue could be reproduced with, for example, modetest (without the > '-v' argument). > > Fixes: f9cb8d8d836e drm/msm/mdp5: rework CTL START signal handling > Signed-off-by: Rob Clark Reviewed-by: Sean Paul > --- > drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c | 12 +++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c > index 9af94e35f678..fcd44d1d1068 100644 > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c > @@ -319,7 +319,17 @@ static int mdp5_encoder_atomic_check(struct drm_encoder > *encoder, > > mdp5_cstate->ctl = ctl; > mdp5_cstate->pipeline.intf = intf; > - mdp5_cstate->defer_start = true; > + > + /* > + * This is a bit awkward, but we want to flush the CTL and hit the > + * START bit at most once for an atomic update. In the non-full- > + * modeset case, this is done from crtc->atomic_flush(), but that > + * is too early in the case of full modeset, in which case we > + * defer to encoder->enable(). But we need to *know* whether > + * encoder->enable() will be called to do this: > + */ > + if (drm_atomic_crtc_needs_modeset(crtc_state)) > + mdp5_cstate->defer_start = true; > > return 0; > } > -- > 2.17.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] drm/msm: Disable mdp5 crtc when there are no active planes
Unlike other compositors, we don't get a crtc disable from weston when the cable is unplugged. As such, when the cable is re-plugged the kernel doesn't detect an enable/mode change and initiates a simple plane update instead of a modeset. This patch clears the mode when all planes are off. Signed-off-by: Sean Paul --- Sorry for the wide distribution, I'm not 100% on whether this is the right place to fix this. Is this expected behavior from weston? Once we have solid fill support, it seems reasonable that a crtc might be left on if no planes are active (for blanking the screen, etc). However, hotplug is currently borked, so I don't want to just leave it as-is if this should be handled in the kernel. Suggestions welcome! Sean drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index 63dcc39b5efd..e89e46a4014e 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -645,7 +645,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, /* bail out early if there aren't any planes */ if (!cnt) - return 0; + return drm_atomic_set_mode_for_crtc(state, NULL); hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 0/6] drm/msm: Fix dpu compile for unlikely #ifdef paths
I took a pass through the driver looking for CONFIG_ paths that were untested. I found a few cases where either compile was broken, or the config path was never used. Here's a few patches to fix it up. Here's hoping this will avoid any nastygrams from folks running into compilation issues once dpu is upstream. Sean Sean Paul (6): drm/msm: Remove DPU_DBG->pr_err ifdef gate drm/msm: Alphabetize dpu files in Makefile drm/msm: Remove dpu bus scaling code drm/msm: Remove ion from dpu drm/msm: Fix dpu compile when CONFIG_DEBUG_FS !defined drm/msm: Remove remnants of dsi-staging drivers/gpu/drm/msm/Makefile | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 35 -- drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h | 4 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 32 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 - .../gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 522 +- .../gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 65 +-- 8 files changed, 10 insertions(+), 677 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 4/6] drm/msm: Remove ion from dpu
It's mostly gone and won't compile with CONFIG_ION, so
remove the remaining pieces.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 25 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4
2 files changed, 29 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 605da85bb53f..fcb94f01d8ad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -599,15 +599,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
return ret;
}
-#ifdef CONFIG_ION
-static void dpu_kms_set_gem_flags(struct msm_gem_object *msm_obj,
- uint32_t flags)
-{
- if (msm_obj)
- msm_obj->flags |= flags;
-}
-#endif
-
#ifdef CONFIG_DEBUG_FS
static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
{
@@ -657,13 +648,6 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
_dpu_debugfs_destroy(dpu_kms);
_dpu_kms_mmu_destroy(dpu_kms);
-#ifdef CONFIG_ION
- if (dpu_kms->iclient) {
- ion_client_destroy(dpu_kms->iclient);
- dpu_kms->iclient = NULL;
- }
-#endif
-
if (dpu_kms->catalog) {
for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
@@ -1131,15 +1115,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
}
}
-#ifdef CONFIG_ION
- dpu_kms->iclient = msm_ion_client_create(dev->unique);
- if (IS_ERR(dpu_kms->iclient)) {
- rc = PTR_ERR(dpu_kms->iclient);
- DPU_DEBUG("msm_ion_client not available: %d\n", rc);
- dpu_kms->iclient = NULL;
- }
-#endif
-
rc = dpu_core_perf_init(_kms->perf, dev, dpu_kms->catalog,
_kms->phandle,
_dpu_kms_get_clk(dpu_kms, "core_clk"));
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index f7a3915b2907..407c1ed27fe6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -19,9 +19,6 @@
#ifndef __DPU_KMS_H__
#define __DPU_KMS_H__
-#ifdef CONFIG_CHROME_MSM_ION
-#include
-#endif
#include "msm_drv.h"
#include "msm_kms.h"
#include "msm_mmu.h"
@@ -118,7 +115,6 @@ struct dpu_kms {
struct dpu_power_handle phandle;
struct dpu_power_client *core_client;
- struct ion_client *iclient;
struct dpu_power_event *power_event;
/* directory entry for debugfs */
--
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[Freedreno] [DPU PATCH 6/6] drm/msm: Remove remnants of dsi-staging
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
index 89edf2526aca..1e6fa945f98b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
@@ -68,15 +68,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, bool
dump_dbgbus_dpu,
*/
void dpu_dbg_set_dpu_top_offset(u32 blk_off);
-/**
- * dsi_ctrl_debug_dump - dump dsi debug dump status
- */
-#if defined(CONFIG_DRM_MSM_DSI_STAGING)
-void dsi_ctrl_debug_dump(void);
-#else
-static inline void dsi_ctrl_debug_dump(void) {}
-#endif
-
#else
static inline void dpu_dbg_init_dbg_buses(u32 hwversion)
@@ -106,10 +97,6 @@ static inline void dpu_dbg_set_dpu_top_offset(u32 blk_off)
{
}
-static inline void dsi_ctrl_debug_dump(void)
-{
-}
-
#endif /* defined(CONFIG_DEBUG_FS) */
--
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[Freedreno] [DPU PATCH 3/6] drm/msm: Remove dpu bus scaling code
QC bus scaling isn't upstream yet, so remove the bus scaling code until
it is.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 35 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +-
.../gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 522 +-
.../gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 65 +--
4 files changed, 4 insertions(+), 625 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 1019ce7594ff..41c5191f9056 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -221,7 +221,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
struct drm_crtc *crtc, u32 bus_id)
{
- u64 bw_sum_of_intfs = 0, bus_ab_quota, bus_ib_quota;
struct dpu_core_perf_params perf = { { 0 } };
enum dpu_crtc_client_type curr_client_type
= dpu_crtc_get_client_type(crtc);
@@ -239,45 +238,11 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms
*kms,
max(perf.max_per_pipe_ib[bus_id],
dpu_cstate->new_perf.max_per_pipe_ib[bus_id]);
- bw_sum_of_intfs += dpu_cstate->new_perf.bw_ctl[bus_id];
-
DPU_DEBUG("crtc=%d bus_id=%d bw=%llu\n",
tmp_crtc->base.id, bus_id,
dpu_cstate->new_perf.bw_ctl[bus_id]);
}
}
-
- bus_ab_quota = max(bw_sum_of_intfs, kms->perf.perf_tune.min_bus_vote);
- bus_ib_quota = perf.max_per_pipe_ib[bus_id];
-
- if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
- bus_ab_quota = kms->perf.fix_core_ab_vote;
- bus_ib_quota = kms->perf.fix_core_ib_vote;
- }
-
- switch (curr_client_type) {
- case NRT_CLIENT:
- ret = dpu_power_data_bus_set_quota(
- >phandle, kms->core_client,
- DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
- bus_id, bus_ab_quota, bus_ib_quota);
- DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
- bus_id, bus_ab_quota, bus_ib_quota);
- break;
-
- case RT_CLIENT:
- ret = dpu_power_data_bus_set_quota(
- >phandle, kms->core_client,
- DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
- bus_id, bus_ab_quota, bus_ib_quota);
- DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
- bus_id, bus_ab_quota, bus_ib_quota);
- break;
-
- default:
- DPU_ERROR("invalid client type:%d\n", curr_client_type);
- break;
- }
return ret;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 3889e4a7dfbc..605da85bb53f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1265,11 +1265,7 @@ static int dpu_bind(struct device *dev, struct device
*master, void *data)
goto clk_rate_error;
}
- ret = dpu_power_resource_init(pdev, _kms->phandle);
- if (ret) {
- pr_err("dpu power resource init failed\n");
- goto power_init_fail;
- }
+ dpu_power_resource_init(pdev, _kms->phandle);
platform_set_drvdata(pdev, dpu_kms);
@@ -1283,7 +1279,6 @@ static int dpu_bind(struct device *dev, struct device
*master, void *data)
priv->kms = _kms->base;
return ret;
-power_init_fail:
clk_rate_error:
msm_dss_put_clk(mp->clk_config, mp->num_clk);
clk_get_error:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
index f997bd9e109c..a68f1249388c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
@@ -24,132 +24,6 @@
#include "dpu_power_handle.h"
#include "dpu_trace.h"
-#ifdef CONFIG_QCOM_BUS_SCALING
-#include
-#include
-
-#define DPU_BUS_VECTOR_ENTRY(src_val, dst_val, ab_val, ib_val) \
- { \
- .src = src_val,\
- .dst = dst_val,\
- .ab = (ab_val),\
- .ib = (ib_val),\
- }
-
-static struct msm_bus_vectors dpu_reg_bus_vectors[] = {
- DPU_BUS_VEC
[Freedreno] [DPU PATCH 2/6] drm/msm: Alphabetize dpu files in Makefile
See subject. Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 2604ccfd0653..3624b5af5ecd 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -70,11 +70,11 @@ msm-y := \ disp/dpu1/dpu_irq.o \ disp/dpu1/dpu_kms.o \ disp/dpu1/dpu_kms_utils.o \ + disp/dpu1/dpu_mdss.o \ disp/dpu1/dpu_plane.o \ + disp/dpu1/dpu_power_handle.o \ disp/dpu1/dpu_rm.o \ disp/dpu1/dpu_vbif.o \ - disp/dpu1/dpu_mdss.o \ - disp/dpu1/dpu_power_handle.o \ msm_atomic.o \ msm_debugfs.o \ msm_drv.o \ -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 1/6] drm/msm: Remove DPU_DBG->pr_err ifdef gate
It's pretty easy to just s/debug/err/ Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h index 773b52e71a22..bc07381d7429 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h @@ -17,11 +17,7 @@ #include #include -#ifdef DEBUG -#define DEV_DBG(fmt, args...) pr_err(fmt, ##args) -#else #define DEV_DBG(fmt, args...) pr_debug(fmt, ##args) -#endif #define DEV_INFO(fmt, args...) pr_info(fmt, ##args) #define DEV_WARN(fmt, args...) pr_warn(fmt, ##args) #define DEV_ERR(fmt, args...) pr_err(fmt, ##args) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 5/6] drm/msm: Fix dpu compile when CONFIG_DEBUG_FS !defined
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/Makefile| 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 3624b5af5ecd..1639ea8c0d13 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -49,7 +49,6 @@ msm-y := \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
- disp/dpu1/dpu_dbg.o \
disp/dpu1/dpu_encoder.o \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
@@ -92,7 +91,8 @@ msm-y := \
msm_ringbuffer.o \
msm_submitqueue.o
-msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o
+msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
+ disp/dpu1/dpu_dbg.o
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-$(CONFIG_COMMON_CLK) += disp/mdp4/mdp4_lvds_pll.o
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
index 05504e676f6a..89edf2526aca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
@@ -98,11 +98,11 @@ static inline void dpu_dbg_destroy(void)
}
static inline void dpu_dbg_dump(bool queue_work, const char *name,
- bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt);
+ bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt)
{
}
-void dpu_dbg_set_dpu_top_offset(u32 blk_off)
+static inline void dpu_dbg_set_dpu_top_offset(u32 blk_off)
{
}
--
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Re: [Freedreno] [DPU PATCH 04/15] drm/msm: Remove more dpu-related code from msm_drv
On Thu, Jun 28, 2018 at 4:10 PM Jordan Crouse wrote:
>
> On Thu, Jun 28, 2018 at 02:28:55PM -0400, Sean Paul wrote:
> > This time the iomap/iounmap helper functions. Move map into dpu and
> > refactor it to reflect their actual use. iounmap wasn't useful, so
> > delete it and call iounmap directly.
> >
> > Signed-off-by: Sean Paul
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 38 +---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 13 ++--
> > drivers/gpu/drm/msm/msm_drv.c| 23 --
> > drivers/gpu/drm/msm/msm_drv.h| 2 --
> > 4 files changed, 38 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index 0b813a089cba..beba919a6ef6 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -77,6 +77,25 @@ bool dpu_is_custom_client(void)
> > return dpucustom;
> > }
> >
> > +static unsigned long dpu_iomap_size(struct platform_device *pdev,
> > + const char *name)
> > +{
> > + struct resource *res;
> > +
> > + if (!name) {
> > + DRM_ERROR("Resource name unspecified\n");
> > + return 0;
> > + }
>
> Maybe Just a WARN instead - a custom string isn't needed for a case that will
> never happen outside of developer error.
>
Hmm, yeah, this was lifted direct from msm_kms, so I didn't think too
much about it. This is one of those "check for NULL even if it'll
never be NULL" checks that is prevalent across dpu. I think I'll just
remove the check so it falls over if name is NULL.
Sean
>
>
> --
> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
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[Freedreno] [DPU PATCH 14/15] drm/msm: Remove atomic_check() from msm_kms
It's never called since we use the atomic helpers
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 26 -
drivers/gpu/drm/msm/msm_kms.h | 3 ---
2 files changed, 29 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index edb5d40f9160..4011525e1d7e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -773,31 +773,6 @@ static void dpu_kms_preclose(struct msm_kms *kms, struct
drm_file *file)
dpu_crtc_cancel_pending_flip(priv->crtcs[i], file);
}
-static int dpu_kms_atomic_check(struct msm_kms *kms,
- struct drm_atomic_state *state)
-{
- struct dpu_kms *dpu_kms;
- struct drm_device *dev;
- int ret;
-
- if (!kms || !state)
- return -EINVAL;
-
- dpu_kms = to_dpu_kms(kms);
- dev = dpu_kms->dev;
-
- if (dpu_kms_is_suspend_blocked(dev)) {
- DPU_DEBUG("suspended, skip atomic_check\n");
- return -EBUSY;
- }
-
- ret = drm_atomic_helper_check(dev, state);
- if (ret)
- return ret;
-
- return 0;
-}
-
static int dpu_kms_pm_suspend(struct device *dev)
{
struct drm_device *ddev;
@@ -962,7 +937,6 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .atomic_check = dpu_kms_atomic_check,
.get_format = dpu_get_msm_format,
.round_pixclk= dpu_kms_round_pixclk,
.pm_suspend = dpu_kms_pm_suspend,
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index e275cc42ecd3..93e46d75bf56 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -60,9 +60,6 @@ struct msm_kms_funcs {
const struct msm_format *msm_fmt,
const struct drm_mode_fb_cmd2 *cmd,
struct drm_gem_object **bos);
- /* perform complete atomic check of given atomic state */
- int (*atomic_check)(struct msm_kms *kms,
- struct drm_atomic_state *state);
/* misc: */
long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
struct drm_encoder *encoder);
--
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[Freedreno] [DPU PATCH 08/15] drm/msm: dpu: Do debugfs init in the debugfs_init() hook
This allows us to remove postinit, which was added with dpu support.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 13 ++---
drivers/gpu/drm/msm/msm_drv.c | 9 -
drivers/gpu/drm/msm/msm_kms.h | 1 -
3 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 61eecae15ab3..1f2163430caf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -323,11 +323,6 @@ static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms)
}
}
#else
-static int _dpu_debugfs_init(struct dpu_kms *dpu_kms)
-{
- return 0;
-}
-
static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms)
{
}
@@ -991,7 +986,8 @@ void dpu_kms_fbo_unreference(struct dpu_kms_fbo *fbo)
}
}
-static int dpu_kms_postinit(struct msm_kms *kms)
+#ifdef CONFIG_DEBUG_FS
+static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
{
struct dpu_kms *dpu_kms = to_dpu_kms(kms);
struct drm_device *dev;
@@ -1010,6 +1006,7 @@ static int dpu_kms_postinit(struct msm_kms *kms)
return rc;
}
+#endif
static long dpu_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
struct drm_encoder *encoder)
@@ -1289,7 +1286,6 @@ void _dpu_kms_set_encoder_mode(struct msm_kms *kms,
static const struct msm_kms_funcs kms_funcs = {
.hw_init = dpu_kms_hw_init,
- .postinit= dpu_kms_postinit,
.irq_preinstall = dpu_irq_preinstall,
.irq_postinstall = dpu_irq_postinstall,
.irq_uninstall = dpu_irq_uninstall,
@@ -1311,6 +1307,9 @@ static const struct msm_kms_funcs kms_funcs = {
.destroy = dpu_kms_destroy,
.get_address_space = _dpu_kms_get_address_space,
.set_encoder_mode = _dpu_kms_set_encoder_mode,
+#ifdef CONFIG_DEBUG_FS
+ .debugfs_init= dpu_kms_debugfs_init,
+#endif
};
/* the caller api needs to turn on clock before calling it */
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index bcd001603768..1e8d67381b5a 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -593,15 +593,6 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
if (ret)
goto fail;
- /* perform subdriver post initialization */
- if (kms && kms->funcs && kms->funcs->postinit) {
- ret = kms->funcs->postinit(kms);
- if (ret) {
- pr_err("kms post init failed: %d\n", ret);
- goto fail;
- }
- }
-
drm_kms_helper_poll_init(ddev);
return 0;
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 3a583ee2f27a..2f1c9702b820 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -34,7 +34,6 @@
struct msm_kms_funcs {
/* hw initialization: */
int (*hw_init)(struct msm_kms *kms);
- int (*postinit)(struct msm_kms *kms);
/* irq handling: */
void (*irq_preinstall)(struct msm_kms *kms);
int (*irq_postinstall)(struct msm_kms *kms);
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 07/15] drm/msm: Remove _dpu_format_calc_offset_linear()
It's unused.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 32 -
1 file changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 12dc6a9d3b25..44fefc97e1b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -1092,38 +1092,6 @@ int dpu_format_populate_layout(
return ret;
}
-static void _dpu_format_calc_offset_linear(struct dpu_hw_fmt_layout *source,
- u32 x, u32 y)
-{
- if ((x == 0) && (y == 0))
- return;
-
- source->plane_addr[0] += y * source->plane_pitch[0];
-
- if (source->num_planes == 1) {
- source->plane_addr[0] += x * source->format->bpp;
- } else {
- uint32_t xoff, yoff;
- uint32_t v_subsample = 1;
- uint32_t h_subsample = 1;
-
- _dpu_get_v_h_subsample_rate(source->format->chroma_sample,
- _subsample, _subsample);
-
- xoff = x / h_subsample;
- yoff = y / v_subsample;
-
- source->plane_addr[0] += x;
- source->plane_addr[1] += xoff +
- (yoff * source->plane_pitch[1]);
- if (source->num_planes == 2) /* pseudo planar */
- source->plane_addr[1] += xoff;
- else /* planar */
- source->plane_addr[2] += xoff +
- (yoff * source->plane_pitch[2]);
- }
-}
-
int dpu_format_check_modified_format(
const struct msm_kms *kms,
const struct msm_format *msm_fmt,
--
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[Freedreno] [DPU PATCH 13/15] drm/msm: Reduce dpu_crtc_atomic_check frame size
Allocate pstates from the heap to avoid the following warning when
building with an arm target.
warning: the frame size of 1080 bytes is larger than 1024 bytes
[-Wframe-larger-than=]
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index c70b609aa7f2..d17128222f45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1737,7 +1737,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct dpu_crtc *dpu_crtc;
- struct plane_state pstates[DPU_STAGE_MAX * 4];
+ struct plane_state *pstates;
struct dpu_crtc_state *cstate;
const struct drm_plane_state *pstate;
@@ -1757,6 +1757,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
return -EINVAL;
}
+ pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
+
dpu_crtc = to_dpu_crtc(crtc);
cstate = to_dpu_crtc_state(state);
@@ -1792,7 +1794,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
dpu_crtc->name, plane->base.id, rc);
goto end;
}
- if (cnt >= ARRAY_SIZE(pstates))
+ if (cnt >= DPU_STAGE_MAX * 4)
continue;
pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
@@ -1959,6 +1961,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
end:
_dpu_crtc_rp_free_unused(>rp);
+ kfree(pstates);
return rc;
}
--
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[Freedreno] [DPU PATCH 10/15] drm/msm: Remove dpu_kms_fbo and associated functions
It's not used anywhere and it lets us revert the changes to msm_fb
to match upstream.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 279
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 69 --
drivers/gpu/drm/msm/msm_drv.h | 3 -
drivers/gpu/drm/msm/msm_fb.c| 4 +-
4 files changed, 3 insertions(+), 352 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 30da3e047384..ddba0873466b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -698,134 +698,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
return ret;
}
-/**
- * struct dpu_kms_fbo_fb - framebuffer creation list
- * @list: list of framebuffer attached to framebuffer object
- * @fb: Pointer to framebuffer attached to framebuffer object
- */
-struct dpu_kms_fbo_fb {
- struct list_head list;
- struct drm_framebuffer *fb;
-};
-
-struct drm_framebuffer *dpu_kms_fbo_create_fb(struct drm_device *dev,
- struct dpu_kms_fbo *fbo)
-{
- struct drm_framebuffer *fb = NULL;
- struct dpu_kms_fbo_fb *fbo_fb;
- struct drm_mode_fb_cmd2 mode_cmd = {0};
- u32 base_offset = 0;
- int i, ret;
-
- if (!dev) {
- DPU_ERROR("invalid drm device node\n");
- return NULL;
- }
-
- fbo_fb = kzalloc(sizeof(struct dpu_kms_fbo_fb), GFP_KERNEL);
- if (!fbo_fb)
- return NULL;
-
- mode_cmd.pixel_format = fbo->pixel_format;
- mode_cmd.width = fbo->width;
- mode_cmd.height = fbo->height;
- mode_cmd.flags = fbo->flags;
-
- for (i = 0; i < fbo->nplane; i++) {
- mode_cmd.offsets[i] = base_offset;
- mode_cmd.pitches[i] = fbo->layout.plane_pitch[i];
- mode_cmd.modifier[i] = fbo->modifier[i];
- base_offset += fbo->layout.plane_size[i];
- DPU_DEBUG("offset[%d]:%x\n", i, mode_cmd.offsets[i]);
- }
-
- fb = msm_framebuffer_init(dev, _cmd, fbo->bo);
- if (IS_ERR(fb)) {
- ret = PTR_ERR(fb);
- fb = NULL;
- DPU_ERROR("failed to allocate fb %d\n", ret);
- goto fail;
- }
-
- /* need to take one reference for gem object */
- for (i = 0; i < fbo->nplane; i++)
- drm_gem_object_get(fbo->bo[i]);
-
- DPU_DEBUG("register private fb:%d\n", fb->base.id);
-
- INIT_LIST_HEAD(_fb->list);
- fbo_fb->fb = fb;
- drm_framebuffer_get(fbo_fb->fb);
- list_add_tail(_fb->list, >fb_list);
-
- return fb;
-
-fail:
- kfree(fbo_fb);
- return NULL;
-}
-
-static void dpu_kms_fbo_destroy(struct dpu_kms_fbo *fbo)
-{
- struct msm_drm_private *priv;
- struct dpu_kms *dpu_kms;
- struct drm_device *dev;
- struct dpu_kms_fbo_fb *curr, *next;
- int i;
-
- if (!fbo) {
- DPU_ERROR("invalid drm device node\n");
- return;
- }
- dev = fbo->dev;
-
- if (!dev || !dev->dev_private) {
- DPU_ERROR("invalid drm device node\n");
- return;
- }
- priv = dev->dev_private;
-
- if (!priv->kms) {
- DPU_ERROR("invalid kms handle\n");
- return;
- }
- dpu_kms = to_dpu_kms(priv->kms);
-
- DPU_DEBUG("%dx%d@%c%c%c%c/%llx/%x\n", fbo->width, fbo->height,
- fbo->pixel_format >> 0, fbo->pixel_format >> 8,
- fbo->pixel_format >> 16, fbo->pixel_format >> 24,
- fbo->modifier[0], fbo->flags);
-
- list_for_each_entry_safe(curr, next, >fb_list, list) {
- DPU_DEBUG("unregister private fb:%d\n", curr->fb->base.id);
- drm_framebuffer_unregister_private(curr->fb);
- drm_framebuffer_put(curr->fb);
- list_del(>list);
- kfree(curr);
- }
-
- for (i = 0; i < fbo->layout.num_planes; i++) {
- if (fbo->bo[i]) {
- mutex_lock(>struct_mutex);
- drm_gem_object_put(fbo->bo[i]);
- mutex_unlock(>struct_mutex);
- fbo->bo[i] = NULL;
- }
- }
-
- if (fbo->dma_buf) {
- dma_buf_put(fbo->dma_buf);
- fbo->dma_buf = NULL;
- }
-
-#ifdef CONFIG_ION
- if (dpu_kms->iclient && fbo->ihandle) {
- ion_free(dpu_kms->iclient, fbo->ihandle);
- fbo->ihandle = NULL;
- }
-#endif
-}
-
#ifdef CONFIG_ION
static void dpu_kms_set_gem_flags(struct m
[Freedreno] [DPU PATCH 12/15] drm/msm: Remove unused backpointers from dpu_crtc
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 52f3e0667c33..c70b609aa7f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2241,12 +2241,10 @@ static int dpu_crtc_debugfs_state_show(struct seq_file
*s, void *v)
{
struct drm_crtc *crtc = (struct drm_crtc *) s->private;
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
- struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_crtc_res *res;
struct dpu_crtc_respool *rp;
int i;
- seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
seq_printf(s, "core_clk_rate: %llu\n",
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 7147dcb2be16..1284e991f686 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -297,8 +297,6 @@ struct dpu_crtc_respool {
/**
* struct dpu_crtc_state - dpu container for atomic crtc state
* @base: Base drm crtc state structure
- * @connectors: Currently associated drm connectors
- * @num_connectors: Number of associated drm connectors
* @is_ppsplit: Whether current topology requires PPSplit special handling
* @bw_control: true if bw/clk controlled by core bw/clk properties
* @bw_split_vote : true if bw controlled by llcc/dram bw properties
@@ -312,8 +310,6 @@ struct dpu_crtc_respool {
struct dpu_crtc_state {
struct drm_crtc_state base;
- struct drm_connector *connectors[MAX_CONNECTORS];
- int num_connectors;
bool bw_control;
bool bw_split_vote;
--
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[Freedreno] [DPU PATCH 15/15] drm/msm: Remove wait_for_tx_complete() from msm_kms
It's not called anywhere.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 44 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 4 ---
drivers/gpu/drm/msm/msm_kms.h | 3 --
3 files changed, 51 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 4011525e1d7e..a3bc4c694c0e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -319,49 +319,6 @@ static void dpu_kms_disable_vblank(struct msm_kms *kms,
struct drm_crtc *crtc)
dpu_crtc_vblank(crtc, false);
}
-static void dpu_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
- struct drm_crtc *crtc)
-{
- struct drm_encoder *encoder;
- struct drm_device *dev;
- int ret;
-
- if (!kms || !crtc || !crtc->state || !crtc->dev) {
- DPU_ERROR("invalid params\n");
- return;
- }
-
- if (!crtc->state->enable) {
- DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
- return;
- }
-
- if (!crtc->state->active) {
- DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
- return;
- }
-
- dev = crtc->dev;
-
- list_for_each_entry(encoder, >mode_config.encoder_list, head) {
- if (encoder->crtc != crtc)
- continue;
- /*
-* Video Mode - Wait for VSYNC
-* Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
-* complete
-*/
- trace_dpu_kms_wait_for_frame_transfer(DRMID(crtc));
- ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
- if (ret && ret != -EWOULDBLOCK) {
- DPU_ERROR(
- "[crtc: %d][enc: %d] wait for commit done returned
%d\n",
- crtc->base.id, encoder->base.id, ret);
- break;
- }
- }
-}
-
static void dpu_kms_prepare_commit(struct msm_kms *kms,
struct drm_atomic_state *state)
{
@@ -933,7 +890,6 @@ static const struct msm_kms_funcs kms_funcs = {
.commit = dpu_kms_commit,
.complete_commit = dpu_kms_complete_commit,
.wait_for_crtc_commit_done = dpu_kms_wait_for_commit_done,
- .wait_for_tx_complete = dpu_kms_wait_for_frame_transfer_complete,
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 1924c6662362..76efc690cce3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -307,10 +307,6 @@ DEFINE_EVENT(dpu_drm_obj_template,
dpu_crtc_complete_commit,
TP_PROTO(uint32_t drm_id),
TP_ARGS(drm_id)
);
-DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_frame_transfer,
- TP_PROTO(uint32_t drm_id),
- TP_ARGS(drm_id)
-);
DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable,
TP_PROTO(uint32_t drm_id),
TP_ARGS(drm_id)
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 93e46d75bf56..6b5535270276 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -48,9 +48,6 @@ struct msm_kms_funcs {
/* functions to wait for atomic commit completed on each CRTC */
void (*wait_for_crtc_commit_done)(struct msm_kms *kms,
struct drm_crtc *crtc);
- /* function pointer to wait for pixel transfer to panel to complete*/
- void (*wait_for_tx_complete)(struct msm_kms *kms,
- struct drm_crtc *crtc);
/* get msm_format w/ optional format modifiers from drm_mode_fb_cmd2 */
const struct msm_format *(*get_format)(struct msm_kms *kms,
const uint32_t format,
--
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[Freedreno] [DPU PATCH 11/15] drm/msm: Remove dpu module parameters
We don't use dpucustom, and the suspend blanking should be done by
userspace instead of in kernel.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 51 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 7
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 --
3 files changed, 70 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ddba0873466b..edb5d40f9160 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -55,27 +55,8 @@ static const char * const iommu_ports[] = {
#define DPU_DEBUGFS_DIR "msm_dpu"
#define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
-/**
- * dpucustom - enable certain driver customizations for dpu clients
- * Enabling this modifies the standard DRM behavior slightly and assumes
- * that the clients have specific knowledge about the modifications that
- * are involved, so don't enable this unless you know what you're doing.
- *
- * Parts of the driver that are affected by this setting may be located by
- * searching for invocations of the 'dpu_is_custom_client()' function.
- *
- * This is disabled by default.
- */
-static bool dpucustom;
-module_param(dpucustom, bool, 0400);
-MODULE_PARM_DESC(dpucustom, "Enable customizations for dpu clients");
-
static int dpu_kms_hw_init(struct msm_kms *kms);
static int _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
-bool dpu_is_custom_client(void)
-{
- return dpucustom;
-}
static unsigned long dpu_iomap_size(struct platform_device *pdev,
const char *name)
@@ -606,10 +587,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
int primary_planes_idx = 0, i, ret;
int max_crtc_count;
- u32 sspp_id[MAX_PLANES];
- u32 master_plane_id[MAX_PLANES];
- u32 num_virt_planes = 0;
-
if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) {
DPU_ERROR("invalid dpu_kms\n");
return -EINVAL;
@@ -646,27 +623,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
if (primary)
primary_planes[primary_planes_idx++] = plane;
-
- if (dpu_hw_sspp_multirect_enabled(>sspp[i]) &&
- dpu_is_custom_client()) {
- int priority =
- catalog->sspp[i].sblk->smart_dma_priority;
- sspp_id[priority - 1] = catalog->sspp[i].id;
- master_plane_id[priority - 1] = plane->base.id;
- num_virt_planes++;
- }
- }
-
- /* Initialize smart DMA virtual planes */
- for (i = 0; i < num_virt_planes; i++) {
- plane = dpu_plane_init(dev, sspp_id[i], false,
- (1UL << max_crtc_count) - 1, master_plane_id[i]);
- if (IS_ERR(plane)) {
- DPU_ERROR("dpu_plane for virtual SSPP init failed\n");
- ret = PTR_ERR(plane);
- goto fail;
- }
- priv->planes[priv->num_planes++] = plane;
}
max_crtc_count = min(max_crtc_count, primary_planes_idx);
@@ -681,13 +637,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
priv->crtcs[priv->num_crtcs++] = crtc;
}
- if (dpu_is_custom_client()) {
- /* All CRTCs are compatible with all planes */
- for (i = 0; i < priv->num_planes; i++)
- priv->planes[i]->possible_crtcs =
- (1 << priv->num_crtcs) - 1;
- }
-
/* All CRTCs are compatible with all encoders */
for (i = 0; i < priv->num_encoders; i++)
priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 6308bd84e6a9..3437598ceef1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -163,13 +163,6 @@ struct vsync_info {
#define to_dpu_kms(x) container_of(x, struct dpu_kms, base)
-/**
- * dpu_is_custom_client - whether or not to enable non-standard customizations
- *
- * Return: Whether or not the 'dpuclient' module parameter was set on boot up
- */
-bool dpu_is_custom_client(void);
-
/**
* dpu_kms_is_suspend_state - whether or not the system is pm suspended
* @dev: Pointer to drm device
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c2088a3bfba7..ae05d4d002a9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -31,14 +31,6 @@
#include "dpu_vbif.h"
#include &q
[Freedreno] [DPU PATCH 03/15] drm/msm: Move dpu_dbg init/destroy into dpu_kms
No need to have this in msm_drv, so move it into dpu. While we're at
it, remove the other CONFIG_DRM_MSM_DPU ifdef gates.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++-
drivers/gpu/drm/msm/msm_drv.c | 41 -
2 files changed, 17 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 3003176e731d..0b813a089cba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -279,6 +279,12 @@ static int _dpu_debugfs_init(struct dpu_kms *dpu_kms)
if (!debugfs_root)
return -EINVAL;
+ rc = dpu_dbg_debugfs_register(debugfs_root);
+ if (rc) {
+ DRM_ERROR("failed to reg dpu dbg debugfs: %d\n", rc);
+ return rc;
+ }
+
/* allow debugfs_root to be NULL */
debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
@@ -1072,6 +1078,8 @@ static void dpu_kms_destroy(struct msm_kms *kms)
}
dpu_kms = to_dpu_kms(kms);
+
+ dpu_dbg_destroy();
_dpu_kms_hw_destroy(dpu_kms);
}
@@ -1401,10 +1409,16 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto end;
}
+ rc = dpu_dbg_init(_kms->pdev->dev);
+ if (rc) {
+ DRM_ERROR("failed to init dpu dbg: %d\n", rc);
+ goto end;
+ }
+
priv = dev->dev_private;
if (!priv) {
DPU_ERROR("invalid private data\n");
- goto end;
+ goto dbg_destroy;
}
dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp_phys", "mdp_phys");
@@ -1592,6 +1606,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
pm_runtime_put_sync(_kms->pdev->dev);
error:
_dpu_kms_hw_destroy(dpu_kms);
+dbg_destroy:
+ dpu_dbg_destroy();
end:
return rc;
}
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 51d6b310ca33..6177b3f18912 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -26,9 +26,6 @@
#include "msm_fence.h"
#include "msm_gpu.h"
#include "msm_kms.h"
-#ifdef CONFIG_DRM_MSM_DPU
-#include "dpu_dbg.h"
-#endif
/*
* MSM driver version:
@@ -307,10 +304,6 @@ static int msm_drm_uninit(struct device *dev)
component_unbind_all(dev, ddev);
-#ifdef CONFIG_DRM_MSM_DPU
- dpu_dbg_destroy();
-#endif
-
debugfs_remove_recursive(priv->debug_root);
if (mdss && mdss->funcs)
@@ -485,14 +478,6 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
drm_mode_config_init(ddev);
-#ifdef CONFIG_DRM_MSM_DPU
- ret = dpu_dbg_init(>dev);
- if (ret) {
- dev_err(dev, "failed to init dpu dbg: %d\n", ret);
- goto dbg_init_fail;
- }
-#endif
-
msm_gem_shrinker_init(ddev);
ret = msm_init_vram(ddev);
@@ -511,11 +496,9 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
case KMS_MDP5:
kms = mdp5_kms_init(ddev);
break;
-#ifdef CONFIG_DRM_MSM_DPU
case KMS_DPU:
kms = dpu_kms_init(ddev);
break;
-#endif
default:
kms = ERR_PTR(-ENODEV);
break;
@@ -665,14 +648,6 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
goto fail;
}
-#ifdef CONFIG_DRM_MSM_DPU
- ret = dpu_dbg_debugfs_register(priv->debug_root);
- if (ret) {
- dev_err(dev, "failed to reg dpu dbg debugfs: %d\n", ret);
- goto fail;
- }
-#endif
-
/* perform subdriver post initialization */
if (kms && kms->funcs && kms->funcs->postinit) {
ret = kms->funcs->postinit(kms);
@@ -690,10 +665,6 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
msm_drm_uninit(dev);
return ret;
bind_fail:
-#ifdef CONFIG_DRM_MSM_DPU
- dpu_dbg_destroy();
-dbg_init_fail:
-#endif
if (mdss && mdss->funcs)
mdss->funcs->destroy(ddev);
mdss_init_fail:
@@ -1413,9 +1384,7 @@ static int msm_pdev_remove(struct platform_device *pdev)
static const struct of_device_id dt_match[] = {
{ .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
-#ifdef CONFIG_DRM_MSM_DPU
{ .compatible = "qcom,dpu-mdss", .data = (void *)KMS_DPU },
-#endif
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
@@ -1430,16 +1399,6 @@ static struct platform_driver msm_platform_driver = {
},
};
-#ifdef CONFI
[Freedreno] [DPU PATCH 05/15] drm/msm: More cleanup in msm_drv
Revert the component_bind function back to upstream.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/msm_drv.c | 30 +-
1 file changed, 5 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 561617db7338..5181f997f071 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -380,26 +380,6 @@ static int msm_init_vram(struct drm_device *dev)
return ret;
}
-#ifdef CONFIG_OF
-static int msm_component_bind_all(struct device *dev,
- struct drm_device *drm_dev)
-{
- int ret;
-
- ret = component_bind_all(dev, drm_dev);
- if (ret)
- DRM_ERROR("component_bind_all failed: %d\n", ret);
-
- return ret;
-}
-#else
-static int msm_component_bind_all(struct device *dev,
- struct drm_device *drm_dev)
-{
- return 0;
-}
-#endif
-
static int msm_drm_init(struct device *dev, struct drm_driver *drv)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -455,16 +435,16 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
drm_mode_config_init(ddev);
- msm_gem_shrinker_init(ddev);
+ /* Bind all our sub-components: */
+ ret = component_bind_all(dev, ddev);
+ if (ret)
+ goto bind_fail;
ret = msm_init_vram(ddev);
if (ret)
goto fail;
- /* Bind all our sub-components: */
- ret = msm_component_bind_all(dev, ddev);
- if (ret)
- goto bind_fail;
+ msm_gem_shrinker_init(ddev);
switch (get_mdp_ver(pdev)) {
case KMS_MDP4:
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 09/15] drm/msm: Remove get_address_space msm_kms hook
It's unused.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/msm_kms.h | 4
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 1f2163430caf..30da3e047384 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1128,13 +1128,6 @@ static int dpu_kms_atomic_check(struct msm_kms *kms,
return 0;
}
-static struct msm_gem_address_space*
-_dpu_kms_get_address_space(struct msm_kms *kms,
- unsigned int domain)
-{
- return kms->aspace;
-}
-
static int dpu_kms_pm_suspend(struct device *dev)
{
struct drm_device *ddev;
@@ -1305,7 +1298,6 @@ static const struct msm_kms_funcs kms_funcs = {
.pm_suspend = dpu_kms_pm_suspend,
.pm_resume = dpu_kms_pm_resume,
.destroy = dpu_kms_destroy,
- .get_address_space = _dpu_kms_get_address_space,
.set_encoder_mode = _dpu_kms_set_encoder_mode,
#ifdef CONFIG_DEBUG_FS
.debugfs_init= dpu_kms_debugfs_init,
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 2f1c9702b820..e275cc42ecd3 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -82,10 +82,6 @@ struct msm_kms_funcs {
int (*pm_resume)(struct device *dev);
/* cleanup: */
void (*destroy)(struct msm_kms *kms);
- /* get address space */
- struct msm_gem_address_space *(*get_address_space)(
- struct msm_kms *kms,
- unsigned int domain);
#ifdef CONFIG_DEBUG_FS
/* debugfs: */
int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor);
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 06/15] drm/msm: Move debugfs root tracking to dpu
We don't use it for anything else, so hide it in dpu. A few other
whitespace/trivial fixes to revert dpu changes in msm.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 37 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/msm_drv.c | 13 -
drivers/gpu/drm/msm/msm_drv.h | 8 +-
4 files changed, 17 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index beba919a6ef6..61eecae15ab3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -272,46 +272,38 @@ void *dpu_debugfs_create_regset32(const char *name,
umode_t mode,
regset, _fops_regset32);
}
-void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms)
-{
- struct msm_drm_private *priv;
-
- if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev_private)
- return NULL;
-
- priv = dpu_kms->dev->dev_private;
- return priv->debug_root;
-}
-
static int _dpu_debugfs_init(struct dpu_kms *dpu_kms)
{
void *p;
int rc;
- void *debugfs_root;
p = dpu_hw_util_get_log_mask_ptr();
if (!dpu_kms || !p)
return -EINVAL;
- debugfs_root = dpu_debugfs_get_root(dpu_kms);
- if (!debugfs_root)
- return -EINVAL;
+ dpu_kms->debugfs_root = debugfs_create_dir("debug",
+ dpu_kms->dev->primary->debugfs_root);
+ if (IS_ERR_OR_NULL(dpu_kms->debugfs_root)) {
+ DRM_ERROR("debugfs create_dir failed %ld\n",
+ PTR_ERR(dpu_kms->debugfs_root));
+ return PTR_ERR(dpu_kms->debugfs_root);
+ }
- rc = dpu_dbg_debugfs_register(debugfs_root);
+ rc = dpu_dbg_debugfs_register(dpu_kms->debugfs_root);
if (rc) {
DRM_ERROR("failed to reg dpu dbg debugfs: %d\n", rc);
return rc;
}
- /* allow debugfs_root to be NULL */
- debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
+ /* allow root to be NULL */
+ debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, dpu_kms->debugfs_root,
p);
- (void) dpu_debugfs_danger_init(dpu_kms, debugfs_root);
- (void) dpu_debugfs_vbif_init(dpu_kms, debugfs_root);
- (void) dpu_debugfs_core_irq_init(dpu_kms, debugfs_root);
+ (void) dpu_debugfs_danger_init(dpu_kms, dpu_kms->debugfs_root);
+ (void) dpu_debugfs_vbif_init(dpu_kms, dpu_kms->debugfs_root);
+ (void) dpu_debugfs_core_irq_init(dpu_kms, dpu_kms->debugfs_root);
- rc = dpu_core_perf_debugfs_init(_kms->perf, debugfs_root);
+ rc = dpu_core_perf_debugfs_init(_kms->perf, dpu_kms->debugfs_root);
if (rc) {
DPU_ERROR("failed to init perf %d\n", rc);
return rc;
@@ -327,6 +319,7 @@ static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms)
dpu_debugfs_vbif_destroy(dpu_kms);
dpu_debugfs_danger_destroy(dpu_kms);
dpu_debugfs_core_irq_destroy(dpu_kms);
+ debugfs_remove_recursive(dpu_kms->debugfs_root);
}
}
#else
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index fb4ae84a388a..4f86a51affdc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -153,6 +153,7 @@ struct dpu_kms {
struct dpu_power_event *power_event;
/* directory entry for debugfs */
+ struct dentry *debugfs_root;
struct dentry *debugfs_danger;
struct dentry *debugfs_vbif;
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 5181f997f071..bcd001603768 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -16,7 +16,6 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include
#include
#include
#include
@@ -281,8 +280,6 @@ static int msm_drm_uninit(struct device *dev)
component_unbind_all(dev, ddev);
- debugfs_remove_recursive(priv->debug_root);
-
if (mdss && mdss->funcs)
mdss->funcs->destroy(ddev);
@@ -596,15 +593,6 @@ static int msm_drm_init(struct device *dev, struct
drm_driver *drv)
if (ret)
goto fail;
- priv->debug_root = debugfs_create_dir("debug",
- ddev->primary->debugfs_root);
- if (IS_ERR_OR_NULL(priv->debug_root)) {
- pr_err("debugfs_root create_dir fail, error %ld\n",
- PTR_ERR(priv->debug_root));
- priv->debug_root = NULL;
- goto fail;
- }
-
/* perform s
[Freedreno] [DPU PATCH 04/15] drm/msm: Remove more dpu-related code from msm_drv
This time the iomap/iounmap helper functions. Move map into dpu and
refactor it to reflect their actual use. iounmap wasn't useful, so
delete it and call iounmap directly.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 38 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 13 ++--
drivers/gpu/drm/msm/msm_drv.c| 23 --
drivers/gpu/drm/msm/msm_drv.h| 2 --
4 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 0b813a089cba..beba919a6ef6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -77,6 +77,25 @@ bool dpu_is_custom_client(void)
return dpucustom;
}
+static unsigned long dpu_iomap_size(struct platform_device *pdev,
+ const char *name)
+{
+ struct resource *res;
+
+ if (!name) {
+ DRM_ERROR("Resource name unspecified\n");
+ return 0;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+ if (!res) {
+ DRM_ERROR("failed to get memory resource: %s\n", name);
+ return 0;
+ }
+
+ return resource_size(res);
+}
+
#ifdef CONFIG_DEBUG_FS
static int _dpu_danger_signal_status(struct seq_file *s,
bool danger_status)
@@ -1056,15 +1075,15 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
dpu_kms->core_client = NULL;
if (dpu_kms->vbif[VBIF_NRT])
- msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_NRT]);
+ devm_iounmap(_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
dpu_kms->vbif[VBIF_NRT] = NULL;
if (dpu_kms->vbif[VBIF_RT])
- msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_RT]);
+ devm_iounmap(_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
dpu_kms->vbif[VBIF_RT] = NULL;
if (dpu_kms->mmio)
- msm_iounmap(dpu_kms->pdev, dpu_kms->mmio);
+ devm_iounmap(_kms->pdev->dev, dpu_kms->mmio);
dpu_kms->mmio = NULL;
}
@@ -1429,7 +1448,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto error;
}
DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
- dpu_kms->mmio_len = msm_iomap_size(dpu_kms->pdev, "mdp_phys");
+ dpu_kms->mmio_len = dpu_iomap_size(dpu_kms->pdev, "mdp_phys");
dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif_phys",
"vbif_phys");
@@ -1439,16 +1458,15 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
dpu_kms->vbif[VBIF_RT] = NULL;
goto error;
}
- dpu_kms->vbif_len[VBIF_RT] = msm_iomap_size(dpu_kms->pdev,
- "vbif_phys");
+ dpu_kms->vbif_len[VBIF_RT] = dpu_iomap_size(dpu_kms->pdev, "vbif_phys");
dpu_kms->vbif[VBIF_NRT] = msm_ioremap(dpu_kms->pdev, "vbif_nrt_phys",
"vbif_nrt_phys");
if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
dpu_kms->vbif[VBIF_NRT] = NULL;
DPU_DEBUG("VBIF NRT is not defined");
} else {
- dpu_kms->vbif_len[VBIF_NRT] = msm_iomap_size(dpu_kms->pdev,
- "vbif_nrt_phys");
+ dpu_kms->vbif_len[VBIF_NRT] = dpu_iomap_size(dpu_kms->pdev,
+"vbif_nrt_phys");
}
dpu_kms->reg_dma = msm_ioremap(dpu_kms->pdev, "regdma_phys",
@@ -1457,8 +1475,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
dpu_kms->reg_dma = NULL;
DPU_DEBUG("REG_DMA is not defined");
} else {
- dpu_kms->reg_dma_len = msm_iomap_size(dpu_kms->pdev,
- "regdma_phys");
+ dpu_kms->reg_dma_len = dpu_iomap_size(dpu_kms->pdev,
+ "regdma_phys");
}
dpu_kms->core_client = dpu_power_client_create(_kms->phandle,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 5c69c2cc5d10..5191c77cd907 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -162,7 +162,7 @@ static void dpu_mdss_destroy(struct drm_device *dev)
devm_kfree(>dev, mp->clk_config);
if
[Freedreno] [DPU PATCH 01/15] drm/msm: Remove more dpu changes from msm core
This patch is removing a bunch more dpu changes that
touch msm core.
Signed-off-by: Sean Paul
Change-Id: I1c82454ad372b34ca5b0d6db2af1b513a5ba2fe1
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 77 +--
drivers/gpu/drm/msm/msm_atomic.c | 3 +-
drivers/gpu/drm/msm/msm_drv.c| 246 ++-
drivers/gpu/drm/msm/msm_drv.h| 154 +-
drivers/gpu/drm/msm/msm_kms.h| 8 +-
drivers/gpu/drm/msm/msm_rd.c | 55 +
include/drm/drm_mipi_dsi.h | 4 -
include/linux/msm_ext_display.h | 182 -
include/uapi/drm/msm_drm.h | 78 ---
9 files changed, 47 insertions(+), 760 deletions(-)
delete mode 100644 include/linux/msm_ext_display.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 86ed8cb45cee..52f3e0667c33 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -563,12 +563,6 @@ void dpu_crtc_res_put(struct drm_crtc_state *state, u32
type, u64 tag)
_dpu_crtc_rp_put(rp, type, tag);
}
-static void _dpu_crtc_deinit_events(struct dpu_crtc *dpu_crtc)
-{
- if (!dpu_crtc)
- return;
-}
-
static void dpu_crtc_destroy(struct drm_crtc *crtc)
{
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
@@ -578,7 +572,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (!crtc)
return;
- _dpu_crtc_deinit_events(dpu_crtc);
dpu_crtc->phandle = NULL;
drm_crtc_cleanup(crtc);
@@ -842,47 +835,6 @@ static void dpu_crtc_vblank_cb(void *data)
trace_dpu_crtc_vblank_cb(DRMID(crtc));
}
-/* _dpu_crtc_idle_notify - signal idle timeout to client */
-static void _dpu_crtc_idle_notify(struct dpu_crtc *dpu_crtc)
-{
- struct drm_crtc *crtc;
- struct drm_event event;
- int ret = 0;
-
- if (!dpu_crtc) {
- DPU_ERROR("invalid dpu crtc\n");
- return;
- }
-
- crtc = _crtc->base;
- event.type = DRM_EVENT_IDLE_NOTIFY;
- event.length = sizeof(u32);
- msm_mode_object_event_notify(>base, crtc->dev, ,
- (u8 *));
-
- DPU_DEBUG("crtc:%d idle timeout notified\n", crtc->base.id);
-}
-
-/*
- * dpu_crtc_handle_event - crtc frame event handle.
- * This API must manage only non-IRQ context events.
- */
-static bool _dpu_crtc_handle_event(struct dpu_crtc *dpu_crtc, u32 event)
-{
- bool event_processed = false;
-
- /**
-* idle events are originated from commit thread and can be processed
-* in same context
-*/
- if (event & DPU_ENCODER_FRAME_EVENT_IDLE) {
- _dpu_crtc_idle_notify(dpu_crtc);
- event_processed = true;
- }
-
- return event_processed;
-}
-
static void dpu_crtc_frame_event_work(struct kthread_work *work)
{
struct msm_drm_private *priv;
@@ -977,23 +929,22 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event)
struct dpu_crtc_frame_event *fevent;
unsigned long flags;
u32 crtc_id;
- bool event_processed = false;
if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
DPU_ERROR("invalid parameters\n");
return;
}
+
+ /* Nothing to do on idle event */
+ if (event & DPU_ENCODER_FRAME_EVENT_IDLE)
+ return;
+
dpu_crtc = to_dpu_crtc(crtc);
priv = crtc->dev->dev_private;
crtc_id = drm_crtc_index(crtc);
trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
- /* try to process the event in caller context */
- event_processed = _dpu_crtc_handle_event(dpu_crtc, event);
- if (event_processed)
- return;
-
spin_lock_irqsave(_crtc->spin_lock, flags);
fevent = list_first_entry_or_null(_crtc->frame_event_list,
struct dpu_crtc_frame_event, list);
@@ -1665,8 +1616,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_display_mode *mode;
struct drm_encoder *encoder;
struct msm_drm_private *priv;
- struct drm_event event;
- u32 power_on;
int ret;
if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
@@ -1685,13 +1634,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
mutex_lock(_crtc->crtc_lock);
- /* update color processing on suspend */
- event.type = DRM_EVENT_CRTC_POWER;
- event.length = sizeof(u32);
- power_on = 0;
- msm_mode_object_event_notify(>base, crtc->dev, ,
- (u8 *)_on);
-
/* wait for frame_event_done completion */
if (_dpu_crtc_wait_for_frame_done(crtc))
DPU_ERROR("crtc%d wait for frame don
[Freedreno] [DPU PATCH 02/15] video: Remove LF copyright in mipi_display.h
It's the only change in that file, so... remove it. Signed-off-by: Sean Paul --- include/video/mipi_display.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h index c83f8a35d765..49a53ef8da96 100644 --- a/include/video/mipi_display.h +++ b/include/video/mipi_display.h @@ -4,7 +4,6 @@ * * Copyright (C) 2010 Guennadi Liakhovetski * Copyright (C) 2006 Nokia Corporation - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * Author: Imre Deak * * This program is free software; you can redistribute it and/or modify -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 00/15] drm/msm: dpu cleanup in msm
Same old thing here, more cleanup patches to reduce the amount of dpu code leaking into msm core. Most of this has already been squashed into for-next, because it should be (mostly) uncontraversial and (mostly) code removal. Sean Sean Paul (15): drm/msm: Remove more dpu changes from msm core video: Remove LF copyright in mipi_display.h drm/msm: Move dpu_dbg init/destroy into dpu_kms drm/msm: Remove more dpu-related code from msm_drv drm/msm: More cleanup in msm_drv drm/msm: Move debugfs root tracking to dpu drm/msm: Remove _dpu_format_calc_offset_linear() drm/msm: dpu: Do debugfs init in the debugfs_init() hook drm/msm: Remove get_address_space msm_kms hook drm/msm: Remove dpu_kms_fbo and associated functions drm/msm: Remove dpu module parameters drm/msm: Remove unused backpointers from dpu_crtc drm/msm: Reduce dpu_crtc_atomic_check frame size drm/msm: Remove atomic_check() from msm_kms drm/msm: Remove wait_for_tx_complete() from msm_kms drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 86 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 4 - drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 32 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 508 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 77 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c| 13 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 4 - drivers/gpu/drm/msm/msm_atomic.c| 3 +- drivers/gpu/drm/msm/msm_drv.c | 362 ++ drivers/gpu/drm/msm/msm_drv.h | 165 +-- drivers/gpu/drm/msm/msm_fb.c| 4 +- drivers/gpu/drm/msm/msm_kms.h | 19 +- drivers/gpu/drm/msm/msm_rd.c| 55 +-- include/drm/drm_mipi_dsi.h | 4 - include/linux/msm_ext_display.h | 182 --- include/uapi/drm/msm_drm.h | 78 --- include/video/mipi_display.h| 1 - 18 files changed, 134 insertions(+), 1475 deletions(-) delete mode 100644 include/linux/msm_ext_display.h -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [DPU PATCH 09/11] drm/msm/dpu: Remove unused code and move the header
On Wed, May 30, 2018 at 10:50 AM Rajesh Yadav wrote:
>
> From: Jordan Crouse
>
> Remove unused code from dpu_io_util.c. The functions are only
> used inside of the msm driver so remove the EXPORT_SYMBOL
> tags and move the header dpu_io_util.h from include/linux.
>
> Signed-off-by: Jordan Crouse
> [rya...@codeaurora.org: rebased and removed some extra unused code]
> Signed-off-by: Rajesh Yadav
Hi Rajesh and Jordan,
I'm backporting this series for testing, and have found that the
mdss-pll driver uses both dpu_io_util and a bunch of functions/struct
members removed in this patchset. Do we anticipate having to add those
back for mdss-pll?
Sean
> ---
> drivers/gpu/drm/msm/dpu_io_util.c | 380
> +-
> drivers/gpu/drm/msm/dpu_io_util.h | 61 ++
> drivers/gpu/drm/msm/msm_drv.h | 1 -
> include/linux/dpu_io_util.h | 115
> 4 files changed, 66 insertions(+), 491 deletions(-)
> create mode 100644 drivers/gpu/drm/msm/dpu_io_util.h
> delete mode 100644 include/linux/dpu_io_util.h
>
> diff --git a/drivers/gpu/drm/msm/dpu_io_util.c
> b/drivers/gpu/drm/msm/dpu_io_util.c
> index ecc297c..f7caec3 100644
> --- a/drivers/gpu/drm/msm/dpu_io_util.c
> +++ b/drivers/gpu/drm/msm/dpu_io_util.c
> @@ -13,318 +13,9 @@
>
> #include
> #include
> -#include
> -#include
> #include
> -#include
>
> -#define MAX_I2C_CMDS 16
> -void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug)
> -{
> - u32 in_val;
> -
> - if (!io || !io->base) {
> - DEV_ERR("%pS->%s: invalid input\n",
> - __builtin_return_address(0), __func__);
> - return;
> - }
> -
> - if (offset > io->len) {
> - DEV_ERR("%pS->%s: offset out of range\n",
> - __builtin_return_address(0), __func__);
> - return;
> - }
> -
> - writel_relaxed(value, io->base + offset);
> - if (debug) {
> - in_val = readl_relaxed(io->base + offset);
> - DEV_DBG("[%08x] => %08x [%08x]\n",
> - (u32)(unsigned long)(io->base + offset),
> - value, in_val);
> - }
> -} /* dss_reg_w */
> -EXPORT_SYMBOL(dss_reg_w);
> -
> -u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug)
> -{
> - u32 value;
> -
> - if (!io || !io->base) {
> - DEV_ERR("%pS->%s: invalid input\n",
> - __builtin_return_address(0), __func__);
> - return -EINVAL;
> - }
> -
> - if (offset > io->len) {
> - DEV_ERR("%pS->%s: offset out of range\n",
> - __builtin_return_address(0), __func__);
> - return -EINVAL;
> - }
> -
> - value = readl_relaxed(io->base + offset);
> - if (debug)
> - DEV_DBG("[%08x] <= %08x\n",
> - (u32)(unsigned long)(io->base + offset), value);
> -
> - return value;
> -} /* dss_reg_r */
> -EXPORT_SYMBOL(dss_reg_r);
> -
> -void dss_reg_dump(void __iomem *base, u32 length, const char *prefix,
> - u32 debug)
> -{
> - if (debug)
> - print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
> - (void *)base, length, false);
> -} /* dss_reg_dump */
> -EXPORT_SYMBOL(dss_reg_dump);
> -
> -static struct resource *msm_dss_get_res_byname(struct platform_device *pdev,
> - unsigned int type, const char *name)
> -{
> - struct resource *res = NULL;
> -
> - res = platform_get_resource_byname(pdev, type, name);
> - if (!res)
> - DEV_ERR("%s: '%s' resource not found\n", __func__, name);
> -
> - return res;
> -} /* msm_dss_get_res_byname */
> -EXPORT_SYMBOL(msm_dss_get_res_byname);
> -
> -int msm_dss_ioremap_byname(struct platform_device *pdev,
> - struct dss_io_data *io_data, const char *name)
> -{
> - struct resource *res = NULL;
> -
> - if (!pdev || !io_data) {
> - DEV_ERR("%pS->%s: invalid input\n",
> - __builtin_return_address(0), __func__);
> - return -EINVAL;
> - }
> -
> - res = msm_dss_get_res_byname(pdev, IORESOURCE_MEM, name);
> - if (!res) {
> - DEV_ERR("%pS->%s: '%s' msm_dss_get_res_byname failed\n",
> - __builtin_return_address(0), __func__, name);
> - return -ENODEV;
> - }
> -
> - io_data->len = (u32)resource_size(res);
> - io_data->base = ioremap(res->start, io_data->len);
> - if (!io_data->base) {
> - DEV_ERR("%pS->%s: '%s' ioremap failed\n",
> - __builtin_return_address(0), __func__, name);
> - return -EIO;
> - }
> -
> - return 0;
> -} /* msm_dss_ioremap_byname */
> -EXPORT_SYMBOL(msm_dss_ioremap_byname);
> -
> -void msm_dss_iounmap(struct dss_io_data *io_data)
> -{
> - if (!io_data) {
> -
[Freedreno] [DPU PATCH] drm/msm: Remove more dpu changes from msm core
This patch is removing a bunch more dpu changes that
touch msm core. I'm pretty sure the event_thread stuff can go, but
I might be wrong about that aspect.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 242 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 102 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 10 -
drivers/gpu/drm/msm/msm_atomic.c| 3 +-
drivers/gpu/drm/msm/msm_drv.c | 299 ++--
drivers/gpu/drm/msm/msm_drv.h | 158 +--
drivers/gpu/drm/msm/msm_kms.h | 8 +-
drivers/gpu/drm/msm/msm_rd.c| 55 +---
include/drm/drm_mipi_dsi.h | 4 -
include/linux/msm_ext_display.h | 182
include/uapi/drm/msm_drm.h | 78 -
11 files changed, 43 insertions(+), 1098 deletions(-)
delete mode 100644 include/linux/msm_ext_display.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 86ed8cb45cee..f54c1aceb17a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -563,12 +563,6 @@ void dpu_crtc_res_put(struct drm_crtc_state *state, u32
type, u64 tag)
_dpu_crtc_rp_put(rp, type, tag);
}
-static void _dpu_crtc_deinit_events(struct dpu_crtc *dpu_crtc)
-{
- if (!dpu_crtc)
- return;
-}
-
static void dpu_crtc_destroy(struct drm_crtc *crtc)
{
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
@@ -578,7 +572,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (!crtc)
return;
- _dpu_crtc_deinit_events(dpu_crtc);
dpu_crtc->phandle = NULL;
drm_crtc_cleanup(crtc);
@@ -842,47 +835,6 @@ static void dpu_crtc_vblank_cb(void *data)
trace_dpu_crtc_vblank_cb(DRMID(crtc));
}
-/* _dpu_crtc_idle_notify - signal idle timeout to client */
-static void _dpu_crtc_idle_notify(struct dpu_crtc *dpu_crtc)
-{
- struct drm_crtc *crtc;
- struct drm_event event;
- int ret = 0;
-
- if (!dpu_crtc) {
- DPU_ERROR("invalid dpu crtc\n");
- return;
- }
-
- crtc = _crtc->base;
- event.type = DRM_EVENT_IDLE_NOTIFY;
- event.length = sizeof(u32);
- msm_mode_object_event_notify(>base, crtc->dev, ,
- (u8 *));
-
- DPU_DEBUG("crtc:%d idle timeout notified\n", crtc->base.id);
-}
-
-/*
- * dpu_crtc_handle_event - crtc frame event handle.
- * This API must manage only non-IRQ context events.
- */
-static bool _dpu_crtc_handle_event(struct dpu_crtc *dpu_crtc, u32 event)
-{
- bool event_processed = false;
-
- /**
-* idle events are originated from commit thread and can be processed
-* in same context
-*/
- if (event & DPU_ENCODER_FRAME_EVENT_IDLE) {
- _dpu_crtc_idle_notify(dpu_crtc);
- event_processed = true;
- }
-
- return event_processed;
-}
-
static void dpu_crtc_frame_event_work(struct kthread_work *work)
{
struct msm_drm_private *priv;
@@ -960,58 +912,6 @@ static void dpu_crtc_frame_event_work(struct kthread_work
*work)
DPU_ATRACE_END("crtc_frame_event");
}
-/*
- * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module
- * registers this API to encoder for all frame event callbacks like
- * frame_error, frame_done, idle_timeout, etc. Encoder may call different
events
- * from different context - IRQ, user thread, commit_thread, etc. Each event
- * should be carefully reviewed and should be processed in proper task context
- * to avoid schedulin delay or properly manage the irq context's bottom half
- * processing.
- */
-static void dpu_crtc_frame_event_cb(void *data, u32 event)
-{
- struct drm_crtc *crtc = (struct drm_crtc *)data;
- struct dpu_crtc *dpu_crtc;
- struct msm_drm_private *priv;
- struct dpu_crtc_frame_event *fevent;
- unsigned long flags;
- u32 crtc_id;
- bool event_processed = false;
-
- if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
- DPU_ERROR("invalid parameters\n");
- return;
- }
- dpu_crtc = to_dpu_crtc(crtc);
- priv = crtc->dev->dev_private;
- crtc_id = drm_crtc_index(crtc);
-
- trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
-
- /* try to process the event in caller context */
- event_processed = _dpu_crtc_handle_event(dpu_crtc, event);
- if (event_processed)
- return;
-
- spin_lock_irqsave(_crtc->spin_lock, flags);
- fevent = list_first_entry_or_null(_crtc->frame_event_list,
- struct dpu_crtc_frame_event, list);
- if (fevent)
- list_del_init(>list);
- spin_unlock_irqrestore(_
[Freedreno] [DPU PATCH 1/2] drm/msm: dpu: Remove dpu_format_populate_layout_with_roi()
It's unused, so let's get rid of it.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 31 -
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 16 ---
2 files changed, 47 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index deaf4a33b776..12dc6a9d3b25 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -1124,37 +1124,6 @@ static void _dpu_format_calc_offset_linear(struct
dpu_hw_fmt_layout *source,
}
}
-int dpu_format_populate_layout_with_roi(
- struct msm_gem_address_space *aspace,
- struct drm_framebuffer *fb,
- struct dpu_rect *roi,
- struct dpu_hw_fmt_layout *layout)
-{
- int ret;
-
- ret = dpu_format_populate_layout(aspace, fb, layout);
- if (ret || !roi)
- return ret;
-
- if (!roi->w || !roi->h || (roi->x + roi->w > fb->width) ||
- (roi->y + roi->h > fb->height)) {
- DRM_ERROR("invalid roi=[%d,%d,%d,%d], fb=[%u,%u]\n",
- roi->x, roi->y, roi->w, roi->h,
- fb->width, fb->height);
- ret = -EINVAL;
- } else if (DPU_FORMAT_IS_LINEAR(layout->format)) {
- _dpu_format_calc_offset_linear(layout, roi->x, roi->y);
- layout->width = roi->w;
- layout->height = roi->h;
- } else if (roi->x || roi->y || (roi->w != fb->width) ||
- (roi->h != fb->height)) {
- DRM_ERROR("non-linear layout with roi not supported\n");
- ret = -EINVAL;
- }
-
- return ret;
-}
-
int dpu_format_check_modified_format(
const struct msm_kms *kms,
const struct msm_format *msm_fmt,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
index 6aa91de93cac..b55bfd13e296 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
@@ -115,22 +115,6 @@ int dpu_format_populate_layout(
struct drm_framebuffer *fb,
struct dpu_hw_fmt_layout *fmtl);
-/**
- * dpu_format_populate_layout_with_roi - populate the given format layout
- * based on mmu, fb, roi, and format found in the fb
- * @aspace:address space pointer
- * @fb:framebuffer pointer
- * @roi: region of interest (optional)
- * @fmtl: format layout structure to populate
- *
- * Return: error code on failure, 0 on success
- */
-int dpu_format_populate_layout_with_roi(
- struct msm_gem_address_space *aspace,
- struct drm_framebuffer *fb,
- struct dpu_rect *roi,
- struct dpu_hw_fmt_layout *fmtl);
-
/**
* dpu_format_get_framebuffer_size - get framebuffer memory size
* @format:DRM pixel format
--
Sean Paul, Software Engineer, Google / Chromium OS
___
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[Freedreno] [DPU PATCH 2/2] drm/msm: dpu: Remove dpu_rect
Well, that was a lot stickier than I thought it would be! This patch
removes dpu_rect and its helpers in favor of drm_rect and its helpers.
Signed-off-by: Sean Paul
---
Based on my tracepoints set.
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 86
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 7 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 54 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c | 25 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 185 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +-
9 files changed, 160 insertions(+), 223 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index eefc1892ad47..86ed8cb45cee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include "dpu_kms.h"
#include "dpu_hw_lm.h"
@@ -607,15 +608,15 @@ static void _dpu_crtc_program_lm_output_roi(struct
drm_crtc *crtc)
lm_horiz_position = 0;
for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
- const struct dpu_rect *lm_roi = _state->lm_bounds[lm_idx];
+ const struct drm_rect *lm_roi = _state->lm_bounds[lm_idx];
struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm;
struct dpu_hw_mixer_cfg cfg;
- if (dpu_kms_rect_is_null(lm_roi))
+ if (!lm_roi || !drm_rect_visible(lm_roi))
continue;
- cfg.out_width = lm_roi->w;
- cfg.out_height = lm_roi->h;
+ cfg.out_width = drm_rect_width(lm_roi);
+ cfg.out_height = drm_rect_height(lm_roi);
cfg.right_mixer = lm_horiz_position++;
cfg.flags = 0;
hw_lm->ops.setup_mixer_out(hw_lm, );
@@ -634,7 +635,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
struct dpu_hw_ctl *ctl;
struct dpu_hw_mixer *lm;
struct dpu_hw_stage_cfg *stage_cfg;
- struct dpu_rect plane_crtc_roi;
u32 flush_mask;
uint32_t stage_idx, lm_idx;
@@ -656,11 +656,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
if (!state)
continue;
- plane_crtc_roi.x = state->crtc_x;
- plane_crtc_roi.y = state->crtc_y;
- plane_crtc_roi.w = state->crtc_w;
- plane_crtc_roi.h = state->crtc_h;
-
pstate = to_dpu_plane_state(state);
fb = state->fb;
@@ -1119,13 +1114,13 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc
*crtc,
crtc_split_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, adj_mode);
for (i = 0; i < dpu_crtc->num_mixers; i++) {
- cstate->lm_bounds[i].x = crtc_split_width * i;
- cstate->lm_bounds[i].y = 0;
- cstate->lm_bounds[i].w = crtc_split_width;
- cstate->lm_bounds[i].h =
- dpu_crtc_get_mixer_height(dpu_crtc, cstate, adj_mode);
- trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i,
- >lm_bounds[i]);
+ struct drm_rect *r = >lm_bounds[i];
+ r->x1 = crtc_split_width * i;
+ r->y1 = 0;
+ r->x2 = r->x1 + crtc_split_width;
+ r->y2 = dpu_crtc_get_mixer_height(dpu_crtc, cstate, adj_mode);
+
+ trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
}
drm_mode_debug_printmodeline(adj_mode);
@@ -1822,6 +1817,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
int multirect_count = 0;
const struct drm_plane_state *pipe_staged[SSPP_MAX];
int left_zpos_cnt = 0, right_zpos_cnt = 0;
+ struct drm_rect crtc_rect = { 0 };
if (!crtc) {
DPU_ERROR("invalid crtc\n");
@@ -1850,8 +1846,13 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
_dpu_crtc_setup_lm_bounds(crtc, state);
+ crtc_rect.x2 = mode->hdisplay;
+ crtc_rect.y2 = mode->vdisplay;
+
/* get plane state for all drm planes associated with crtc state */
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
+ struct drm_rect dst, clip = crtc_rect;
+
if (IS_ERR_OR_NULL(pstate)) {
rc = PTR_ERR(pstate);
DPU_ERROR("%s: failed to get plane%d state, %d\n",
@@ -1879,14 +1880,13 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
cn
[Freedreno] [DPU PATCH 17/19] drm/msm: dpu: Remove dsi debug block name
Leftover from dsi-staging, it looks like.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/dpu_dbg.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 2a9b8c732e33..51d46975cc27 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -130,7 +130,6 @@ struct dpu_dbg_vbif_debug_bus {
* @dump_work: work struct for deferring register dump work to separate thread
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
- * @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
struct list_head reg_base_list;
@@ -140,7 +139,6 @@ static struct dpu_dbg_base {
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
- bool dsi_dbg_bus;
} dpu_dbg_base;
static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base,
@@ -2270,9 +2268,6 @@ void dpu_dbg_dump(bool queue_work, const char *name, ...)
if (!strcmp(blk_name, "vbif_dbg_bus"))
dump_dbgbus_vbif_rt = true;
-
- if (!strcmp(blk_name, "dsi_dbg_bus"))
- dpu_dbg_base.dsi_dbg_bus = true;
}
va_end(args);
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 19/19] drm/msm: dpu: Move dpu_dbg into dpu1 directory
Now that dpu_dbg is cleaned up, move it into dpu directory with the
rest of dpu things.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c | 0
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.h | 0
3 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c (100%)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.h (100%)
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 9c182a9dab2b..1745447922bf 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -49,6 +49,7 @@ msm-y := \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
+ disp/dpu1/dpu_dbg.o \
disp/dpu1/dpu_encoder.o \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
@@ -74,7 +75,6 @@ msm-y := \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_mdss.o \
disp/dpu1/dpu_power_handle.o \
- dpu_dbg.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
similarity index 100%
rename from drivers/gpu/drm/msm/dpu_dbg.c
rename to drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
diff --git a/drivers/gpu/drm/msm/dpu_dbg.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
similarity index 100%
rename from drivers/gpu/drm/msm/dpu_dbg.h
rename to drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
--
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[Freedreno] [DPU PATCH 15/19] drm/msm: dpu: Remove arbitrary register dumps
This can be achieved via /dev/mem. Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c| 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 - .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 3 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 - drivers/gpu/drm/msm/dpu_dbg.c | 716 +- drivers/gpu/drm/msm/dpu_dbg.h | 59 -- 10 files changed, 7 insertions(+), 822 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c index 24b0dbc76f3a..da6f0609be5f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c @@ -301,9 +301,6 @@ struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - /* * Perform any default initialization for the chroma down module * @setup default csc coefficients diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index ad02316fafce..06be7cf7ce50 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -524,9 +524,6 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 7386d4643115..d280df5613c9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -332,9 +332,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 5b4d529a1a89..4ab72b0f07a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -245,9 +245,6 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 12e90b8e5466..cc3a623903f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -234,9 +234,6 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, goto blk_init_error; } - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off, - c->hw.blk_off + c->hw.length, c->hw.xin_id); - return c; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 6640906e4f03..2b3f5e88af98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -734,20 +734,6 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, goto blk_init_error; } - if (!is_virtual_pipe) - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, - hw_pipe->hw.blk_off, - hw_pipe->hw.blk_off + hw_pipe->hw.length, - hw_pipe->hw.xin_id); - - if (cfg->sblk->scaler_blk.len && !is_virtual_pipe) - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, - cfg->sblk->scaler_blk.name, - hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base, - hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base + - cfg->sblk->scaler_blk.len, - hw_pipe->hw.xin_id); - return hw_pipe; blk_init_error: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 115eeedd90e8..42fc72cf48dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1
[Freedreno] [DPU PATCH 10/19] drm/msm: dpu_core_irq: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_core_irq with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 52
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 50 +++
2 files changed, 71 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 33ab2ac46833..530c24dec017 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -18,6 +18,7 @@
#include
#include "dpu_core_irq.h"
+#include "dpu_trace.h"
/**
* dpu_core_irq_callback_handler - dispatch core interrupts
@@ -34,10 +35,8 @@ static void dpu_core_irq_callback_handler(void *arg, int
irq_idx)
pr_debug("irq_idx=%d\n", irq_idx);
if (list_empty(_obj->irq_cb_tbl[irq_idx])) {
- DPU_ERROR("irq_idx=%d has no registered callback\n", irq_idx);
- DPU_EVT32_IRQ(irq_idx, atomic_read(
- _kms->irq_obj.enable_counts[irq_idx]),
- DPU_EVTLOG_ERROR);
+ DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,
+ atomic_read(_kms->irq_obj.enable_counts[irq_idx]));
}
atomic_inc(_obj->irq_counts[irq_idx]);
@@ -80,7 +79,7 @@ int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
{
unsigned long irq_flags;
- int ret = 0;
+ int ret = 0, enable_count;
if (!dpu_kms || !dpu_kms->hw_intr ||
!dpu_kms->irq_obj.enable_counts ||
@@ -94,11 +93,10 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms,
int irq_idx)
return -EINVAL;
}
- DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
- atomic_read(_kms->irq_obj.enable_counts[irq_idx]));
+ enable_count = atomic_read(_kms->irq_obj.enable_counts[irq_idx]);
+ DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
+ trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
- DPU_EVT32(irq_idx,
- atomic_read(_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_inc_return(_kms->irq_obj.enable_counts[irq_idx]) == 1) {
ret = dpu_kms->hw_intr->ops.enable_irq(
dpu_kms->hw_intr,
@@ -130,11 +128,8 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int
*irq_idxs, u32 irq_count)
}
counts = atomic_read(_kms->irq_obj.enable_counts[irq_idxs[0]]);
- if (counts) {
- DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n",
- __builtin_return_address(0), irq_idxs[0], counts);
- DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR);
- }
+ if (counts)
+ DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
for (i = 0; (i < irq_count) && !ret; i++)
ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
@@ -149,7 +144,7 @@ int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int
*irq_idxs, u32 irq_count)
*/
static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
{
- int ret = 0;
+ int ret = 0, enable_count;
if (!dpu_kms || !dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
DPU_ERROR("invalid params\n");
@@ -161,11 +156,10 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms,
int irq_idx)
return -EINVAL;
}
- DPU_DEBUG("irq_idx=%d enable_count=%d\n", irq_idx,
- atomic_read(_kms->irq_obj.enable_counts[irq_idx]));
+ enable_count = atomic_read(_kms->irq_obj.enable_counts[irq_idx]);
+ DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
+ trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
- DPU_EVT32(irq_idx,
- atomic_read(_kms->irq_obj.enable_counts[irq_idx]));
if (atomic_dec_return(_kms->irq_obj.enable_counts[irq_idx]) == 0) {
ret = dpu_kms->hw_intr->ops.disable_irq(
dpu_kms->hw_intr,
@@ -189,11 +183,8 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int
*irq_idxs, u32 irq_count)
}
counts = atomic_read(_kms->irq_obj.enable_counts[irq_idxs[0]]);
- if (counts == 2) {
- DPU_ERROR("%pS: irq_idx=%d enable_count=%d\n",
- __builtin_return_address(0), irq_idxs[0], counts);
- DPU_EVT32(irq_idxs[0], counts, DPU_EVTLOG_ERROR);
- }
+ if (counts == 2)
+ DRM_ERROR("irq_idx=%d enable_count=%d\
[Freedreno] [DPU PATCH 00/19] drm/msm: dpu: Clean up dpu_dbg
Well hello,
This patchset attempts to clean up some of dpu_dbg that was duplicating
functionality already upstream. The majority of the set is replacing
all instances of DPU_EVT* functions with proper tracepoints instead of
the obfuscated ones that exist now. The second part of the set disects
dpu_dbg.[ch] a bit and removes the arbitrary register reads, and evtlog
duplication. Finally, the dpu_dbg files are moved into the dpu1
directory.
Sean
Sean Paul (19):
drm/msm: dpu_encoder: Replace DPU_EVT with tracepoints
drm/msm: dpu_crtc: Replace DPU_EVT with tracepoints
drm/msm: dpu_plane: Replace DPU_EVT with tracepoints
drm/msm: dpu_rm: Replace DPU_EVT with tracepoints
drm/msm: dpu_kms: Replace DPU_EVT with tracepoints
drm/msm: dpu_encoder_phys_cmd: Replace DPU_EVT with tracepoints
drm/msm: dpu_encoder_phys_vid: Replace DPU_EVT with tracepoints
drm/msm: dpu_vbif: Replace DPU_EVT with tracepoints
drm/msm: dpu_pingpong: Replace DPU_EVT with tracepoints
drm/msm: dpu_core_irq: Replace DPU_EVT with tracepoints
drm/msm: dpu_core_perf: Replace DPU_EVT with tracepoints
drm/msm: dpu_mdss: Replace DPU_EVT with DRM_ERROR
drm/msm: dpu: Remove dpu evtlog
drm/msm: dpu_dbg: Remove dump_all option for dumping registers
drm/msm: dpu: Remove arbitrary register dumps
drm/msm: dpu: Remove panic from dpu debug dump
drm/msm: dpu: Remove dsi debug block name
drm/msm: dpu_dbg: Remove string parsing from DBG_DUMP
drm/msm: dpu: Move dpu_dbg into dpu1 directory
drivers/gpu/drm/msm/Makefile | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 52 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 122 +--
drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c | 944 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 116 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 292 +++---
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 81 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 38 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 -
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 14 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 3 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 46 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 5 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 19 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 65 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 836 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 7 +-
drivers/gpu/drm/msm/dpu_dbg.h | 406
drivers/gpu/drm/msm/dpu_dbg_evtlog.c | 306 --
24 files changed, 1251 insertions(+), 2124 deletions(-)
rename drivers/gpu/drm/msm/{ => disp/dpu1}/dpu_dbg.c (70%)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
delete mode 100644 drivers/gpu/drm/msm/dpu_dbg.h
delete mode 100644 drivers/gpu/drm/msm/dpu_dbg_evtlog.c
--
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[Freedreno] [DPU PATCH 02/19] drm/msm: dpu_crtc: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_crtc with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 122 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 166 ++
2 files changed, 210 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9ca8325877a1..eefc1892ad47 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -431,18 +431,12 @@ static void *_dpu_crtc_rp_get(struct dpu_crtc_respool
*rp, u32 type, u64 tag)
list_for_each_entry(res, _rp->res_list, list) {
if (res->type != type)
continue;
- DPU_DEBUG(
- "crtc%d.%u found res:0x%x//%pK/ in
crtc%d.%d\n",
- crtc->base.id,
- rp->sequence_id,
- res->type, res->val,
- crtc->base.id,
- old_rp->sequence_id);
- DPU_EVT32_VERBOSE(crtc->base.id,
- rp->sequence_id,
- res->type, res->val,
- crtc->base.id,
- old_rp->sequence_id);
+ DRM_DEBUG_KMS("crtc%d.%u found res:0x%x//%pK/ "
+ "in crtc%d.%d\n",
+ crtc->base.id, rp->sequence_id,
+ res->type, res->val,
+ crtc->base.id,
+ old_rp->sequence_id);
if (res->ops.get)
res->ops.get(res->val, 0, -1);
val = res->val;
@@ -688,23 +682,17 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
- DPU_EVT32(DRMID(crtc), DRMID(plane),
- state->fb ? state->fb->base.id : -1,
- state->src_x >> 16, state->src_y >> 16,
- state->src_w >> 16, state->src_h >> 16,
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h);
-
stage_idx = zpos_cnt[pstate->stage]++;
stage_cfg->stage[pstate->stage][stage_idx] =
dpu_plane_pipe(plane);
stage_cfg->multirect_index[pstate->stage][stage_idx] =
pstate->multirect_index;
- DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
- dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- pstate->multirect_index, pstate->multirect_mode,
- format->base.pixel_format, fb ? fb->modifier : 0);
+ trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
+ state, pstate, stage_idx,
+ dpu_plane_pipe(plane) - SSPP_VIG0,
+ format->base.pixel_format,
+ fb ? fb->modifier : 0);
/* blend config update */
for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
@@ -821,7 +809,7 @@ static void _dpu_crtc_complete_flip(struct drm_crtc *crtc,
dpu_crtc->event = NULL;
DRM_DEBUG_VBL("%s: send event: %pK\n",
dpu_crtc->name, event);
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_crtc_complete_flip(DRMID(crtc));
drm_crtc_send_vblank_event(crtc, event);
}
}
@@ -856,8 +844,7 @@ static void dpu_crtc_vblank_cb(void *data)
dpu_crtc->vblank_cb_count++;
_dpu_crtc_complete_flip(crtc, NULL);
drm_crtc_handle_vblank(crtc);
- DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_crtc_vblank_cb(DRMID(crtc));
}
/* _dpu_crtc_idle_notify - signa
[Freedreno] [DPU PATCH 11/19] drm/msm: dpu_core_perf: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_core_perf with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 17 +
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 6c0f66cc177f..1019ce7594ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -474,7 +474,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
if (update_clk) {
clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
- DPU_EVT32(kms->dev, stop_req, clk_rate);
+ trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate);
ret = _dpu_core_perf_set_core_clk_rate(kms, clk_rate);
if (ret) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index ee41db86a2e9..d6f117bdad24 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -1016,6 +1016,23 @@ DEFINE_EVENT(dpu_core_irq_callback_template,
dpu_core_irq_unregister_callback,
TP_ARGS(irq_idx, callback)
);
+TRACE_EVENT(dpu_core_perf_update_clk,
+ TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
+ TP_ARGS(dev, stop_req, clk_rate),
+ TP_STRUCT__entry(
+ __field(struct drm_device *,dev )
+ __field(bool, stop_req)
+ __field(u64,clk_rate)
+ ),
+ TP_fast_assign(
+ __entry->dev = dev;
+ __entry->stop_req = stop_req;
+ __entry->clk_rate = clk_rate;
+ ),
+ TP_printk("dev:%s stop_req:%s clk_rate:%llu", __entry->dev->unique,
+ __entry->stop_req ? "true" : "false", __entry->clk_rate)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 03/19] drm/msm: dpu_plane: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_plane with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 19 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 44 +++
2 files changed, 49 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 6090ace6012a..2c3dc00477b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -609,18 +609,9 @@ static inline void _dpu_plane_set_scanout(struct drm_plane
*plane,
else if (ret)
DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
else if (pdpu->pipe_hw->ops.setup_sourceaddress) {
- DPU_EVT32_VERBOSE(pdpu->pipe_hw->idx,
- pipe_cfg->layout.width,
- pipe_cfg->layout.height,
- pipe_cfg->layout.plane_addr[0],
- pipe_cfg->layout.plane_size[0],
- pipe_cfg->layout.plane_addr[1],
- pipe_cfg->layout.plane_size[1],
- pipe_cfg->layout.plane_addr[2],
- pipe_cfg->layout.plane_size[2],
- pipe_cfg->layout.plane_addr[3],
- pipe_cfg->layout.plane_size[3],
- pstate->multirect_index);
+ trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx,
+ _cfg->layout,
+ pstate->multirect_index);
pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg,
pstate->multirect_index);
}
@@ -1420,8 +1411,8 @@ static void _dpu_plane_atomic_disable(struct drm_plane
*plane,
state = plane->state;
pstate = to_dpu_plane_state(state);
- DPU_EVT32(DRMID(plane), is_dpu_plane_virtual(plane),
- pstate->multirect_mode);
+ trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane),
+ pstate->multirect_mode);
pstate->pending = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 877621184782..5d3aa5a994be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -725,6 +725,50 @@ TRACE_EVENT(dpu_crtc_disable_frame_pending,
__entry->frame_pending)
);
+TRACE_EVENT(dpu_plane_set_scanout,
+ TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
+enum dpu_sspp_multirect_index multirect_index),
+ TP_ARGS(index, layout, multirect_index),
+ TP_STRUCT__entry(
+ __field(enum dpu_sspp, index )
+ __field(struct dpu_hw_fmt_layout*, layout )
+ __field(enum dpu_sspp_multirect_index, multirect_index)
+ ),
+ TP_fast_assign(
+ __entry->index = index;
+ __entry->layout = layout;
+ __entry->multirect_index = multirect_index;
+ ),
+ TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
+ "multirect_index:%d", __entry->index, __entry->layout->width,
+ __entry->layout->height, __entry->layout->plane_addr[0],
+ __entry->layout->plane_size[0],
+ __entry->layout->plane_addr[1],
+ __entry->layout->plane_size[1],
+ __entry->layout->plane_addr[2],
+ __entry->layout->plane_size[2],
+ __entry->layout->plane_addr[3],
+ __entry->layout->plane_size[3], __entry->multirect_index)
+);
+
+TRACE_EVENT(dpu_plane_disable,
+ TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
+ TP_ARGS(drm_id, is_virtual, multirect_mode),
+ TP_STRUCT__entry(
+ __field(uint32_t, drm_id )
+ __field(bool, is_virtual )
+ __field(uint32_t, multirect_mode )
+ ),
+ TP_fast_assign(
+ __entry->drm_id = drm_id;
+ __entry->is_virtual = is_virtual;
+ __entry->multirect_mode = multirect_mode;
+ ),
+ TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
+ __entry->is_virtual ? "true" : "false",
+ __entry->multirect_mode)
+);
+
#define
[Freedreno] [DPU PATCH 07/19] drm/msm: dpu_encoder_phys_vid: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_encoder_phys_vid with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 36 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 35 ++
2 files changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 73e59382eeac..fc83745b48fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -458,12 +458,8 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
goto end;
}
- DPU_DEBUG_VIDENC(vid_enc, "[%pS] enable=%d/%d\n",
- __builtin_return_address(0),
- enable, atomic_read(_enc->vblank_refcount));
-
- DPU_EVT32(DRMID(phys_enc->parent), enable,
- atomic_read(_enc->vblank_refcount));
+ DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
+ atomic_read(_enc->vblank_refcount));
if (enable && atomic_inc_return(_enc->vblank_refcount) == 1)
ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
@@ -473,12 +469,10 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
end:
if (ret) {
- DPU_ERROR_VIDENC(vid_enc,
- "control vblank irq error %d, enable %d\n",
- ret, enable);
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0,
- enable, refcount, DPU_EVTLOG_ERROR);
+ DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n",
+ DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0, ret, enable,
+ refcount);
}
return ret;
}
@@ -697,11 +691,9 @@ static void dpu_encoder_phys_vid_disable(struct
dpu_encoder_phys *phys_enc)
ret = _dpu_encoder_phys_vid_wait_for_vblank(phys_enc, false);
if (ret) {
atomic_set(_enc->pending_kickoff_cnt, 0);
- DPU_ERROR_VIDENC(vid_enc,
- "failure waiting for disable: %d\n",
- ret);
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0, ret);
+ DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
+ DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0, ret);
}
}
@@ -727,8 +719,8 @@ static void dpu_encoder_phys_vid_handle_post_kickoff(
* Video encoders need to turn on their interfaces now
*/
if (phys_enc->enable_state == DPU_ENC_ENABLING) {
- DPU_EVT32(DRMID(phys_enc->parent),
- vid_enc->hw_intf->idx - INTF_0);
+ trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0);
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
vid_enc->hw_intf->ops.enable_timing(vid_enc->hw_intf, 1);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
@@ -747,8 +739,10 @@ static void dpu_encoder_phys_vid_irq_control(struct
dpu_encoder_phys *phys_enc,
vid_enc = to_dpu_encoder_phys_vid(phys_enc);
- DPU_EVT32(DRMID(phys_enc->parent), vid_enc->hw_intf->idx - INTF_0,
- enable, atomic_read(_enc->vblank_refcount));
+ trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent),
+ vid_enc->hw_intf->idx - INTF_0,
+ enable,
+ atomic_read(_enc->vblank_refcount));
if (enable) {
ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index a6313c4343c8..c9041e2a7aa1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -672,6 +672,41 @@ TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
__entry->kickoff_count, __entry->event)
);
+TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
+ TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
+ TP_ARGS(drm_id, intf_idx),
+ TP_STRUCT__entry(
+ __field(uint32_t, drm_id )
+
[Freedreno] [DPU PATCH 08/19] drm/msm: dpu_vbif: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_vbif with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 15 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 7 +++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index c9041e2a7aa1..73f76387803f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -20,6 +20,7 @@
#include "dpu_crtc.h"
#include "dpu_encoder_phys.h"
#include "dpu_hw_mdss.h"
+#include "dpu_hw_vbif.h"
#include "dpu_plane.h"
#undef TRACE_SYSTEM
@@ -937,6 +938,20 @@ TRACE_EVENT(dpu_rm_reserve_lms,
__entry->type, __entry->enc_id, __entry->pp_id)
);
+TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
+ TP_PROTO(enum dpu_vbif index, u32 xin_id),
+ TP_ARGS(index, xin_id),
+ TP_STRUCT__entry(
+ __field(enum dpu_vbif, index )
+ __field(u32,xin_id )
+ ),
+ TP_fast_assign(
+ __entry->index = index;
+ __entry->xin_id = xin_id;
+ ),
+ TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
index 801155fe0989..295528292296 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
@@ -204,7 +204,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,
ret = _dpu_vbif_wait_for_xin_halt(vbif, params->xin_id);
if (ret)
- DPU_EVT32(vbif->idx, params->xin_id);
+ trace_dpu_vbif_wait_xin_halt_fail(vbif->idx, params->xin_id);
vbif->ops.set_halt_ctrl(vbif, params->xin_id, false);
@@ -284,9 +284,8 @@ void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms)
if (vbif && vbif->ops.clear_errors) {
vbif->ops.clear_errors(vbif, , );
if (pnd || src) {
- DPU_EVT32(i, pnd, src);
- DPU_DEBUG("VBIF %d: pnd 0x%X, src 0x%X\n",
- vbif->idx - VBIF_0, pnd, src);
+ DRM_DEBUG_KMS("VBIF %d: pnd 0x%X, src 0x%X\n",
+ vbif->idx - VBIF_0, pnd, src);
}
}
}
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 12/19] drm/msm: dpu_mdss: Replace DPU_EVT with DRM_ERROR
The events are only issued in error cases, so use DRM_ERROR instead.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 04accdf483c0..5c69c2cc5d10 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -33,13 +33,14 @@ static irqreturn_t dpu_mdss_irq(int irq, void *arg)
mapping = irq_find_mapping(dpu_mdss->irq_controller.domain,
hwirq);
if (mapping == 0) {
- DPU_EVT32(hwirq, DPU_EVTLOG_ERROR);
+ DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
return IRQ_NONE;
}
rc = generic_handle_irq(mapping);
if (rc < 0) {
- DPU_EVT32(hwirq, mapping, rc, DPU_EVTLOG_ERROR);
+ DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
+ hwirq, mapping, rc);
return IRQ_NONE;
}
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [DPU PATCH 04/19] drm/msm: dpu_rm: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_rm with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 65 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 49 +
2 files changed, 78 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index eff316bb2134..13c0a36d4ef9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -20,6 +20,7 @@
#include "dpu_hw_pingpong.h"
#include "dpu_hw_intf.h"
#include "dpu_encoder.h"
+#include "dpu_trace.h"
#define RESERVED_BY_OTHER(h, r) \
((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
@@ -121,9 +122,8 @@ static void _dpu_rm_print_rsvps(
DPU_DEBUG("%d\n", stage);
list_for_each_entry(rsvp, >rsvps, list) {
- DPU_DEBUG("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
- rsvp->enc_id, rsvp->topology);
- DPU_EVT32(stage, rsvp->seq, rsvp->enc_id, rsvp->topology);
+ DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
+ rsvp->enc_id, rsvp->topology);
}
for (type = 0; type < DPU_HW_BLK_MAX; type++) {
@@ -131,14 +131,7 @@ static void _dpu_rm_print_rsvps(
if (!blk->rsvp && !blk->rsvp_nxt)
continue;
- DPU_DEBUG("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
- (blk->rsvp) ? blk->rsvp->seq : 0,
- (blk->rsvp) ? blk->rsvp->enc_id : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
- (blk->rsvp_nxt) ? blk->rsvp_nxt->enc_id : 0,
- blk->type, blk->id);
-
- DPU_EVT32(stage,
+ DRM_DEBUG_KMS("%d rsvp[s%ue%u->s%ue%u] %d %d\n", stage,
(blk->rsvp) ? blk->rsvp->seq : 0,
(blk->rsvp) ? blk->rsvp->enc_id : 0,
(blk->rsvp_nxt) ? blk->rsvp_nxt->seq : 0,
@@ -597,7 +590,8 @@ static int _dpu_rm_reserve_lms(
lm[i]->rsvp_nxt = rsvp;
pp[i]->rsvp_nxt = rsvp;
- DPU_EVT32(lm[i]->type, rsvp->enc_id, lm[i]->id, pp[i]->id);
+ trace_dpu_rm_reserve_lms(lm[i]->id, lm[i]->type, rsvp->enc_id,
+pp[i]->id);
}
return rc;
@@ -642,7 +636,8 @@ static int _dpu_rm_reserve_ctls(
for (i = 0; i < ARRAY_SIZE(ctls) && i < top->num_ctl; i++) {
ctls[i]->rsvp_nxt = rsvp;
- DPU_EVT32(ctls[i]->type, rsvp->enc_id, ctls[i]->id);
+ trace_dpu_rm_reserve_ctls(ctls[i]->id, ctls[i]->type,
+ rsvp->enc_id);
}
return 0;
@@ -656,6 +651,8 @@ static int _dpu_rm_reserve_cdm(
{
struct dpu_rm_hw_iter iter;
+ DRM_DEBUG_KMS("type %d id %d\n", type, id);
+
dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_CDM);
while (_dpu_rm_get_hw_locked(rm, )) {
const struct dpu_hw_cdm *cdm = to_dpu_hw_cdm(iter.blk->hw);
@@ -668,14 +665,16 @@ static int _dpu_rm_reserve_cdm(
if (type == DPU_HW_BLK_INTF && id != INTF_MAX)
match = test_bit(id, >intf_connect);
- DPU_DEBUG("type %d id %d, cdm intfs %lu match %d\n",
- type, id, caps->intf_connect, match);
+ DRM_DEBUG_KMS("iter: type:%d id:%d enc:%d cdm:%lu match:%d\n",
+ iter.blk->type, iter.blk->id, rsvp->enc_id,
+ caps->intf_connect, match);
if (!match)
continue;
+ trace_dpu_rm_reserve_cdm(iter.blk->id, iter.blk->type,
+rsvp->enc_id);
iter.blk->rsvp_nxt = rsvp;
- DPU_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
break;
}
@@ -709,7 +708,8 @@ static int _dpu_rm_reserve_intf(
}
iter.blk->rsvp_nxt = rsvp;
- DPU_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
+ trace_dpu_rm_reserve_intf(iter.blk->id, iter.blk->type,
+ rsvp->enc_id);
break;
}
@@ -801,7 +801,6 @@ static int _dpu_rm_populate_requir
[Freedreno] [DPU PATCH 13/19] drm/msm: dpu: Remove dpu evtlog
Now that everything has been converted to tracepoints, remove the dpu
evtlog.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 33 ---
drivers/gpu/drm/msm/dpu_dbg.c | 147 +--
drivers/gpu/drm/msm/dpu_dbg.h | 224 +---
drivers/gpu/drm/msm/dpu_dbg_evtlog.c | 306 --
6 files changed, 11 insertions(+), 705 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dpu_dbg_evtlog.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index dc56904367d8..9c182a9dab2b 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -75,7 +75,6 @@ msm-y := \
disp/dpu1/dpu_mdss.o \
disp/dpu1/dpu_power_handle.o \
dpu_dbg.o \
- dpu_dbg_evtlog.o \
msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 6ae5bba21074..4fd5e1d7261e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -43,11 +43,6 @@ static const char * const iommu_ports[] = {
"mdp_0",
};
-/**
- * Controls size of event log buffer. Specified as a power of 2.
- */
-#define DPU_EVTLOG_SIZE1024
-
/*
* To enable overall DRM driver logging
* # echo 0x2 > /sys/module/drm/parameters/debug
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index d6f117bdad24..41fd6a227d8b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -165,39 +165,6 @@ TRACE_EVENT(dpu_trace_counter,
__get_str(counter_name), __entry->value)
)
-#define DPU_TRACE_EVTLOG_SIZE 15
-TRACE_EVENT(dpu_evtlog,
- TP_PROTO(const char *tag, u32 tag_id, u32 cnt, u32 data[]),
- TP_ARGS(tag, tag_id, cnt, data),
- TP_STRUCT__entry(
- __field(int, pid)
- __string(evtlog_tag, tag)
- __field(u32, tag_id)
- __array(u32, data, DPU_TRACE_EVTLOG_SIZE)
- ),
- TP_fast_assign(
- __entry->pid = current->tgid;
- __assign_str(evtlog_tag, tag);
- __entry->tag_id = tag_id;
- if (cnt > DPU_TRACE_EVTLOG_SIZE)
- cnt = DPU_TRACE_EVTLOG_SIZE;
- memcpy(__entry->data, data, cnt * sizeof(u32));
- memset(&__entry->data[cnt], 0,
- (DPU_TRACE_EVTLOG_SIZE - cnt) * sizeof(u32));
- ),
- TP_printk("%d|%s:%d|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x|%x",
- __entry->pid, __get_str(evtlog_tag),
- __entry->tag_id,
- __entry->data[0], __entry->data[1],
- __entry->data[2], __entry->data[3],
- __entry->data[4], __entry->data[5],
- __entry->data[6], __entry->data[7],
- __entry->data[8], __entry->data[9],
- __entry->data[10], __entry->data[11],
- __entry->data[12], __entry->data[13],
- __entry->data[14])
-)
-
TRACE_EVENT(dpu_perf_crtc_update,
TP_PROTO(u32 crtc, u64 bw_ctl_mnoc, u64 bw_ctl_llcc,
u64 bw_ctl_ebi, u32 core_clk_rate,
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 27538bc6c290..9495a0f17f1b 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -165,7 +165,6 @@ struct dpu_dbg_vbif_debug_bus {
/**
* struct dpu_dbg_base - global dpu debug base structure
- * @evtlog: event log instance
* @reg_base_list: list of register dumping regions
* @dev: device pointer
* @req_dump_blks: list of blocks requested for dumping
@@ -179,7 +178,6 @@ struct dpu_dbg_vbif_debug_bus {
* @dsi_dbg_bus: dump dsi debug bus register
*/
static struct dpu_dbg_base {
- struct dpu_dbg_evtlog *evtlog;
struct list_head reg_base_list;
struct device *dev;
@@ -196,9 +194,6 @@ static struct dpu_dbg_base {
bool dsi_dbg_bus;
} dpu_dbg_base;
-/* dpu_dbg_base_evtlog - global pointer to main dpu event log for macro use */
-struct dpu_dbg_evtlog *dpu_dbg_base_evtlog;
-
static void _dpu_debug_bus_xbar_dump(void __iomem *mem_base,
struct dpu_debug_bus_entry *entry, u32 val)
{
@@ -2526,8 +2521,6 @@ static void _dpu_dump_array(struct dpu_dbg_reg_base
*blk_arr[],
{
int i;
- dpu_evtlog_dump_all(dpu_dbg_base.evtlog);
-
if (dump_all || !blk_arr || !len) {
_dpu_dump_re
[Freedreno] [DPU PATCH 05/19] drm/msm: dpu_kms: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_kms with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 16
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fe614c06bb7b..6ae5bba21074 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -362,7 +362,7 @@ static void dpu_kms_wait_for_frame_transfer_complete(struct
msm_kms *kms,
* Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
* complete
*/
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_kms_wait_for_frame_transfer(DRMID(crtc));
ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
if (ret && ret != -EWOULDBLOCK) {
DPU_ERROR(
@@ -410,7 +410,7 @@ void dpu_kms_encoder_enable(struct drm_encoder *encoder)
funcs->commit(encoder);
if (crtc && crtc->state->active) {
- DPU_EVT32(DRMID(crtc));
+ trace_dpu_kms_enc_enable(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
}
}
@@ -427,7 +427,7 @@ static void dpu_kms_commit(struct msm_kms *kms, struct
drm_atomic_state *state)
continue;
if (crtc->state->active) {
- DPU_EVT32(DRMID(crtc));
+ trace_dpu_kms_commit(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
}
}
@@ -450,12 +450,14 @@ static void dpu_kms_complete_commit(struct msm_kms *kms,
return;
priv = dpu_kms->dev->dev_private;
+ DPU_ATRACE_BEGIN("kms_complete_commit");
+
for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
dpu_crtc_complete_commit(crtc, old_crtc_state);
pm_runtime_put_sync(_kms->pdev->dev);
- DPU_EVT32_VERBOSE(DPU_EVTLOG_FUNC_EXIT);
+ DPU_ATRACE_END("kms_complete_commit");
}
static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
@@ -490,7 +492,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms
*kms,
* plane_cleanup. For example, wait for vsync in case of video
* mode panels. This may be a no-op for command mode panels.
*/
- DPU_EVT32_VERBOSE(DRMID(crtc));
+ trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
if (ret && ret != -EWOULDBLOCK) {
DPU_ERROR("wait for commit done returned %d\n", ret);
@@ -1137,7 +1139,6 @@ static int dpu_kms_pm_suspend(struct device *dev)
return -EINVAL;
dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev));
- DPU_EVT32(0);
/* disable hot-plug polling */
drm_kms_helper_poll_disable(ddev);
@@ -1146,6 +1147,8 @@ static int dpu_kms_pm_suspend(struct device *dev)
drm_modeset_acquire_init(, 0);
retry:
+ DPU_ATRACE_BEGIN("kms_pm_suspend");
+
ret = drm_modeset_lock_all_ctx(ddev, );
if (ret)
goto unlock;
@@ -1195,6 +1198,7 @@ static int dpu_kms_pm_suspend(struct device *dev)
drm_modeset_drop_locks();
drm_modeset_acquire_fini();
+ DPU_ATRACE_END("kms_pm_suspend");
return 0;
}
@@ -1213,7 +1217,7 @@ static int dpu_kms_pm_resume(struct device *dev)
dpu_kms = to_dpu_kms(ddev_to_msm_kms(ddev));
- DPU_EVT32(dpu_kms->suspend_state != NULL);
+ DPU_ATRACE_BEGIN("kms_pm_resume");
drm_mode_config_reset(ddev);
@@ -1236,6 +1240,7 @@ static int dpu_kms_pm_resume(struct device *dev)
/* enable hot-plug polling */
drm_kms_helper_poll_enable(ddev);
+ DPU_ATRACE_END("kms_pm_resume");
return 0;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 99c45b8d84c0..7169ff3a9805 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -338,6 +338,22 @@ DEFINE_EVENT(dpu_drm_obj_template,
dpu_crtc_complete_commit,
TP_PROTO(uint32_t drm_id),
TP_ARGS(drm_id)
);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_frame_transfer,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
+ TP_PROTO(uint32_t drm_id),
+ TP_ARGS(drm_id)
+);
+DEFINE_EVENT(dpu_drm_obj_template
[Freedreno] [DPU PATCH 16/19] drm/msm: dpu: Remove panic from dpu debug dump
Better not to allow arbitrary panics of the kernel when poking debugfs
files.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/dpu_dbg.c | 31 +++
drivers/gpu/drm/msm/dpu_dbg.h | 4 ---
5 files changed, 8 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5ff627827be9..3519f7e84f0f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1563,7 +1563,7 @@ void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys
*phys_enc)
rc = ctl->ops.reset(ctl);
if (rc) {
DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
phys_enc->enable_state = DPU_ENC_ENABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 5589d1289da9..19f5b5064ed8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -262,7 +262,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
atomic_read(_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
atomic_add_unless(_enc->pending_kickoff_cnt, -1, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 8ac7f0537c05..54f4e78cf1fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -638,7 +638,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
DPU_ERROR_VIDENC(vid_enc, "ctl %d reset failure: %d\n",
ctl->idx, rc);
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
- DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus", "panic");
+ DPU_DBG_DUMP("dbg_bus", "vbif_dbg_bus");
}
}
diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
index 3572e3cbec6c..2a9b8c732e33 100644
--- a/drivers/gpu/drm/msm/dpu_dbg.c
+++ b/drivers/gpu/drm/msm/dpu_dbg.c
@@ -26,7 +26,6 @@
#include "disp/dpu1/dpu_hw_catalog.h"
-#define DEFAULT_PANIC 1
#define DEFAULT_DBGBUS_DPU DPU_DBG_DUMP_IN_MEM
#define DEFAULT_DBGBUS_VBIFRT DPU_DBG_DUMP_IN_MEM
#define REG_BASE_NAME_LEN 80
@@ -128,9 +127,7 @@ struct dpu_dbg_vbif_debug_bus {
* struct dpu_dbg_base - global dpu debug base structure
* @reg_base_list: list of register dumping regions
* @dev: device pointer
- * @panic_on_err: whether to kernel panic after triggering dump via debugfs
* @dump_work: work struct for deferring register dump work to separate thread
- * @work_panic: panic after dump if internal user passed "panic" special region
* @dbgbus_dpu: debug bus structure for the dpu
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
* @dsi_dbg_bus: dump dsi debug bus register
@@ -139,9 +136,7 @@ static struct dpu_dbg_base {
struct list_head reg_base_list;
struct device *dev;
- u32 panic_on_err;
struct work_struct dump_work;
- bool work_panic;
struct dpu_dbg_dpu_debug_bus dbgbus_dpu;
struct dpu_dbg_vbif_debug_bus dbgbus_vbif_rt;
@@ -2230,22 +2225,18 @@ static void _dpu_dbg_dump_vbif_dbg_bus(struct
dpu_dbg_vbif_debug_bus *bus)
/**
* _dpu_dump_array - dump array of register bases
- * @do_panic: whether to trigger a panic after dumping
* @name: string indicating origin of dump
* @dump_dbgbus_dpu: whether to dump the dpu debug bus
* @dump_dbgbus_vbif_rt: whether to dump the vbif rt debug bus
*/
-static void _dpu_dump_array(bool do_panic, const char *name,
- bool dump_dbgbus_dpu, bool dump_dbgbus_vbif_rt)
+static void _dpu_dump_array(const char *name, bool dump_dbgbus_dpu,
+ bool dump_dbgbus_vbif_rt)
{
if (dump_dbgbus_dpu)
_dpu_dbg_dump_dpu_dbg_bus(_dbg_base.dbgbus_dpu);
if (dump_dbgbus_vbif_rt)
_dpu_dbg_dump_vbif_dbg_bus(_dbg_base.dbgbus_vbif_rt);
-
- if (do_panic && dpu_dbg_base.panic_on_err)
- panic(name);
}
/**
@@ -2254,14 +2245,13 @@
[Freedreno] [DPU PATCH 06/19] drm/msm: dpu_encoder_phys_cmd: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_encoder_phys_cmd with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 79 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 68
2 files changed, 104 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 388de384e2cf..eb9314aaa85f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -108,8 +108,9 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg,
int irq_idx)
new_cnt = atomic_add_unless(_enc->pending_kickoff_cnt, -1, 0);
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
- DPU_EVT32_IRQ(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0, new_cnt, event);
+ trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ new_cnt, event);
/* Signal any waiting atomic commit thread */
wake_up_all(_enc->pending_kickoff_wq);
@@ -245,21 +246,20 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
do_log = true;
}
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- cmd_enc->pp_timeout_report_cnt,
- atomic_read(_enc->pending_kickoff_cnt),
- frame_event);
+ trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent),
+phys_enc->hw_pp->idx - PINGPONG_0,
+cmd_enc->pp_timeout_report_cnt,
+atomic_read(_enc->pending_kickoff_cnt),
+frame_event);
/* to avoid flooding, only log first time, and "dead" time */
if (do_log) {
- DPU_ERROR_CMDENC(cmd_enc,
- "pp:%d kickoff timed out ctl %d cnt %d koff_cnt
%d\n",
- phys_enc->hw_pp->idx - PINGPONG_0,
- phys_enc->hw_ctl->idx - CTL_0,
- cmd_enc->pp_timeout_report_cnt,
- atomic_read(_enc->pending_kickoff_cnt));
-
- DPU_EVT32(DRMID(phys_enc->parent), DPU_EVTLOG_FATAL);
+ DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ phys_enc->hw_ctl->idx - CTL_0,
+ cmd_enc->pp_timeout_report_cnt,
+ atomic_read(_enc->pending_kickoff_cnt));
dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
@@ -308,8 +308,6 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
struct dpu_encoder_phys *phys_enc,
bool enable)
{
- struct dpu_encoder_phys_cmd *cmd_enc =
- to_dpu_encoder_phys_cmd(phys_enc);
int ret = 0;
int refcount;
@@ -330,10 +328,9 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
goto end;
}
- DPU_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
- __builtin_return_address(0), enable, refcount);
- DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- enable, refcount);
+ DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ enable ? "true" : "false", refcount);
if (enable && atomic_inc_return(_enc->vblank_refcount) == 1)
ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR);
@@ -343,12 +340,10 @@ static int dpu_encoder_phys_cmd_control_vblank_irq(
end:
if (ret) {
- DPU_ERROR_CMDENC(cmd_enc,
- "control vblank irq error %d, enable %d,
refcount %d\n",
- ret, enable, refcount);
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->hw_pp->idx - PINGPONG_0,
- enable, refcount, DPU_EVTLOG_ERROR);
+ DRM_ERROR("vblank irq err id:%u pp:%d ret:%d, enable %s/%d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0, ret,
+ enable ?
[Freedreno] [DPU PATCH 01/19] drm/msm: dpu_encoder: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_encoder with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 290 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 329
2 files changed, 464 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 11a1045bf132..6aad40dccb05 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -254,11 +254,9 @@ static inline int _dpu_encoder_power_enable(struct
dpu_encoder_virt *dpu_enc,
void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx)
{
- DPU_EVT32(DRMID(phys_enc->parent),
- phys_enc->intf_idx - INTF_0,
- phys_enc->hw_pp->idx - PINGPONG_0,
- intr_idx);
- DPU_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
+ DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
+ DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
+ phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
if (phys_enc->parent_ops.handle_frame_done)
phys_enc->parent_ops.handle_frame_done(
@@ -284,25 +282,23 @@ int dpu_encoder_helper_wait_for_irq(struct
dpu_encoder_phys *phys_enc,
/* return EWOULDBLOCK since we know the wait isn't necessary */
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
- DPU_ERROR_PHYS(phys_enc, "encoder is disabled\n");
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, intr_idx, DPU_EVTLOG_ERROR);
+ DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx);
return -EWOULDBLOCK;
}
if (irq->irq_idx < 0) {
- DPU_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
- irq->name, irq->hw_idx);
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx);
+ DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->name);
return 0;
}
- DPU_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
- atomic_read(wait_info->atomic_cnt));
- DPU_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
- irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt), DPU_EVTLOG_FUNC_ENTRY);
+ DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
+ DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+ irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(wait_info->atomic_cnt));
ret = dpu_encoder_helper_wait_event_timeout(
DRMID(phys_enc->parent),
@@ -315,36 +311,33 @@ int dpu_encoder_helper_wait_for_irq(struct
dpu_encoder_phys *phys_enc,
if (irq_status) {
unsigned long flags;
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx,
- irq->hw_idx, irq->irq_idx,
- phys_enc->hw_pp->idx - PINGPONG_0,
- atomic_read(wait_info->atomic_cnt));
- DPU_DEBUG_PHYS(phys_enc,
- "done but irq %d not triggered\n",
- irq->irq_idx);
+ DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
+ "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+ DRMID(phys_enc->parent), intr_idx,
+ irq->hw_idx, irq->irq_idx,
+ phys_enc->hw_pp->idx - PINGPONG_0,
+ atomic_read(wait_info->atomic_cnt));
local_irq_save(flags);
irq->cb.func(phys_enc, irq->irq_idx);
local_irq_restore(flags);
ret = 0;
} else {
ret = -ETIMEDOUT;
- DPU_EVT32(DRMID(phys_enc->parent), intr_idx,
- irq->h
[Freedreno] [DPU PATCH 09/19] drm/msm: dpu_pingpong: Replace DPU_EVT with tracepoints
This patch converts all DPU_EVTs in dpu_pingpong with either a DRM_* log
message or a linux tracepoint.
Signed-off-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 14 ++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 84d2176ecafb..12e90b8e5466 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -18,6 +18,7 @@
#include "dpu_hw_pingpong.h"
#include "dpu_dbg.h"
#include "dpu_kms.h"
+#include "dpu_trace.h"
#define PP_TEAR_CHECK_EN0x000
#define PP_SYNC_CONFIG_VSYNC0x004
@@ -134,7 +135,7 @@ static int dpu_hw_pp_connect_external_te(struct
dpu_hw_pingpong *pp,
else
cfg &= ~BIT(20);
DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
- DPU_EVT32(pp->idx - PINGPONG_0, cfg);
+ trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
return orig;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 73f76387803f..9d044f5ce26e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -952,6 +952,20 @@ TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
);
+TRACE_EVENT(dpu_pp_connect_ext_te,
+ TP_PROTO(enum dpu_pingpong pp, u32 cfg),
+ TP_ARGS(pp, cfg),
+ TP_STRUCT__entry(
+ __field(enum dpu_pingpong, pp )
+ __field(u32,cfg )
+ ),
+ TP_fast_assign(
+ __entry->pp = pp;
+ __entry->cfg = cfg;
+ ),
+ TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
+);
+
#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
--
Sean Paul, Software Engineer, Google / Chromium OS
___
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Re: [Freedreno] [DPU PATCH 4/4] drm/msm/dpu: use private obj to track hw resources
On Tue, Jun 12, 2018 at 06:17:47PM -0700, Jeykumar Sankaran wrote:
> Switch to state based resource management. This patch
> overhauls the resource manager and HW allocation methods by
> maintaining the global resource pool and allocated hw
> blocks in respective drm component states.
>
> Global resource manager(RM) is tracked in private object.
> Allocation strategy is switched from single point allocation
> of HW resources for the display pipeline to per component
> based allocation, where each drm component allocates HW
> blocks mapped to it's domain and tracks them in their respective
> state objects.
>
> Fixes resource contention due to race conditions between
> user space and display thread by reserving resources
> only in atomic check.
>
> Signed-off-by: Jeykumar Sankaran
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 210 +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 59 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 223 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 4 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 9 +-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 32 +-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 86 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 19 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 8 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 805
> ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++--
> 11 files changed, 534 insertions(+), 1070 deletions(-)
Ok, there's a lot going on here. It's pretty easy to review megapatches where
the diffstat is mostly negative. However, this patch has a lot of code deleted
and moving around, along with the new private obj. It's really hard to review
changes like this.
Could you please split this up into a bunch of simple patches which do one
thing? ie: Moving topology is a patch, using cstate instead of crtc is a patch,
using private obj is a patch, etc, etc.
Basically, cut things down into small enough pieces such that each patch can
be easily explained without using "and" in the commit message :-)
/snip
> +
> dpu_crtc = to_dpu_crtc(crtc);
> cstate = to_dpu_crtc_state(crtc->state);
> mode = >base.adjusted_mode;
> priv = crtc->dev->dev_private;
> + dpu_kms = to_dpu_kms(priv->kms);
> +
> + /* accessing after swap state. piv_obj.state is the current state */
s/piv_obj/priv_obj/
> + dpu_priv_state = to_dpu_private_state(dpu_kms->priv_obj.state);
>
> DPU_DEBUG("crtc%d\n", crtc->base.id);
>
/snip
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [DPU PATCH 0/4] Atomic resource management
On Tue, Jun 12, 2018 at 06:17:43PM -0700, Jeykumar Sankaran wrote: > This patchset introduces drm private object in KMS to manage HW > resource management. It modifies the resource manager by > introducing API's to do per DRM object resource allocation/cleanups. > > The patchset is based on: https://patchwork.kernel.org/patch/10461375/ > > Jeykumar Sankaran (4): > drm/msm/dpu: add atomic private object to dpu kms > drm/msm/dpu: remove scalar config definitions > drm/msm/dpu: remove resource pool manager > drm/msm/dpu: use private obj to track hw resources Kind of an odd arrangement of patches. Since you're respinning anyways, can you please reorder to: drm/msm/dpu: remove scalar config definitions drm/msm/dpu: remove resource pool manager drm/msm/dpu: add atomic private object to dpu kms drm/msm/dpu: use private obj to track hw resources Sean > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 704 +++--- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 144 ++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 223 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 4 - > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 9 +- > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 32 +- > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 86 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h| 10 - > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 85 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 23 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 805 > ++--- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++-- > 12 files changed, 615 insertions(+), 1659 deletions(-) > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
