Re: [Freedreno] [DPU PATCH 4/4] drm/msm/dpu: use private obj to track hw resources

[Sean Paul]

On Wed, Jun 13, 2018 at 12:01:21PM -0700, Jeykumar Sankaran wrote:
> On 2018-06-13 09:44, Jordan Crouse wrote:
> > On Tue, Jun 12, 2018 at 06:17:47PM -0700, Jeykumar Sankaran wrote:
> > > Switch to state based resource management. This patch
> > > overhauls the resource manager and HW allocation methods by
> > > maintaining the global resource pool and allocated hw
> > > blocks in respective drm component states.
> > > 
> > > Global resource manager(RM) is tracked in private object.
> > > Allocation strategy is switched from single point allocation
> > > of HW resources for the display pipeline to per component
> > > based allocation, where each drm component allocates HW
> > > blocks mapped to it's domain and tracks them in their respective
> > > state objects.
> > > 
> > > Fixes resource contention due to race conditions between
> > > user space and display thread by reserving resources
> > > only in atomic check.
> > > 
> > > Signed-off-by: Jeykumar Sankaran 
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 210 +++---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |  59 +-
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 223 ++
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   4 -
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   9 +-
> > >  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  32 +-
> > >  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  86 +--
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  19 +-
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   8 +-
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 805
> > ++---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++--
> > >  11 files changed, 534 insertions(+), 1070 deletions(-)

/snip

> > cstate->num_mixers);
> > 
> > Nit - this could be worded a bit better - "too many mixers" would be
> > better, but
> > I have to ask - under what circumstances would the number of mixers be
> > larger
> > than CRTC_DUAL_MIXERS and/or why don't we support a dynamic number of
> > mixers?
> > 
> Comes from downstream driver implementation where CRTC iterates through
> RM free pool to identify mixers tagged with the current crtc id. If the
> previous clean up was screwed up this may have more than 2 mixers. With
> the new state based RM, its very unlikely we hit this condition.
> 

In this case, add a comment with "/* This should never happen */"

I'm just kidding, that would virtually guarantee that it does happen and we
certainly don't need that bad juju around!

Sean

> We do support dynamic mixer counts. Based on the connector (panel)
> resolution,
> CRTC allocates 1 or 2 (panel_width > hw mixer width) mixer block(s) on the
> first
> atomic check. DPU limits max no. of hw mixers that can be ganged up for a
> display to 2.
> 
> > >   return;
> > >   }
> > 

/snip

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [DPU PATCH v3 0/7] clean up DPU custom properties

[Sean Paul]

processing.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h
>  delete mode 100644 drivers/gpu/drm/msm/msm_prop.c
>  delete mode 100644 drivers/gpu/drm/msm/msm_prop.h
>  delete mode 100644 include/uapi/drm/dpu_drm.h
>  delete mode 100644 include/uapi/drm/msm_drm_pp.h
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [DPU PATCH v2 2/7] drm/msm/dpu: clean up dpu plane custom properties

[Sean Paul]

On Tue, Jun 05, 2018 at 08:45:33PM -0700, Jeykumar Sankaran wrote:
> This change removes all the dpu plane custom properties
> and its handlers.
> 
> changs in v2:
>   - remove stale code in blend config(Sean Paul)
>   - Makefile changes to remove warning flags(Sean Paul)
> 
> Signed-off-by: Jeykumar Sankaran 
> ---
>  drivers/gpu/drm/msm/Makefile   |8 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h|   99 --
>  .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   | 1521 
> 
>  .../gpu/drm/msm/disp/dpu1/dpu_color_processing.h   |  120 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  205 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |3 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|2 -
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c|1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c | 1443 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   72 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   89 --
>  .../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h|   69 -
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c   |  242 
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h   |   40 -
>  .../drm/msm/disp/dpu1/dpu_hw_color_processing.h|   20 -
>  .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c   |  565 
>  .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h   |   92 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |   44 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |   15 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c|  209 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h|  220 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   44 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   68 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|6 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  |  757 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h  |   27 -
>  .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c   |  943 
>  .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h   |   75 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c|  219 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h|   73 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c|1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h|  156 ++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|3 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 1269 +---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |   31 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c|  139 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h|  310 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  102 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |2 -
>  drivers/gpu/drm/msm/msm_drv.h  |   28 -
>  include/uapi/drm/dpu_drm.h |  187 ---
>  include/uapi/drm/msm_drm.h |1 -
>  44 files changed, 282 insertions(+), 9241 deletions(-)
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c
>  delete mode 100644 
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h
> 

/snip

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c

/snip

> -
&

Re: [Freedreno] [DPU PATCH 4/7] drm/msm/dpu: switch to drm zpos property

[Sean Paul]

f (kms->catalog->mixer_count &&
> > +   kms->catalog->mixer[0].sblk->maxblendstages) {
> > +   zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
> > +   if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
> > +   zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
> > +   }
> > +
> > +   ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
> > +   if (ret)
> > +   DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
> > +
> 
> drm_plane_create_zpos_property() can either return 0 or -ENOMEM 

This may not always be true.

> so
> printing the return value isn't interesting.

Also if I was reviewing or casual reading this without the ret print, I would
probably leave a comment such as "print the return value" since I don't
generally keep track of all possible return values.

So printing the return value seems reasonable to me.

Sean

> 
> > /* success! finalize initialization */
> > drm_plane_helper_add(plane, _plane_helper_funcs);
> >  
> > -- 
> > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> > a Linux Foundation Collaborative Project
> > 
> > ___
> > Freedreno mailing list
> > Freedreno@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/freedreno
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

-- 
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Re: [Freedreno] [DPU PATCH 4/7] drm/msm/dpu: switch to drm zpos property

[Sean Paul]

On Wed, May 23, 2018 at 12:30:59PM -0700, Jeykumar Sankaran wrote:
> Replace custom plane zpos property with drm core zpos
> property. CRTC relies on the normalized zpos values
> to configure blend stages of each plane.
> 
> Signed-off-by: Jeykumar Sankaran 
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 36 
> +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +---
>  2 files changed, 16 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index d439a9e..a0b702f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -2631,24 +2631,6 @@ struct plane_state {
>   u32 pipe_id;
>  };
>  
> -static int pstate_cmp(const void *a, const void *b)
> -{
> - struct plane_state *pa = (struct plane_state *)a;
> - struct plane_state *pb = (struct plane_state *)b;
> - int rc = 0;
> - int pa_zpos, pb_zpos;
> -
> - pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS);
> - pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS);
> -
> - if (pa_zpos != pb_zpos)
> - rc = pa_zpos - pb_zpos;
> - else
> - rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
> -
> - return rc;
> -}
> -
>  static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>   struct drm_crtc_state *state)
>  {
> @@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>  
>   pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
>   pstates[cnt].drm_pstate = pstate;
> - pstates[cnt].stage = dpu_plane_get_property(
> - pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS);
> + pstates[cnt].stage = pstate->normalized_zpos;
>   pstates[cnt].pipe_id = dpu_plane_pipe(plane);
>  
>   /* check dim layer stage with every plane */
> @@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>   }
>   }
>  
> - /* assign mixer stages based on sorted zpos property */
> - sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
> -
> - if (!dpu_is_custom_client()) {
> - int stage_old = pstates[0].stage;
> -
> - z_pos = 0;
> - for (i = 0; i < cnt; i++) {
> - if (stage_old != pstates[i].stage)
> - ++z_pos;
> - stage_old = pstates[i].stage;
> - pstates[i].stage = z_pos;
> - }
> - }
> -
>   z_pos = -1;
>   for (i = 0; i < cnt; i++) {
>   /* reset counts at every new blend stage */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index b033653..28735c8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -59,6 +59,7 @@
>  #define DPU_NAME_SIZE  12
>  
>  #define DPU_PLANE_COLOR_FILL_FLAGBIT(31)
> +#define DPU_ZPOS_MAX 255
>  
>  /* multirect rect index */
>  enum {
> @@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct 
> drm_plane *plane,
>   /* reserve zpos == 0 for primary planes */
>   zpos_def = drm_plane_index(plane) + 1;
>   }
> -
> - msm_property_install_range(>property_info, "zpos",
> - 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
>  }
>  
>  static int dpu_plane_atomic_set_property(struct drm_plane *plane,
> @@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
>   struct msm_drm_private *priv;
>   struct dpu_kms *kms;
>   enum drm_plane_type type;
> + int zpos_max = DPU_ZPOS_MAX;
>   int ret = -EINVAL;
>  
>   if (!dev) {
> @@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device 
> *dev,
>   if (ret)
>   goto clean_sspp;
>  
> + pdpu->catalog = kms->catalog;
> +

Why is this here? It seems unrelated to the patch.

> + if (kms->catalog->mixer_count &&
> + kms->catalog->mixer[0].sblk->maxblendstages) {
> + zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
> + if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
> + zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
> + }
> +
> + ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
> + if (ret)
> + DPU_ERROR("faile

Re: [Freedreno] [DPU PATCH 6/7] drm/msm: remove msm_prop files

[Sean Paul]

On Wed, May 23, 2018 at 12:31:01PM -0700, Jeykumar Sankaran wrote:
> Remove hand rolled msm property caching to handle DPU
> custom properties. This change also cleans up all its
> dependencies to cache and restore respective drm
> states.
> 
> Signed-off-by: Jeykumar Sankaran 

Reviewed-by: Sean Paul 

> ---
>  drivers/gpu/drm/msm/Makefile  |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 239 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  16 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 123 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  12 -
>  drivers/gpu/drm/msm/msm_drv.h |  16 +-
>  drivers/gpu/drm/msm/msm_prop.c| 688 
> --
>  drivers/gpu/drm/msm/msm_prop.h| 438 
>  10 files changed, 8 insertions(+), 1529 deletions(-)
>  delete mode 100644 drivers/gpu/drm/msm/msm_prop.c
>  delete mode 100644 drivers/gpu/drm/msm/msm_prop.h
> 
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index d289503..5331188 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -76,7 +76,6 @@ msm-y := \
>   dpu_io_util.o \
>   dpu_dbg_evtlog.o \
>   dpu_power_handle.o \
> - msm_prop.o \
>   msm_atomic.o \
>   msm_debugfs.o \
>   msm_drv.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index c4820de..e4b82d5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -19,8 +19,6 @@
>  #include 
>  #include 
>  
> -#include "msm_prop.h"
> -
>  #include "dpu_kms.h"
>  #include "dpu_trace.h"
>  #include "dpu_crtc.h"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index b0a3a30..43d9985 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -579,10 +579,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
>   if (!crtc)
>   return;
>  
> - if (dpu_crtc->blob_info)
> - drm_property_blob_put(dpu_crtc->blob_info);
> - msm_property_destroy(_crtc->property_info);
> -
>   _dpu_crtc_deinit_events(dpu_crtc);
>  
>   drm_crtc_cleanup(crtc);
> @@ -1390,9 +1386,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc 
> *crtc,
>  
>   __drm_atomic_helper_crtc_destroy_state(state);
>  
> - /* destroy value helper */
> - msm_property_destroy_state(_crtc->property_info, cstate,
> - >property_state);
> + kfree(cstate);
>  }
>  
>  static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
> @@ -1641,17 +1635,12 @@ static struct drm_crtc_state 
> *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
>  
>   dpu_crtc = to_dpu_crtc(crtc);
>   old_cstate = to_dpu_crtc_state(crtc->state);
> - cstate = msm_property_alloc_state(_crtc->property_info);
> + cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
>   if (!cstate) {
>   DPU_ERROR("failed to allocate state\n");
>   return NULL;
>   }
>  
> - /* duplicate value helper */
> - msm_property_duplicate_state(_crtc->property_info,
> - old_cstate, cstate,
> - >property_state, cstate->property_values);
> -
>   /* duplicate base helper */
>   __drm_atomic_helper_crtc_duplicate_state(crtc, >base);
>  
> @@ -1687,17 +1676,12 @@ static void dpu_crtc_reset(struct drm_crtc *crtc)
>   }
>  
>   dpu_crtc = to_dpu_crtc(crtc);
> - cstate = msm_property_alloc_state(_crtc->property_info);
> + cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
>   if (!cstate) {
>   DPU_ERROR("failed to allocate state\n");
>   return;
>   }
>  
> - /* reset value helper */
> - msm_property_reset_state(_crtc->property_info, cstate,
> - >property_state,
> - cstate->property_values);
> -
>   _dpu_crtc_rp_reset(>rp, _crtc->rp_lock,
>   _crtc->rp_head);
>  
> @@ -2194,212 +2178,6 @@ void dpu_crtc_cancel_pending_flip(struct drm_crtc 
> *crtc, struct drm_file *file)
>   _dpu_crtc_complete_flip(crtc, file);
>  }
>  
> -/**
> - * dpu_crtc_install_properties - install all drm pr

Re: [Freedreno] [DPU PATCH 5/7] drm/msm/dpu: clean up dpu crtc custom properties

[Sean Paul]

On Wed, May 23, 2018 at 12:31:00PM -0700, Jeykumar Sankaran wrote:
> Remove dpu crtc custom properties and its handlers.
> 
> Signed-off-by: Jeykumar Sankaran 

Reviewed-by: Sean Paul 

> ---
>  drivers/gpu/drm/msm/Makefile  |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  28 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 856 
> +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  27 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  12 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c | 149 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h | 111 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |  67 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h |  14 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |  16 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c|  71 +--
>  drivers/gpu/drm/msm/msm_drv.h |  15 -
>  12 files changed, 11 insertions(+), 1356 deletions(-)
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h
> 
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 7bc3921..d289503 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -57,7 +57,6 @@ msm-y := \
>   disp/dpu1/dpu_hw_catalog.o \
>   disp/dpu1/dpu_hw_cdm.o \
>   disp/dpu1/dpu_hw_ctl.o \
> - disp/dpu1/dpu_hw_ds.o \
>   disp/dpu1/dpu_hw_interrupts.o \
>   disp/dpu1/dpu_hw_intf.o \
>   disp/dpu1/dpu_hw_lm.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index 981f77f..c4820de 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -102,34 +102,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
>   dpu_cstate = to_dpu_crtc_state(state);
>   memset(perf, 0, sizeof(struct dpu_core_perf_params));
>  
> - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
> - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
> -
> - if (dpu_cstate->bw_split_vote) {
> - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_AB);
> - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_IB);
> - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_AB);
> - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_IB);
> - } else {
> - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
> - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
> - perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
> - perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
> - }
> -
> - perf->core_clk_rate =
> - dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_CLK);
> -
>   if (!dpu_cstate->bw_control) {
>   for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
>   perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index a0b702f..b0a3a30 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -570,18 +570,6 @@ static void _dpu_crtc_deinit_events(struct dpu_crtc 
> *dpu_crtc)
>   return;
>  }
>  
> -/**
> - * dpu_crtc_destroy_dest_scaler - free memory allocated for scaler lut
> - * @dpu_crtc: Pointer to dpu crtc
> - */
> -static void _dpu_crtc_destroy_dest_scaler(struct dpu_crtc *dpu_crtc)
> -{
> - if (!dpu_crtc)
> - return;
> -
> - kfree(dpu_crtc->scl3_lut_cfg);
> -}
> -
>  static void dpu_crtc_destroy(struct drm_crtc *crtc)
>  {
>   struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> @@ -594,7 +582,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
>  

Re: [Freedreno] [DPU PATCH 2/7] drm/msm/dpu: clean up dpu plane custom properties

[Sean Paul]

a_v1_color_proc.h
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h
> 
> diff --git a/Makefile b/Makefile
> index 3c00040..1f23c66 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -364,7 +364,7 @@ HOST_LFS_LIBS := $(shell getconf LFS_LIBS)
>  HOSTCC   = gcc
>  HOSTCXX  = g++
>  HOSTCFLAGS   := -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 \
> - -fomit-frame-pointer -std=gnu89 $(HOST_LFS_CFLAGS)
> + -fomit-frame-pointer -std=gnu89 -Wmaybe-uninitialized 
> $(HOST_LFS_CFLAGS)

What's up with the compiler flag warnings? Seems unrelated (and we should
probably remove all of them in a separate patch anyways).

>  HOSTCXXFLAGS := -O2 $(HOST_LFS_CFLAGS)
>  HOSTLDFLAGS  := $(HOST_LFS_LDFLAGS)
>  HOST_LOADLIBES := $(HOST_LFS_LIBS)

/snip

> index 48920b05..d439a9e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -20,7 +20,6 @@
>  #include 
>  #include 
>  #include 
> -#include 
>  #include 
>  #include 
>  #include 
> @@ -31,13 +30,18 @@
>  #include "dpu_hw_ctl.h"
>  #include "dpu_crtc.h"
>  #include "dpu_plane.h"
> -#include "dpu_color_processing.h"
>  #include "dpu_encoder.h"
>  #include "dpu_vbif.h"
>  #include "dpu_power_handle.h"
>  #include "dpu_core_perf.h"
>  #include "dpu_trace.h"
>  
> +#define DPU_DRM_BLEND_OP_NOT_DEFINED0
> +#define DPU_DRM_BLEND_OP_OPAQUE 1
> +#define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
> +#define DPU_DRM_BLEND_OP_COVERAGE   3
> +#define DPU_DRM_BLEND_OP_MAX4
> +
>  /* layer mixer index on dpu_crtc */
>  #define LEFT_MIXER 0
>  #define RIGHT_MIXER 1
> @@ -590,7 +594,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
>   if (dpu_crtc->blob_info)
>   drm_property_blob_put(dpu_crtc->blob_info);
>   msm_property_destroy(_crtc->property_info);
> - dpu_cp_crtc_destroy_properties(crtc);
>   _dpu_crtc_destroy_dest_scaler(dpu_crtc);
>  
>   _dpu_crtc_deinit_events(dpu_crtc);
> @@ -624,15 +627,11 @@ static void _dpu_crtc_setup_blend_cfg(struct 
> dpu_crtc_mixer *mixer,
>   struct dpu_hw_mixer *lm = mixer->hw_lm;
>  
>   /* default to opaque blending */
> - fg_alpha = dpu_plane_get_property(pstate, PLANE_PROP_ALPHA);
> + fg_alpha = 0XFF;
>   bg_alpha = 0xFF - fg_alpha;

This goes to 0 and the fg_alpha != 0xff checks are always false. So let's clean
the rest of the function to remove the dead code and variables.

> - blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_BG_CONST;
> - blend_type = dpu_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
> -
> - DPU_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
> + blend_type = DPU_DRM_BLEND_OP_OPAQUE;
>  
>   switch (blend_type) {
> -
>   case DPU_DRM_BLEND_OP_OPAQUE:
>   blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
>   DPU_BLEND_BG_ALPHA_BG_CONST;
>


/snip

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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[Freedreno] [PATCH] drm/msm: Fix NULL deref on bind/probe deferral

[Sean Paul]

This patch avoids dereferencing msm_host->dev when it is NULL.

If we find ourselves tearing down dsi before calling
(mdp4|mdp5|dpu)_kms_init(), we'll end up in a state where the dev
pointer is NULL and trying to extract priv from it will fail.

This was introduced in a seemingly innocuous commit to ensure the
arguments to msm_gem_put_iova() are correct (even though that
function has been a stub for ~5 years). Correctness FTW! \o/

Fixes: b01884a286b0 drm/msm: use correct aspace pointer in msm_gem_put_iova()
Cc: Daniel Mack 
Cc: Rob Clark 
Signed-off-by: Sean Paul 
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b916f464f4ec..2f1a2780658a 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1066,8 +1066,18 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host 
*msm_host, int size)
 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
 {
struct drm_device *dev = msm_host->dev;
-   struct msm_drm_private *priv = dev->dev_private;
+   struct msm_drm_private *priv;
+
+   /*
+* This is possible if we're tearing down before we've had a chance to
+* fully initialize. A very real possibility if our probe is deferred,
+* in which case we'll hit msm_dsi_host_destroy() without having run
+* through the dsi_tx_buf_alloc().
+*/
+   if (!dev)
+   return;
 
+   priv = dev->dev_private;
if (msm_host->tx_gem_obj) {
msm_gem_put_iova(msm_host->tx_gem_obj, priv->kms->aspace);
drm_gem_object_put_unlocked(msm_host->tx_gem_obj);
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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Re: [Freedreno] [DPU PATCH v2 5/6] drm/msm: hook up DPU with upstream DSI

[Sean Paul]

On Thu, Apr 19, 2018 at 04:52:03PM -0700, Jeykumar Sankaran wrote:
> Switch DPU from dsi-staging to upstream dsi driver. To make
> the switch atomic, this change includes:
> - remove dpu connector layers
> - clean up dpu connector dependencies in encoder/crtc
> - compile out writeback and display port drivers
> - compile out dsi-staging driver (separate patch submitted to
>   remove the driver)
> - adapt upstream device hierarchy
> 
> changes in v2:
>   - remove files not applicable upstream (Sean Paul)
>   - remove compiled out non-dsi display init (Sean Paul)
>   - split unrelated changes into separate patch set (Sean Paul)
> 
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/Makefile   |1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1184 
> 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |9 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  179 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   10 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |8 +-
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |6 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  489 +---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|6 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |   54 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   11 +
>  drivers/gpu/drm/msm/dpu_dbg.c  |3 -
>  drivers/gpu/drm/msm/msm_drv.c  |   47 +-
>  drivers/gpu/drm/msm/msm_drv.h  |   39 -
>  15 files changed, 158 insertions(+), 2443 deletions(-)
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h
> 

/snip

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index c8c12d3..af8205f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -23,7 +23,6 @@
>  #include "dpu_hw_intf.h"
>  #include "dpu_hw_wb.h"
>  #include "dpu_encoder.h"
> -#include "dpu_connector.h"
>  
>  #define RESERVED_BY_OTHER(h, r) \
>   ((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
> @@ -158,6 +157,18 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
>   return rm->hw_mdp;
>  }
>  
> +enum dpu_rm_topology_name
> +dpu_rm_get_topology_name(struct msm_display_topology topology)
> +{
> + int i;
> +
> + for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++)
> + if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], topology))
> + return g_top_table[i].top_name;
> +
> + return DPU_RM_TOPOLOGY_NONE;
> +}
> +
>  void dpu_rm_init_hw_iter(
>   struct dpu_rm_hw_iter *iter,
>   uint32_t enc_id,
> @@ -954,20 +965,19 @@ static int _dpu_rm_populate_requirements(
>   struct drm_encoder *enc,
>   struct drm_crtc_state *crtc_state,
>   struct drm_connector_state *conn_state,
> - struct dpu_rm_requirements *reqs)
> + struct dpu_rm_requirements *reqs,
> + struct msm_display_topology req_topology)
>  {
>   const struct drm_display_mode *mode = _state->mode;
>   int i;
>  
>   memset(reqs, 0, sizeof(*reqs));
>  
> - reqs->top_ctrl = dpu_connector_get_property(conn_state,
> - CONNECTOR_PROP_TOPOLOGY_CONTROL);
>   dpu_encoder_get_hw_resources(enc, >hw_res, conn_state);
>  
>   for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++) {
>   if (RM_IS_TOPOLOGY_MATCH(g_top_table[i],
> - reqs->hw_res.topology)) {
> + req_topology)) {
>   reqs->topology = _top_table[i];
>   break;
>   }
> @@ -978,10 +988,6 @@ static int _dpu_rm_populate_requirements(
>   return -EINVAL;
>   }
>  
> - /* DSC blocks are hardwired for control path 0 and 1 */
> - if (reqs->topology->num_comp_enc)
> - reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DSPP);
> -
>   /**
>* Set the requirement based on caps if not set from user space
>* This will ensure to select LM tied with DS blocks
> @@ -1110,9 +1116,6 @@ void dpu_rm_release(struct dpu_rm *rm, struct 
> drm_encoder *enc)
>   goto end;
>   }
>  
> - top_ctrl = dpu_connector_get_prope

Re: [Freedreno] [DPU PATCH v2 03/12] drm/msm/dpu: add MDSS top level driver for dpu

[Sean Paul]

On Fri, May 11, 2018 at 11:05:24AM -0600, Jordan Crouse wrote:
> On Fri, May 11, 2018 at 08:19:29PM +0530, Rajesh Yadav wrote:
> > SoCs containing dpu have a MDSS top level wrapper
> > which includes sub-blocks as dpu, dsi, phy, dp etc.
> > MDSS top level wrapper manages common resources like
> > common clocks, power and irq for its sub-blocks.
> > 
> > Currently, in dpu driver, all the power resource
> > management is part of power_handle which manages
> > these resources via a custom implementation. And
> > the resource relationships are not modelled properly
> > in dt.  Moreover the irq domain handling code is part
> > of dpu device (which is a child device) due to lack
> > of a dedicated driver for MDSS top level wrapper
> > device.
> > 
> > This change adds dpu_mdss top level driver to handle
> > common clock like - core clock, ahb clock
> > (for register access), main power supply (i.e. gdsc)
> > and irq management.
> > The top level mdss device/driver acts as an interrupt
> > controller and manage hwirq mapping for its child
> > devices.
> > 
> > It implements runtime_pm support for resource management.
> > Child nodes can control these resources via runtime_pm
> > get/put calls on their corresponding devices due to parent
> > child relationship defined in dt.
> > 
> > Changes in v2:
> > - merge _dpu_mdss_hw_rev_init to dpu_mdss_init (Sean Paul)
> > - merge _dpu_mdss_get_intr_sources to dpu_mdss_irq (Sean Paul)
> > - fix indentation for irq_find_mapping call (Sean Paul)
> > - remove unnecessary goto statements from dpu_mdss_irq (Sean Paul)
> > - remove redundant param checks from
> >   dpu_mdss_irq_mask/unmask (Sean Paul/Jordan Crouse)
> > - remove redundant param checks from
> >   dpu_mdss_irqdomain_map (Sean Paul/Jordan Crouse)
> > - return error code from dpu_mdss_enable/disable (Sean Paul/Jordan 
> > Crouse)
> > - remove redundant param check from dpu_mdss_destroy (Sean Paul)
> > - remove explicit calls to devm_kfree (Sean Paul/Jordan Crouse)
> > - remove compatibility check from dpu_mdss_init as
> >   it is conditionally called from msm_drv (Sean Paul)
> > - reworked msm_dss_parse_clock() to add return checks for
> >   of_property_read_* calls, fix log message and
> >   fix alignment issues (Sean Paul/Jordan Crouse)
> > - remove extra line before dpu_mdss_init (Sean Paul)
> > - remove redundant param checks from __intr_offset and
> >   make it a void function to avoid unnecessary error
> >   handling from caller (Jordan Crouse)
> > - remove redundant param check from dpu_mdss_irq (Jordan Crouse)
> > - change mdss address space log message to debug and use %pK for
> >   kernel pointers (Jordan Crouse)
> > - remove unnecessary log message from msm_dss_parse_clock (Jordan 
> > Crouse)
> > - don't export msm_dss_parse_clock since it is used
> >   only by dpu driver (Jordan Crouse)
> > 
> > Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
> 
> Reviewed-by: Jordan Crouse <jcro...@codeaurora.org>
> 
> I know you'll get a hundred different opinions from a hundred different people

I'll interpret this as solicitation of my opinion :-)

I find this level of detail _extremely_ useful when reviewing, especially on
sets as big as this one.

It's a pretty good strategy to make reviews go as smoothly as possible, since
it's generally more difficult to read code than to write it.

Sean

/opinion

> but you don't need to credit me for every change - just a single line "fixed
> bugs" works for me.
> 
> > ---
> >  drivers/gpu/drm/msm/Makefile  |   1 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  97 -
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h  |  14 --
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|   9 -
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   7 -
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |  28 +--
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  11 -
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c   |  48 +---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   6 -
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |   2 -
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c  | 254 
> > ++
> >  drivers/gpu/drm/msm/dpu_io_util.c |  57 +
> >  drivers/gpu/drm/msm/msm_drv.c |  26 ++-
> >  drivers/gpu/drm/msm/msm_drv.h |   2 +-
>

Re: [Freedreno] [DPU PATCH v2 12/12] drm/msm/dpu: add error handling in dpu_core_perf_crtc_update

[Sean Paul]

On Fri, May 11, 2018 at 08:19:38PM +0530, Rajesh Yadav wrote:
> dpu_core_perf_crtc_update() is responsible for aggregating
> the data bus bandwidth and dpu core clock rate requirements
> and request the same for all active crtcs.
> Currently, there is no error handling support in this function
> so there is no way caller can know if the perf request fails.
> This change adds error handling code in dpu_core_perf_crtc_update().
> The caller side error handling is not added in this patch.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Cool! Thanks for doing this :-)

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 37 
> ++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |  3 ++-
>  2 files changed, 27 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index d3a1ed9..85c0229 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -248,7 +248,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
>   return 0;
>  }
>  
> -static void _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
> +static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,
>   struct drm_crtc *crtc, u32 bus_id)
>  {
>   u64 bw_sum_of_intfs = 0, bus_ab_quota, bus_ib_quota;
> @@ -257,6 +257,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms 
> *kms,
>   = dpu_crtc_get_client_type(crtc);
>   struct drm_crtc *tmp_crtc;
>   struct dpu_crtc_state *dpu_cstate;
> + int ret = 0;
>  
>   drm_for_each_crtc(tmp_crtc, crtc->dev) {
>   if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
> @@ -286,25 +287,28 @@ static void _dpu_core_perf_crtc_update_bus(struct 
> dpu_kms *kms,
>  
>   switch (curr_client_type) {
>   case NRT_CLIENT:
> - dpu_power_data_bus_set_quota(>phandle, kms->core_client,
> + ret = dpu_power_data_bus_set_quota(
> + >phandle, kms->core_client,
>   DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
>   bus_id, bus_ab_quota, bus_ib_quota);
>   DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
> - bus_id, bus_ab_quota, bus_ib_quota);
> +   bus_id, bus_ab_quota, bus_ib_quota);
>   break;
>  
>   case RT_CLIENT:
> - dpu_power_data_bus_set_quota(>phandle, kms->core_client,
> + ret = dpu_power_data_bus_set_quota(
> + >phandle, kms->core_client,
>   DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
>   bus_id, bus_ab_quota, bus_ib_quota);
>   DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
> - bus_id, bus_ab_quota, bus_ib_quota);
> +   bus_id, bus_ab_quota, bus_ib_quota);
>   break;
>  
>   default:
>   DPU_ERROR("invalid client type:%d\n", curr_client_type);
>   break;
>   }
> + return ret;
>  }
>  
>  /**
> @@ -399,7 +403,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct 
> dpu_kms *kms)
>   return clk_rate;
>  }
>  
> -void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
> +int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
>   int params_changed, bool stop_req)
>  {
>   struct dpu_core_perf_params *new, *old;
> @@ -410,16 +414,17 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
>   int i;
>   struct msm_drm_private *priv;
>   struct dpu_kms *kms;
> + int ret;
>  
>   if (!crtc) {
>   DPU_ERROR("invalid crtc\n");
> - return;
> + return -EINVAL;
>   }
>  
>   kms = _dpu_crtc_get_kms(crtc);
>   if (!kms || !kms->catalog) {
>   DPU_ERROR("invalid kms\n");
> - return;
> + return -EINVAL;
>   }
>   priv = kms->dev->dev_private;
>  
> @@ -482,8 +487,14 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
>   update_bus, update_clk);
>  
>   for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
> - if (update_bus & BIT(i))
> - _dpu_core_perf_crtc_update_bus(kms, crtc, i);
> + if (update_bus & BIT(i)) {
> + 

Re: [Freedreno] [DPU PATCH v2 11/12] drm/msm/dpu: move dpu_power_handle to dpu folder

[Sean Paul]

On Fri, May 11, 2018 at 08:19:37PM +0530, Rajesh Yadav wrote:
> Now, since dpu_power_handle manages only bus scaling
> and power enable/disable notifications which are restricted
> to dpu driver, move dpu_power_handle to dpu folder.
> 
> Changes in v2:
>   - resolved conflict in dpu_unbind
>   - dropped (Reviewed-by: Sean Paul) due to above change
> 

Reviewed-by: Sean Paul <seanp...@chromium.org>

> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/Makefile |   2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c|   5 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c |   7 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   2 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  39 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h  |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 693 
> +++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++
>  drivers/gpu/drm/msm/dpu_power_handle.c   | 693 
> ---
>  drivers/gpu/drm/msm/dpu_power_handle.h   | 288 --
>  drivers/gpu/drm/msm/msm_drv.c|   9 -
>  drivers/gpu/drm/msm/msm_drv.h|   4 -
>  14 files changed, 1013 insertions(+), 1020 deletions(-)
>  create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
>  create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
>  delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c
>  delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h
> 
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index d9826c1..f578d5a 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -82,10 +82,10 @@ msm-y := \
>   disp/dpu1/dpu_rm.o \
>   disp/dpu1/dpu_vbif.o \
>   disp/dpu1/dpu_mdss.o \
> + disp/dpu1/dpu_power_handle.o \
>   dpu_dbg.o \
>   dpu_io_util.o \
>   dpu_dbg_evtlog.o \
> - dpu_power_handle.o \
>   msm_prop.o \
>   msm_atomic.o \
>   msm_debugfs.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index 5c5cc56..33ab2ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -18,7 +18,6 @@
>  #include 
>  
>  #include "dpu_core_irq.h"
> -#include "dpu_power_handle.h"
>  
>  /**
>   * dpu_core_irq_callback_handler - dispatch core interrupts
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index 2cf3fca..d3a1ed9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -257,7 +257,6 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms 
> *kms,
>   = dpu_crtc_get_client_type(crtc);
>   struct drm_crtc *tmp_crtc;
>   struct dpu_crtc_state *dpu_cstate;
> - struct msm_drm_private *priv = kms->dev->dev_private;
>  
>   drm_for_each_crtc(tmp_crtc, crtc->dev) {
>   if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
> @@ -287,7 +286,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms 
> *kms,
>  
>   switch (curr_client_type) {
>   case NRT_CLIENT:
> - dpu_power_data_bus_set_quota(>phandle, kms->core_client,
> + dpu_power_data_bus_set_quota(>phandle, kms->core_client,
>   DPU_POWER_HANDLE_DATA_BUS_CLIENT_NRT,
>   bus_id, bus_ab_quota, bus_ib_quota);
>   DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "nrt",
> @@ -295,7 +294,7 @@ static void _dpu_core_perf_crtc_update_bus(struct dpu_kms 
> *kms,
>   break;
>  
>   case RT_CLIENT:
> - dpu_power_data_bus_set_quota(>phandle, kms->core_client,
> + dpu_power_data_bus_set_quota(>phandle, kms->core_client,
>   DPU_POWER_HANDLE_DATA_BUS_CLIENT_RT,
>   bus_id, bus_ab_quota, bus_ib_quota);
>   DPU_DEBUG("client:%s bus_id=%d ab=%llu ib=%llu\n", "rt",
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index e2d2e32..99c5e75 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dp

Re: [Freedreno] [DPU PATCH v2 10/12] drm/msm/dpu: use runtime_pm calls in dpu_dbg

[Sean Paul]

On Fri, May 11, 2018 at 08:19:36PM +0530, Rajesh Yadav wrote:
> Currently, msm_drv was creating dpu_power_handle client
> which was used by dpu_dbg module to enable power resources
> before register debug dumping.
> 
> Now since, the mdss core power resource handling is
> implemented via runtime_pm and same has been removed
> from dpu_power_handle. Remove dpu_power_handle dependency
> from msm_drv and use pm_runtime_get/put_sync calls from
> dpu_dbg module on dpu_mdss top level device for core,
> ahb clock and power resource management (for register access).
> 
> Changes in v2:
>   - resolved conflict in dpu_core_perf_init
>   - dropped (Reviewed-by: Sean Paul) due to above change

Reviewed-by: Sean Paul <seanp...@chromium.org>

> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  7 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |  4 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |  3 +--
>  drivers/gpu/drm/msm/dpu_dbg.c | 18 +++---
>  drivers/gpu/drm/msm/dpu_dbg.h | 13 ++---
>  drivers/gpu/drm/msm/msm_drv.c | 27 
> +--
>  drivers/gpu/drm/msm/msm_drv.h |  1 -
>  7 files changed, 11 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index 5b79077..2cf3fca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -673,18 +673,11 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
>   struct drm_device *dev,
>   struct dpu_mdss_cfg *catalog,
>   struct dpu_power_handle *phandle,
> - struct dpu_power_client *pclient,
>   struct dss_clk *core_clk)
>  {
> - if (!pclient) {
> - DPU_ERROR("invalid parameters\n");
> - return -EINVAL;
> - }
> -
>   perf->dev = dev;
>   perf->catalog = catalog;
>   perf->phandle = phandle;
> - perf->pclient = pclient;
>   perf->core_clk = core_clk;
>  
>   perf->max_core_clk_rate = core_clk->max_rate;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
> index 9c1a719..cde48df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
> @@ -53,7 +53,6 @@ struct dpu_core_perf_tune {
>   * @debugfs_root: top level debug folder
>   * @catalog: Pointer to catalog configuration
>   * @phandle: Pointer to power handler
> - * @pclient: Pointer to power client
>   * @core_clk: Pointer to core clock structure
>   * @core_clk_rate: current core clock rate
>   * @max_core_clk_rate: maximum allowable core clock rate
> @@ -68,7 +67,6 @@ struct dpu_core_perf {
>   struct dentry *debugfs_root;
>   struct dpu_mdss_cfg *catalog;
>   struct dpu_power_handle *phandle;
> - struct dpu_power_client *pclient;
>   struct dss_clk *core_clk;
>   u64 core_clk_rate;
>   u64 max_core_clk_rate;
> @@ -115,14 +113,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
>   * @dev: Pointer to drm device
>   * @catalog: Pointer to catalog
>   * @phandle: Pointer to power handle
> - * @pclient: Pointer to power client
>   * @core_clk: pointer to core clock
>   */
>  int dpu_core_perf_init(struct dpu_core_perf *perf,
>   struct drm_device *dev,
>   struct dpu_mdss_cfg *catalog,
>   struct dpu_power_handle *phandle,
> - struct dpu_power_client *pclient,
>   struct dss_clk *core_clk);
>  
>  /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 349bda5..9c3b220 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1721,8 +1721,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>  #endif
>  
>   rc = dpu_core_perf_init(_kms->perf, dev, dpu_kms->catalog,
> - >phandle, priv->pclient,
> - _dpu_kms_get_clk(dpu_kms, "core_clk"));
> + >phandle, _dpu_kms_get_clk(dpu_kms, "core_clk"));
>   if (rc) {
>   DPU_ERROR("failed to init perf %d\n", rc);
>   goto perf_err;
> diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
> index 4a39b82..27538bc 100644
> --- a/drivers/gpu/drm/msm/dpu_dbg.c
> +++ b/drivers/gpu/drm/msm/dpu_dbg.c
> @@ -2

Re: [Freedreno] [DPU PATCH v2 08/12] drm/msm/dpu: remove power management code from dpu_power_handle

[Sean Paul]

On Fri, May 11, 2018 at 08:19:34PM +0530, Rajesh Yadav wrote:
> Mdss main power supply (mdss_gdsc) is implemented as a
> generic power domain and mdss top level wrapper device
> manage it via runtime_pm. Remove custom power management
> code from dpu_power_handle.
> 
> Changes in v2:
>   - resolved merge conflict in dpu_power_resource_init
>   - dropped (Reviewed-by: Sean Paul) due to above change
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dpu_power_handle.c | 194 
> +
>  drivers/gpu/drm/msm/dpu_power_handle.h |   2 -
>  2 files changed, 3 insertions(+), 193 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dpu_power_handle.c 
> b/drivers/gpu/drm/msm/dpu_power_handle.c
> index 12602ae..77be106 100644
> --- a/drivers/gpu/drm/msm/dpu_power_handle.c
> +++ b/drivers/gpu/drm/msm/dpu_power_handle.c

/snip

> @@ -614,33 +470,18 @@ int dpu_power_resource_init(struct platform_device 
> *pdev,
>   struct dpu_power_handle *phandle)
>  {
>   int rc = 0, i;
> - struct dss_module_power *mp;
>  
>   if (!phandle || !pdev) {

Can this ever happen? It seems like another case of unnecessary checking.

Aside from this,

Reviewed-by: Sean Paul <seanp...@chromium.org>


>   pr_err("invalid input param\n");
> - rc = -EINVAL;
> - goto end;
> - }
> - mp = >mp;
> - phandle->dev = >dev;
> -
> - rc = dpu_power_parse_dt_supply(pdev, mp);
> - if (rc) {
> - pr_err("device vreg supply parsing failed\n");
> - return rc;
> + return -EINVAL;
>   }
>  
> - rc = msm_dss_config_vreg(>dev,
> - mp->vreg_config, mp->num_vreg, 1);
> - if (rc) {
> - pr_err("vreg config failed rc=%d\n", rc);
> - goto vreg_err;
> - }
> + phandle->dev = >dev;
>  
>   rc = dpu_power_reg_bus_parse(pdev, phandle);
>   if (rc) {
>   pr_err("register bus parse failed rc=%d\n", rc);
> - goto bus_err;
> + return rc;
>   }
>  
>   for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
> @@ -666,19 +507,12 @@ int dpu_power_resource_init(struct platform_device 
> *pdev,
>   for (i--; i >= 0; i--)
>   dpu_power_data_bus_unregister(>data_bus_handle[i]);
>   dpu_power_reg_bus_unregister(phandle->reg_bus_hdl);
> -bus_err:
> - msm_dss_config_vreg(>dev, mp->vreg_config, mp->num_vreg, 0);
> -vreg_err:
> - if (mp->vreg_config)
> - devm_kfree(>dev, mp->vreg_config);
> - mp->num_vreg = 0;
>   return rc;
>  }
>  
>  void dpu_power_resource_deinit(struct platform_device *pdev,
>   struct dpu_power_handle *phandle)
>  {
> - struct dss_module_power *mp;
>   struct dpu_power_client *curr_client, *next_client;
>   struct dpu_power_event *curr_event, *next_event;
>   int i;
> @@ -687,7 +521,6 @@ void dpu_power_resource_deinit(struct platform_device 
> *pdev,
>   pr_err("invalid input param\n");
>   return;
>   }
> - mp = >mp;
>  
>   mutex_lock(>phandle_lock);
>   list_for_each_entry_safe(curr_client, next_client,
> @@ -713,13 +546,6 @@ void dpu_power_resource_deinit(struct platform_device 
> *pdev,
>   dpu_power_data_bus_unregister(>data_bus_handle[i]);
>  
>   dpu_power_reg_bus_unregister(phandle->reg_bus_hdl);
> -
> - msm_dss_config_vreg(>dev, mp->vreg_config, mp->num_vreg, 0);
> -
> - if (mp->vreg_config)
> - devm_kfree(>dev, mp->vreg_config);
> -
> - mp->num_vreg = 0;
>  }
>  
>  int dpu_power_resource_enable(struct dpu_power_handle *phandle,
> @@ -729,15 +555,12 @@ int dpu_power_resource_enable(struct dpu_power_handle 
> *phandle,
>   bool changed = false;
>   u32 max_usecase_ndx = VOTE_INDEX_DISABLE, prev_usecase_ndx;
>   struct dpu_power_client *client;
> - struct dss_module_power *mp;
>  
>   if (!phandle || !pclient) {
>   pr_err("invalid input argument\n");
>   return -EINVAL;
>   }
>  
> - mp = >mp;
> -
>   mutex_lock(>phandle_lock);
>   if (enable)
>   pclient->refcount++;
> @@ -782,13 +605,6 @@ int dpu_power_resource_enable(struct dpu_power_handle 
> *phandle,
>   }
>   }
>  
> - rc = msm_dss_enable_vreg(mp->vreg_config, mp->num

Re: [Freedreno] [DPU PATCH v2 07/12] drm/msm/dpu: remove clock management code from dpu_power_handle

[Sean Paul]

On Fri, May 11, 2018 at 08:19:33PM +0530, Rajesh Yadav wrote:
> MDSS and dpu drivers manage their respective clocks via
> runtime_pm. Remove custom clock management code from
> dpu_power_handle.
> 
> Also dpu core clock management code is restricted to
> dpu_core_perf module.
> 
> Changes in v2:
>   - remove local variable to hold and return error code
> in _dpu_core_perf_set_core_clk_rate() instead return
> retcode directly from msm_dss_clk_set_rate() call (Sean Paul)
>   - dpu_core_perf_init() is called from dpu_kms_hw_init() and
> most of the params passed are already validated so remove
> redundant checks from dpu_core_perf_init() (Sean Paul)
>   - return >clk_config[i] directly to avoid local variable
> in _dpu_kms_get_clk() (Sean Paul)
>   - invert conditional check to eliminate local rate variable
> from dpu_kms_get_clk_rate() (Sean Paul)
>   - remove end label from dpu_power_resource_init() and return
> directly on dpu_power_parse_dt_supply() failure as no cleanup
> is needed (Sean Paul)
>   - remove checks for vtotal and vrefresh from
> dpu_encoder_phys_cmd_tearcheck_config() as they should be
> valid in mode_set call (Sean Paul)
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c  |  41 ++---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h  |   8 +-
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   9 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  28 ++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   9 +
>  drivers/gpu/drm/msm/dpu_power_handle.c | 196 
> +
>  drivers/gpu/drm/msm/dpu_power_handle.h |  40 -
>  7 files changed, 63 insertions(+), 268 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index 981f77f..5b79077 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -365,6 +365,17 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc)
>   }
>  }
>  
> +static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
> +{
> + struct dss_clk *core_clk = kms->perf.core_clk;
> +
> + if (core_clk->max_rate && (rate > core_clk->max_rate))
> + rate = core_clk->max_rate;
> +
> + core_clk->rate = rate;
> + return msm_dss_clk_set_rate(core_clk, 1);
> +}
> +
>  static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
>  {
>   u64 clk_rate = kms->perf.perf_tune.min_core_clk;
> @@ -376,7 +387,8 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct 
> dpu_kms *kms)
>   dpu_cstate = to_dpu_crtc_state(crtc->state);
>   clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
>   clk_rate);
> - clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
> + clk_rate = clk_round_rate(kms->perf.core_clk->clk,
> + clk_rate);
>   }
>   }
>  
> @@ -484,15 +496,11 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
>  
>   DPU_EVT32(kms->dev, stop_req, clk_rate);
>  
> - /* Temp change to avoid crash in clk_set_rate API. */
> -#ifdef QCOM_DPU_SET_CLK
> - if (dpu_power_clk_set_rate(>phandle,
> -kms->perf.clk_name, clk_rate)) {
> + if (_dpu_core_perf_set_core_clk_rate(kms, clk_rate)) {
>   DPU_ERROR("failed to set %s clock rate %llu\n",
> - kms->perf.clk_name, clk_rate);
> + kms->perf.core_clk->clk_name, clk_rate);
>   return;
>   }
> -#endif
>  
>   kms->perf.core_clk_rate = clk_rate;
>   DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
> @@ -656,7 +664,6 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf)
>   dpu_core_perf_debugfs_destroy(perf);
>   perf->max_core_clk_rate = 0;
>   perf->core_clk = NULL;
> - perf->clk_name = NULL;
>   perf->phandle = NULL;
>   perf->catalog = NULL;
>   perf->dev = NULL;
> @@ -667,9 +674,9 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
>   struct dpu_mdss_cfg *catalog,
>   struct dpu_po

Re: [Freedreno] [DPU PATCH v2 04/12] drm/msm/dpu: create new platform driver for dpu device

[Sean Paul]

On Fri, May 11, 2018 at 08:19:30PM +0530, Rajesh Yadav wrote:
> Current MSM display controller HW matches a tree like
> hierarchy where MDSS top level wrapper is parent device
> and mdp5/dpu, dsi, dp are child devices.
> 
> Each child device like mdp5, dsi etc. have a separate driver,
> but currently dpu handling is tied to a single driver which
> was managing both mdss and dpu resources.
> 
> Inorder to have the cleaner one to one device and driver
> association, this change adds a new platform_driver for dpu
> child device node which implements the kms functionality.
> 
> The dpu driver implements runtime_pm support for managing clocks
> and bus bandwidth etc.
> 
> Changes in v2:
>   - remove redundant param check from _dpu_kms_hw_destroy (Sean Paul)
>   - remove explicit calls to devm_kfree (Sean Paul)
>   - merge dpu_init into dpu_bind (Sean Paul)
>   - merge dpu_destroy into dpu_unbind (Sean Paul)
>   - use %pK for kernel pointer printing (Jordan Crouse)
>   - remove explicit devm allocation failure message (Jordan Crouse)
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 238 
> +---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |   4 +
>  drivers/gpu/drm/msm/msm_drv.c   |   2 +
>  drivers/gpu/drm/msm/msm_drv.h   |   3 +
>  4 files changed, 196 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index e4ab753..85f3dbc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1030,16 +1030,12 @@ static long dpu_kms_round_pixclk(struct msm_kms *kms, 
> unsigned long rate,
>   return rate;
>  }
>  
> -static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms,
> - struct platform_device *pdev)
> +static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
>  {
>   struct drm_device *dev;
>   struct msm_drm_private *priv;
>   int i;
>  
> - if (!dpu_kms || !pdev)
> - return;
> -
>   dev = dpu_kms->dev;
>   if (!dev)
>   return;
> @@ -1091,15 +1087,15 @@ static void _dpu_kms_hw_destroy(struct dpu_kms 
> *dpu_kms,
>   dpu_kms->core_client = NULL;
>  
>   if (dpu_kms->vbif[VBIF_NRT])
> - msm_iounmap(pdev, dpu_kms->vbif[VBIF_NRT]);
> + msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_NRT]);
>   dpu_kms->vbif[VBIF_NRT] = NULL;
>  
>   if (dpu_kms->vbif[VBIF_RT])
> - msm_iounmap(pdev, dpu_kms->vbif[VBIF_RT]);
> + msm_iounmap(dpu_kms->pdev, dpu_kms->vbif[VBIF_RT]);
>   dpu_kms->vbif[VBIF_RT] = NULL;
>  
>   if (dpu_kms->mmio)
> - msm_iounmap(pdev, dpu_kms->mmio);
> + msm_iounmap(dpu_kms->pdev, dpu_kms->mmio);
>   dpu_kms->mmio = NULL;
>  
>   dpu_reg_dma_deinit();
> @@ -1172,8 +1168,6 @@ int dpu_kms_mmu_attach(struct dpu_kms *dpu_kms, bool 
> secure_only)
>  static void dpu_kms_destroy(struct msm_kms *kms)
>  {
>   struct dpu_kms *dpu_kms;
> - struct drm_device *dev;
> - struct platform_device *platformdev;
>  
>   if (!kms) {
>   DPU_ERROR("invalid kms\n");
> @@ -1181,20 +1175,7 @@ static void dpu_kms_destroy(struct msm_kms *kms)
>   }
>  
>   dpu_kms = to_dpu_kms(kms);
> - dev = dpu_kms->dev;
> - if (!dev) {
> - DPU_ERROR("invalid device\n");
> - return;
> - }
> -
> - platformdev = to_platform_device(dev->dev);
> - if (!platformdev) {
> - DPU_ERROR("invalid platform device\n");
> - return;
> - }
> -
> - _dpu_kms_hw_destroy(dpu_kms, platformdev);
> - kfree(dpu_kms);
> + _dpu_kms_hw_destroy(dpu_kms);
>  }
>  
>  static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file *file)
> @@ -1550,7 +1531,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>   struct dpu_kms *dpu_kms;
>   struct drm_device *dev;
>   struct msm_drm_private *priv;
> - struct platform_device *platformdev;
>   int i, rc = -EINVAL;
>  
>   if (!kms) {
> @@ -1565,34 +1545,28 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>   goto end;
>   }
>  
> - platformdev = to_platform_device(dev->dev);
> - if (!platformdev) {
> - DPU_ERROR("invalid platform device\n");
> - goto end;
> - }
>

Re: [Freedreno] [DPU PATCH v2 03/12] drm/msm/dpu: add MDSS top level driver for dpu

[Sean Paul]

On Fri, May 11, 2018 at 08:19:29PM +0530, Rajesh Yadav wrote:
> SoCs containing dpu have a MDSS top level wrapper
> which includes sub-blocks as dpu, dsi, phy, dp etc.
> MDSS top level wrapper manages common resources like
> common clocks, power and irq for its sub-blocks.
> 
> Currently, in dpu driver, all the power resource
> management is part of power_handle which manages
> these resources via a custom implementation. And
> the resource relationships are not modelled properly
> in dt.  Moreover the irq domain handling code is part
> of dpu device (which is a child device) due to lack
> of a dedicated driver for MDSS top level wrapper
> device.
> 
> This change adds dpu_mdss top level driver to handle
> common clock like - core clock, ahb clock
> (for register access), main power supply (i.e. gdsc)
> and irq management.
> The top level mdss device/driver acts as an interrupt
> controller and manage hwirq mapping for its child
> devices.
> 
> It implements runtime_pm support for resource management.
> Child nodes can control these resources via runtime_pm
> get/put calls on their corresponding devices due to parent
> child relationship defined in dt.
> 
> Changes in v2:
>   - merge _dpu_mdss_hw_rev_init to dpu_mdss_init (Sean Paul)
>   - merge _dpu_mdss_get_intr_sources to dpu_mdss_irq (Sean Paul)
>   - fix indentation for irq_find_mapping call (Sean Paul)
>   - remove unnecessary goto statements from dpu_mdss_irq (Sean Paul)
>   - remove redundant param checks from
> dpu_mdss_irq_mask/unmask (Sean Paul/Jordan Crouse)
>   - remove redundant param checks from
> dpu_mdss_irqdomain_map (Sean Paul/Jordan Crouse)
>   - return error code from dpu_mdss_enable/disable (Sean Paul/Jordan 
> Crouse)
>   - remove redundant param check from dpu_mdss_destroy (Sean Paul)
>   - remove explicit calls to devm_kfree (Sean Paul/Jordan Crouse)
>   - remove compatibility check from dpu_mdss_init as
> it is conditionally called from msm_drv (Sean Paul)
>   - reworked msm_dss_parse_clock() to add return checks for
> of_property_read_* calls, fix log message and
> fix alignment issues (Sean Paul/Jordan Crouse)
>   - remove extra line before dpu_mdss_init (Sean Paul)
>   - remove redundant param checks from __intr_offset and
> make it a void function to avoid unnecessary error
> handling from caller (Jordan Crouse)
>   - remove redundant param check from dpu_mdss_irq (Jordan Crouse)
>   - change mdss address space log message to debug and use %pK for
> kernel pointers (Jordan Crouse)
>   - remove unnecessary log message from msm_dss_parse_clock (Jordan 
> Crouse)
>   - don't export msm_dss_parse_clock since it is used
> only by dpu driver (Jordan Crouse)
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/Makefile  |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  97 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h  |  14 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|   9 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   7 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |  28 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  11 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c   |  48 +---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   6 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c  | 254 
> ++
>  drivers/gpu/drm/msm/dpu_io_util.c |  57 +
>  drivers/gpu/drm/msm/msm_drv.c |  26 ++-
>  drivers/gpu/drm/msm/msm_drv.h |   2 +-
>  drivers/gpu/drm/msm/msm_kms.h |   1 +
>  include/linux/dpu_io_util.h   |   2 +
>  16 files changed, 339 insertions(+), 226 deletions(-)
>  create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> 

/snip

> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> new file mode 100644
> index 000..ce680ea
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

/snip

> +
> +int dpu_mdss_init(struct drm_device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev->dev);
> + struct msm_drm_private *priv = dev->dev_private;
> + struct dpu_mdss *dpu_mdss;
> + struct dss_module_power *mp;
> + int ret = 0;
> +
> + dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
> + if (!dpu_mdss)
> + return -ENOMEM;
> +
> + dpu_mdss-

Re: [Freedreno] [DPU PATCH 11/11] drm/msm/dpu: move dpu_power_handle to dpu folder

[Sean Paul]

On Thu, May 10, 2018 at 01:59:45PM +0530, Rajesh Yadav wrote:
> Now, since dpu_power_handle manages only bus scaling
> and power enable/disable notifications which are restricted
> to dpu driver, move dpu_power_handle to dpu folder.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/Makefile |   2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c|   5 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c |   7 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   2 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  39 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h  |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 694 
> +++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 288 ++
>  drivers/gpu/drm/msm/dpu_power_handle.c   | 694 
> ---
>  drivers/gpu/drm/msm/dpu_power_handle.h   | 288 --
>  drivers/gpu/drm/msm/msm_drv.c|   9 -
>  drivers/gpu/drm/msm/msm_drv.h|   4 -
>  14 files changed, 1014 insertions(+), 1021 deletions(-)
>  create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
>  create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
>  delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.c
>  delete mode 100644 drivers/gpu/drm/msm/dpu_power_handle.h
> 



> @@ -1863,6 +1863,12 @@ static int dpu_init(struct platform_device *pdev, 
> struct drm_device *dev)
>   goto clk_rate_error;
>   }
>  
> + ret = dpu_power_resource_init(pdev, _kms->phandle);
> + if (ret) {
> + pr_err("dpu power resource init failed\n");
> + goto power_init_fail;
> + }
> +
>   platform_set_drvdata(pdev, dpu_kms);
>  
>   msm_kms_init(_kms->base, _funcs);
> @@ -1876,6 +1882,7 @@ static int dpu_init(struct platform_device *pdev, 
> struct drm_device *dev)
>  
>   return ret;
>  
> +power_init_fail:

Nit: No need to add an empty label, just use clk_rate_error above.

With that fixed,

Reviewed-by: Sean Paul <seanp...@chromium.org>


>  clk_rate_error:
>   msm_dss_put_clk(mp->clk_config, mp->num_clk);
>  clk_get_error:



-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [DPU PATCH 10/11] drm/msm/dpu: use runtime_pm calls in dpu_dbg

[Sean Paul]

On Thu, May 10, 2018 at 01:59:44PM +0530, Rajesh Yadav wrote:
> Currently, msm_drv was creating dpu_power_handle client
> which was used by dpu_dbg module to enable power resources
> before register debug dumping.
> 
> Now since, the mdss core power resource handling is
> implemented via runtime_pm and same has been removed
> from dpu_power_handle. Remove dpu_power_handle dependency
> from msm_drv and use pm_runtime_get/put_sync calls from
> dpu_dbg module on dpu_mdss top level device for core,
> ahb clock and power resource management (for register access).
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  4 +---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |  4 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |  3 +--
>  drivers/gpu/drm/msm/dpu_dbg.c | 18 +++---
>  drivers/gpu/drm/msm/dpu_dbg.h | 13 ++---
>  drivers/gpu/drm/msm/msm_drv.c | 27 
> +--
>  drivers/gpu/drm/msm/msm_drv.h |  1 -
>  7 files changed, 12 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index d1364fa..e2e7c06 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -676,10 +676,9 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
>   struct drm_device *dev,
>   struct dpu_mdss_cfg *catalog,
>   struct dpu_power_handle *phandle,
> - struct dpu_power_client *pclient,
>   struct dss_clk *core_clk)
>  {
> - if (!perf || !dev || !catalog || !phandle || !pclient || !core_clk) {
> + if (!perf || !dev || !catalog || !phandle || !core_clk) {
>   DPU_ERROR("invalid parameters\n");
>   return -EINVAL;
>   }
> @@ -687,7 +686,6 @@ int dpu_core_perf_init(struct dpu_core_perf *perf,
>   perf->dev = dev;
>   perf->catalog = catalog;
>   perf->phandle = phandle;
> - perf->pclient = pclient;
>   perf->core_clk = core_clk;
>  
>   perf->max_core_clk_rate = core_clk->max_rate;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
> index 9c1a719..cde48df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
> @@ -53,7 +53,6 @@ struct dpu_core_perf_tune {
>   * @debugfs_root: top level debug folder
>   * @catalog: Pointer to catalog configuration
>   * @phandle: Pointer to power handler
> - * @pclient: Pointer to power client
>   * @core_clk: Pointer to core clock structure
>   * @core_clk_rate: current core clock rate
>   * @max_core_clk_rate: maximum allowable core clock rate
> @@ -68,7 +67,6 @@ struct dpu_core_perf {
>   struct dentry *debugfs_root;
>   struct dpu_mdss_cfg *catalog;
>   struct dpu_power_handle *phandle;
> - struct dpu_power_client *pclient;
>   struct dss_clk *core_clk;
>   u64 core_clk_rate;
>   u64 max_core_clk_rate;
> @@ -115,14 +113,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
>   * @dev: Pointer to drm device
>   * @catalog: Pointer to catalog
>   * @phandle: Pointer to power handle
> - * @pclient: Pointer to power client
>   * @core_clk: pointer to core clock
>   */
>  int dpu_core_perf_init(struct dpu_core_perf *perf,
>   struct drm_device *dev,
>   struct dpu_mdss_cfg *catalog,
>   struct dpu_power_handle *phandle,
> - struct dpu_power_client *pclient,
>   struct dss_clk *core_clk);
>  
>  /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index f6511c9..67bef32 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1728,8 +1728,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
>  #endif
>  
>   rc = dpu_core_perf_init(_kms->perf, dev, dpu_kms->catalog,
> - >phandle, priv->pclient,
> - _dpu_kms_get_clk(dpu_kms, "core_clk"));
> + >phandle, _dpu_kms_get_clk(dpu_kms, "core_clk"));
>   if (rc) {
>   DPU_ERROR("failed to init perf %d\n", rc);
>   goto perf_err;
> diff --git a/drivers/gpu/drm/msm/dpu_dbg.c b/drivers/gpu/drm/msm/dpu_dbg.c
> index 4a39b82..27538bc 100644
> --- a/drivers/gpu/drm/msm/dpu_dbg.c
> +++ b/

Re: [Freedreno] [DPU PATCH 09/11] drm/msm/dp: remove dpu_power_handle calls from dp driver

[Sean Paul]

On Thu, May 10, 2018 at 01:59:43PM +0530, Rajesh Yadav wrote:
> DP driver was dependent on dpu_power_handle for MDSS
> common clocks and gdsc (main power supply).
> The common clocks and power is managed by MDSS top
> wrapper device now which is parent of all sub-devices
> like DP device.
> For same reason, clock and power management code is
> removed from dpu_power_handle. Hence, remove the
> dpu_power_handle calls from dp driver.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/dp/dp_power.c | 32 +---
>  drivers/gpu/drm/msm/dp/dp_power.h |  4 +---
>  2 files changed, 2 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dp/dp_power.c 
> b/drivers/gpu/drm/msm/dp/dp_power.c
> index f6e341b..2a85b38 100644
> --- a/drivers/gpu/drm/msm/dp/dp_power.c
> +++ b/drivers/gpu/drm/msm/dp/dp_power.c
> @@ -26,8 +26,6 @@ struct dp_power_private {
>   struct clk *pixel_parent;
>  
>   struct dp_power dp_power;
> - struct dpu_power_client *dp_core_client;
> - struct dpu_power_handle *phandle;
>  
>   bool core_clks_on;
>   bool link_clks_on;
> @@ -410,8 +408,7 @@ static int dp_power_config_gpios(struct dp_power_private 
> *power, bool flip,
>   return 0;
>  }
>  
> -static int dp_power_client_init(struct dp_power *dp_power,
> - struct dpu_power_handle *phandle)
> +static int dp_power_client_init(struct dp_power *dp_power)
>  {
>   int rc = 0;
>   struct dp_power_private *power;
> @@ -436,19 +433,8 @@ static int dp_power_client_init(struct dp_power 
> *dp_power,
>   goto error_clk;
>   }
>  
> - power->phandle = phandle;
> - snprintf(dp_client_name, DP_CLIENT_NAME_SIZE, "dp_core_client");
> - power->dp_core_client = dpu_power_client_create(phandle,
> - dp_client_name);
> - if (IS_ERR_OR_NULL(power->dp_core_client)) {
> - pr_err("[%s] client creation failed for DP", dp_client_name);
> - rc = -EINVAL;
> - goto error_client;
> - }
>   return 0;
>  
> -error_client:
> - dp_power_clk_init(power, false);
>  error_clk:
>   dp_power_regulator_deinit(power);
>  error_power:
> @@ -466,7 +452,6 @@ static void dp_power_client_deinit(struct dp_power 
> *dp_power)
>  
>   power = container_of(dp_power, struct dp_power_private, dp_power);
>  
> - dpu_power_client_destroy(power->phandle, power->dp_core_client);
>   dp_power_clk_init(power, false);
>   dp_power_regulator_deinit(power);
>  }
> @@ -521,13 +506,6 @@ static int dp_power_init(struct dp_power *dp_power, bool 
> flip)
>   goto err_gpio;
>   }
>  
> - rc = dpu_power_resource_enable(power->phandle,
> - power->dp_core_client, true);
> - if (rc) {
> - pr_err("Power resource enable failed\n");
> - goto err_dpu_power;
> - }
> -
>   rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true);
>   if (rc) {
>   pr_err("failed to enable DP core clocks\n");
> @@ -537,8 +515,6 @@ static int dp_power_init(struct dp_power *dp_power, bool 
> flip)
>   return 0;
>  
>  err_clk:
> - dpu_power_resource_enable(power->phandle, power->dp_core_client, false);
> -err_dpu_power:
>   dp_power_config_gpios(power, flip, false);
>  err_gpio:
>   dp_power_pinctrl_set(power, false);
> @@ -562,12 +538,6 @@ static int dp_power_deinit(struct dp_power *dp_power)
>   power = container_of(dp_power, struct dp_power_private, dp_power);
>  
>   dp_power_clk_enable(dp_power, DP_CORE_PM, false);
> - rc = dpu_power_resource_enable(power->phandle,
> - power->dp_core_client, false);
> - if (rc) {
> - pr_err("Power resource enable failed, rc=%d\n", rc);
> - goto exit;
> - }
>   dp_power_config_gpios(power, false, false);
>   dp_power_pinctrl_set(power, false);
>   dp_power_regulator_ctrl(power, false);
> diff --git a/drivers/gpu/drm/msm/dp/dp_power.h 
> b/drivers/gpu/drm/msm/dp/dp_power.h
> index 84fe01d..d9dab72 100644
> --- a/drivers/gpu/drm/msm/dp/dp_power.h
> +++ b/drivers/gpu/drm/msm/dp/dp_power.h
> @@ -16,7 +16,6 @@
>  #define _DP_POWER_H_
>  
>  #include "dp_parser.h"
> -#include "dpu_power_handle.h"
>  
>  /**
>   * sruct dp_power - DisplayPort's power related data
> @@ -32,8 +31,7 @@ struct dp_power {
>   int (*clk_enable)(struct dp_power *power, enum dp_pm_type pm_type,
&

Re: [Freedreno] [DPU PATCH 08/11] drm/msm/dpu: remove power management code from dpu_power_handle

[Sean Paul]

On Thu, May 10, 2018 at 01:59:42PM +0530, Rajesh Yadav wrote:
> Mdss main power supply (mdss_gdsc) is implemented as a
> generic power domain and mdss top level wrapper device
> manage it via runtime_pm. Remove custom power management
> code from dpu_power_handle.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/dpu_power_handle.c | 190 
> +
>  drivers/gpu/drm/msm/dpu_power_handle.h |   2 -
>  2 files changed, 1 insertion(+), 191 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dpu_power_handle.c 
> b/drivers/gpu/drm/msm/dpu_power_handle.c
> index 17bae4b..909fbb8 100644
> --- a/drivers/gpu/drm/msm/dpu_power_handle.c
> +++ b/drivers/gpu/drm/msm/dpu_power_handle.c
> @@ -101,150 +101,6 @@ void dpu_power_client_destroy(struct dpu_power_handle 
> *phandle,
>   }
>  }
>  
> -static int dpu_power_parse_dt_supply(struct platform_device *pdev,
> - struct dss_module_power *mp)
> -{
> - int i = 0, rc = 0;
> - u32 tmp = 0;
> - struct device_node *of_node = NULL, *supply_root_node = NULL;
> - struct device_node *supply_node = NULL;
> -
> - if (!pdev || !mp) {
> - pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
> - return -EINVAL;
> - }
> -
> - of_node = pdev->dev.of_node;
> -
> - mp->num_vreg = 0;
> - supply_root_node = of_get_child_by_name(of_node,
> - "qcom,platform-supply-entries");
> - if (!supply_root_node) {
> - pr_debug("no supply entry present\n");
> - return rc;
> - }
> -
> - for_each_child_of_node(supply_root_node, supply_node)
> - mp->num_vreg++;
> -
> - if (mp->num_vreg == 0) {
> - pr_debug("no vreg\n");
> - return rc;
> - }
> -
> - pr_debug("vreg found. count=%d\n", mp->num_vreg);
> - mp->vreg_config = devm_kzalloc(>dev, sizeof(struct dss_vreg) *
> - mp->num_vreg, GFP_KERNEL);
> - if (!mp->vreg_config) {
> - rc = -ENOMEM;
> - return rc;
> - }
> -
> - for_each_child_of_node(supply_root_node, supply_node) {
> -
> - const char *st = NULL;
> -
> - rc = of_property_read_string(supply_node,
> - "qcom,supply-name", );
> - if (rc) {
> - pr_err("error reading name. rc=%d\n", rc);
> - goto error;
> - }
> -
> - strlcpy(mp->vreg_config[i].vreg_name, st,
> - sizeof(mp->vreg_config[i].vreg_name));
> -
> - rc = of_property_read_u32(supply_node,
> - "qcom,supply-min-voltage", );
> - if (rc) {
> - pr_err("error reading min volt. rc=%d\n", rc);
> - goto error;
> - }
> - mp->vreg_config[i].min_voltage = tmp;
> -
> - rc = of_property_read_u32(supply_node,
> - "qcom,supply-max-voltage", );
> - if (rc) {
> - pr_err("error reading max volt. rc=%d\n", rc);
> - goto error;
> - }
> - mp->vreg_config[i].max_voltage = tmp;
> -
> - rc = of_property_read_u32(supply_node,
> - "qcom,supply-enable-load", );
> - if (rc) {
> - pr_err("error reading enable load. rc=%d\n", rc);
> - goto error;
> - }
> - mp->vreg_config[i].enable_load = tmp;
> -
> - rc = of_property_read_u32(supply_node,
> - "qcom,supply-disable-load", );
> - if (rc) {
> - pr_err("error reading disable load. rc=%d\n", rc);
> - goto error;
> - }
> - mp->vreg_config[i].disable_load = tmp;
> -
> - rc = of_property_read_u32(supply_node,
> - "qcom,supply-pre-on-sleep", );
> - if (rc)
> - pr_debug("error reading supply pre sleep value. 
> rc=%d\n",
> - rc);
> -
> - mp-&g

Re: [Freedreno] [DPU PATCH 07/11] drm/msm/dpu: remove clock management code from dpu_power_handle

[Sean Paul]

dev;
>  
> - rc = dpu_power_parse_dt_clock(pdev, mp);
> - if (rc) {
> - pr_err("device clock parsing failed\n");
> - goto end;
> - }
> -
>   rc = dpu_power_parse_dt_supply(pdev, mp);
>   if (rc) {
>   pr_err("device vreg supply parsing failed\n");
> - goto parse_vreg_err;
> + goto end;

Just return directly and remove the end label.

>   }
>  
>   rc = msm_dss_config_vreg(>dev,
> @@ -700,18 +637,6 @@ int dpu_power_resource_init(struct platform_device *pdev,
>   goto vreg_err;
>   }
>  
> - rc = msm_dss_get_clk(>dev, mp->clk_config, mp->num_clk);
> - if (rc) {
> - pr_err("clock get failed rc=%d\n", rc);
> - goto clk_err;
> - }
> -
> - rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
> - if (rc) {
> - pr_err("clock set rate failed rc=%d\n", rc);
> - goto bus_err;
> - }
> -
>   rc = dpu_power_reg_bus_parse(pdev, phandle);
>   if (rc) {
>   pr_err("register bus parse failed rc=%d\n", rc);
> @@ -742,17 +667,11 @@ int dpu_power_resource_init(struct platform_device 
> *pdev,
>   dpu_power_data_bus_unregister(>data_bus_handle[i]);
>   dpu_power_reg_bus_unregister(phandle->reg_bus_hdl);
>  bus_err:
> - msm_dss_put_clk(mp->clk_config, mp->num_clk);
> -clk_err:
>   msm_dss_config_vreg(>dev, mp->vreg_config, mp->num_vreg, 0);
>  vreg_err:
>   if (mp->vreg_config)
>   devm_kfree(>dev, mp->vreg_config);
>   mp->num_vreg = 0;
> -parse_vreg_err:
> - if (mp->clk_config)
> - devm_kfree(>dev, mp->clk_config);
> - mp->num_clk = 0;
>  end:
>   return rc;
>  }



-- 
Sean Paul, Software Engineer, Google / Chromium OS
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
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Re: [Freedreno] [DPU PATCH 06/11] drm/msm/dpu: use runtime_pm calls on dpu device

[Sean Paul]

On Thu, May 10, 2018 at 01:59:40PM +0530, Rajesh Yadav wrote:
> The dpu driver implements runtime_pm support for managing
> dpu specific resources like - clocks, bus bandwidth etc.
> 
> Use pm_runtime_get/put_sync calls on dpu device.
> 
> The common clocks and power management for all child nodes
> (mdp5/dpu, dsi, dp etc) is done by parent MDSS device/driver
> via runtime_pm due to parent child relationship.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c |  8 ++---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  | 16 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  | 45 
> +++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c|  6 ++--
>  5 files changed, 31 insertions(+), 56 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index 977adc4..5c5cc56 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -452,10 +452,10 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
>   }
>   priv = dpu_kms->dev->dev_private;
>  
> - dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
> + pm_runtime_get_sync(_kms->pdev->dev);
>   dpu_clear_all_irqs(dpu_kms);
>   dpu_disable_all_irqs(dpu_kms);
> - dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
> + pm_runtime_put_sync(_kms->pdev->dev);
>  
>   spin_lock_init(_kms->irq_obj.cb_lock);
>  
> @@ -496,7 +496,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
>   }
>   priv = dpu_kms->dev->dev_private;
>  
> - dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
> + pm_runtime_get_sync(_kms->pdev->dev);
>   for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
>   if (atomic_read(_kms->irq_obj.enable_counts[i]) ||
>   !list_empty(_kms->irq_obj.irq_cb_tbl[i]))
> @@ -504,7 +504,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
>  
>   dpu_clear_all_irqs(dpu_kms);
>   dpu_disable_all_irqs(dpu_kms);
> - dpu_power_resource_enable(>phandle, dpu_kms->core_client, false);
> + pm_runtime_put_sync(_kms->pdev->dev);
>  
>   kfree(dpu_kms->irq_obj.irq_cb_tbl);
>   kfree(dpu_kms->irq_obj.enable_counts);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 48920b05..e2d2e32 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -86,8 +86,12 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc 
> *dpu_crtc, bool enable)
>  
>   dpu_kms = to_dpu_kms(priv->kms);
>  
> - return dpu_power_resource_enable(>phandle, dpu_kms->core_client,
> - enable);
> + if (enable)
> + pm_runtime_get_sync(_kms->pdev->dev);
> + else
> + pm_runtime_put_sync(_kms->pdev->dev);
> +
> + return 0;
>  }
>  
>  /**
> @@ -2250,7 +2254,6 @@ static int _dpu_crtc_vblank_enable_no_lock(
>  
>   /* drop lock since power crtc cb may try to re-acquire lock */
>   mutex_unlock(_crtc->crtc_lock);
> - pm_runtime_get_sync(dev->dev);
>   ret = _dpu_crtc_power_enable(dpu_crtc, true);
>   mutex_lock(_crtc->crtc_lock);
>   if (ret)
> @@ -2580,7 +2583,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>   /* disable clk & bw control until clk & bw properties are set */
>   cstate->bw_control = false;
>   cstate->bw_split_vote = false;
> - pm_runtime_put_sync(crtc->dev->dev);
>  
>   mutex_unlock(_crtc->crtc_lock);
>  }
> @@ -2611,8 +2613,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
>   return;
>   }
>  
> - pm_runtime_get_sync(crtc->dev->dev);
> -
>   drm_for_each_encoder(encoder, crtc->dev) {
>   if (encoder->crtc != crtc)
>   continue;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 4386360..298a6ef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -268,8 +268,12 @@ static inline int _dpu_encoder_power_enable(struct 
>

Re: [Freedreno] [DPU PATCH 05/11] drm/msm/dpu: update dpu sub-block offsets wrt dpu base address

[Sean Paul]

On Thu, May 10, 2018 at 01:59:39PM +0530, Rajesh Yadav wrote:
> The dpu sub-block offsets were defined wrt mdss base address
> instead of dpu base address.
> Since, dpu is now defined as a separate device, update hw catalog
> offsets for all dpu sub blocks wrt dpu base address.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 68 
> +++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
>  2 files changed, 43 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index c5b370f..2fd3254 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -80,7 +80,7 @@
>  static struct dpu_mdp_cfg sdm845_mdp[] = {
>   {
>   .name = "top_0", .id = MDP_TOP,
> - .base = 0x1000, .len = 0x45C,
> + .base = 0x0, .len = 0x45C,
>   .features = 0,
>   .highest_bank_bit = 0x2,
>   .has_dest_scaler = true,
> @@ -111,27 +111,27 @@
>  static struct dpu_ctl_cfg sdm845_ctl[] = {
>   {
>   .name = "ctl_0", .id = CTL_0,
> - .base = 0x2000, .len = 0xE4,
> + .base = 0x1000, .len = 0xE4,
>   .features = BIT(DPU_CTL_SPLIT_DISPLAY)
>   },
>   {
>   .name = "ctl_1", .id = CTL_1,
> - .base = 0x2200, .len = 0xE4,
> + .base = 0x1200, .len = 0xE4,
>   .features = BIT(DPU_CTL_SPLIT_DISPLAY)
>   },
>   {
>   .name = "ctl_2", .id = CTL_2,
> - .base = 0x2400, .len = 0xE4,
> + .base = 0x1400, .len = 0xE4,
>   .features = 0
>   },
>   {
>   .name = "ctl_3", .id = CTL_3,
> - .base = 0x2600, .len = 0xE4,
> + .base = 0x1600, .len = 0xE4,
>   .features = 0
>   },
>   {
>   .name = "ctl_4", .id = CTL_4,
> - .base = 0x2800, .len = 0xE4,
> + .base = 0x1800, .len = 0xE4,
>   .features = 0
>   },
>  };
> @@ -211,21 +211,21 @@
>   }
>  
>  static struct dpu_sspp_cfg sdm845_sspp[] = {
> - SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
> + SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
>   sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
> - SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
> + SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
>   sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
> - SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
> + SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
>   sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
> - SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
> + SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
>   sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
> - SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
> + SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
>   sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
> - SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
> + SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
>   sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
> - SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
> + SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
>   sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
> - SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
> + SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
>   sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
>  };
>  
> @@ -252,17 +252,17 @@
>   .lm_pair_mask = (1 << _lmpair) \
>   }
>  static struct dpu_lm_cfg sdm845_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
> + LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
>   DS_0, PINGPONG_0, LM_1),
> - LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
> + LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
>   DS_1, PINGPONG_1, LM_0),
> - LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
> + LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
>   DS_MAX, PINGPONG_2, LM_5),
>   LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
>   DS_MAX, PINGPONG_MAX, 0),
>   LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
>   DS_MAX, PINGPONG_MAX, 0),
> - LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
> + LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
>   DS_MAX, PINGPONG_3, LM_2),
>  };
>  
> @@ -270,7 +270,7 @@
>   * DSPP sub blocks config
>   ***

Re: [Freedreno] [DPU PATCH 01/11] drm/msm: remove redundant pm_runtime_enable call from msm_drv

[Sean Paul]

On Thu, May 10, 2018 at 01:59:35PM +0530, Rajesh Yadav wrote:
> MDSS top level device includes the common power resources
> and it's corresponding driver (i.e. mdp5_mdss) handles call
> to enable/disable runtime_pm for enabling these resources.
> Remove redundant pm_runtime_enable call from msm_drv.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/msm_drv.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index ebc40a9..9bb436f 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -581,7 +581,6 @@ static int msm_drm_init(struct device *dev, struct 
> drm_driver *drv)
>   goto fail;
>   }
>   priv->kms = kms;
> - pm_runtime_enable(dev);
>  
>   /**
>* Since kms->funcs->hw_init(kms) might call
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [Freedreno] [DPU PATCH 04/11] drm/msm/dpu: create new platform driver for dpu device

[Sean Paul]

v.c
> @@ -1731,6 +1731,7 @@ static int __init msm_drm_register(void)
>  
>   DBG("init");
>   msm_mdp_register();
> + msm_dpu_register();
>   msm_dsi_register();
>   msm_edp_register();
>   msm_hdmi_register();
> @@ -1747,6 +1748,7 @@ static void __exit msm_drm_unregister(void)
>   msm_edp_unregister();
>   msm_dsi_unregister();
>   msm_mdp_unregister();
> + msm_dpu_unregister();
>  }
>  
>  module_init(msm_drm_register);
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e8e5e73..22a3096 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -682,6 +682,9 @@ static inline int msm_dsi_modeset_init(struct msm_dsi 
> *msm_dsi,
>  void __init msm_mdp_register(void);
>  void __exit msm_mdp_unregister(void);
>  
> +void __init msm_dpu_register(void);
> +void __exit msm_dpu_unregister(void);
> +
>  #ifdef CONFIG_DEBUG_FS
>  void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
>  void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [Freedreno] [DPU PATCH 03/11] drm/msm/dpu: add MDSS top level driver for dpu

[Sean Paul]

e not defined\n");

what's up with pr_err/*debug*/ ?

> + goto clk_err;
> + }
> +
> + mp->num_clk = num_clk;
> + mp->clk_config = devm_kzalloc(>dev,
> + sizeof(struct dss_clk) * num_clk, GFP_KERNEL);
> + if (!mp->clk_config) {
> + rc = -ENOMEM;
> + mp->num_clk = 0;

Just do the mp->num_clk assignment below this conditional, then you don't need
to reset it.

> + goto clk_err;
> + }
> +
> + for (i = 0; i < num_clk; i++) {
> + of_property_read_string_index(pdev->dev.of_node, "clock-names",

Check the return value

> + i, _name);

Align with the other arguments.

> + strlcpy(mp->clk_config[i].clk_name, clock_name,
> + sizeof(mp->clk_config[i].clk_name));

alignment

> +
> + of_property_read_u32_index(pdev->dev.of_node, "clock-rate",

Check the return value

> + i, _rate);

alignment

> + mp->clk_config[i].rate = clock_rate;
> +
> + if (!clock_rate)
> + mp->clk_config[i].type = DSS_CLK_AHB;
> + else
> + mp->clk_config[i].type = DSS_CLK_PCLK;
> +
> + clock_max_rate = 0;

Instead of re-initializing this every loop, you could have just scoped it
properly. At any rate, you can just pass mp->clk_config[i].max_rate directly
since the value is only written on success.

> + of_property_read_u32_index(pdev->dev.of_node, "clock-max-rate",

Check return.

> + i, _max_rate);

alignment

> + mp->clk_config[i].max_rate = clock_max_rate;
> + }
> +
> +clk_err:
> + return rc;

No need for this label, just return directly.

> +}
> +EXPORT_SYMBOL(msm_dss_parse_clock);
>  
>  int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
>   uint8_t reg_offset, uint8_t *read_buf)
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index 5d8f1b6..a0e73ea 100644
> --- a/drivers/gpu/drm/msm/msm_drv.c
> +++ b/drivers/gpu/drm/msm/msm_drv.c
> @@ -503,7 +503,18 @@ static int msm_drm_init(struct device *dev, struct 
> drm_driver *drv)
>   ddev->dev_private = priv;
>   priv->dev = ddev;
>  
> - ret = mdp5_mdss_init(ddev);
> + switch (get_mdp_ver(pdev)) {
> + case KMS_MDP5:
> + ret = mdp5_mdss_init(ddev);
> + break;
> + case KMS_DPU:
> + ret = dpu_mdss_init(ddev);
> + break;
> + default:
> + ret = 0;
> + break;
> + }
> +
>   if (ret)
>   goto mdss_init_fail;
>  
> @@ -1539,12 +1550,13 @@ static int add_display_components(struct device *dev,
>   int ret;
>  
>   /*
> -  * MDP5 based devices don't have a flat hierarchy. There is a top level
> -  * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
> -  * children devices, find the MDP5 node, and then add the interfaces
> -  * to our components list.
> +  * MDP5/DPU based devices don't have a flat hierarchy. There is a top
> +  * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
> +  * Populate the children devices, find the MDP5/DPU node, and then add
> +  * the interfaces to our components list.
>*/
> - if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {
> + if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
> + of_device_is_compatible(dev->of_node, "qcom,dpu-mdss")) {

Align with the previous condition, ie:

if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
of_device_is_compatible(dev->of_node, "qcom,dpu-mdss")) {


>   ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
>   if (ret) {
>   dev_err(dev, "failed to populate children devices\n");
> @@ -1686,7 +1698,7 @@ static int msm_pdev_remove(struct platform_device *pdev)
>   { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
>   { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
>  #ifdef CONFIG_DRM_MSM_DPU
> - { .compatible = "qcom,dpu-kms", .data = (void *)KMS_DPU },
> + { .compatible = "qcom,dpu-mdss", .data = (void *)KMS_DPU },

This requires a dt binding change.

>  #endif
>   {}
>  };
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 90a2521..e8e5e73 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -381,7 +381,7 @@ struct msm_drm_private {
>   /* subordinate devices, if present: */
>   struct platform_device *gpu_pdev;
>  
> - /* top level MDSS wrapper device (for MDP5 only) */
> + /* top level MDSS wrapper device (for MDP5/DPU only) */
>   struct msm_mdss *mdss;
>  
>   /* possibly this should be in the kms component, but it is
> diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
> index 9a7bc7d..8f50613 100644
> --- a/drivers/gpu/drm/msm/msm_kms.h
> +++ b/drivers/gpu/drm/msm/msm_kms.h
> @@ -145,6 +145,8 @@ struct msm_mdss {
>  
>  int mdp5_mdss_init(struct drm_device *dev);
>  

Remove this line.

> +int dpu_mdss_init(struct drm_device *dev);
> +
>  /**
>   * Mode Set Utility Functions
>   */
> diff --git a/include/linux/dpu_io_util.h b/include/linux/dpu_io_util.h
> index 7c73899..45e606f 100644
> --- a/include/linux/dpu_io_util.h
> +++ b/include/linux/dpu_io_util.h
> @@ -104,6 +104,8 @@ int msm_dss_config_vreg(struct device *dev, struct 
> dss_vreg *in_vreg,
>  void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
>  int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
>  int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
> +int msm_dss_parse_clock(struct platform_device *pdev,
> + struct dss_module_power *mp);
>  
>  int dpu_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
>  uint8_t reg_offset, uint8_t *read_buf);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [Freedreno] [PATCH v5 1/4] drm/bridge: add support for sn65dsi86 bridge driver

[Sean Paul]

On Wed, May 02, 2018 at 10:01:59AM +0530, Sandeep Panda wrote:
> Add support for TI's sn65dsi86 dsi2edp bridge chip.
> The chip converts DSI transmitted signal to eDP signal,
> which is fed to the connected eDP panel.
> 
> This chip can be controlled via either i2c interface or
> dsi interface. Currently in driver all the control registers
> are being accessed through i2c interface only.
> Also as of now HPD support has not been added to bridge
> chip driver.
> 
> Changes in v1:
>  - Split the dt-bindings and the driver support into separate patches
>(Andrzej Hajda).
>  - Use of gpiod APIs to parse and configure gpios instead of obsolete ones
>(Andrzej Hajda).
>  - Use macros to define the register offsets (Andrzej Hajda).
> 
> Changes in v2:
>  - Separate out edp panel specific HW resource handling from bridge
>driver and create a separate edp panel drivers to handle panel
>specific mode information and HW resources (Sean Paul).
>  - Replace pr_* APIs to DRM_* APIs to log error or debug information
>(Sean Paul).
>  - Remove some of the unnecessary structure/variable from driver (Sean
>Paul).
>  - Rename the function and structure prefix "sn65dsi86" to "ti_sn_bridge"
>(Sean Paul / Rob Herring).
>  - Remove most of the hard-coding and modified the bridge init sequence
>based on current mode (Sean Paul).
>  - Remove the existing function to retrieve the EDID data and
>implemented this as an i2c_adapter and use drm_get_edid() (Sean Paul).
>  - Remove the dummy irq handler implementation, will add back the
>proper irq handling later (Sean Paul).
>  - Capture the required enable gpios in a single array based on dt entry
>instead of having individual descriptor for each gpio (Sean Paul).
> 
> Changes in v3:
>  - Remove usage of irq_gpio and replace it as "interrupts" property (Rob
>Herring).
>  - Remove the unnecessary header file inclusions (Sean Paul).
>  - Rearrange the header files in alphabetical order (Sean Paul).
>  - Use regmap interface to perform i2c transactions.
>  - Update Copyright/License field and address other review comments
>(Jordan Crouse).
> 
> Changes in v4:
>  - Update License/Copyright (Sean Paul).
>  - Add Kconfig and Makefile changes (Sean Paul).
>  - Drop i2c gpio handling from this bridge driver, since i2c sda/scl gpios
>will be handled by i2c master.
>  - Remove unnecessary goto statements (Sean Paul).
>  - Add mutex lock to power_ctrl API to avoid race conditions (Sean
>Paul).
>  - Add support to parse reference clk frequency from dt(optional).
>  - Update the bridge chip enable/disable sequence.

It seems like you also added 2 new supply names, as well as remove the
configurable gpios?

> 
> Changes in v5:
>  - Fixed Kbuild test service reported warnings.
> 
> Signed-off-by: Sandeep Panda <spa...@codeaurora.org>
> ---
>  drivers/gpu/drm/bridge/Kconfig|   9 +
>  drivers/gpu/drm/bridge/Makefile   |   1 +
>  drivers/gpu/drm/bridge/ti-sn65dsi86.c | 725 
> ++
>  3 files changed, 735 insertions(+)
>  create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
> 
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 3b99d5a..8153150 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -108,6 +108,15 @@ config DRM_TI_TFP410
>   ---help---
> Texas Instruments TFP410 DVI/HDMI Transmitter driver
>  
> +config DRM_TI_SN65DSI86
> + tristate "TI SN65DSI86 DSI to eDP bridge"
> + depends on OF
> + select DRM_KMS_HELPER
> + select REGMAP_I2C
> + select DRM_PANEL
> + ---help---
> +   Texas Instruments SN65DSI86 DSI to eDP Bridge driver
> +
>  source "drivers/gpu/drm/bridge/analogix/Kconfig"
>  
>  source "drivers/gpu/drm/bridge/adv7511/Kconfig"
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 373eb28..3711be8 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -12,4 +12,5 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
>  obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
>  obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
>  obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
> +obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
>  obj-y += synopsys/
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c 
> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> new file mode 100644
> index 000..019c7cd
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -0,0 +1,725 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright

Re: [Freedreno] [[RFC]DPU PATCH 3/4] drm/panel: add Innolux TV123WAM eDP panel driver

[Sean Paul]

 +
> +static int innolux_edp_2k_panel_enable(struct drm_panel *panel)
> +{
> + struct innolux_edp_2k_panel *pdata = to_innolux_edp_2k_panel(panel);
> +
> + if (pdata->enabled)
> + return 0;
> +
> + if (pdata->backlight) {
> + pdata->backlight->props.state &= ~BL_CORE_FBBLANK;
> + pdata->backlight->props.power = FB_BLANK_UNBLANK;
> + backlight_update_status(pdata->backlight);
> + }
> +
> + pdata->enabled = true;
> +
> + return 0;
> +}
> +
> +static int innolux_edp_2k_panel_get_modes(struct drm_panel *panel)
> +{
> + struct innolux_edp_2k_panel *pdata = to_innolux_edp_2k_panel(panel);
> + struct drm_connector *connector = pdata->base.connector;
> + struct drm_device *drm = pdata->base.drm;
> + struct drm_display_mode *mode;
> + unsigned int i, num = 0;
> +
> + if (!pdata->desc || !connector || !drm)
> + return 0;
> +
> + for (i = 0; i < pdata->desc->num_modes; i++) {
> + const struct drm_display_mode *m = >desc->modes[i];
> +
> + mode = drm_mode_duplicate(drm, m);
> + if (!mode) {
> + dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
> + m->hdisplay, m->vdisplay, m->vrefresh);
> + continue;
> + }
> +
> + mode->type |= DRM_MODE_TYPE_DRIVER;
> +
> + if (pdata->desc->num_modes == 1)
> + mode->type |= DRM_MODE_TYPE_PREFERRED;
> +
> + drm_mode_set_name(mode);
> +
> + drm_mode_probed_add(connector, mode);
> + num++;
> + }
> +
> + connector->display_info.bpc = pdata->desc->bpc;
> + connector->display_info.bus_flags = pdata->desc->bus_flags;
> +
> + return num;
> +}
> +
> +static const struct drm_panel_funcs innolux_edp_2k_panel_funcs = {
> + .disable = innolux_edp_2k_panel_disable,
> + .unprepare = innolux_edp_2k_panel_unprepare,
> + .prepare = innolux_edp_2k_panel_prepare,
> + .enable = innolux_edp_2k_panel_enable,
> + .get_modes = innolux_edp_2k_panel_get_modes,
> +};
> +
> +static int innolux_edp_2k_panel_probe(struct platform_device *pdev)
> +{
> + struct device *dev = >dev;
> + const struct of_device_id *id;
> + struct device_node *backlight;
> + struct innolux_edp_2k_panel *pdata;
> + int ret;
> +
> + id = of_match_node(platform_of_match, pdev->dev.of_node);
> + if (!id)
> + return -ENODEV;
> +
> + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
> + if (!pdata)
> + return -ENOMEM;
> +
> + pdata->enabled = false;
> + pdata->prepared = false;
> + pdata->desc = id->data;
> +
> + pdata->supply = devm_regulator_get(dev, "power");
> + if (IS_ERR(pdata->supply))
> + return PTR_ERR(pdata->supply);
> +
> + pdata->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
> + if (IS_ERR(pdata->enable_gpio))
> + return PTR_ERR(pdata->enable_gpio);
> +
> + backlight = of_parse_phandle(dev->of_node, "backlight", 0);
> + if (backlight) {
> + pdata->backlight = of_find_backlight_by_node(backlight);
> + of_node_put(backlight);
> +
> + if (!pdata->backlight)
> + return -EPROBE_DEFER;
> + }
> +
> + drm_panel_init(>base);
> + pdata->base.dev = dev;
> + pdata->base.funcs = _edp_2k_panel_funcs;
> +
> + ret = drm_panel_add(>base);
> + if (ret < 0)
> + goto free_backlight;
> +
> + dev_set_drvdata(dev, pdata);
> +
> + return 0;
> +
> +free_backlight:
> + if (pdata->backlight)
> + put_device(>backlight->dev);
> +
> + return ret;
> +}
> +
> +static int innolux_edp_2k_panel_remove(struct platform_device *pdev)
> +{
> + struct device *dev = >dev;
> + struct innolux_edp_2k_panel *pdata = dev_get_drvdata(dev);
> +
> + drm_panel_detach(>base);
> + drm_panel_remove(>base);
> +
> + innolux_edp_2k_panel_disable(>base);
> + innolux_edp_2k_panel_unprepare(>base);
> +
> + if (pdata->backlight)
> + put_device(>backlight->dev);
> +
> + return 0;
> +}
> +
> +static struct platform_driver innolux_edp_2k_panel_driver = {
> + .driver = {
> + .name = "innolux-2k-edp-panel",
> + .of_match_table = platform_of_match,
> + },
> + .probe = innolux_edp_2k_panel_probe,
> + .remove = innolux_edp_2k_panel_remove,
> +};
> +
> +static int __init innolux_edp_2k_panel_init(void)
> +{
> + int ret;
> +
> + ret = platform_driver_register(_edp_2k_panel_driver);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +module_init(innolux_edp_2k_panel_init);
> +
> +static void __exit innolux_edp_2k_panel_exit(void)
> +{
> + platform_driver_unregister(_edp_2k_panel_driver);
> +}
> +module_exit(innolux_edp_2k_panel_exit);
> +
> +MODULE_DESCRIPTION("Innolux 2k eDP panel driver");
> +MODULE_LICENSE("GPL");
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
___
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Re: [Freedreno] [[RFC]DPU PATCH 1/4] drm/bridge: add support for sn65dsi86 bridge driver

[Sean Paul]

On Thu, Apr 19, 2018 at 11:26:05PM +0530, Sandeep Panda wrote:
> Add support for TI's sn65dsi86 dsi2edp bridge chip.
> The chip converts DSI transmitted signal to eDP signal,
> which is fed to the connected eDP panel.
> 
> This chip can be controlled via either i2c interface or
> dsi interface. Currently in driver all the control registers
> are being accessed through i2c interface only.
> Also as of now HPD support has not been added to bridge
> chip driver.
> 
> Changes in v1:
>  - Split the dt-bindings and the driver support into separate patches
>(Andrzej Hajda).
>  - Use of gpiod APIs to parse and configure gpios instead of obsolete ones
>(Andrzej Hajda).
>  - Use macros to define the register offsets (Andrzej Hajda).
> 
> Changes in v2:
>  - Separate out edp panel specific HW resource handling from bridge
>driver and create a separate edp panel drivers to handle panel
>specific mode information and HW resources (Sean Paul).
>  - Replace pr_* APIs to DRM_* APIs to log error or debug information
>(Sean Paul).
>  - Remove some of the unnecessary structure/variable from driver (Sean
>Paul).
>  - Rename the function and structure prefix "sn65dsi86" to "ti_sn_bridge"
>(Sean Paul / Rob Herring).
>  - Remove most of the hard-coding and modified the bridge init sequence
>based on current mode (Sean Paul).
>  - Remove the existing function to retrieve the EDID data and
>implemented this as an i2c_adapter and use drm_get_edid() (Sean Paul).
>  - Remove the dummy irq handler implementation, will add back the
>proper irq handling later (Sean Paul).
>  - Capture the required enable gpios in a single array based on dt entry
>instead of having individual descriptor for each gpio (Sean Paul).
> 
> Changes in v3:
>  - Remove usage of irq_gpio and replace it as "interrupts" property (Rob
>Herring).
>  - Remove the unnecessary header file inclusions (Sean Paul).
>  - Rearrange the header files in alphabetical order (Sean Paul).
>  - Use regmap interface to perform i2c transactions.
>  - Update Copyright/License field and address other review comments
>(Jordan Crouse).
> 
> Signed-off-by: Sandeep Panda <spa...@codeaurora.org>
> ---
>  drivers/gpu/drm/bridge/ti-sn65dsi86.c | 690 
> ++

What about Kconfig/Makefile?

>  1 file changed, 690 insertions(+)
>  create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
> 
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c 
> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> new file mode 100644
> index 000..a2a95f5
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -0,0 +1,690 @@
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */

Use SPDX license

> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define SN_BRIDGE_REVISION_ID 0x2
> +
> +/* Link Training specific registers */
> +#define SN_DEVICE_REV_REG0x08
> +#define SN_REFCLK_FREQ_REG   0x0A
> +#define SN_DSI_LANES_REG 0x10
> +#define SN_DSIA_CLK_FREQ_REG 0x12
> +#define SN_ENH_FRAME_REG 0x5A
> +#define SN_SSC_CONFIG_REG0x93
> +#define SN_DATARATE_CONFIG_REG   0x94
> +#define SN_PLL_ENABLE_REG0x0D
> +#define SN_SCRAMBLE_CONFIG_REG   0x95
> +#define SN_AUX_WDATA0_REG0x64
> +#define SN_AUX_ADDR_19_16_REG0x74
> +#define SN_AUX_ADDR_15_8_REG 0x75
> +#define SN_AUX_ADDR_7_0_REG  0x76
> +#define SN_AUX_LENGTH_REG0x77
> +#define SN_AUX_CMD_REG   0x78
> +#define SN_ML_TX_MODE_REG0x96
> +/* video config specific registers */
> +#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG0x20
> +#define SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG   0x21
> +#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
> +#define SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG0x25
> +#

[Freedreno] [DPU PATCH] drm/msm: dpu: Fix build warnings

[Sean Paul]

Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   |  5 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  | 14 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  |  9 +
 drivers/gpu/drm/msm/dpu_dbg.c  | 14 --
 drivers/gpu/drm/msm/dsi/dsi_manager.c  |  2 +-
 6 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
index c6fc0a28d76f..f13d1cc8f635 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
@@ -244,7 +244,8 @@ static int dpu_cp_handle_range_property(struct dpu_cp_node 
*prop_node,
return 0;
}
 
-   ret = copy_from_user(blob_ptr->data, (void *)val, blob_ptr->length);
+   ret = copy_from_user(blob_ptr->data, u64_to_user_ptr(val),
+blob_ptr->length);
if (ret) {
DRM_ERROR("failed to get the property info ret %d", ret);
ret = -EFAULT;
@@ -910,7 +911,7 @@ int dpu_cp_crtc_set_property(struct drm_crtc *crtc,
 */
if (!dpu_crtc->num_mixers ||
dpu_crtc->num_mixers > ARRAY_SIZE(dpu_crtc->mixers)) {
-   DRM_ERROR("Invalid mixer config act cnt %d max cnt %ld\n",
+   DRM_ERROR("Invalid mixer config act cnt %d max cnt %zd\n",
dpu_crtc->num_mixers, ARRAY_SIZE(dpu_crtc->mixers));
return -EINVAL;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 631ba7ebf596..f7ac9c85c336 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -3366,11 +3366,11 @@ static int dpu_crtc_atomic_set_property(struct drm_crtc 
*crtc,
switch (idx) {
case CRTC_PROP_DIM_LAYER_V1:
_dpu_crtc_set_dim_layer_v1(cstate,
-   (void __user *)val);
+   u64_to_user_ptr(val));
break;
case CRTC_PROP_DEST_SCALER:
ret = _dpu_crtc_set_dest_scaler(dpu_crtc,
-   cstate, (void __user *)val);
+   cstate, u64_to_user_ptr(val));
break;
case CRTC_PROP_DEST_SCALER_LUT_ED:
case CRTC_PROP_DEST_SCALER_LUT_CIR:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
index e0d46c545c14..7c2772f7219f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
@@ -171,7 +171,7 @@ static void get_decode_sel(unsigned long blk, u32 
*decode_sel)
*decode_sel |= BIT(21);
break;
default:
-   DRM_ERROR("block not supported %zx\n", BIT(i));
+   DRM_ERROR("block not supported %lx\n", BIT(i));
break;
}
}
@@ -275,7 +275,7 @@ static int validate_write_multi_lut_reg(struct 
dpu_reg_dma_setup_ops_cfg *cfg)
return rc;
 
if (cfg->wrap_size < WRAP_MIN_SIZE || cfg->wrap_size > WRAP_MAX_SIZE) {
-   DRM_ERROR("invalid wrap sz %d min %d max %zd\n",
+   DRM_ERROR("invalid wrap sz %d min %d max %ld\n",
cfg->wrap_size, WRAP_MIN_SIZE, WRAP_MAX_SIZE);
rc = -EINVAL;
}
@@ -302,7 +302,7 @@ static int validate_write_reg(struct 
dpu_reg_dma_setup_ops_cfg *cfg)
}
if ((SIZE_DWORD(cfg->data_size)) > MAX_DWORDS_SZ ||
NOT_WORD_ALIGNED(cfg->data_size)) {
-   DRM_ERROR("Invalid data size %d max %zd align %x\n",
+   DRM_ERROR("Invalid data size %d max %ld align %x\n",
cfg->data_size, MAX_DWORDS_SZ,
NOT_WORD_ALIGNED(cfg->data_size));
return -EINVAL;
@@ -310,7 +310,7 @@ static int validate_write_reg(struct 
dpu_reg_dma_setup_ops_cfg *cfg)
 
if (cfg->blk_offset > MAX_RELATIVE_OFF ||
NOT_WORD_ALIGNED(cfg->blk_offset)) {
-   DRM_ERROR("invalid offset %d max %zd align %x\n",
+   DRM_ERROR("invalid offset %d max %ld align %x\n",
cfg->blk_offset, MAX_RELATIVE_OFF

Re: [Freedreno] [DPU PATCH v3 2/2] drm/msm/dsi: Use one connector for dual DSI mode

[Sean Paul]

On Wed, Apr 18, 2018 at 12:45:15PM -0700, Chandan Uddaraju wrote:
> Current DSI driver uses two connectors for dual DSI case even
> though we only have one panel. Fix this by implementing one
> connector/bridge for dual DSI use case. Use master DSI
> controllers to register one connector/bridge.
> 
> Changes in V2:
> -Removed Change-Id from the commit text tags.
> -Remove extra parentheses
> 
> Changes in V3:
> -None
> 
> Signed-off-by: Chandan Uddaraju <chand...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/dsi/dsi.c |   3 +
>  drivers/gpu/drm/msm/dsi/dsi.h |   1 +
>  drivers/gpu/drm/msm/dsi/dsi_manager.c | 110 
> --
>  3 files changed, 29 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index b744bcc..ff8164c 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -208,6 +208,9 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct 
> drm_device *dev,
>   goto fail;
>   }
>  
> + if (!msm_dsi_manager_validate_current_config(msm_dsi->id))
> + goto fail;
> +
>   msm_dsi->encoder = encoder;
>  
>   msm_dsi->bridge = msm_dsi_manager_bridge_init(msm_dsi->id);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 01c38f6..c858e8e 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -100,6 +100,7 @@ struct msm_dsi {
>  void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
>  int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
>  void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
> +bool msm_dsi_manager_validate_current_config(u8 id);
>  
>  /* msm dsi */
>  static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 3bb506b..2a11f82 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -306,67 +306,6 @@ static void dsi_mgr_connector_destroy(struct 
> drm_connector *connector)
>   kfree(dsi_connector);
>  }
>  
> -static void dsi_dual_connector_fix_modes(struct drm_connector *connector)
> -{
> - struct drm_display_mode *mode, *m;
> -
> - /* Only support left-right mode */
> - list_for_each_entry_safe(mode, m, >probed_modes, head) {
> - mode->clock >>= 1;
> - mode->hdisplay >>= 1;
> - mode->hsync_start >>= 1;
> - mode->hsync_end >>= 1;
> - mode->htotal >>= 1;
> - drm_mode_set_name(mode);
> - }
> -}
> -
> -static int dsi_dual_connector_tile_init(
> - struct drm_connector *connector, int id)
> -{
> - struct drm_display_mode *mode;
> - /* Fake topology id */
> - char topo_id[8] = {'M', 'S', 'M', 'D', 'U', 'D', 'S', 'I'};
> -
> - if (connector->tile_group) {
> - DBG("Tile property has been initialized");
> - return 0;
> - }
> -
> - /* Use the first mode only for now */
> - mode = list_first_entry(>probed_modes,
> - struct drm_display_mode,
> - head);
> - if (!mode)
> - return -EINVAL;
> -
> - connector->tile_group = drm_mode_get_tile_group(
> - connector->dev, topo_id);
> - if (!connector->tile_group)
> - connector->tile_group = drm_mode_create_tile_group(
> - connector->dev, topo_id);
> - if (!connector->tile_group) {
> - pr_err("%s: failed to create tile group\n", __func__);
> - return -ENOMEM;
> - }
> -
> - connector->has_tile = true;
> - connector->tile_is_single_monitor = true;
> -
> - /* mode has been fixed */
> - connector->tile_h_size = mode->hdisplay;
> - connector->tile_v_size = mode->vdisplay;
> -
> - /* Only support left-right mode */
> - connector->num_h_tile = 2;
> - connector->num_v_tile = 1;
> -
> - connector->tile_v_loc = 0;
> - connector->tile_h_loc = (id == DSI_RIGHT) ? 1 : 0;
> -
> - return 0;
> -}
> -
>  static int dsi_mgr_connector_get_modes(struct drm_connector *connector)
>  {
>   int id = dsi_mgr_connector_get_id(connector);
> @@ -377,31 +316,15 @@ static int dsi_mgr_connector_get_modes(struct 

Re: [Freedreno] [DPU PATCH v3 2/2] drm/msm/dsi: Use one connector for dual DSI mode

[Sean Paul]

On Wed, Apr 18, 2018 at 12:45:15PM -0700, Chandan Uddaraju wrote:
> Current DSI driver uses two connectors for dual DSI case even
> though we only have one panel. Fix this by implementing one
> connector/bridge for dual DSI use case. Use master DSI
> controllers to register one connector/bridge.
> 
> Changes in V2:
> -Removed Change-Id from the commit text tags.
> -Remove extra parentheses
> 
> Changes in V3:
> -None
> 
> Signed-off-by: Chandan Uddaraju <chand...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/dsi/dsi.c |   3 +
>  drivers/gpu/drm/msm/dsi/dsi.h |   1 +
>  drivers/gpu/drm/msm/dsi/dsi_manager.c | 110 
> --
>  3 files changed, 29 insertions(+), 85 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index b744bcc..ff8164c 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -208,6 +208,9 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct 
> drm_device *dev,
>   goto fail;
>   }
>  
> + if (!msm_dsi_manager_validate_current_config(msm_dsi->id))
> + goto fail;
> +
>   msm_dsi->encoder = encoder;
>  
>   msm_dsi->bridge = msm_dsi_manager_bridge_init(msm_dsi->id);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 01c38f6..c858e8e 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -100,6 +100,7 @@ struct msm_dsi {
>  void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
>  int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
>  void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi);
> +bool msm_dsi_manager_validate_current_config(u8 id);
>  
>  /* msm dsi */
>  static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi)
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 3bb506b..2a11f82 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -306,67 +306,6 @@ static void dsi_mgr_connector_destroy(struct 
> drm_connector *connector)
>   kfree(dsi_connector);
>  }
>  
> -static void dsi_dual_connector_fix_modes(struct drm_connector *connector)
> -{
> - struct drm_display_mode *mode, *m;
> -
> - /* Only support left-right mode */
> - list_for_each_entry_safe(mode, m, >probed_modes, head) {
> - mode->clock >>= 1;
> - mode->hdisplay >>= 1;
> - mode->hsync_start >>= 1;
> - mode->hsync_end >>= 1;
> - mode->htotal >>= 1;
> - drm_mode_set_name(mode);
> - }
> -}
> -
> -static int dsi_dual_connector_tile_init(
> - struct drm_connector *connector, int id)
> -{
> - struct drm_display_mode *mode;
> - /* Fake topology id */
> - char topo_id[8] = {'M', 'S', 'M', 'D', 'U', 'D', 'S', 'I'};
> -
> - if (connector->tile_group) {
> - DBG("Tile property has been initialized");
> - return 0;
> - }
> -
> - /* Use the first mode only for now */
> - mode = list_first_entry(>probed_modes,
> - struct drm_display_mode,
> - head);
> - if (!mode)
> - return -EINVAL;
> -
> - connector->tile_group = drm_mode_get_tile_group(
> - connector->dev, topo_id);
> - if (!connector->tile_group)
> - connector->tile_group = drm_mode_create_tile_group(
> - connector->dev, topo_id);
> - if (!connector->tile_group) {
> - pr_err("%s: failed to create tile group\n", __func__);
> - return -ENOMEM;
> - }
> -
> - connector->has_tile = true;
> - connector->tile_is_single_monitor = true;
> -
> - /* mode has been fixed */
> - connector->tile_h_size = mode->hdisplay;
> - connector->tile_v_size = mode->vdisplay;
> -
> - /* Only support left-right mode */
> - connector->num_h_tile = 2;
> - connector->num_v_tile = 1;
> -
> - connector->tile_v_loc = 0;
> - connector->tile_h_loc = (id == DSI_RIGHT) ? 1 : 0;
> -
> - return 0;
> -}
> -
>  static int dsi_mgr_connector_get_modes(struct drm_connector *connector)
>  {
>   int id = dsi_mgr_connector_get_id(connector);
> @@ -377,31 +316,15 @@ static int dsi_mgr_connector_get_modes(struct 

Re: [Freedreno] [DPU PATCH 6/6] drm/msm: remove dsi-staging driver

[Sean Paul]

On Mon, Apr 16, 2018 at 11:22:21AM -0700, Jeykumar Sankaran wrote:
> SDM845 has switched from dsi-staging to dsi driver. Removing
> stale code.
> 
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
> ---
>  .../config/arm64/chromiumos-arm64.flavour.config   |1 -
>  .../arm64/chromiumos-qualcomm.flavour.config   |1 -
>  drivers/gpu/drm/msm/Kconfig|   12 -
>  drivers/gpu/drm/msm/Makefile   |   21 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c  |  241 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h  |  201 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_clk.h  |  276 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c  | 1235 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c | 2846 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h |  623 ---
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h  |  752 
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c  |  480 ---
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_0.c  |  234 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c  |   42 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c  | 1312 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h |  196 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_defs.h |  579 ---
>  drivers/gpu/drm/msm/dsi-staging/dsi_display.c  | 4221 
> 
>  drivers/gpu/drm/msm/dsi-staging/dsi_display.h  |  556 ---
>  drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c |  114 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h |   31 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |  688 
>  drivers/gpu/drm/msm/dsi-staging/dsi_drm.h  |  127 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_hw.h   |   48 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_panel.c| 3321 ---
>  drivers/gpu/drm/msm/dsi-staging/dsi_panel.h|  257 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_phy.c  |  937 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_phy.h  |  235 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h   |  260 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v2_0.c  |  252 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c  |  447 ---
>  .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c  |  676 
>  .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.h  |  144 -
>  .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v2_0.c  |  126 -
>  .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c  |  107 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_pwr.c  |  365 --
>  drivers/gpu/drm/msm/dsi-staging/dsi_pwr.h  |   93 -
>  37 files changed, 22057 deletions(-)

Awesome!

Reviewed-by: Sean Paul <seanp...@chromium.org>



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[Freedreno] [PULL] msm fixes/improvements

[Sean Paul]

Hey Rob,
Here's a few patches from the DPU sets that can go into msm as-is. 

In addition to these, there is the atomic helper conversion that I am anxious
to get in as well. If you'd like, I can round those up into a PR, but the
latest version should be bundled up in a set on the ML. I've tested it on both
mdp5 and dpu, fwiw.

Cheers,

Sean


The following changes since commit 288e5c8898c488298c39ff4bbf58928d30fbf99f:

  drm/msm: fix building without debugfs (2018-03-19 06:33:39 -0400)

are available in the Git repository at:

  https://gitlab.freedesktop.org/seanpaul/dpu-staging.git tags/for-rob-0418

for you to fetch changes up to e8b50958962d11ef8f64b06ad4d9821bf57be827:

  drm/msm: Add modifier to mdp_get_format arguments (2018-04-18 10:55:28 -0400)


Abhinav Kumar (3):
  drm/msm/dsi: check return value for video done waits
  drm/msm/dsi: check video mode engine status before waiting
  drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY

Jeykumar Sankaran (1):
  drm/msm: Add modifier to mdp_get_format arguments

Sean Paul (1):
  drm/msm: Mark the crtc->state->event consumed

 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c  |   1 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c  |   1 +
 drivers/gpu/drm/msm/disp/mdp_format.c  |   3 +-
 drivers/gpu/drm/msm/disp/mdp_kms.h |   2 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c |  14 +++-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c  | 109 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h  |   2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c |  28 
 drivers/gpu/drm/msm/msm_fb.c   |   3 +-
 drivers/gpu/drm/msm/msm_kms.h  |   5 +-
 10 files changed, 133 insertions(+), 35 deletions(-)

-- 
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Re: [Freedreno] [[RFC]DPU PATCH 0/4] Add suppport for sn65dsi86 bridge chip and Innolux 2k edp panel driver

[Sean Paul]

On Wed, Apr 18, 2018 at 05:49:58PM +0530, Sandeep Panda wrote:
> Changelog:
> 
> v3 -> v4:

I didn't really bother to do a thorough review given that there are obvious
mistakes and ignored feedback, it's a waste of time, tbh. Please go through
the previous reviews and resend a more polished version.

Sean

> Current patchset separates out eDP panel specific resources from sn65dsi86
> bridge driver and creates a separate driver for the innloux edp panel.
> 
> Now bridge driver check if any panel is attached or not to get the supported
> modes. If any panel is attached then query from panel driver to get the modes,
> or else probe the provided i2c adapter to read the modes from EDID.
> 
> Removed hardcoding of bridge init sequence. With this patchset bridge driver 
> now
> will program the init sequence based on the current mode set by drm framework.
> 
> Current patchset is not tested on actual bridge chip/panel.
> 
> Sandeep Panda (4):
>   drm/bridge: add support for sn65dsi86 bridge driver
>   dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
>   drm/panel: add Innolux TV123WAM eDP panel driver
>   dt-bindings: Add Innolux TV123WAM panel bindings
> 
>  .../bindings/display/bridge/ti,sn65dsi86.txt   |  60 ++
>  .../display/panel/innolux,edp-2k-panel.txt |  21 +
>  drivers/gpu/drm/bridge/ti-sn65dsi86.c  | 742 
> +
>  drivers/gpu/drm/panel/panel-innolux-tv123wam.c | 299 +
>  4 files changed, 1122 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
>  create mode 100644 
> Documentation/devicetree/bindings/display/panel/innolux,edp-2k-panel.txt
>  create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi86.c
>  create mode 100644 drivers/gpu/drm/panel/panel-innolux-tv123wam.c
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [Freedreno] [DPU PATCH v2 2/2] drm/panel: add backlight control support for truly panel

[Sean Paul]

On Wed, Apr 18, 2018 at 11:52:18AM +0100, Daniel Thompson wrote:
> On Tue, Apr 17, 2018 at 05:42:04PM -0700, abhin...@codeaurora.org wrote:
> > Adding another point.
> > 
> > On 2018-04-17 17:04, abhin...@codeaurora.org wrote:
> > > Hi Bjorn
> > > 
> > > Apologies if the prev reply wasnt clear.
> > > 
> > > Hope this one is.
> > > 
> > > reply inline.
> > > 
> > > On 2018-04-17 14:29, Bjorn Andersson wrote:
> > > > On Tue 17 Apr 11:21 PDT 2018, abhin...@codeaurora.org wrote:
> > > > > On 2018-04-16 23:13, Bjorn Andersson wrote:
> > > > [..]
> > > > > > If the panel isn't actually a piece of backlight hardware then it 
> > > > > > should
> > > > > > not register a backlight device. Why do you need your own sysfs?
> > > > > >
> > > > > > Regards,
> > > > > > Bjorn
> > > > > [Abhinav] This particular panel isnt a piece of backlight hardware.
> > > > > But, we want to have our own sysfs to give flexibility to our
> > > > > userspace
> > > > > to write and read stuff for its proprietary uses.
> > > > 
> > > > Please be more specific in your replies, no one will accept code that
> > > > "does stuff" and expecting a reviewer to spend time guessing or
> > > > pulling
> > > > the information out of you is a sure way to get your patches ignored.
> > > > 
> > > > Exactly what kind of stuff are you talking about here and exactly
> > > > which
> > > > problem are you solving.
> > > > 
> > > > > Thats how our downstream has been working so far and hence to
> > > > > maintain
> > > > > the compatibility would like to have it.
> > > > 
> > > > Make your proprietary code work with the upstream kernel and you
> > > > shouldn't ever have to modify it.
> > > > 
> > > > Regards,
> > > > Bjorn
> > > 
> > > [Abhinav] We have a few userspace clients today for the backlight sysfs
> > > node
> > > which read/write directly to
> > > "/sys/class/backlight/panel0-backlight/brightness"
> > > When I said "stuff" I was only referring to the brightness value.
> > > This separate sysfs node allows us to validate those userspace features
> > > of ours
> > > which directly edit the backlight value on our reference platform.
> > > Since our reference platform uses this panel,hence having our own
> > > sysfs alias helps.
> > > Otherwise, whenever we try to use this panel with upstream code we
> > > will have to end up
> > > changing all those places in our userspace/framework to change the sysfs
> > > path.
> > > Hence we wanted to preserve that sysfs node name.
> > > The wled device is not created under /sys/class/backlight but under
> > > /sys/class/leds/wled.
> > > So we will have to change the name of this node across all our
> > > userspace.
> > > 
> > > If this isnt a convincing reason enough to have its own sysfs node
> > > path, I will use
> > > your approach.
> > > 
> > > Let me know your comments or if this is still not clear.
> > > 
> > [Abhinav] We also might not be using the brightness value "as-it-is".
> > 
> > We will potentially scale it up/down based on some requirements.
> > 
> > If we do not have our own sysfs alias for this, how do we account for
> > providing this interface for our chipset specific backlight dependent
> > feature.
> > 
> > Can you please comment on this?
> 
> Not easily. It's rather unclear what this chipset specific backlight
> dependent feature you have alluded to is so how can we suggest how to
> control or model it in the upstream kernel?
> 

The code is here:

https://gitlab.freedesktop.org/seanpaul/dpu-staging/blob/mtp-squashed/drivers/gpu/drm/msm/dsi-staging/dsi_display.c#L76

AFAICT, there's nothing fancy in the kernel aside from scaling the brightness
level down twice. I assume the magic is in userspace. My initial reaction was
that the scaling factor should just be applied in userspace. Especially since
the scaling factor reduces the resolution of the backlight, and that's not
immediately obvious by looking at "brightness".

Sean


> I can make a guess that is might be to do with brightness curves... but
> I'd really prefer not to have to guess.
> 
> There are some problems with the current interface because it is not
> well defined with the brightness control is linear or
> logarithmic/perceptual (patches welcome) but for other common embedded
> backlights (pwm_bl particularly) we expect calibration of the
> brightness curve to be a job for the device tree (because it is a
> property of the hardware it can be described in the DT) and there are
> patches pending to improve this.
> 
> 
> Daniel.
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

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Re: [Freedreno] [DPU PATCH 4/6] drm/msm: strip down custom event ioctl's

[Sean Paul]

On Mon, Apr 16, 2018 at 11:22:19AM -0700, Jeykumar Sankaran wrote:
> Remove custom ioctl support in SDM845 which allows
> user space to register/unregister for hw events.
> 
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 218 
> +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  31 -
>  drivers/gpu/drm/msm/msm_drv.c| 201 
>  drivers/gpu/drm/msm/msm_kms.h|   2 -
>  5 files changed, 1 insertion(+), 452 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 8e464fa..387919a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -39,31 +39,6 @@
>  #include "dpu_core_perf.h"
>  #include "dpu_trace.h"
>  
> -struct dpu_crtc_irq_info {
> - struct dpu_irq_callback irq;
> - u32 event;
> - int (*func)(struct drm_crtc *crtc, bool en,
> - struct dpu_irq_callback *irq);
> - struct list_head list;
> -};
> -
> -struct dpu_crtc_custom_events {
> - u32 event;
> - int (*func)(struct drm_crtc *crtc, bool en,
> - struct dpu_irq_callback *irq);
> -};
> -
> -static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
> - bool en, struct dpu_irq_callback *ad_irq);
> -static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
> - bool en, struct dpu_irq_callback *idle_irq);
> -
> -static struct dpu_crtc_custom_events custom_events[] = {
> - {DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
> - {DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
> - {DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
> -};
> -
>  /* layer mixer index on dpu_crtc */
>  #define LEFT_MIXER 0
>  #define RIGHT_MIXER 1
> @@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
> void *arg)
>   struct drm_encoder *encoder;
>   struct dpu_crtc_mixer *m;
>   u32 i, misr_status;
> - unsigned long flags;
> - struct dpu_crtc_irq_info *node = NULL;
> - int ret = 0;
>  
>   if (!crtc) {
>   DPU_ERROR("invalid crtc\n");
> @@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 
> event_type, void *arg)
>   dpu_encoder_virt_restore(encoder);
>   }
>  
> - spin_lock_irqsave(_crtc->spin_lock, flags);
> - list_for_each_entry(node, _crtc->user_event_list, list) {
> - ret = 0;
> - if (node->func)
> - ret = node->func(crtc, true, >irq);
> - if (ret)
> - DPU_ERROR("%s failed to enable event %x\n",
> - dpu_crtc->name, node->event);
> - }
> - spin_unlock_irqrestore(_crtc->spin_lock, flags);
> -
>   dpu_cp_crtc_post_ipc(crtc);
>  
>   for (i = 0; i < dpu_crtc->num_mixers; ++i) {
> @@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 
> event_type, void *arg)
>   dpu_crtc->misr_data[i];
>   }
>  
> - spin_lock_irqsave(_crtc->spin_lock, flags);
> - node = NULL;
> - list_for_each_entry(node, _crtc->user_event_list, list) {
> - ret = 0;
> - if (node->func)
> - ret = node->func(crtc, false, >irq);
> - if (ret)
> - DPU_ERROR("%s failed to disable event %x\n",
> - dpu_crtc->name, node->event);
> - }
> - spin_unlock_irqrestore(_crtc->spin_lock, flags);
> -
>   dpu_cp_crtc_pre_ipc(crtc);
>   break;
>   case DPU_POWER_EVENT_POST_DISABLE:
> @@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>   struct drm_display_mode *mode;
>   struct drm_encoder *encoder;
>   struct msm_drm_private *priv;
> - unsigned long flags;
> - struct dpu_crtc_irq_info *node = NULL;
>   struct drm_event event;
>   u32 power_on;
>   int ret;
> @@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>   atomic_set(_crtc->frame_pending, 0);
> 

Re: [Freedreno] [DPU PATCH 3/6] drm/msm: remove panel autorefresh support for SDM845

[Sean Paul]

On Mon, Apr 16, 2018 at 11:22:18AM -0700, Jeykumar Sankaran wrote:
> Remove autorefresh support for smart panels in SDM845 for now.
> It needs more discussion to figure out the user space
> communication to set preference for the feature.
> 
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   7 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  37 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 --
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 298 
> +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  41 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  18 --
>  6 files changed, 11 insertions(+), 410 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> index f7e9f76..dc0978d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> @@ -24,9 +24,6 @@
>  
>  #define BL_NODE_NAME_SIZE 32
>  
> -/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely 
> */
> -#define AUTOREFRESH_MAX_FRAME_CNT 6
> -
>  #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
>   (c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
>  
> @@ -1126,10 +1123,6 @@ struct drm_connector *dpu_connector_init(struct 
> drm_device *dev,
>   CONNECTOR_PROP_AD_BL_SCALE);
>  #endif
>  
> - msm_property_install_range(_conn->property_info, "autorefresh",
> - 0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
> - CONNECTOR_PROP_AUTOREFRESH);
> -
>   /* enum/bitmask properties */
>   msm_property_install_enum(_conn->property_info, "topology_name",
>   DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 32375b1..3004569 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -815,7 +815,6 @@ static void _dpu_encoder_resource_control_helper(struct 
> drm_encoder *drm_enc,
>  static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
>   u32 sw_event)
>  {
> - bool autorefresh_enabled = false;
>   unsigned int lp, idle_timeout;
>   struct dpu_encoder_virt *dpu_enc;
>   struct msm_drm_private *priv;
> @@ -922,13 +921,6 @@ static int dpu_encoder_resource_control(struct 
> drm_encoder *drm_enc,
>   return 0;
>   }
>  
> - /* schedule delayed off work if autorefresh is disabled */
> - if (dpu_enc->cur_master &&
> - dpu_enc->cur_master->ops.is_autorefresh_enabled)
> - autorefresh_enabled =
> - dpu_enc->cur_master->ops.is_autorefresh_enabled(
> - dpu_enc->cur_master);
> -
>   /* set idle timeout based on master connector's lp value */
>   if (dpu_enc->cur_master)
>   lp = dpu_connector_get_lp(
> @@ -941,13 +933,12 @@ static int dpu_encoder_resource_control(struct 
> drm_encoder *drm_enc,
>   else
>   idle_timeout = dpu_enc->idle_timeout;
>  
> - if (!autorefresh_enabled)
> - kthread_queue_delayed_work(
> - _thread->worker,
> - _enc->delayed_off_work,
> - msecs_to_jiffies(idle_timeout));
> + kthread_queue_delayed_work(
> + _thread->worker,
> + _enc->delayed_off_work,
> + msecs_to_jiffies(idle_timeout));
> +
>   DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
> - autorefresh_enabled,
>   idle_timeout, DPU_EVTLOG_FUNC_CASE2);
>   DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
>   sw_event);
> @@ -1990,7 +1981,6 @@ static void dpu_encoder_vsync_event_handler(struct 
> timer_list *t)
>   struct drm_encoder *drm_enc = _enc->base;
>   struct msm_drm_private *priv;
>   struct msm_drm_thread *event_thread;
> - bool autorefresh_enabled = false;
>  
>   if (!drm_enc->dev || !drm_enc->dev->dev_private ||
>   !drm_

Re: [Freedreno] [DPU PATCH 2/6] drm/msm: remove support for ping pong split topology

[Sean Paul]

On Mon, Apr 16, 2018 at 11:22:17AM -0700, Jeykumar Sankaran wrote:
> Ping pong split topology was meant for low end soc's which
> doesn't have enough layer mixers to support split panels.
> Considering how uncommon the topology is for current chipset's and
> also to simply the driver programming, striping off the support
> for SDM845.
> 
> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  19 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 179 
> +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   5 -
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 110 +
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  33 
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |  11 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |   4 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  37 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   2 -
>  13 files changed, 15 insertions(+), 415 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> index 1237efc..f7e9f76 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> @@ -41,8 +41,8 @@
>   {DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
>   {DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
>   {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
> - {DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
>  };
> +
>  static const struct drm_prop_enum_list e_topology_control[] = {
>   {DPU_RM_TOPCTL_RESERVE_LOCK,"reserve_lock"},
>   {DPU_RM_TOPCTL_RESERVE_CLEAR,   "reserve_clear"},
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 516458e..8e464fa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc 
> *crtc)
>   mutex_unlock(_crtc->crtc_lock);
>  }
>  
> -static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
> -{
> - int i;
> - struct dpu_crtc_state *cstate;
> -
> - cstate = to_dpu_crtc_state(state);
> -
> - cstate->is_ppsplit = false;
> - for (i = 0; i < cstate->num_connectors; i++) {
> - struct drm_connector *conn = cstate->connectors[i];
> -
> - if (dpu_connector_get_topology_name(conn) ==
> - DPU_RM_TOPOLOGY_PPSPLIT)
> - cstate->is_ppsplit = true;
> - }
> -}
> -
>  static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
>   struct drm_crtc_state *state)
>  {
> @@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
>  
>   if (!dpu_crtc->num_mixers) {
>   _dpu_crtc_setup_mixers(crtc);
> - _dpu_crtc_setup_is_ppsplit(crtc->state);
>   _dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>   }
>  
> @@ -2901,7 +2883,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>  
>   mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
>  
> - _dpu_crtc_setup_is_ppsplit(state);
>   _dpu_crtc_setup_lm_bounds(crtc, state);
>  
>/* get plane state for all drm planes associated with crtc state */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 6f12355..32375b1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
>   struct dpu_encoder_virt *dpu_enc;
>   struct split_pipe_cfg cfg = { 0 };
>   struct dpu_hw_mdp *hw_mdptop;
> - enum dpu_rm_topology_name topology;
>   struct msm_display_info *disp_info;
>  
>   if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
> @@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
>   if (phys_enc->split_role == ENC_ROLE_SOLO) {
>   if (hw_mdptop->ops.setup_split_pipe)
>   hw_mdptop->ops.setup_split_pipe(hw_mdptop, );
> - 

Re: [Freedreno] [DPU PATCH v2 1/2] drm/msm/dsi: adjust dsi timing for dual dsi mode

[Sean Paul]

On Mon, Apr 16, 2018 at 05:40:13PM -0700, Chandan Uddaraju wrote:
> For dual dsi mode, the horizontal timing needs
> to be divided by half since both the dsi controllers
> will be driving this panel. Adjust the pixel clock and
> DSI timing accordingly.
> 
> Changes in V2:
> --Removed Change-Id from the commit text tags.

You ignored my feedback on v1

> 
> Signed-off-by: Chandan Uddaraju <chand...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi.h |  1 +
>  drivers/gpu/drm/msm/dsi/dsi_host.c| 17 +
>  drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 +++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 70d9a9a..4131b47 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -161,6 +161,7 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host 
> *host,
>   u32 dma_base, u32 len);
>  int msm_dsi_host_enable(struct mipi_dsi_host *host);
>  int msm_dsi_host_disable(struct mipi_dsi_host *host);
> +void msm_dsi_host_adjust_timing_config(struct mipi_dsi_host *host);
>  int msm_dsi_host_power_on(struct mipi_dsi_host *host,
>   struct msm_dsi_phy_shared_timings *phy_shared_timings);
>  int msm_dsi_host_power_off(struct mipi_dsi_host *host);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7a03a94..66a21cb 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2237,6 +2237,23 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host 
> *msm_host, bool enable)
>   SFPB_GPREG_MASTER_PORT_EN(en));
>  }
>  
> +void msm_dsi_host_adjust_timing_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> + struct drm_display_mode *mode = NULL;
> +
> + mode = msm_host->mode;
> +
> + mutex_lock(_host->dev_mutex);
> + mode->htotal >>= 1;
> + mode->hdisplay >>= 1;
> + mode->hsync_start >>= 1;
> + mode->hsync_end >>= 1;
> +
> + mode->clock >>= 1;
> + mutex_unlock(_host->dev_mutex);
> +}
> +
>  int msm_dsi_host_power_on(struct mipi_dsi_host *host,
>   struct msm_dsi_phy_shared_timings *phy_shared_timings)
>  {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 4cb1cb6..8ef1c3d 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -627,6 +627,21 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge 
> *bridge,
>   msm_dsi_host_set_display_mode(host, adjusted_mode);
>   if (is_dual_dsi && other_dsi)
>   msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode);
> +
> + /*
> +  * For dual DSI mode, the current DRM mode has
> +  * the complete width of the panel. Since, the complete
> +  * panel is driven by two DSI controllers, the
> +  * horizontal timings and the pixel clock have to be
> +  * split between the two dsi controllers. Adjust the
> +  * DSI host timing structures accordingly.
> +  */
> + if (is_dual_dsi) {
> + msm_dsi_host_adjust_timing_config(host);
> + if (other_dsi)
> + msm_dsi_host_adjust_timing_config(other_dsi->host);
> + }
> +
>  }
>  
>  static const struct drm_connector_funcs dsi_mgr_connector_funcs = {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

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Re: [Freedreno] [DPU PATCH v3 1/2] drm/msm/dsi: check video mode engine status before waiting

[Sean Paul]

On Mon, Apr 16, 2018 at 06:56:45PM -0700, Abhinav Kumar wrote:
> Make sure the video mode engine is on before waiting
> for the video done interrupt.
> 
> Changes in v2:
> - Replace pr_err with dev_err
> - Changed error message
> 
> Changes in v3:
> - Move the return value check to another
>   patch
> 
> Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7a03a94..8df0d44 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -173,6 +173,7 @@ struct msm_dsi_host {
>  
>   bool registered;
>   bool power_on;
> + bool enabled;
>   int irq;
>  };
>  
> @@ -1001,7 +1002,7 @@ static void dsi_wait4video_eng_busy(struct msm_dsi_host 
> *msm_host)
>   if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
>   return;
>  
> - if (msm_host->power_on) {
> + if (msm_host->power_on && msm_host->enabled) {
>   dsi_wait4video_done(msm_host);
>   /* delay 4 ms to skip BLLP */
>   usleep_range(2000, 4000);
> @@ -2203,7 +2204,7 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host)
>*  pm_runtime_put_autosuspend(_host->pdev->dev);
>* }
>*/
> -
> + msm_host->enabled = true;
>   return 0;
>  }
>  
> @@ -2219,7 +2220,7 @@ int msm_dsi_host_disable(struct mipi_dsi_host *host)
>* Reset to disable video engine so that we can send off cmd.
>*/
>   dsi_sw_reset(msm_host);
> -
> + msm_host->enabled = false;

I thought this was moving to the start of the function?

>   return 0;
>  }
>  
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

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Re: [Freedreno] [DPU PATCH v2 1/2] drm/msm/dsi: check video mode engine status before waiting

[Sean Paul]

On Mon, Apr 16, 2018 at 10:44:57AM -0700, abhin...@codeaurora.org wrote:
> Hi Sean
> 
> Thanks for reviewing.
> 
> Reply inline.
> 
> On 2018-04-16 10:07, Sean Paul wrote:
> > On Fri, Apr 13, 2018 at 03:04:48PM -0700, abhin...@codeaurora.org wrote:
> > > On 2018-04-13 14:10, abhin...@codeaurora.org wrote:
> > > > Hi Sean
> > > >
> > > > Thanks for the review.
> > > >
> > > > Reply inline.
> > > >
> > > > On 2018-04-13 13:26, Sean Paul wrote:
> > > > > On Tue, Apr 10, 2018 at 06:54:06PM -0700, Abhinav Kumar wrote:
> > > > > > Make sure the video mode engine is on before waiting
> > > > > > for the video done interrupt.
> > > > > >
> > > > > > Otherwise it leads to silent timeouts increasing display
> > > > > > turn ON time.
> > > > > >
> > > > > > Changes in v2:
> > > > > > - Replace pr_err with dev_err
> > > > > > - Changed error message
> > > > > >
> > > > > > Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
> > > > > > ---
> > > > > >  drivers/gpu/drm/msm/dsi/dsi_host.c | 15 +++
> > > > > >  1 file changed, 11 insertions(+), 4 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > > > b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > > > index 7a03a94..5b7b290 100644
> > > > > > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > > > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > > > @@ -173,6 +173,7 @@ struct msm_dsi_host {
> > > > > >
> > > > > > bool registered;
> > > > > > bool power_on;
> > > > > > +   bool enabled;
> > > > > > int irq;
> > > > > >  };
> > > > > >
> > > > > > @@ -986,13 +987,19 @@ static void dsi_set_tx_power_mode(int
> > > > > > mode, struct msm_dsi_host *msm_host)
> > > > > >
> > > > > >  static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
> > > > > >  {
> > > > > > +   u32 ret = 0;
> > > > > > +   struct device *dev = _host->pdev->dev;
> > > > > > +
> > > > > > dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
> > > > > >
> > > > > > reinit_completion(_host->video_comp);
> > > > > >
> > > > > > -   wait_for_completion_timeout(_host->video_comp,
> > > > > > +   ret = wait_for_completion_timeout(_host->video_comp,
> > > > > > msecs_to_jiffies(70));
> > > > > >
> > > > > > +   if (ret <= 0)
> > > > > > +   dev_err(dev, "wait for video done timed out\n");
> > > > > > +
> > > > > > dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
> > > > > >  }
> > > > > >
> > > > > > @@ -1001,7 +1008,7 @@ static void dsi_wait4video_eng_busy(struct
> > > > > > msm_dsi_host *msm_host)
> > > > > > if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
> > > > > > return;
> > > > > >
> > > > > > -   if (msm_host->power_on) {
> > > > > > +   if (msm_host->power_on && msm_host->enabled) {
> > > > > > dsi_wait4video_done(msm_host);
> > > > > > /* delay 4 ms to skip BLLP */
> > > > > > usleep_range(2000, 4000);
> > > > > > @@ -2203,7 +2210,7 @@ int msm_dsi_host_enable(struct
> > > > > > mipi_dsi_host *host)
> > > > > >  *  pm_runtime_put_autosuspend(_host->pdev->dev);
> > > > > >  * }
> > > > > >  */
> > > > > > -
> > > > > > +   msm_host->enabled = true;
> > > > > > return 0;
> > > > > >  }
> > > > > >
> > > > > > @@ -2219,7 +2226,7 @@ int msm_dsi_host_disable(struct
> > > > > > mipi_dsi_host *host)
> > > > > >  * Reset to disable video engine so that we can send off cmd.
> > > > > >  */
> > > &

Re: [Freedreno] [DPU PATCH v2 1/2] drm/msm/dsi: check video mode engine status before waiting

[Sean Paul]

On Fri, Apr 13, 2018 at 03:04:48PM -0700, abhin...@codeaurora.org wrote:
> On 2018-04-13 14:10, abhin...@codeaurora.org wrote:
> > Hi Sean
> > 
> > Thanks for the review.
> > 
> > Reply inline.
> > 
> > On 2018-04-13 13:26, Sean Paul wrote:
> > > On Tue, Apr 10, 2018 at 06:54:06PM -0700, Abhinav Kumar wrote:
> > > > Make sure the video mode engine is on before waiting
> > > > for the video done interrupt.
> > > > 
> > > > Otherwise it leads to silent timeouts increasing display
> > > > turn ON time.
> > > > 
> > > > Changes in v2:
> > > > - Replace pr_err with dev_err
> > > > - Changed error message
> > > > 
> > > > Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
> > > > ---
> > > >  drivers/gpu/drm/msm/dsi/dsi_host.c | 15 +++
> > > >  1 file changed, 11 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > index 7a03a94..5b7b290 100644
> > > > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > > > @@ -173,6 +173,7 @@ struct msm_dsi_host {
> > > > 
> > > > bool registered;
> > > > bool power_on;
> > > > +   bool enabled;
> > > > int irq;
> > > >  };
> > > > 
> > > > @@ -986,13 +987,19 @@ static void dsi_set_tx_power_mode(int
> > > > mode, struct msm_dsi_host *msm_host)
> > > > 
> > > >  static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
> > > >  {
> > > > +   u32 ret = 0;
> > > > +   struct device *dev = _host->pdev->dev;
> > > > +
> > > > dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
> > > > 
> > > > reinit_completion(_host->video_comp);
> > > > 
> > > > -   wait_for_completion_timeout(_host->video_comp,
> > > > +   ret = wait_for_completion_timeout(_host->video_comp,
> > > > msecs_to_jiffies(70));
> > > > 
> > > > +   if (ret <= 0)
> > > > +   dev_err(dev, "wait for video done timed out\n");
> > > > +
> > > > dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
> > > >  }
> > > > 
> > > > @@ -1001,7 +1008,7 @@ static void dsi_wait4video_eng_busy(struct
> > > > msm_dsi_host *msm_host)
> > > > if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
> > > > return;
> > > > 
> > > > -   if (msm_host->power_on) {
> > > > +   if (msm_host->power_on && msm_host->enabled) {
> > > > dsi_wait4video_done(msm_host);
> > > > /* delay 4 ms to skip BLLP */
> > > > usleep_range(2000, 4000);
> > > > @@ -2203,7 +2210,7 @@ int msm_dsi_host_enable(struct
> > > > mipi_dsi_host *host)
> > > >  *  pm_runtime_put_autosuspend(_host->pdev->dev);
> > > >  * }
> > > >  */
> > > > -
> > > > +   msm_host->enabled = true;
> > > > return 0;
> > > >  }
> > > > 
> > > > @@ -2219,7 +2226,7 @@ int msm_dsi_host_disable(struct
> > > > mipi_dsi_host *host)
> > > >  * Reset to disable video engine so that we can send off cmd.
> > > >  */
> > > > dsi_sw_reset(msm_host);
> > > > -
> > > > +   msm_host->enabled = false;
> > > 
> > > This should go at the start of the function. Also, it's unclear from
> > > this patch,
> > > but I assume this is protected by a lock?
> > > 
> > > Sean
> > [Abhinav] Yes, will move this to the start.
> > No, there is no lock here but at this point doesnt need one.
> > The reason is that, this variable will be written to and read by the
> > same process
> > (suspend thread OR resume thread which sends the panel ON/OFF commands).
> > If we decide to expose other interfaces to send commands like debugfs
> > or sysfs and
> > introduce more threads, we will add the locking.
> [Abhinav] Correction to my prev comment, we do have the msm_host->cmd_mutex
> which will
> ensure this entire process is protected. That should suffice.

Ok, thanks for confirming. Could you also please split this patch into the
wait4video_done ret fix and the ->enabled addition? The 2 seem mostly unrelated.

Sean

> > > 
> > > 
> > > > return 0;
> > > >  }
> > > > 
> > > > --
> > > > The Qualcomm Innovation Center, Inc. is a member of the Code
> > > > Aurora Forum,
> > > > a Linux Foundation Collaborative Project
> > > > 
> > > > ___
> > > > Freedreno mailing list
> > > > Freedreno@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/freedreno
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm"
> > in
> > the body of a message to majord...@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html

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Re: [Freedreno] [DPU PATCH 2/2] drm/panel: add backlight control support for truly panel

[Sean Paul]

On Fri, Apr 13, 2018 at 01:59:29PM -0700, abhin...@codeaurora.org wrote:
> Hi Sean
> 
> Thanks for the comments.
> 
> Some replies inline.
> 
> On 2018-04-13 13:46, Sean Paul wrote:
> > On Sat, Apr 07, 2018 at 12:06:53AM -0700, Abhinav Kumar wrote:
> > > Register truly panel as a backlight led device and
> > > provide methods to control its backlight operation.
> > > 
> > > Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
> > > ---



> > > + if (!ctx->backlight) {
> > > + memset(, 0, sizeof(props));
> > > + props.type = BACKLIGHT_RAW;
> > > + props.power = FB_BLANK_UNBLANK;
> > > + props.max_brightness = 4096;
> > > +
> > > + snprintf(bl_node_name, BL_NODE_NAME_SIZE, "panel%u-backlight",
> > > +  PRIM_DISPLAY_NODE);
> > 
> > Given that PRIM_DISPLAY_NODE is always 0, this seems like overkill for a
> > pretty
> > generic name "panel0-backlight". So let's just call it "truly_backlight"
> > in the
> > register call.
> > 
> [Abhinav] The reason for keeping it "panel0-backlight" is because userspace
> is using
> this node name to write the backlight. Changing the name will need more
> changes in our
> userspace.
> 

Unless the userspace is opensource (I'm guessing it's not?), that's not
something we need to code around. It sounds like this is mostly a moot point
given Bjorn's comments on the v2.

Sean



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Re: [Freedreno] [[RFC]DPU PATCH 1/2] drm/bridge: add support for sn65dsi86 bridge driver

[Sean Paul]

On Mon, Apr 16, 2018 at 11:32:50AM +0530, spa...@codeaurora.org wrote:
> On 2018-04-14 00:59, Sean Paul wrote:
> > On Fri, Apr 13, 2018 at 10:53:00AM +0530, Sandeep Panda wrote:
> > > Add support for TI's sn65dsi86 dsi2edp bridge chip.
> > > The chip converts DSI transmitted signal to eDP signal,
> > > which is fed to the connected eDP panel.
> > > 
> > > This chip can be controlled via either i2c interface or
> > > dsi interface. Currently in driver all the control registers
> > > are being accessed through i2c interface only.
> > > Also as of now HPD support has not been added to bridge
> > > chip driver.
> > > 
> > > Signed-off-by: Sandeep Panda <spa...@codeaurora.org>



> > > +{
> > > + struct mipi_dsi_host *host;
> > > + struct mipi_dsi_device *dsi;
> > > + struct sn65dsi86 *pdata = bridge_to_sn65dsi86(bridge);
> > > + int ret;
> > > + const struct mipi_dsi_device_info info = { .type = "sn65dsi86",
> > > +.channel = 0,
> > > +.node = NULL,
> > > +  };
> > > +
> > > + if (!bridge->encoder) {
> > > + DRM_ERROR("Parent encoder object not found");
> > > + return -ENODEV;
> > > + }
> > > +
> > > + /* HPD not supported */
> > > + pdata->connector.polled = 0;
> > > +
> > 
> > You'll need to refactor the below to accommodate panels. If you're not
> > planning
> > on supporting hotplug, you should probably remove all of the
> > connector-related
> > stuff from this driver, since you will always be using a panel driver.
> > 
> 
> Thanks for reviewing the patch in detail.
> 
> I have one doubt here. If we remove connector from bridge driver, then how
> will detect()
> and get_modes() called. If you are suggesting to use panel func's detect()
> and get_mode()
> then it might not work, because once upstream DSI driver sees an external
> bridge is connected
> to DSI, then it does not create a connector of it own, it expects the
> external bridge
> to create the connector node. I think here the external bridge has to create
> the connector
> and when detect() and get_modes() call come to external bridge then it
> should query connected
> panel's detect() and get_modes() API.
> 

Right, thanks for setting me straight. You'll need to call the drm_panel_*
helper functions if the panel is present for the connector hooks.

Sean




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Re: [Freedreno] [DPU PATCH 2/2] drm/panel: add backlight control support for truly panel

[Sean Paul]

struct mipi_dsi_device 
> *dsi)
>   secondary = of_find_mipi_dsi_device_by_node(np);
>   of_node_put(np);
>  
> + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
> +

Why move this?

>   if (!secondary)
>   return -EPROBE_DEFER;
>  
> - ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
>   if (!ctx) {
>   put_device(>dev);
>   return -ENOMEM;
> @@ -485,6 +569,12 @@ static int truly_wqxga_probe(struct mipi_dsi_device *dsi)
>   put_device(>dev);
>   return ret;
>   }
> +
> + ret = truly_backlight_setup(ctx);
> + if (ret) {
> + put_device(>dev);
> + return ret;
> + }
>   }
>  
>   ret = mipi_dsi_attach(dsi);
> @@ -504,8 +594,10 @@ static int truly_wqxga_remove(struct mipi_dsi_device 
> *dsi)
>   mipi_dsi_detach(dsi);
>  
>   /* delete panel only for the DSI1 interface */
> - if (ctx)
> + if (ctx) {
>   truly_wqxga_panel_del(ctx);
> + kfree(ctx);
> + }
>  
>   return 0;
>  }
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

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Re: [Freedreno] [DPU PATCH v2 1/2] drm/msm/dsi: check video mode engine status before waiting

[Sean Paul]

On Tue, Apr 10, 2018 at 06:54:06PM -0700, Abhinav Kumar wrote:
> Make sure the video mode engine is on before waiting
> for the video done interrupt.
> 
> Otherwise it leads to silent timeouts increasing display
> turn ON time.
> 
> Changes in v2:
> - Replace pr_err with dev_err
> - Changed error message
> 
> Signed-off-by: Abhinav Kumar <abhin...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c | 15 +++
>  1 file changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7a03a94..5b7b290 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -173,6 +173,7 @@ struct msm_dsi_host {
>  
>   bool registered;
>   bool power_on;
> + bool enabled;
>   int irq;
>  };
>  
> @@ -986,13 +987,19 @@ static void dsi_set_tx_power_mode(int mode, struct 
> msm_dsi_host *msm_host)
>  
>  static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
>  {
> + u32 ret = 0;
> + struct device *dev = _host->pdev->dev;
> +
>   dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
>  
>   reinit_completion(_host->video_comp);
>  
> - wait_for_completion_timeout(_host->video_comp,
> + ret = wait_for_completion_timeout(_host->video_comp,
>   msecs_to_jiffies(70));
>  
> + if (ret <= 0)
> + dev_err(dev, "wait for video done timed out\n");
> +
>   dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
>  }
>  
> @@ -1001,7 +1008,7 @@ static void dsi_wait4video_eng_busy(struct msm_dsi_host 
> *msm_host)
>   if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
>   return;
>  
> - if (msm_host->power_on) {
> + if (msm_host->power_on && msm_host->enabled) {
>   dsi_wait4video_done(msm_host);
>   /* delay 4 ms to skip BLLP */
>   usleep_range(2000, 4000);
> @@ -2203,7 +2210,7 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host)
>*  pm_runtime_put_autosuspend(_host->pdev->dev);
>* }
>*/
> -
> + msm_host->enabled = true;
>   return 0;
>  }
>  
> @@ -2219,7 +2226,7 @@ int msm_dsi_host_disable(struct mipi_dsi_host *host)
>* Reset to disable video engine so that we can send off cmd.
>*/
>   dsi_sw_reset(msm_host);
> -
> + msm_host->enabled = false;

This should go at the start of the function. Also, it's unclear from this patch,
but I assume this is protected by a lock?

Sean


>   return 0;
>  }
>  
> -- 
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> a Linux Foundation Collaborative Project
> 
> ___
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Re: [Freedreno] [DPU PATCH 2/2] drm/msm/dsi: Use one connector for dual DSI mode

[Sean Paul]

t;  
> - /* Since we have 2 connectors, but only 1 drm_panel in dual DSI mode,
> -  * panel should not attach to any connector.
> -  * Only temporarily attach panel to the current connector here,
> -  * to let panel set mode to this connector.
> + /*
> +  * In dual DSI mode, we have one connector that can be
> +  * attached to the drm_panel.
>*/
>   drm_panel_attach(panel, connector);
>   num = drm_panel_get_modes(panel);
> - drm_panel_detach(panel);
>   if (!num)
>   return 0;
>  
> - if (IS_DUAL_DSI()) {
> - /* report half resolution to user */
> - dsi_dual_connector_fix_modes(connector);
> - ret = dsi_dual_connector_tile_init(connector, id);
> - if (ret)
> - return ret;
> - ret = drm_mode_connector_set_tile_property(connector);
> - if (ret) {
> - pr_err("%s: set tile property failed, %d\n",
> - __func__, ret);
> - return ret;
> - }
> - }
> -
>   return num;
>  }
>  
> @@ -454,8 +377,8 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge 
> *bridge)
>   if (ret)
>   goto phy_en_fail;
>  
> - /* Do nothing with the host if it is DSI 1 in case of dual DSI */
> - if (is_dual_dsi && (DSI_1 == id))
> + /* Do nothing with the host if it is slave-DSI in case of dual DSI */
> + if (is_dual_dsi && (!IS_MASTER_DSI_LINK(id)))

You have extra parentheses here and below.

Sean

>   return;
>  
>   ret = msm_dsi_host_power_on(host, _shared_timings[id]);
> @@ -556,11 +479,11 @@ static void dsi_mgr_bridge_post_disable(struct 
> drm_bridge *bridge)
>   return;
>  
>   /*
> -  * Do nothing with the host if it is DSI 1 in case of dual DSI.
> +  * Do nothing with the host if it is slave-DSI in case of dual DSI.
>* It is safe to call dsi_mgr_phy_disable() here because a single PHY
>* won't be diabled until both PHYs request disable.
>*/
> - if (is_dual_dsi && (DSI_1 == id))
> + if (is_dual_dsi && (!IS_MASTER_DSI_LINK(id)))
>   goto disable_phy;
>  
>   if (panel) {
> @@ -621,7 +544,7 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge 
> *bridge,
>   mode->vsync_end, mode->vtotal,
>   mode->type, mode->flags);
>  
> - if (is_dual_dsi && (DSI_1 == id))
> + if (is_dual_dsi && (!IS_MASTER_DSI_LINK(id)))
>   return;
>  
>   msm_dsi_host_set_display_mode(host, adjusted_mode);
> @@ -704,6 +627,23 @@ struct drm_connector *msm_dsi_manager_connector_init(u8 
> id)
>   return connector;
>  }
>  
> +bool msm_dsi_manager_validate_current_config(u8 id)
> +{
> + bool is_dual_dsi = IS_DUAL_DSI();
> +
> + /*
> +  * For dual DSI, we only have one drm panel. For this
> +  * use case, we register only one bridge/connector.
> +  * Skip bridge/connector initialisation if it is
> +  * slave-DSI for dual DSI configuration.
> +  */
> + if (is_dual_dsi && (!IS_MASTER_DSI_LINK(id))) {
> + DBG("Skip bridge registration for slave DSI->id: %d\n", id);
> + return false;
> + }
> + return true;
> +}
> +
>  /* initialize bridge */
>  struct drm_bridge *msm_dsi_manager_bridge_init(u8 id)
>  {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

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Re: [Freedreno] [DPU PATCH 1/2] drm/msm/dsi: adjust dsi timing for dual dsi mode

[Sean Paul]

On Tue, Apr 10, 2018 at 06:16:07PM -0700, Chandan Uddaraju wrote:
> For dual dsi mode, the horizontal timing needs
> to be divided by half since both the dsi controllers
> will be driving this panel. Adjust the pixel clock and
> DSI timing accordingly.
> 
> Change-Id: Iee1226b2eef9eea23d9653e3d738ee8cd2a2dd8e
> Signed-off-by: Chandan Uddaraju <chand...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi.h |  1 +
>  drivers/gpu/drm/msm/dsi/dsi_host.c| 17 +
>  drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 +++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 70d9a9a..4131b47 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -161,6 +161,7 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host 
> *host,
>   u32 dma_base, u32 len);
>  int msm_dsi_host_enable(struct mipi_dsi_host *host);
>  int msm_dsi_host_disable(struct mipi_dsi_host *host);
> +void msm_dsi_host_adjust_timing_config(struct mipi_dsi_host *host);
>  int msm_dsi_host_power_on(struct mipi_dsi_host *host,
>   struct msm_dsi_phy_shared_timings *phy_shared_timings);
>  int msm_dsi_host_power_off(struct mipi_dsi_host *host);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7a03a94..66a21cb 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2237,6 +2237,23 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host 
> *msm_host, bool enable)
>   SFPB_GPREG_MASTER_PORT_EN(en));
>  }
>  
> +void msm_dsi_host_adjust_timing_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> + struct drm_display_mode *mode = NULL;
> +
> + mode = msm_host->mode;
> +
> + mutex_lock(_host->dev_mutex);
> + mode->htotal >>= 1;
> + mode->hdisplay >>= 1;
> + mode->hsync_start >>= 1;
> + mode->hsync_end >>= 1;
> +
> + mode->clock >>= 1;

I don't think you should alter the mode. Instead, apply the division when you're
writing out to hardware. Also, no need to get fancy with a bitshift, just use /2
and trust that the compiler is smart :)

Sean

> + mutex_unlock(_host->dev_mutex);
> +}
> +
>  int msm_dsi_host_power_on(struct mipi_dsi_host *host,
>   struct msm_dsi_phy_shared_timings *phy_shared_timings)
>  {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
> b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index 4cb1cb6..8ef1c3d 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -627,6 +627,21 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge 
> *bridge,
>   msm_dsi_host_set_display_mode(host, adjusted_mode);
>   if (is_dual_dsi && other_dsi)
>   msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode);
> +
> + /*
> +  * For dual DSI mode, the current DRM mode has
> +  * the complete width of the panel. Since, the complete
> +  * panel is driven by two DSI controllers, the
> +  * horizontal timings and the pixel clock have to be
> +  * split between the two dsi controllers. Adjust the
> +  * DSI host timing structures accordingly.
> +  */
> + if (is_dual_dsi) {
> + msm_dsi_host_adjust_timing_config(host);
> + if (other_dsi)
> +     msm_dsi_host_adjust_timing_config(other_dsi->host);
> + }
> +
>  }
>  
>  static const struct drm_connector_funcs dsi_mgr_connector_funcs = {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

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Re: [Freedreno] [[RFC]DPU PATCH 1/2] drm/bridge: add support for sn65dsi86 bridge driver

[Sean Paul]

{
> + pr_err("failed to get enable gpio from DT\n");
> + ret = PTR_ERR(pdata->gpios.enable_gpio);
> + goto exit;
> + }
> +
> + pdata->gpios.aux_i2c_scl = devm_gpiod_get(pdata->dev, "aux-scl",
> +   GPIOD_OUT_HIGH);
> + if (IS_ERR(pdata->gpios.aux_i2c_scl)) {
> + pr_err("failed to get aux scl gpio from DT\n");
> + ret = PTR_ERR(pdata->gpios.aux_i2c_scl);
> + goto exit;
> + }
> +
> + pdata->gpios.aux_i2c_sda = devm_gpiod_get(pdata->dev, "aux-sda",
> +   GPIOD_OUT_HIGH);
> + if (IS_ERR(pdata->gpios.aux_i2c_sda)) {
> + pr_err("failed to get aux sda gpio from DT\n");
> + ret = PTR_ERR(pdata->gpios.aux_i2c_sda);
> + goto exit;
> + }
> +
> + pdata->gpios.edp_bias_en = devm_gpiod_get(pdata->dev, "bias-en",
> +   GPIOD_OUT_HIGH);
> + if (IS_ERR(pdata->gpios.edp_bias_en)) {
> + pr_err("failed to get bias en gpio from DT\n");
> + ret = PTR_ERR(pdata->gpios.edp_bias_en);
> + goto exit;
> + }
> +
> + pdata->gpios.edp_bklt_en = devm_gpiod_get(pdata->dev, "bklt-en",
> +   GPIOD_OUT_HIGH);
> + if (IS_ERR(pdata->gpios.edp_bklt_en)) {
> + pr_err("failed to get bklt en gpio from DT\n");
> + ret = PTR_ERR(pdata->gpios.edp_bklt_en);
> + goto exit;
> + }
> +
> + pdata->gpios.irq_gpio = devm_gpiod_get_optional(pdata->dev, "irq",
> +   GPIOD_OUT_HIGH);
> + if (IS_ERR(pdata->gpios.irq_gpio))
> + pr_err("failed to get irq gpio from DT\n");
> +
> + pdata->gpios.edp_bklt_ctrl = devm_gpiod_get_optional(pdata->dev,
> + "bklt-ctrl", GPIOD_OUT_HIGH);
> + if (IS_ERR(pdata->gpios.edp_bklt_ctrl))
> + pr_err("failed to get bklt ctrl gpio from DT\n");
> +
> +exit:
> + return ret;
> +}
> +
> +static int sn65dsi86_parse_dt(struct device *dev, struct sn65dsi86 *pdata)
> +{
> + struct device_node *np = dev->of_node;
> + struct device_node *end_node;
> + int ret = 0;
> +
> + end_node = of_graph_get_endpoint_by_regs(np, 0, 0);
> + if (!end_node) {
> + pr_err("remote endpoint not found\n");
> + return -ENODEV;
> + }
> +
> + pdata->host_node = of_graph_get_remote_port_parent(end_node);
> + of_node_put(end_node);
> + if (!pdata->host_node) {
> + pr_err("remote node not found\n");
> + return -ENODEV;
> + }
> + of_node_put(pdata->host_node);
> +
> + ret = sn65dsi86_parse_gpios(np, pdata);
> +
> + pdata->is_pluggable = of_property_read_bool(np, "sn,is-pluggable");
> + pr_debug("is_pluggable = %d\n", pdata->is_pluggable);
> + if (!pdata->is_pluggable) {
> + INIT_LIST_HEAD(>mode_list);
> + sn65dsi86_parse_dt_modes(np,
> + >mode_list, >num_of_modes);
> + }
> +
> + return ret;
> +}
> +
> +static int sn65dsi86_probe(struct i2c_client *client,
> +  const struct i2c_device_id *id)
> +{
> + struct sn65dsi86 *pdata;
> + int ret = 0;
> + struct drm_display_mode *mode, *n;
> +
> + if (!client || !client->dev.of_node) {
> + pr_err("invalid input\n");
> + return -EINVAL;
> + }
> +
> + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
> + pr_err("device doesn't support I2C\n");
> + return -ENODEV;
> + }
> +
> + pdata = devm_kzalloc(>dev,
> + sizeof(struct sn65dsi86), GFP_KERNEL);
> + if (!pdata)
> + return -ENOMEM;
> +
> + pdata->power_on = false;
> + pdata->is_pluggable = false;
> + pdata->connector_status = connector_status_disconnected;
> + pdata->dev = >dev;
> + pdata->i2c_client = client;
> + pr_debug("I2C address is %x\n", client->addr);
> +
> + ret = sn65dsi86_parse_dt(>dev, pdata);
> + if (ret) {
> + pr_err("failed to parse device tree\n");
> + goto err_dt_parse;
> + }
> +
> + sn65dsi86_gpio_configure(pdata, true);
> +
> + ret = sn65dsi86_init_regulators(pdata);
> + if (ret) {
> + pr_err("failed to enable regulators\n");
> + goto err_gpio_config;
> + }
> +
> + ret = sn65dsi86_read_device_rev(pdata);
> + if (ret) {
> + pr_err("failed to read chip rev\n");
> + goto err_gpio_config;
> + } else {
> + pr_debug("bridge chip enabled successfully\n");
> + pdata->power_on = true;
> + }
> +
> + pdata->irq = gpiod_to_irq(pdata->gpios.irq_gpio);
> + ret = request_threaded_irq(pdata->irq, NULL,
> + sn65dsi86_irq_thread_handler,
> + IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
> + "sn65dsi86", pdata);
> +
> + i2c_set_clientdata(client, pdata);
> + dev_set_drvdata(>dev, pdata);
> +
> + pdata->bridge.funcs = _bridge_funcs;
> + pdata->bridge.of_node = client->dev.of_node;
> +
> + drm_bridge_add(>bridge);
> +
> + return ret;
> +
> +err_gpio_config:
> + sn65dsi86_gpio_configure(pdata, false);
> +err_dt_parse:
> + if (!pdata->is_pluggable) {
> + list_for_each_entry_safe(mode, n, >mode_list, head) {
> + list_del(>head);
> + kfree(mode);
> + }
> + pdata->num_of_modes = 0;
> + }
> + devm_kfree(>dev, pdata);
> + return ret;
> +}
> +
> +static int sn65dsi86_remove(struct i2c_client *client)
> +{
> + int ret = -EINVAL;
> + struct sn65dsi86 *pdata = i2c_get_clientdata(client);
> + struct drm_display_mode *mode, *n;
> +
> + if (!pdata)
> + goto end;
> +
> + mipi_dsi_detach(pdata->dsi);
> + mipi_dsi_device_unregister(pdata->dsi);
> +
> + drm_bridge_remove(>bridge);
> +
> + disable_irq(pdata->irq);
> + free_irq(pdata->irq, pdata);
> +
> + sn65dsi86_gpio_configure(pdata, false);
> +
> + if (!pdata->is_pluggable) {
> + list_for_each_entry_safe(mode, n, >mode_list, head) {
> + list_del(>head);
> + kfree(mode);
> + }
> + }
> +
> + devm_kfree(>dev, pdata);
> +
> +end:
> + return ret;
> +}
> +
> +static struct i2c_device_id sn65dsi86_id[] = {
> + { "ti,sn65dsi86", 0},
> + {}
> +};
> +MODULE_DEVICE_TABLE(i2c, sn65dsi86_id);
> +
> +static const struct of_device_id sn65dsi86_match_table[] = {
> + {.compatible = "ti,sn65dsi86"},
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, sn65dsi86_match_table);
> +
> +static struct i2c_driver sn65dsi86_driver = {
> + .driver = {
> + .name = "sn65dsi86",
> + .owner = THIS_MODULE,
> + .of_match_table = sn65dsi86_match_table,
> + },
> + .probe = sn65dsi86_probe,
> + .remove = sn65dsi86_remove,
> + .id_table = sn65dsi86_id,
> +};
> +
> +module_i2c_driver(sn65dsi86_driver);
> +MODULE_DESCRIPTION("SN65DSI86 DSI to eDP bridge driver");
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [Freedreno] [[RFC]DPU PATCH 2/2] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings

[Sean Paul]

On Fri, Apr 13, 2018 at 1:23 AM Sandeep Panda  wrote:

> Document the bindings used for the sn65dsi86 DSI to eDP bridge.

> Signed-off-by: Sandeep Panda 
> ---
>   .../bindings/display/bridge/ti,sn65dsi86.txt   | 75
++
>   1 file changed, 75 insertions(+)
>   create mode 100644
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt

> diff --git
a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
> new file mode 100644
> index 000..cbd2f0e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
> @@ -0,0 +1,75 @@
> +SN65DSI86 DSI to eDP bridge chip
> +
> +
> +This is the binding for Texas Instruments SN65DSI86 bridge.
> +
> +Required properties:
> +- compatible: Must be "ti,sn65dsi86"
> +- reg: i2c address of the chip, 0x2d as per datasheet
> +- enable-gpios: OF device-tree gpio specification for EDP_BRIJ_EN pin
> +- aux-sda-gpios: OF device-tree gpio specification for EDP_BRIJ_I2C_SDA
pin of AUX channel
> +- aux-scl-gpios: OF device-tree gpio specification for EDP_BRIJ_I2C_SCL
pin of AUX channel
> +- bias-en-gpios: OF device-tree gpio specification for EN_PP3300_DX_EDP
pin to


PP3300?


> +   enable 3.3V supply to eDP connector
> +- bklt-en-gpios: OF device-tree gpio specification for AP_EDP_BKLTEN pin


I don't see any of these pins listed in the SN65DSI86 datasheet. Can you
please use the actual pin names?


> +
> +- vccio-supply: A 1.8V supply that powers up the PHY.
> +- vcca-supply: A 1.2V supply that powers up the Controller.
> +- vccs-supply: A 3.3V supply that power the eDP connector
> +
> +Optional properties:
> +
> +- irq-gpios: OF device-tree gpio specification for interrupt pin
> +- bklt-ctrl-gpios: OF device-tree gpio specification for EDP_BKLTCTL pin


Same comment here, this isn't listed in the datasheet


> +
> +- sn,is-pluggable: boolean property to specify if HPD supported or not


Could you infer this from whether there's a panel present in the dts?


> +- sn,custom-modes: OF device-tree specifiction to add support for custom
modes


Please drop custom-modes, it doesn't belong on the bridge.

> +
> +Required nodes:
> +
> +This device has two video ports. Their connections are modelled using
the OF
> +graph bindings specified in Documentation/devicetree/bindings/graph.txt.
> +
> +- Video port 0 for DSI input
> +- Video port 1 for eDP output
> +
> +Example
> +---
> +
> +edp-bridge@2d {
> +   compatible = "ti,sn65dsi86";
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +   reg = <0x2d>;
> +
> +   enable-gpios = < 33 GPIO_ACTIVE_HIGH>;
> +   aux-sda-gpios = < 34 GPIO_ACTIVE_HIGH>;
> +   aux-scl-gpios = < 35 GPIO_ACTIVE_HIGH>;
> +   bias-en-gpios = < 36 GPIO_ACTIVE_HIGH>;
> +   bklt-en-gpios = < 37 GPIO_ACTIVE_HIGH>;
> +
> +   vccio-supply = <_l17>;
> +   vcca-supply = <_l6>;
> +   vccs-supply = <_l7>;
> +
> +   ports {
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +
> +   port@0 {
> +   reg = <0>;
> +
> +   edp_bridge_in: endpoint {
> +   remote-endpoint = <_out>;
> +   };
> +   };
> +
> +   port@1 {
> +   reg = <1>;
> +
> +   edp_bridge_out: endpoint {
> +   remote-endpoint = <_panel_in>;
> +   };
> +   };
> +   };
> +}
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
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Re: [Freedreno] [DPU PATCH v2 0/2] Remove DPU RSC support

[Sean Paul]

On Wed, Apr 04, 2018 at 02:34:40PM +0530, Rajesh Yadav wrote:
> MSM display controller hardware (DPU) has an inbuilt RSC block
> which can control power resources and bus bandwidth voting
> based on frame timing parameters w/o DPU driver intervention.
> In absence of RSC HW, DPU driver controls these resources.
> 
> Downstream driver relies on RSC driver for controlling these
> resources (via RSC HW block) for better power benefits.
> 
> Since, DPU driver can control these resources, removing RSC
> driver support. Corresponding devicetree binding are also removed.
> 
> Details for DPU driver upstreaming:
> https://lists.freedesktop.org/archives/freedreno/2018-February/001678.html
> 
> Changes in v2:
>   - Remove last reference to dpu_power_rsc_update
>   - Add DPU PATCH tag for better filtering
>   - Rebase on tip of for-next-staging

Hi Rajesh,
Unrelated to this change, but I've noticed the threading seems off on the patch
sets you're sending. Are you sending the emails one-by-one, or specifying
--no-thread in git send-email?

Sean

> 
> Rajesh Yadav (2):
>   dt-bindings: msm/disp: Remove DPU RSC device bindings
>   drm/msm: Remove RSC support from DPU driver
> 
>  .../devicetree/bindings/display/msm/dpu-rsc.txt|   96 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c  |  130 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h  |6 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |   14 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |9 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  242 +---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|7 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |   20 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |3 -
>  drivers/gpu/drm/msm/dpu_dbg.c  |   27 -
>  drivers/gpu/drm/msm/dpu_dbg.h  |   10 -
>  drivers/gpu/drm/msm/dpu_power_handle.c |   73 +-
>  drivers/gpu/drm/msm/dpu_power_handle.h |4 -
>  drivers/gpu/drm/msm/dpu_rsc.c  | 1367 
> 
>  drivers/gpu/drm/msm/dpu_rsc_hw.c   |  818 
>  drivers/gpu/drm/msm/dpu_rsc_priv.h |  191 ---
>  include/linux/dpu_rsc.h|  302 -
>  18 files changed, 42 insertions(+), 3278 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu-rsc.txt
>  delete mode 100644 drivers/gpu/drm/msm/dpu_rsc.c
>  delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_hw.c
>  delete mode 100644 drivers/gpu/drm/msm/dpu_rsc_priv.h
>  delete mode 100644 include/linux/dpu_rsc.h
> 
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [Freedreno] [DPU PATCH 3/3] drm/msm/dsi-staging: Gate bus scale code

[Sean Paul]

On Wed, Mar 28, 2018 at 11:48:48AM +0530, Rajesh Yadav wrote:
> DSI driver relies on downstream bus scaling
> driver (msm_bus) for bus bandwidth voting.
> Gate the bus bandwidth voting code under
> CONFIG_QCOM_BUS_SCALING.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Thank you for your patch. Since dsi-staging isn't going upstream, let's hold
off on this.

Sean

> ---
>  drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c | 8 
>  drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c| 7 ++-
>  drivers/gpu/drm/msm/dsi-staging/dsi_phy.c | 2 ++
>  3 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c 
> b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c
> index 919de1e..047f759 100644
> --- a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c
> +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c
> @@ -17,7 +17,9 @@
>  #include 
>  #include "dsi_clk.h"
>  
> +#ifdef CONFIG_QCOM_BUS_SCALING
>  #include 
> +#endif
>  
>  struct dsi_core_clks {
>   struct dsi_core_clk_info clks;
> @@ -226,6 +228,7 @@ int dsi_core_clk_start(struct dsi_core_clks *c_clks)
>   }
>   }
>  
> +#ifdef CONFIG_QCOM_BUS_SCALING
>   if (c_clks->bus_handle) {
>   rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 1);
>   if (rc) {
> @@ -233,11 +236,14 @@ int dsi_core_clk_start(struct dsi_core_clks *c_clks)
>   goto error_disable_mmss_clk;
>   }
>   }
> +#endif
>   return rc;
>  
> +#ifdef CONFIG_QCOM_BUS_SCALING
>  error_disable_mmss_clk:
>   if (c_clks->clks.core_mmss_clk)
>   clk_disable_unprepare(c_clks->clks.core_mmss_clk);
> +#endif
>  
>  error_disable_bus_clk:
>   if (c_clks->clks.bus_clk)
> @@ -259,6 +265,7 @@ int dsi_core_clk_stop(struct dsi_core_clks *c_clks)
>  {
>   int rc = 0;
>  
> +#ifdef CONFIG_QCOM_BUS_SCALING
>   if (c_clks->bus_handle) {
>   rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 0);
>   if (rc) {
> @@ -266,6 +273,7 @@ int dsi_core_clk_stop(struct dsi_core_clks *c_clks)
>   return rc;
>   }
>   }
> +#endif
>  
>   if (c_clks->clks.core_mmss_clk)
>   clk_disable_unprepare(c_clks->clks.core_mmss_clk);
> diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c 
> b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
> index fae1b565..0ab92bb 100644
> --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
> +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
> @@ -17,7 +17,9 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_QCOM_BUS_SCALING
>  #include 
> +#endif
>  #include 
>  #include 
>  
> @@ -716,6 +718,7 @@ static int dsi_ctrl_axi_bus_client_init(struct 
> platform_device *pdev,
>   struct dsi_ctrl *ctrl)
>  {
>   int rc = 0;
> +#ifdef CONFIG_QCOM_BUS_SCALING
>   struct dsi_ctrl_bus_scale_info *bus = >axi_bus_info;
>  
>   bus->bus_scale_table = msm_bus_cl_get_pdata(pdev);
> @@ -731,12 +734,13 @@ static int dsi_ctrl_axi_bus_client_init(struct 
> platform_device *pdev,
>   rc = -EINVAL;
>   pr_err("failed to register axi bus client\n");
>   }
> -
> +#endif
>   return rc;
>  }
>  
>  static int dsi_ctrl_axi_bus_client_deinit(struct dsi_ctrl *ctrl)
>  {
> +#ifdef CONFIG_QCOM_BUS_SCALING
>   struct dsi_ctrl_bus_scale_info *bus = >axi_bus_info;
>  
>   if (bus->bus_handle) {
> @@ -744,6 +748,7 @@ static int dsi_ctrl_axi_bus_client_deinit(struct dsi_ctrl 
> *ctrl)
>  
>   bus->bus_handle = 0;
>   }
> +#endif
>   return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c 
> b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
> index c13e5bb..e712c61 100644
> --- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
> @@ -17,7 +17,9 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_QCOM_BUS_SCALING
>  #include 
> +#endif
>  #include 
>  
>  #include "msm_drv.h"
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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Re: [Freedreno] [DPU PATCH 1/3] drm/msm: Remove unused variables

[Sean Paul]

On Wed, Mar 28, 2018 at 11:47:46AM +0530, Rajesh Yadav wrote:
> Fix compilation errors due to unused variables.
> 
> Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>

Reviewed-by: Sean Paul <seanp...@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 1 -
>  4 files changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index bf46cf1..51cffc4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -2587,7 +2587,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>   struct dpu_crtc_irq_info *node = NULL;
>   struct drm_event event;
>   u32 power_on;
> - int ret, i;
> + int ret;
>  
>   if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
>   DPU_ERROR("invalid crtc\n");
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> index 2bc5894..3b1212b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> @@ -264,7 +264,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct 
> dpu_encoder_phys *phys_enc,
>   const struct msm_format *format;
>   int ret;
>   struct msm_gem_address_space *aspace;
> - u32 fb_mode;
>  
>   if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog ||
>   !phys_enc->connector) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 7186c64..8ef75f5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -426,7 +426,6 @@ static void dpu_kms_commit(struct msm_kms *kms, struct 
> drm_atomic_state *state)
>  {
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *crtc_state;
> - struct dpu_crtc_state *cstate;
>   int i;
>  
>   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index c657e6b..b11a918 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -2742,7 +2742,6 @@ static void dpu_plane_destroy_state(struct drm_plane 
> *plane,
>   struct dpu_plane *pdpu;
>   struct dpu_plane_state *pstate;
>   struct dpu_plane_state *old_state;
> - struct drm_property *drm_prop;
>  
>   if (!plane) {
>   DPU_ERROR("invalid plane\n");
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
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[Freedreno] [PATCH v4 5/9] drm/msm: Move implicit sync handling to prepare_fb

[Sean Paul]

In preparation for moving to atomic helpers, move the implicit sync
fence handling out of atomic commit and into the plane->prepare_fb()
hook. While we're at it, de-duplicate the mdp*_prepare_fb functions.

Changes in v4:
- Added

Reported-by: Rob Clark <robdcl...@gmail.com>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 17 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 16 +---
 drivers/gpu/drm/msm/msm_atomic.c   | 22 ++
 drivers/gpu/drm/msm/msm_drv.h  |  2 ++
 4 files changed, 26 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index 7a1ad3af08e3..20e956e14c21 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -98,21 +98,6 @@ static const struct drm_plane_funcs mdp4_plane_funcs = {
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 };
 
-static int mdp4_plane_prepare_fb(struct drm_plane *plane,
-struct drm_plane_state *new_state)
-{
-   struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
-   struct mdp4_kms *mdp4_kms = get_kms(plane);
-   struct msm_kms *kms = _kms->base.base;
-   struct drm_framebuffer *fb = new_state->fb;
-
-   if (!fb)
-   return 0;
-
-   DBG("%s: prepare: FB[%u]", mdp4_plane->name, fb->base.id);
-   return msm_framebuffer_prepare(fb, kms->aspace);
-}
-
 static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
  struct drm_plane_state *old_state)
 {
@@ -152,7 +137,7 @@ static void mdp4_plane_atomic_update(struct drm_plane 
*plane,
 }
 
 static const struct drm_plane_helper_funcs mdp4_plane_helper_funcs = {
-   .prepare_fb = mdp4_plane_prepare_fb,
+   .prepare_fb = msm_atomic_prepare_fb,
.cleanup_fb = mdp4_plane_cleanup_fb,
.atomic_check = mdp4_plane_atomic_check,
.atomic_update = mdp4_plane_atomic_update,
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 5dc42d89b588..d1006ed69aad 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -245,20 +245,6 @@ static const struct drm_plane_funcs mdp5_plane_funcs = {
.atomic_print_state = mdp5_plane_atomic_print_state,
 };
 
-static int mdp5_plane_prepare_fb(struct drm_plane *plane,
-struct drm_plane_state *new_state)
-{
-   struct mdp5_kms *mdp5_kms = get_kms(plane);
-   struct msm_kms *kms = _kms->base.base;
-   struct drm_framebuffer *fb = new_state->fb;
-
-   if (!new_state->fb)
-   return 0;
-
-   DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
-   return msm_framebuffer_prepare(fb, kms->aspace);
-}
-
 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
  struct drm_plane_state *old_state)
 {
@@ -553,7 +539,7 @@ static void mdp5_plane_atomic_async_update(struct drm_plane 
*plane,
 }
 
 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
-   .prepare_fb = mdp5_plane_prepare_fb,
+   .prepare_fb = msm_atomic_prepare_fb,
.cleanup_fb = mdp5_plane_cleanup_fb,
.atomic_check = mdp5_plane_atomic_check,
.atomic_update = mdp5_plane_atomic_update,
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index c18f0bee20d4..94f9c3e0e7bf 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -16,6 +16,7 @@
  */
 
 #include "msm_drv.h"
+#include "msm_gem.h"
 #include "msm_kms.h"
 #include "msm_gem.h"
 #include "msm_fence.h"
@@ -97,6 +98,27 @@ static void msm_atomic_wait_for_commit_done(struct 
drm_device *dev,
}
 }
 
+int msm_atomic_prepare_fb(struct drm_plane *plane,
+ struct drm_plane_state *new_state)
+{
+   struct msm_drm_private *priv = plane->dev->dev_private;
+   struct msm_kms *kms = priv->kms;
+   struct drm_gem_object *obj;
+   struct msm_gem_object *msm_obj;
+   struct dma_fence *fence;
+
+   if (!new_state->fb)
+   return 0;
+
+   obj = msm_framebuffer_bo(new_state->fb, 0);
+   msm_obj = to_msm_bo(obj);
+   fence = reservation_object_get_excl_rcu(msm_obj->resv);
+
+   drm_atomic_set_fence_for_plane(new_state, fence);
+
+   return msm_framebuffer_prepare(new_state->fb, kms->aspace);
+}
+
 static void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
struct drm_device *dev = state->dev;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm

[Freedreno] [PATCH v4 3/9] drm/msm: Don't subclass drm_atomic_state anymore

[Sean Paul]

From: Archit Taneja <arch...@codeaurora.org>

With the addition of "private_objs" in drm_atomic_state, we no longer
need to subclass drm_atomic_state to store state of share resources
that don't perfectly fit within planes/crtc/connector state information.
We can now save this state within drm_atomic_state itself using
the private objects.

Remove the infrastructure that allowed subclassing of drm_atomic_state
in the driver.

Changes in v3:
- Added to the msm atomic helper patch set
Changes in v4:
- None

Signed-off-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 46 
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 22 
 drivers/gpu/drm/msm/msm_atomic.c | 31 
 drivers/gpu/drm/msm/msm_drv.c|  3 --
 drivers/gpu/drm/msm/msm_kms.h| 14 
 5 files changed, 116 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 6ada098dba0b..6e12e275deba 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -70,42 +70,6 @@ static int mdp5_hw_init(struct msm_kms *kms)
return 0;
 }
 
-struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s)
-{
-   struct msm_drm_private *priv = s->dev->dev_private;
-   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct msm_kms_state *state = to_kms_state(s);
-   struct mdp5_state *new_state;
-   int ret;
-
-   if (state->state)
-   return state->state;
-
-   ret = drm_modeset_lock(_kms->state_lock, s->acquire_ctx);
-   if (ret)
-   return ERR_PTR(ret);
-
-   new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
-   if (!new_state)
-   return ERR_PTR(-ENOMEM);
-
-   /* Copy state: */
-   new_state->hwpipe = mdp5_kms->state->hwpipe;
-   new_state->hwmixer = mdp5_kms->state->hwmixer;
-   if (mdp5_kms->smp)
-   new_state->smp = mdp5_kms->state->smp;
-
-   state->state = new_state;
-
-   return new_state;
-}
-
-static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state 
*state)
-{
-   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
-   swap(to_kms_state(state)->state, mdp5_kms->state);
-}
-
 /* Global/shared object state funcs */
 
 /*
@@ -315,7 +279,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.irq = mdp5_irq,
.enable_vblank   = mdp5_enable_vblank,
.disable_vblank  = mdp5_disable_vblank,
-   .swap_state  = mdp5_swap_state,
.prepare_commit  = mdp5_prepare_commit,
.complete_commit = mdp5_complete_commit,
.wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done,
@@ -815,8 +778,6 @@ static void mdp5_destroy(struct platform_device *pdev)
 
drm_atomic_private_obj_fini(_kms->glob_state);
drm_modeset_lock_fini(_kms->glob_state_lock);
-
-   kfree(mdp5_kms->state);
 }
 
 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
@@ -969,13 +930,6 @@ static int mdp5_init(struct platform_device *pdev, struct 
drm_device *dev)
mdp5_kms->dev = dev;
mdp5_kms->pdev = pdev;
 
-   drm_modeset_lock_init(_kms->state_lock);
-   mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
-   if (!mdp5_kms->state) {
-   ret = -ENOMEM;
-   goto fail;
-   }
-
ret = mdp5_global_obj_init(mdp5_kms);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
index 76f0ddfca322..854dfd30e829 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
@@ -28,8 +28,6 @@
 #include "mdp5_ctl.h"
 #include "mdp5_smp.h"
 
-struct mdp5_state;
-
 struct mdp5_kms {
struct mdp_kms base;
 
@@ -49,12 +47,6 @@ struct mdp5_kms {
struct mdp5_cfg_handler *cfg;
uint32_t caps;  /* MDP capabilities (MDP_CAP_XXX bits) */
 
-   /**
-* Global atomic state.  Do not access directly, use mdp5_get_state()
-*/
-   struct mdp5_state *state;
-   struct drm_modeset_lock state_lock;
-
/*
 * Global private object state, Do not access directly, use
 * mdp5_global_get_state()
@@ -88,20 +80,6 @@ struct mdp5_kms {
 };
 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
 
-/* Global atomic state for tracking resources that are shared across
- * multiple kms objects (planes/crtcs/etc).
- *
- * For atomic updates which require modifying global state,
- */
-struct mdp5_state {
-

[Freedreno] [PATCH v4 4/9] drm/msm: Refactor complete_commit() to look more the helpers

[Sean Paul]

Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.

Changes in v2:
- None
Changes in v3:
- Rebased on Archit's private_obj set
Changes in v4:
- None

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 25 -
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 9d0a0ca1f0cb..c18f0bee20d4 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -97,18 +97,12 @@ static void msm_atomic_wait_for_commit_done(struct 
drm_device *dev,
}
 }
 
-/* The (potentially) asynchronous part of the commit.  At this point
- * nothing can fail short of armageddon.
- */
-static void complete_commit(struct msm_commit *c, bool async)
+static void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
-   struct drm_atomic_state *state = c->state;
struct drm_device *dev = state->dev;
struct msm_drm_private *priv = dev->dev_private;
struct msm_kms *kms = priv->kms;
 
-   drm_atomic_helper_wait_for_fences(dev, state, false);
-
kms->funcs->prepare_commit(kms, state);
 
drm_atomic_helper_commit_modeset_disables(dev, state);
@@ -135,6 +129,19 @@ static void complete_commit(struct msm_commit *c, bool 
async)
drm_atomic_helper_cleanup_planes(dev, state);
 
kms->funcs->complete_commit(kms, state);
+}
+
+/* The (potentially) asynchronous part of the commit.  At this point
+ * nothing can fail short of armageddon.
+ */
+static void complete_commit(struct msm_commit *c)
+{
+   struct drm_atomic_state *state = c->state;
+   struct drm_device *dev = state->dev;
+
+   drm_atomic_helper_wait_for_fences(dev, state, false);
+
+   msm_atomic_commit_tail(state);
 
drm_atomic_state_put(state);
 
@@ -143,7 +150,7 @@ static void complete_commit(struct msm_commit *c, bool 
async)
 
 static void commit_worker(struct work_struct *work)
 {
-   complete_commit(container_of(work, struct msm_commit, work), true);
+   complete_commit(container_of(work, struct msm_commit, work));
 }
 
 /**
@@ -248,7 +255,7 @@ int msm_atomic_commit(struct drm_device *dev,
return 0;
}
 
-   complete_commit(c, false);
+   complete_commit(c);
 
return 0;
 
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[Freedreno] [PATCH v4 8/9] drm/msm: Remove msm_commit/worker, use atomic helper commit

[Sean Paul]

Moving further towards switching fully to the the atomic helpers, this
patch removes the hand-rolled worker nonblock commit code and uses the
atomic helpers commit_work model.

Changes in v2:
- Remove commit_destroy()
- Shuffle order of commit_tail calls to further serialize commits
- Use stall in swap_state to avoid abandoned events on disable
Changes in v3:
- Rebased on Archit's private_obj set
Changes in v4:
- None

Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 153 +--
 drivers/gpu/drm/msm/msm_drv.c|   1 -
 drivers/gpu/drm/msm/msm_drv.h|   4 -
 3 files changed, 42 insertions(+), 116 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 94f9c3e0e7bf..95c7868445dd 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -21,66 +21,6 @@
 #include "msm_gem.h"
 #include "msm_fence.h"
 
-struct msm_commit {
-   struct drm_device *dev;
-   struct drm_atomic_state *state;
-   struct work_struct work;
-   uint32_t crtc_mask;
-};
-
-static void commit_worker(struct work_struct *work);
-
-/* block until specified crtcs are no longer pending update, and
- * atomically mark them as pending update
- */
-static int start_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
-{
-   int ret;
-
-   spin_lock(>pending_crtcs_event.lock);
-   ret = wait_event_interruptible_locked(priv->pending_crtcs_event,
-   !(priv->pending_crtcs & crtc_mask));
-   if (ret == 0) {
-   DBG("start: %08x", crtc_mask);
-   priv->pending_crtcs |= crtc_mask;
-   }
-   spin_unlock(>pending_crtcs_event.lock);
-
-   return ret;
-}
-
-/* clear specified crtcs (no longer pending update)
- */
-static void end_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
-{
-   spin_lock(>pending_crtcs_event.lock);
-   DBG("end: %08x", crtc_mask);
-   priv->pending_crtcs &= ~crtc_mask;
-   wake_up_all_locked(>pending_crtcs_event);
-   spin_unlock(>pending_crtcs_event.lock);
-}
-
-static struct msm_commit *commit_init(struct drm_atomic_state *state)
-{
-   struct msm_commit *c = kzalloc(sizeof(*c), GFP_KERNEL);
-
-   if (!c)
-   return NULL;
-
-   c->dev = state->dev;
-   c->state = state;
-
-   INIT_WORK(>work, commit_worker);
-
-   return c;
-}
-
-static void commit_destroy(struct msm_commit *c)
-{
-   end_atomic(c->dev->dev_private, c->crtc_mask);
-   kfree(c);
-}
-
 static void msm_atomic_wait_for_commit_done(struct drm_device *dev,
struct drm_atomic_state *old_state)
 {
@@ -148,31 +88,37 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
msm_atomic_wait_for_commit_done(dev, state);
 
-   drm_atomic_helper_cleanup_planes(dev, state);
-
kms->funcs->complete_commit(kms, state);
+
+   drm_atomic_helper_wait_for_vblanks(dev, state);
+
+   drm_atomic_helper_commit_hw_done(state);
+
+   drm_atomic_helper_cleanup_planes(dev, state);
 }
 
 /* The (potentially) asynchronous part of the commit.  At this point
  * nothing can fail short of armageddon.
  */
-static void complete_commit(struct msm_commit *c)
+static void commit_tail(struct drm_atomic_state *state)
 {
-   struct drm_atomic_state *state = c->state;
-   struct drm_device *dev = state->dev;
+   drm_atomic_helper_wait_for_fences(state->dev, state, false);
 
-   drm_atomic_helper_wait_for_fences(dev, state, false);
+   drm_atomic_helper_wait_for_dependencies(state);
 
msm_atomic_commit_tail(state);
 
-   drm_atomic_state_put(state);
+   drm_atomic_helper_commit_cleanup_done(state);
 
-   commit_destroy(c);
+   drm_atomic_state_put(state);
 }
 
-static void commit_worker(struct work_struct *work)
+static void commit_work(struct work_struct *work)
 {
-   complete_commit(container_of(work, struct msm_commit, work));
+   struct drm_atomic_state *state = container_of(work,
+ struct drm_atomic_state,
+ commit_work);
+   commit_tail(state);
 }
 
 /**
@@ -191,17 +137,12 @@ int msm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state, bool nonblock)
 {
struct msm_drm_private *priv = dev->dev_private;
-   struct msm_commit *c;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
int i, ret;
 
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
/*
 * Note that plane->atomic_async_check() should fail if we need
 * to

[Freedreno] [PATCH v4 7/9] drm/msm: Issue queued events when disabling crtc

[Sean Paul]

Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).

Changes in v2:
- None
Changes in v3:
- Rebased on Archit's private_obj set
Changes in v4:
- None

Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 76b96081916f..10271359789e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -430,6 +430,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct device *dev = _kms->pdev->dev;
+   unsigned long flags;
 
DBG("%s", crtc->name);
 
@@ -445,6 +446,14 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
mdp_irq_unregister(_kms->base, _crtc->err);
pm_runtime_put_sync(dev);
 
+   if (crtc->state->event && !crtc->state->active) {
+   WARN_ON(mdp5_crtc->event);
+   spin_lock_irqsave(_kms->dev->event_lock, flags);
+   drm_crtc_send_vblank_event(crtc, crtc->state->event);
+   crtc->state->event = NULL;
+   spin_unlock_irqrestore(_kms->dev->event_lock, flags);
+   }
+
mdp5_crtc->enabled = false;
 }
 
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[Freedreno] [PATCH v4 1/9] drm/msm/mdp5: Add global state as a private atomic object

[Sean Paul]

From: Archit Taneja <arch...@codeaurora.org>

Global shared resources (hwpipes, hwmixers and SMP) for MDP5 are
implemented as a part of atomic state by subclassing drm_atomic_state.

The preferred approach is to use the drm_private_obj infrastructure
available in the atomic core.

mdp5_global_state is introduced as a drm atomic private object. The two
funcs mdp5_get_global_state() and mdp5_get_existing_global_state() are
the two variants that will be used to access mdp5_global_state.

This will replace the existing mdp5_state struct (which subclasses
drm_atomic_state) and the funcs around it. These will be removed later
once we mdp5_global_state is put to use everywhere.

Changes in v3:
- Added glob_state_lock instead of pushing it into the core
- Added to the msm atomic helper patch set
Changes in v4:
- None

Signed-off-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 87 
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 25 +++
 2 files changed, 112 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 6d8e3a9a6fc0..fcbdef385a8a 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -106,6 +106,86 @@ static void mdp5_swap_state(struct msm_kms *kms, struct 
drm_atomic_state *state)
swap(to_kms_state(state)->state, mdp5_kms->state);
 }
 
+/* Global/shared object state funcs */
+
+/*
+ * This is a helper that returns the private state currently in operation.
+ * Note that this would return the "old_state" if called in the atomic check
+ * path, and the "new_state" after the atomic swap has been done.
+ */
+struct mdp5_global_state *
+mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms)
+{
+   return to_mdp5_global_state(mdp5_kms->glob_state.state);
+}
+
+/*
+ * This acquires the modeset lock set aside for global state, creates
+ * a new duplicated private object state.
+ */
+struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s)
+{
+   struct msm_drm_private *priv = s->dev->dev_private;
+   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
+   struct drm_private_state *priv_state;
+   int ret;
+
+   ret = drm_modeset_lock(_kms->glob_state_lock, s->acquire_ctx);
+   if (ret)
+   return ERR_PTR(ret);
+
+   priv_state = drm_atomic_get_private_obj_state(s, _kms->glob_state);
+   if (IS_ERR(priv_state))
+   return ERR_CAST(priv_state);
+
+   return to_mdp5_global_state(priv_state);
+}
+
+static struct drm_private_state *
+mdp5_global_duplicate_state(struct drm_private_obj *obj)
+{
+   struct mdp5_global_state *state;
+
+   state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
+   if (!state)
+   return NULL;
+
+   __drm_atomic_helper_private_obj_duplicate_state(obj, >base);
+
+   return >base;
+}
+
+static void mdp5_global_destroy_state(struct drm_private_obj *obj,
+ struct drm_private_state *state)
+{
+   struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
+
+   kfree(mdp5_state);
+}
+
+static const struct drm_private_state_funcs mdp5_global_state_funcs = {
+   .atomic_duplicate_state = mdp5_global_duplicate_state,
+   .atomic_destroy_state = mdp5_global_destroy_state,
+};
+
+static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
+{
+   struct mdp5_global_state *state;
+
+   drm_modeset_lock_init(_kms->glob_state_lock);
+
+   state = kzalloc(sizeof(*state), GFP_KERNEL);
+   if (!state)
+   return -ENOMEM;
+
+   state->mdp5_kms = mdp5_kms;
+
+   drm_atomic_private_obj_init(_kms->glob_state,
+   >base,
+   _global_state_funcs);
+   return 0;
+}
+
 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state 
*state)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
@@ -727,6 +807,9 @@ static void mdp5_destroy(struct platform_device *pdev)
if (mdp5_kms->rpm_enabled)
pm_runtime_disable(>dev);
 
+   drm_atomic_private_obj_fini(_kms->glob_state);
+   drm_modeset_lock_fini(_kms->glob_state_lock);
+
kfree(mdp5_kms->state);
 }
 
@@ -887,6 +970,10 @@ static int mdp5_init(struct platform_device *pdev, struct 
drm_device *dev)
goto fail;
}
 
+   ret = mdp5_global_obj_init(mdp5_kms);
+   if (ret)
+   goto fail;
+
mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
if (IS_ERR(mdp5_kms->mmio)) {
ret = PTR_ERR(mdp5_kms->mmio);
diff --git a/drivers/gpu/dr

[Freedreno] [PATCH v4 9/9] drm/msm: Switch to atomic_helper_commit()

[Sean Paul]

Now that all of the msm-specific goo is tucked safely away we can switch
over to using the atomic helper commit directly. \o/

Changes in v2:
- None
Changes in v3:
- Rebased on Archit's private_obj set
Changes in v4:
- None

Cc: Abhinav Kumar <abhin...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 139 +--
 drivers/gpu/drm/msm/msm_drv.c|   7 +-
 drivers/gpu/drm/msm/msm_drv.h|   3 +-
 3 files changed, 8 insertions(+), 141 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 95c7868445dd..f0635c3da7f4 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -18,8 +18,6 @@
 #include "msm_drv.h"
 #include "msm_gem.h"
 #include "msm_kms.h"
-#include "msm_gem.h"
-#include "msm_fence.h"
 
 static void msm_atomic_wait_for_commit_done(struct drm_device *dev,
struct drm_atomic_state *old_state)
@@ -59,7 +57,7 @@ int msm_atomic_prepare_fb(struct drm_plane *plane,
return msm_framebuffer_prepare(new_state->fb, kms->aspace);
 }
 
-static void msm_atomic_commit_tail(struct drm_atomic_state *state)
+void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
struct drm_device *dev = state->dev;
struct msm_drm_private *priv = dev->dev_private;
@@ -73,19 +71,6 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
drm_atomic_helper_commit_modeset_enables(dev, state);
 
-   /* NOTE: _wait_for_vblanks() only waits for vblank on
-* enabled CRTCs.  So we end up faulting when disabling
-* due to (potentially) unref'ing the outgoing fb's
-* before the vblank when the disable has latched.
-*
-* But if it did wait on disabled (or newly disabled)
-* CRTCs, that would be racy (ie. we could have missed
-* the irq.  We need some way to poll for pipe shut
-* down.  Or just live with occasionally hitting the
-* timeout in the CRTC disable path (which really should
-* not be critical path)
-*/
-
msm_atomic_wait_for_commit_done(dev, state);
 
kms->funcs->complete_commit(kms, state);
@@ -96,125 +81,3 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
drm_atomic_helper_cleanup_planes(dev, state);
 }
-
-/* The (potentially) asynchronous part of the commit.  At this point
- * nothing can fail short of armageddon.
- */
-static void commit_tail(struct drm_atomic_state *state)
-{
-   drm_atomic_helper_wait_for_fences(state->dev, state, false);
-
-   drm_atomic_helper_wait_for_dependencies(state);
-
-   msm_atomic_commit_tail(state);
-
-   drm_atomic_helper_commit_cleanup_done(state);
-
-   drm_atomic_state_put(state);
-}
-
-static void commit_work(struct work_struct *work)
-{
-   struct drm_atomic_state *state = container_of(work,
- struct drm_atomic_state,
- commit_work);
-   commit_tail(state);
-}
-
-/**
- * drm_atomic_helper_commit - commit validated state object
- * @dev: DRM device
- * @state: the driver state object
- * @nonblock: nonblocking commit
- *
- * This function commits a with drm_atomic_helper_check() pre-validated state
- * object. This can still fail when e.g. the framebuffer reservation fails.
- *
- * RETURNS
- * Zero for success or -errno.
- */
-int msm_atomic_commit(struct drm_device *dev,
-   struct drm_atomic_state *state, bool nonblock)
-{
-   struct msm_drm_private *priv = dev->dev_private;
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *crtc_state;
-   struct drm_plane *plane;
-   struct drm_plane_state *old_plane_state, *new_plane_state;
-   int i, ret;
-
-   /*
-* Note that plane->atomic_async_check() should fail if we need
-* to re-assign hwpipe or anything that touches global atomic
-* state, so we'll never go down the async update path in those
-* cases.
-*/
-   if (state->async_update) {
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
-   drm_atomic_helper_async_commit(dev, state);
-   drm_atomic_helper_cleanup_planes(dev, state);
-   return 0;
-   }
-
-   ret = drm_atomic_helper_setup_commit(state, nonblock);
-   if (ret)
-   return ret;
-
-   INIT_WORK(>commit_work, commit_work);
-
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
-   if (!nonblock) {
-   ret = drm_atomic_helper_wait_for_fences(dev, state, true);
-   if (ret)
-   goto error;
-   }
-
-   /*
-* T

[Freedreno] [PATCH v4 2/9] drm/msm/mdp5: Use the new private_obj state

[Sean Paul]

From: Archit Taneja <arch...@codeaurora.org>

This replaces the usage of the subclassed atomic state (mdp5_state)
with a private_obj state embedded within drm_atomic_state. The latter
method is the preferred approach, since it's simpler to implement
and less prone to errors.

The new API replaces the older and equivalent mdp5_state usage in the
following pattern:
- References to "mdp5_kms->state" (i.e, the old/existing state) is
  replaced with mdp5_get_existing_global_state(). In the atomic_check
  path, this should be called with the glob_state_lock drm_modeset_lock
  alredy taken.
- References to "mdp5_get_state()" are replaced with
  mdp5_get_global_state(). This acquires glob_state_lock and uses
  drm_atomic_get_private_obj_state() to create a new duplicated state.

Changes in v3:
- Acquire glob_state_lock in mdp5_smp.c
- Added to the msm atomic helper patch set
Changes in v4:
- None

Signed-off-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c   | 10 --
 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c | 12 ++--
 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c  | 20 +++-
 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c   | 17 -
 4 files changed, 37 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index fcbdef385a8a..6ada098dba0b 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -190,20 +190,26 @@ static void mdp5_prepare_commit(struct msm_kms *kms, 
struct drm_atomic_state *st
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
struct device *dev = _kms->pdev->dev;
+   struct mdp5_global_state *global_state;
+
+   global_state = mdp5_get_existing_global_state(mdp5_kms);
 
pm_runtime_get_sync(dev);
 
if (mdp5_kms->smp)
-   mdp5_smp_prepare_commit(mdp5_kms->smp, _kms->state->smp);
+   mdp5_smp_prepare_commit(mdp5_kms->smp, _state->smp);
 }
 
 static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state 
*state)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
struct device *dev = _kms->pdev->dev;
+   struct mdp5_global_state *global_state;
+
+   global_state = mdp5_get_existing_global_state(mdp5_kms);
 
if (mdp5_kms->smp)
-   mdp5_smp_complete_commit(mdp5_kms->smp, _kms->state->smp);
+   mdp5_smp_complete_commit(mdp5_kms->smp, _state->smp);
 
pm_runtime_put_sync(dev);
 }
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c
index 8a00991f03c7..113e6b569562 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c
@@ -52,14 +52,14 @@ int mdp5_mixer_assign(struct drm_atomic_state *s, struct 
drm_crtc *crtc,
 {
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct mdp5_state *state = mdp5_get_state(s);
+   struct mdp5_global_state *global_state = mdp5_get_global_state(s);
struct mdp5_hw_mixer_state *new_state;
int i;
 
-   if (IS_ERR(state))
-   return PTR_ERR(state);
+   if (IS_ERR(global_state))
+   return PTR_ERR(global_state);
 
-   new_state = >hwmixer;
+   new_state = _state->hwmixer;
 
for (i = 0; i < mdp5_kms->num_hwmixers; i++) {
struct mdp5_hw_mixer *cur = mdp5_kms->hwmixers[i];
@@ -129,8 +129,8 @@ int mdp5_mixer_assign(struct drm_atomic_state *s, struct 
drm_crtc *crtc,
 
 void mdp5_mixer_release(struct drm_atomic_state *s, struct mdp5_hw_mixer 
*mixer)
 {
-   struct mdp5_state *state = mdp5_get_state(s);
-   struct mdp5_hw_mixer_state *new_state = >hwmixer;
+   struct mdp5_global_state *global_state = mdp5_get_global_state(s);
+   struct mdp5_hw_mixer_state *new_state = _state->hwmixer;
 
if (!mixer)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
index ff52c49095f9..1ef26bc63163 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
@@ -24,17 +24,19 @@ int mdp5_pipe_assign(struct drm_atomic_state *s, struct 
drm_plane *plane,
 {
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct mdp5_state *state;
+   struct mdp5_global_state *new_global_state, *old_global_state;
struct mdp5_hw_pipe_state *old_state, *new_state;
int i, j;
 
-   state = mdp5_get_state(s);
-   if (IS_ERR(s

[Freedreno] [PATCH v4 6/9] drm/msm: Mark the crtc->state->event consumed

[Sean Paul]

Don't leave the event != NULL once it's consumed, this is used a signal
to the atomic helpers that the event will be handled by the driver.

Changes in v2:
- None
Changes in v3:
- Rebased on Archit's private_obj set
Changes in v4:
- None

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 1 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 6e5e1aa54ce1..b001699297c4 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -351,6 +351,7 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp4_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
blend_setup(crtc);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 9893e43ba6c5..76b96081916f 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -708,6 +708,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp5_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
/*
-- 
Sean Paul, Software Engineer, Google / Chromium OS

___
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Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

[Freedreno] [DPU PATCH 3/3] drm/msm: Fix dpu build warnings

[Sean Paul]

A bunch of warning fixes, build is clean now.

Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 7 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c | 4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c  | 2 +-
 drivers/gpu/drm/msm/dpu_dbg.c | 2 +-
 7 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 36607e36672d..a57495f95663 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -32,9 +32,6 @@
 
 #define DPU_ERROR_CONN(c, fmt, ...) DPU_ERROR("conn%d " fmt,\
(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
-static u32 dither_matrix[DITHER_MATRIX_SZ] = {
-   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
-};
 
 static const struct drm_prop_enum_list e_topology_name[] = {
{DPU_RM_TOPOLOGY_NONE,  "dpu_none"},
@@ -226,6 +223,10 @@ void dpu_connector_unregister_event(struct drm_connector 
*connector,
 }
 
 #ifdef CONFIG_DRM_MSM_DSI_STAGING
+static u32 dither_matrix[DITHER_MATRIX_SZ] = {
+   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
+};
+
 static int _dpu_connector_get_default_dither_cfg_v1(
struct dpu_connector *c_conn, void *cfg)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 3308929bc9d6..b0c170373632 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2587,7 +2587,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct dpu_crtc_irq_info *node = NULL;
struct drm_event event;
u32 power_on;
-   int ret, i;
+   int ret;
 
if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
DPU_ERROR("invalid crtc\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
index bb4547748ce9..e0d46c545c14 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
@@ -374,7 +374,7 @@ static int validate_dma_cfg(struct 
dpu_reg_dma_setup_ops_cfg *cfg)
}
 
if (cfg->dma_buf->iova & GUARD_BYTES || !cfg->dma_buf->vaddr) {
-   DRM_ERROR("iova not aligned to %zx iova %x kva %pK",
+   DRM_ERROR("iova not aligned to %zx iova %llx kva %pK",
ADDR_ALIGN, cfg->dma_buf->iova,
cfg->dma_buf->vaddr);
return -EINVAL;
@@ -433,7 +433,7 @@ static int validate_kick_off_v1(struct 
dpu_reg_dma_kickoff_cfg *cfg)
(WRITE_TRIGGER);
 
if (cfg->dma_buf->iova & GUARD_BYTES) {
-   DRM_ERROR("Address is not aligned to %zx iova %x", ADDR_ALIGN,
+   DRM_ERROR("Address is not aligned to %zx iova %llx", ADDR_ALIGN,
cfg->dma_buf->iova);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 36657aa97bd7..aad5a94c726a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -426,7 +426,6 @@ static void dpu_kms_commit(struct msm_kms *kms, struct 
drm_atomic_state *state)
 {
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
-   struct dpu_crtc_state *cstate;
int i;
 
for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 33a894e3d580..7844d6463220 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -2742,7 +2742,6 @@ dpu_plane_duplicate_state(struct drm_plane *plane)
struct dpu_plane *pdpu;
struct dpu_plane_state *pstate;
struct dpu_plane_state *old_state;
-   struct drm_property *drm_prop;
 
if (!plane) {
DPU_ERROR("invalid plane\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
index 801155fe0989..074223383a98 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
@@ -321,7 +321,7 @@ void dpu_debugfs_vbif_destroy(struct dpu_kms *dpu_kms)
 
 int dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
 {
-   char vbif_name[32];
+   char vbif_name[64];
struct dentry *debugfs_vbif;
int i, 

[Freedreno] [PATCH v3 8/8] drm/msm: Switch to atomic_helper_commit()

[Sean Paul]

Now that all of the msm-specific goo is tucked safely away we can switch
over to using the atomic helper commit directly. \o/

Changes in v2:
- None
Changes in v3:
- Rebased on Archit's private_obj set

Cc: Abhinav Kumar <abhin...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 139 +--
 drivers/gpu/drm/msm/msm_drv.c|   7 +-
 drivers/gpu/drm/msm/msm_drv.h|   3 +-
 3 files changed, 8 insertions(+), 141 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index a31aa417b80d..2da5e2150d15 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -17,8 +17,6 @@
 
 #include "msm_drv.h"
 #include "msm_kms.h"
-#include "msm_gem.h"
-#include "msm_fence.h"
 
 static void msm_atomic_wait_for_commit_done(struct drm_device *dev,
struct drm_atomic_state *old_state)
@@ -37,7 +35,7 @@ static void msm_atomic_wait_for_commit_done(struct drm_device 
*dev,
}
 }
 
-static void msm_atomic_commit_tail(struct drm_atomic_state *state)
+void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
struct drm_device *dev = state->dev;
struct msm_drm_private *priv = dev->dev_private;
@@ -51,19 +49,6 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
drm_atomic_helper_commit_modeset_enables(dev, state);
 
-   /* NOTE: _wait_for_vblanks() only waits for vblank on
-* enabled CRTCs.  So we end up faulting when disabling
-* due to (potentially) unref'ing the outgoing fb's
-* before the vblank when the disable has latched.
-*
-* But if it did wait on disabled (or newly disabled)
-* CRTCs, that would be racy (ie. we could have missed
-* the irq.  We need some way to poll for pipe shut
-* down.  Or just live with occasionally hitting the
-* timeout in the CRTC disable path (which really should
-* not be critical path)
-*/
-
msm_atomic_wait_for_commit_done(dev, state);
 
kms->funcs->complete_commit(kms, state);
@@ -74,125 +59,3 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
drm_atomic_helper_cleanup_planes(dev, state);
 }
-
-/* The (potentially) asynchronous part of the commit.  At this point
- * nothing can fail short of armageddon.
- */
-static void commit_tail(struct drm_atomic_state *state)
-{
-   drm_atomic_helper_wait_for_fences(state->dev, state, false);
-
-   drm_atomic_helper_wait_for_dependencies(state);
-
-   msm_atomic_commit_tail(state);
-
-   drm_atomic_helper_commit_cleanup_done(state);
-
-   drm_atomic_state_put(state);
-}
-
-static void commit_work(struct work_struct *work)
-{
-   struct drm_atomic_state *state = container_of(work,
- struct drm_atomic_state,
- commit_work);
-   commit_tail(state);
-}
-
-/**
- * drm_atomic_helper_commit - commit validated state object
- * @dev: DRM device
- * @state: the driver state object
- * @nonblock: nonblocking commit
- *
- * This function commits a with drm_atomic_helper_check() pre-validated state
- * object. This can still fail when e.g. the framebuffer reservation fails.
- *
- * RETURNS
- * Zero for success or -errno.
- */
-int msm_atomic_commit(struct drm_device *dev,
-   struct drm_atomic_state *state, bool nonblock)
-{
-   struct msm_drm_private *priv = dev->dev_private;
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *crtc_state;
-   struct drm_plane *plane;
-   struct drm_plane_state *old_plane_state, *new_plane_state;
-   int i, ret;
-
-   /*
-* Note that plane->atomic_async_check() should fail if we need
-* to re-assign hwpipe or anything that touches global atomic
-* state, so we'll never go down the async update path in those
-* cases.
-*/
-   if (state->async_update) {
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
-   drm_atomic_helper_async_commit(dev, state);
-   drm_atomic_helper_cleanup_planes(dev, state);
-   return 0;
-   }
-
-   ret = drm_atomic_helper_setup_commit(state, nonblock);
-   if (ret)
-   return ret;
-
-   INIT_WORK(>commit_work, commit_work);
-
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
-   if (!nonblock) {
-   ret = drm_atomic_helper_wait_for_fences(dev, state, true);
-   if (ret)
-   goto error;
-   }
-
-   /*
-* This is the point of no return - everything below never fails except
-* when the hw goes bonghi

[Freedreno] [PATCH v3 7/8] drm/msm: Remove msm_commit/worker, use atomic helper commit

[Sean Paul]

Moving further towards switching fully to the the atomic helpers, this
patch removes the hand-rolled worker nonblock commit code and uses the
atomic helpers commit_work model.

Changes in v2:
- Remove commit_destroy()
- Shuffle order of commit_tail calls to further serialize commits
- Use stall in swap_state to avoid abandoned events on disable
Changes in v3:
- Rebased on Archit's private_obj set

Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 153 +--
 drivers/gpu/drm/msm/msm_drv.c|   1 -
 drivers/gpu/drm/msm/msm_drv.h|   4 -
 3 files changed, 42 insertions(+), 116 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index c18f0bee20d4..a31aa417b80d 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -20,66 +20,6 @@
 #include "msm_gem.h"
 #include "msm_fence.h"
 
-struct msm_commit {
-   struct drm_device *dev;
-   struct drm_atomic_state *state;
-   struct work_struct work;
-   uint32_t crtc_mask;
-};
-
-static void commit_worker(struct work_struct *work);
-
-/* block until specified crtcs are no longer pending update, and
- * atomically mark them as pending update
- */
-static int start_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
-{
-   int ret;
-
-   spin_lock(>pending_crtcs_event.lock);
-   ret = wait_event_interruptible_locked(priv->pending_crtcs_event,
-   !(priv->pending_crtcs & crtc_mask));
-   if (ret == 0) {
-   DBG("start: %08x", crtc_mask);
-   priv->pending_crtcs |= crtc_mask;
-   }
-   spin_unlock(>pending_crtcs_event.lock);
-
-   return ret;
-}
-
-/* clear specified crtcs (no longer pending update)
- */
-static void end_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
-{
-   spin_lock(>pending_crtcs_event.lock);
-   DBG("end: %08x", crtc_mask);
-   priv->pending_crtcs &= ~crtc_mask;
-   wake_up_all_locked(>pending_crtcs_event);
-   spin_unlock(>pending_crtcs_event.lock);
-}
-
-static struct msm_commit *commit_init(struct drm_atomic_state *state)
-{
-   struct msm_commit *c = kzalloc(sizeof(*c), GFP_KERNEL);
-
-   if (!c)
-   return NULL;
-
-   c->dev = state->dev;
-   c->state = state;
-
-   INIT_WORK(>work, commit_worker);
-
-   return c;
-}
-
-static void commit_destroy(struct msm_commit *c)
-{
-   end_atomic(c->dev->dev_private, c->crtc_mask);
-   kfree(c);
-}
-
 static void msm_atomic_wait_for_commit_done(struct drm_device *dev,
struct drm_atomic_state *old_state)
 {
@@ -126,31 +66,37 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
msm_atomic_wait_for_commit_done(dev, state);
 
-   drm_atomic_helper_cleanup_planes(dev, state);
-
kms->funcs->complete_commit(kms, state);
+
+   drm_atomic_helper_wait_for_vblanks(dev, state);
+
+   drm_atomic_helper_commit_hw_done(state);
+
+   drm_atomic_helper_cleanup_planes(dev, state);
 }
 
 /* The (potentially) asynchronous part of the commit.  At this point
  * nothing can fail short of armageddon.
  */
-static void complete_commit(struct msm_commit *c)
+static void commit_tail(struct drm_atomic_state *state)
 {
-   struct drm_atomic_state *state = c->state;
-   struct drm_device *dev = state->dev;
+   drm_atomic_helper_wait_for_fences(state->dev, state, false);
 
-   drm_atomic_helper_wait_for_fences(dev, state, false);
+   drm_atomic_helper_wait_for_dependencies(state);
 
msm_atomic_commit_tail(state);
 
-   drm_atomic_state_put(state);
+   drm_atomic_helper_commit_cleanup_done(state);
 
-   commit_destroy(c);
+   drm_atomic_state_put(state);
 }
 
-static void commit_worker(struct work_struct *work)
+static void commit_work(struct work_struct *work)
 {
-   complete_commit(container_of(work, struct msm_commit, work));
+   struct drm_atomic_state *state = container_of(work,
+ struct drm_atomic_state,
+ commit_work);
+   commit_tail(state);
 }
 
 /**
@@ -169,17 +115,12 @@ int msm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state, bool nonblock)
 {
struct msm_drm_private *priv = dev->dev_private;
-   struct msm_commit *c;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
int i, ret;
 
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
/*
 * Note that plane->atomic_async_check() should fail if we need
 * to re-assign hwpipe 

[Freedreno] [PATCH v3 5/8] drm/msm: Mark the crtc->state->event consumed

[Sean Paul]

Don't leave the event != NULL once it's consumed, this is used a signal
to the atomic helpers that the event will be handled by the driver.

Changes in v2:
- None
Changes in v3:
- Rebased on Archit's private_obj set

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 1 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 6e5e1aa54ce1..b001699297c4 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -351,6 +351,7 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp4_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
blend_setup(crtc);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 9893e43ba6c5..76b96081916f 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -708,6 +708,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp5_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
/*
-- 
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[Freedreno] [PATCH v3 6/8] drm/msm: Issue queued events when disabling crtc

[Sean Paul]

Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).

Changes in v2:
- None
Changes in v3:
- Rebased on Archit's private_obj set

Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 76b96081916f..10271359789e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -430,6 +430,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct device *dev = _kms->pdev->dev;
+   unsigned long flags;
 
DBG("%s", crtc->name);
 
@@ -445,6 +446,14 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
mdp_irq_unregister(_kms->base, _crtc->err);
pm_runtime_put_sync(dev);
 
+   if (crtc->state->event && !crtc->state->active) {
+   WARN_ON(mdp5_crtc->event);
+   spin_lock_irqsave(_kms->dev->event_lock, flags);
+   drm_crtc_send_vblank_event(crtc, crtc->state->event);
+   crtc->state->event = NULL;
+   spin_unlock_irqrestore(_kms->dev->event_lock, flags);
+   }
+
mdp5_crtc->enabled = false;
 }
 
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[Freedreno] [PATCH v3 2/8] drm/msm/mdp5: Use the new private_obj state

[Sean Paul]

From: Archit Taneja <arch...@codeaurora.org>

This replaces the usage of the subclassed atomic state (mdp5_state)
with a private_obj state embedded within drm_atomic_state. The latter
method is the preferred approach, since it's simpler to implement
and less prone to errors.

The new API replaces the older and equivalent mdp5_state usage in the
following pattern:
- References to "mdp5_kms->state" (i.e, the old/existing state) is
  replaced with mdp5_get_existing_global_state(). In the atomic_check
  path, this should be called with the glob_state_lock drm_modeset_lock
  alredy taken.
- References to "mdp5_get_state()" are replaced with
  mdp5_get_global_state(). This acquires glob_state_lock and uses
  drm_atomic_get_private_obj_state() to create a new duplicated state.

Changes in v3:
- Acquire glob_state_lock in mdp5_smp.c
- Added to the msm atomic helper patch set

Signed-off-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Rob Clark <robdcl...@gmail.com>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c   | 10 --
 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c | 12 ++--
 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c  | 20 +++-
 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c   | 17 -
 4 files changed, 37 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index fcbdef385a8a..6ada098dba0b 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -190,20 +190,26 @@ static void mdp5_prepare_commit(struct msm_kms *kms, 
struct drm_atomic_state *st
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
struct device *dev = _kms->pdev->dev;
+   struct mdp5_global_state *global_state;
+
+   global_state = mdp5_get_existing_global_state(mdp5_kms);
 
pm_runtime_get_sync(dev);
 
if (mdp5_kms->smp)
-   mdp5_smp_prepare_commit(mdp5_kms->smp, _kms->state->smp);
+   mdp5_smp_prepare_commit(mdp5_kms->smp, _state->smp);
 }
 
 static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state 
*state)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
struct device *dev = _kms->pdev->dev;
+   struct mdp5_global_state *global_state;
+
+   global_state = mdp5_get_existing_global_state(mdp5_kms);
 
if (mdp5_kms->smp)
-   mdp5_smp_complete_commit(mdp5_kms->smp, _kms->state->smp);
+   mdp5_smp_complete_commit(mdp5_kms->smp, _state->smp);
 
pm_runtime_put_sync(dev);
 }
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c
index 8a00991f03c7..113e6b569562 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c
@@ -52,14 +52,14 @@ int mdp5_mixer_assign(struct drm_atomic_state *s, struct 
drm_crtc *crtc,
 {
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct mdp5_state *state = mdp5_get_state(s);
+   struct mdp5_global_state *global_state = mdp5_get_global_state(s);
struct mdp5_hw_mixer_state *new_state;
int i;
 
-   if (IS_ERR(state))
-   return PTR_ERR(state);
+   if (IS_ERR(global_state))
+   return PTR_ERR(global_state);
 
-   new_state = >hwmixer;
+   new_state = _state->hwmixer;
 
for (i = 0; i < mdp5_kms->num_hwmixers; i++) {
struct mdp5_hw_mixer *cur = mdp5_kms->hwmixers[i];
@@ -129,8 +129,8 @@ int mdp5_mixer_assign(struct drm_atomic_state *s, struct 
drm_crtc *crtc,
 
 void mdp5_mixer_release(struct drm_atomic_state *s, struct mdp5_hw_mixer 
*mixer)
 {
-   struct mdp5_state *state = mdp5_get_state(s);
-   struct mdp5_hw_mixer_state *new_state = >hwmixer;
+   struct mdp5_global_state *global_state = mdp5_get_global_state(s);
+   struct mdp5_hw_mixer_state *new_state = _state->hwmixer;
 
if (!mixer)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
index ff52c49095f9..1ef26bc63163 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c
@@ -24,17 +24,19 @@ int mdp5_pipe_assign(struct drm_atomic_state *s, struct 
drm_plane *plane,
 {
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct mdp5_state *state;
+   struct mdp5_global_state *new_global_state, *old_global_state;
struct mdp5_hw_pipe_state *old_state, *new_state;
int i, j;
 
-   state = mdp5_get_state(s);
-   if (IS_ERR(s

[Freedreno] [PATCH v2 4/6] drm/msm: Issue queued events when disabling crtc

[Sean Paul]

Ensure that any queued events are issued when disabling the crtc. This
avoids timeouts when we come back and wait for dependencies (like the
previous frame's flip_done).

Changes in v2:
- None

Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 76b96081916f..10271359789e 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -430,6 +430,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct device *dev = _kms->pdev->dev;
+   unsigned long flags;
 
DBG("%s", crtc->name);
 
@@ -445,6 +446,14 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,
mdp_irq_unregister(_kms->base, _crtc->err);
pm_runtime_put_sync(dev);
 
+   if (crtc->state->event && !crtc->state->active) {
+   WARN_ON(mdp5_crtc->event);
+   spin_lock_irqsave(_kms->dev->event_lock, flags);
+   drm_crtc_send_vblank_event(crtc, crtc->state->event);
+   crtc->state->event = NULL;
+   spin_unlock_irqrestore(_kms->dev->event_lock, flags);
+   }
+
mdp5_crtc->enabled = false;
 }
 
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[Freedreno] [PATCH v2 3/6] drm/msm: Mark the crtc->state->event consumed

[Sean Paul]

Don't leave the event != NULL once it's consumed, this is used a signal
to the atomic helpers that the event will be handled by the driver.

Changes in v2:
- None

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 1 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 6e5e1aa54ce1..b001699297c4 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -351,6 +351,7 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp4_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
blend_setup(crtc);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 9893e43ba6c5..76b96081916f 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -708,6 +708,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp5_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
/*
-- 
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[Freedreno] [PATCH v2 2/6] drm/msm: Refactor complete_commit() to look more the helpers

[Sean Paul]

Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.

Changes in v2:
- None

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 25 -
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index e792158676aa..671a18ee977d 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -97,18 +97,12 @@ static void msm_atomic_wait_for_commit_done(struct 
drm_device *dev,
}
 }
 
-/* The (potentially) asynchronous part of the commit.  At this point
- * nothing can fail short of armageddon.
- */
-static void complete_commit(struct msm_commit *c, bool async)
+static void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
-   struct drm_atomic_state *state = c->state;
struct drm_device *dev = state->dev;
struct msm_drm_private *priv = dev->dev_private;
struct msm_kms *kms = priv->kms;
 
-   drm_atomic_helper_wait_for_fences(dev, state, false);
-
kms->funcs->prepare_commit(kms, state);
 
drm_atomic_helper_commit_modeset_disables(dev, state);
@@ -135,6 +129,19 @@ static void complete_commit(struct msm_commit *c, bool 
async)
drm_atomic_helper_cleanup_planes(dev, state);
 
kms->funcs->complete_commit(kms, state);
+}
+
+/* The (potentially) asynchronous part of the commit.  At this point
+ * nothing can fail short of armageddon.
+ */
+static void complete_commit(struct msm_commit *c)
+{
+   struct drm_atomic_state *state = c->state;
+   struct drm_device *dev = state->dev;
+
+   drm_atomic_helper_wait_for_fences(dev, state, false);
+
+   msm_atomic_commit_tail(state);
 
drm_atomic_state_put(state);
 
@@ -143,7 +150,7 @@ static void complete_commit(struct msm_commit *c, bool 
async)
 
 static void commit_worker(struct work_struct *work)
 {
-   complete_commit(container_of(work, struct msm_commit, work), true);
+   complete_commit(container_of(work, struct msm_commit, work));
 }
 
 /**
@@ -242,7 +249,7 @@ int msm_atomic_commit(struct drm_device *dev,
return 0;
}
 
-   complete_commit(c, false);
+   complete_commit(c);
 
return 0;
 
-- 
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[Freedreno] [PATCH 2/4] drm/msm: Mark the crtc->state->event consumed

[Sean Paul]

Don't leave the event != NULL once it's consumed, this is used a signal
to the atomic helpers that the event will be handled by the driver.

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 1 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 6e5e1aa54ce1..b001699297c4 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -351,6 +351,7 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp4_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
blend_setup(crtc);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 9893e43ba6c5..76b96081916f 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -708,6 +708,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
 
spin_lock_irqsave(>event_lock, flags);
mdp5_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
 
/*
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[Freedreno] [PATCH 0/4] drm/msm: Switch to atomic helpers

[Sean Paul]

I originally sent these patches targetted against the msm dpu code, but
I've rebased them on msm-next since they're _mostly_ the same. The set
is based on 'drm/msm: Use drm_private_obj/state instead of subclassing'
which I sent up earlier.

The set has been tested on mdp5 db410c.

Sean

Sean Paul (4):
  drm/msm: Refactor complete_commit() to look more the helpers
  drm/msm: Mark the crtc->state->event consumed
  drm/msm: Remove msm_commit/worker, use atomic helper commit
  drm/msm: Switch to atomic_helper_commit()

 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c |   1 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c |   1 +
 drivers/gpu/drm/msm/msm_atomic.c  | 190 +-
 drivers/gpu/drm/msm/msm_drv.c |   8 +-
 drivers/gpu/drm/msm/msm_drv.h |   7 +-
 5 files changed, 14 insertions(+), 193 deletions(-)

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[Freedreno] [PATCH 3/4] drm/msm: Remove msm_commit/worker, use atomic helper commit

[Sean Paul]

Moving further towards switching fully to the the atomic helpers, this
patch removes the hand-rolled worker nonblock commit code and uses the
atomic helpers commit_work model.

Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 145 +--
 drivers/gpu/drm/msm/msm_drv.c|   1 -
 drivers/gpu/drm/msm/msm_drv.h|   4 -
 3 files changed, 39 insertions(+), 111 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 9c6fa52a40b7..af828df6e060 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -20,66 +20,6 @@
 #include "msm_gem.h"
 #include "msm_fence.h"
 
-struct msm_commit {
-   struct drm_device *dev;
-   struct drm_atomic_state *state;
-   struct work_struct work;
-   uint32_t crtc_mask;
-};
-
-static void commit_worker(struct work_struct *work);
-
-/* block until specified crtcs are no longer pending update, and
- * atomically mark them as pending update
- */
-static int start_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
-{
-   int ret;
-
-   spin_lock(>pending_crtcs_event.lock);
-   ret = wait_event_interruptible_locked(priv->pending_crtcs_event,
-   !(priv->pending_crtcs & crtc_mask));
-   if (ret == 0) {
-   DBG("start: %08x", crtc_mask);
-   priv->pending_crtcs |= crtc_mask;
-   }
-   spin_unlock(>pending_crtcs_event.lock);
-
-   return ret;
-}
-
-/* clear specified crtcs (no longer pending update)
- */
-static void end_atomic(struct msm_drm_private *priv, uint32_t crtc_mask)
-{
-   spin_lock(>pending_crtcs_event.lock);
-   DBG("end: %08x", crtc_mask);
-   priv->pending_crtcs &= ~crtc_mask;
-   wake_up_all_locked(>pending_crtcs_event);
-   spin_unlock(>pending_crtcs_event.lock);
-}
-
-static struct msm_commit *commit_init(struct drm_atomic_state *state)
-{
-   struct msm_commit *c = kzalloc(sizeof(*c), GFP_KERNEL);
-
-   if (!c)
-   return NULL;
-
-   c->dev = state->dev;
-   c->state = state;
-
-   INIT_WORK(>work, commit_worker);
-
-   return c;
-}
-
-static void commit_destroy(struct msm_commit *c)
-{
-   end_atomic(c->dev->dev_private, c->crtc_mask);
-   kfree(c);
-}
-
 static void msm_atomic_wait_for_commit_done(struct drm_device *dev,
struct drm_atomic_state *old_state)
 {
@@ -126,6 +66,10 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
msm_atomic_wait_for_commit_done(dev, state);
 
+   drm_atomic_helper_commit_hw_done(state);
+
+   drm_atomic_helper_wait_for_vblanks(dev, state);
+
drm_atomic_helper_cleanup_planes(dev, state);
 
kms->funcs->complete_commit(kms, state);
@@ -134,21 +78,25 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 /* The (potentially) asynchronous part of the commit.  At this point
  * nothing can fail short of armageddon.
  */
-static void complete_commit(struct msm_commit *c)
+static void commit_tail(struct drm_atomic_state *state)
 {
-   struct drm_atomic_state *state = c->state;
-   struct drm_device *dev = state->dev;
+   drm_atomic_helper_wait_for_fences(state->dev, state, false);
 
-   drm_atomic_helper_wait_for_fences(dev, state, false);
+   drm_atomic_helper_wait_for_dependencies(state);
 
msm_atomic_commit_tail(state);
 
+   drm_atomic_helper_commit_cleanup_done(state);
+
drm_atomic_state_put(state);
 }
 
-static void commit_worker(struct work_struct *work)
+static void commit_work(struct work_struct *work)
 {
-   complete_commit(container_of(work, struct msm_commit, work), true);
+   struct drm_atomic_state *state = container_of(work,
+ struct drm_atomic_state,
+ commit_work);
+   commit_tail(state);
 }
 
 /**
@@ -167,17 +115,12 @@ int msm_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state, bool nonblock)
 {
struct msm_drm_private *priv = dev->dev_private;
-   struct msm_commit *c;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
int i, ret;
 
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
/*
 * Note that plane->atomic_async_check() should fail if we need
 * to re-assign hwpipe or anything that touches global atomic
@@ -185,44 +128,38 @@ int msm_atomic_commit(struct drm_device *dev,
 * cases.
 */
if (state->async_update) {
+   ret = drm_atomic_helper_prepare_planes(dev, st

[Freedreno] [PATCH 4/4] drm/msm: Switch to atomic_helper_commit()

[Sean Paul]

Now that all of the msm-specific goo is tucked safely away we can switch
over to using the atomic helper commit directly. \o/

Cc: Abhinav Kumar <abhin...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 120 +--
 drivers/gpu/drm/msm/msm_drv.c|   7 +-
 drivers/gpu/drm/msm/msm_drv.h|   3 +-
 3 files changed, 8 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index af828df6e060..0a63ce8f33a3 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -17,8 +17,6 @@
 
 #include "msm_drv.h"
 #include "msm_kms.h"
-#include "msm_gem.h"
-#include "msm_fence.h"
 
 static void msm_atomic_wait_for_commit_done(struct drm_device *dev,
struct drm_atomic_state *old_state)
@@ -37,7 +35,7 @@ static void msm_atomic_wait_for_commit_done(struct drm_device 
*dev,
}
 }
 
-static void msm_atomic_commit_tail(struct drm_atomic_state *state)
+void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
struct drm_device *dev = state->dev;
struct msm_drm_private *priv = dev->dev_private;
@@ -74,119 +72,3 @@ static void msm_atomic_commit_tail(struct drm_atomic_state 
*state)
 
kms->funcs->complete_commit(kms, state);
 }
-
-/* The (potentially) asynchronous part of the commit.  At this point
- * nothing can fail short of armageddon.
- */
-static void commit_tail(struct drm_atomic_state *state)
-{
-   drm_atomic_helper_wait_for_fences(state->dev, state, false);
-
-   drm_atomic_helper_wait_for_dependencies(state);
-
-   msm_atomic_commit_tail(state);
-
-   drm_atomic_helper_commit_cleanup_done(state);
-
-   drm_atomic_state_put(state);
-}
-
-static void commit_work(struct work_struct *work)
-{
-   struct drm_atomic_state *state = container_of(work,
- struct drm_atomic_state,
- commit_work);
-   commit_tail(state);
-}
-
-/**
- * drm_atomic_helper_commit - commit validated state object
- * @dev: DRM device
- * @state: the driver state object
- * @nonblock: nonblocking commit
- *
- * This function commits a with drm_atomic_helper_check() pre-validated state
- * object. This can still fail when e.g. the framebuffer reservation fails.
- *
- * RETURNS
- * Zero for success or -errno.
- */
-int msm_atomic_commit(struct drm_device *dev,
-   struct drm_atomic_state *state, bool nonblock)
-{
-   struct msm_drm_private *priv = dev->dev_private;
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *crtc_state;
-   struct drm_plane *plane;
-   struct drm_plane_state *old_plane_state, *new_plane_state;
-   int i, ret;
-
-   /*
-* Note that plane->atomic_async_check() should fail if we need
-* to re-assign hwpipe or anything that touches global atomic
-* state, so we'll never go down the async update path in those
-* cases.
-*/
-   if (state->async_update) {
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
-   drm_atomic_helper_async_commit(dev, state);
-   drm_atomic_helper_cleanup_planes(dev, state);
-   return 0;
-   }
-
-   ret = drm_atomic_helper_setup_commit(state, nonblock);
-   if (ret)
-   return ret;
-
-   INIT_WORK(>commit_work, commit_work);
-
-   ret = drm_atomic_helper_prepare_planes(dev, state);
-   if (ret)
-   return ret;
-
-   if (!nonblock) {
-   ret = drm_atomic_helper_wait_for_fences(dev, state, true);
-   if (ret)
-   goto error;
-   }
-
-   /*
-* This is the point of no return - everything below never fails except
-* when the hw goes bonghits. Which means we can commit the new state on
-* the software side now.
-*
-* swap driver private state while still holding state_lock
-*/
-   BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
-
-   /*
-* Everything below can be run asynchronously without the need to grab
-* any modeset locks at all under one conditions: It must be guaranteed
-* that the asynchronous work has either been cancelled (if the driver
-* supports it, which at least requires that the framebuffers get
-* cleaned up with drm_atomic_helper_cleanup_planes()) or completed
-* before the new state gets committed on the software side with
-* drm_atomic_helper_swap_state().
-*
-* This scheme allows new atomic state updates to be prepared and
-* checked in parallel to the asynchronous completion of the previous
-* update. Which is imp

[Freedreno] [PATCH 1/4] drm/msm: Refactor complete_commit() to look more the helpers

[Sean Paul]

Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/msm_atomic.c | 23 ++-
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index e792158676aa..9c6fa52a40b7 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -97,18 +97,12 @@ static void msm_atomic_wait_for_commit_done(struct 
drm_device *dev,
}
 }
 
-/* The (potentially) asynchronous part of the commit.  At this point
- * nothing can fail short of armageddon.
- */
-static void complete_commit(struct msm_commit *c, bool async)
+static void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
-   struct drm_atomic_state *state = c->state;
struct drm_device *dev = state->dev;
struct msm_drm_private *priv = dev->dev_private;
struct msm_kms *kms = priv->kms;
 
-   drm_atomic_helper_wait_for_fences(dev, state, false);
-
kms->funcs->prepare_commit(kms, state);
 
drm_atomic_helper_commit_modeset_disables(dev, state);
@@ -135,10 +129,21 @@ static void complete_commit(struct msm_commit *c, bool 
async)
drm_atomic_helper_cleanup_planes(dev, state);
 
kms->funcs->complete_commit(kms, state);
+}
 
-   drm_atomic_state_put(state);
+/* The (potentially) asynchronous part of the commit.  At this point
+ * nothing can fail short of armageddon.
+ */
+static void complete_commit(struct msm_commit *c)
+{
+   struct drm_atomic_state *state = c->state;
+   struct drm_device *dev = state->dev;
 
-   commit_destroy(c);
+   drm_atomic_helper_wait_for_fences(dev, state, false);
+
+   msm_atomic_commit_tail(state);
+
+   drm_atomic_state_put(state);
 }
 
 static void commit_worker(struct work_struct *work)
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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[Freedreno] [PATCH v4] drm/msm: Use drm_private_obj/state instead of subclassing

[Sean Paul]

Now that we have private state handled by the core, we can use those
instead of rolling our own swap_state for private data.

Originally posted here: https://patchwork.freedesktop.org/patch/211361/

Changes in v2:
 - Use state->state in disp duplicate_state callback (Jeykumar)
Changes in v3:
 - Update comment describing msm_kms_state (Jeykumar)
Changes in v4:
 - Rebased on msm-next
 - Don't always use private state from atomic state (Archit)
 - Renamed some of the state accessors 
 - Tested on mdp5 db410c

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Cc: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c   | 77 ++-
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h   | 11 +--
 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c | 12 ++-
 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c  | 28 ---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c   | 19 +++--
 drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h   |  4 +-
 drivers/gpu/drm/msm/msm_atomic.c   | 37 -
 drivers/gpu/drm/msm/msm_drv.c  | 87 +-
 drivers/gpu/drm/msm/msm_drv.h  |  3 -
 drivers/gpu/drm/msm/msm_kms.h  | 21 --
 10 files changed, 183 insertions(+), 116 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 6d8e3a9a6fc0..366670043190 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -70,60 +70,62 @@ static int mdp5_hw_init(struct msm_kms *kms)
return 0;
 }
 
-struct mdp5_state *mdp5_get_state(struct drm_atomic_state *s)
+struct mdp5_state *mdp5_state_from_atomic(struct drm_atomic_state *state)
 {
-   struct msm_drm_private *priv = s->dev->dev_private;
-   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct msm_kms_state *state = to_kms_state(s);
-   struct mdp5_state *new_state;
-   int ret;
+   struct msm_kms_state *kms_state = msm_kms_state_from_atomic(state);
 
-   if (state->state)
-   return state->state;
+   if (IS_ERR_OR_NULL(kms_state))
+   return (struct mdp5_state *)kms_state; /* casting ERR_PTR */
 
-   ret = drm_modeset_lock(_kms->state_lock, s->acquire_ctx);
-   if (ret)
-   return ERR_PTR(ret);
+   return kms_state->state;
+}
 
-   new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
-   if (!new_state)
-   return ERR_PTR(-ENOMEM);
+struct mdp5_state *mdp5_state_from_dev(struct drm_device *dev)
+{
+   struct msm_kms_state *kms_state = msm_kms_state_from_dev(dev);
 
-   /* Copy state: */
-   new_state->hwpipe = mdp5_kms->state->hwpipe;
-   new_state->hwmixer = mdp5_kms->state->hwmixer;
-   if (mdp5_kms->smp)
-   new_state->smp = mdp5_kms->state->smp;
+   if (IS_ERR_OR_NULL(kms_state))
+   return (struct mdp5_state *)kms_state; /* casting ERR_PTR */
 
-   state->state = new_state;
+   return kms_state->state;
+}
+
+static void *mdp5_duplicate_state(void *state)
+{
+   if (!state)
+   return kzalloc(sizeof(struct mdp5_state), GFP_KERNEL);
 
-   return new_state;
+   return kmemdup(state, sizeof(struct mdp5_state), GFP_KERNEL);
 }
 
-static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state 
*state)
+static void mdp5_destroy_state(void *state)
 {
-   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
-   swap(to_kms_state(state)->state, mdp5_kms->state);
+   struct mdp5_state *mdp_state = (struct mdp5_state *)state;
+   kfree(mdp_state);
 }
 
-static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state 
*state)
+static void mdp5_prepare_commit(struct msm_kms *kms,
+   struct drm_atomic_state *old_state)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+   struct mdp5_state *mdp5_state = mdp5_state_from_dev(mdp5_kms->dev);
struct device *dev = _kms->pdev->dev;
 
pm_runtime_get_sync(dev);
 
if (mdp5_kms->smp)
-   mdp5_smp_prepare_commit(mdp5_kms->smp, _kms->state->smp);
+   mdp5_smp_prepare_commit(mdp5_kms->smp, _state->smp);
 }
 
-static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state 
*state)
+static void mdp5_complete_commit(struct msm_kms *kms,
+struct drm_atomic_state *old_state)
 {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+   struct mdp5_state *mdp5_state = mdp5_state_from_dev(mdp5_kms->dev);
struct device *dev = _kms->pdev->dev;
 
if (mdp5_kms->smp)
-   mdp5_smp_complete_commit(mdp5_kms->smp, _kms->state->smp);
+   mdp5_smp_complete_

Re: [Freedreno] [DPU PATCH 2/2] drm/msm: Add hardware catalog file for SDM845

[Sean Paul]

On Wed, Mar 21, 2018 at 04:05:31PM +0530, skoll...@codeaurora.org wrote:
> On 2018-03-20 20:47, Sean Paul wrote:
> > On Tue, Mar 20, 2018 at 07:13:38PM +0530, skoll...@codeaurora.org wrote:
> > > On 2018-03-19 19:29, Sean Paul wrote:
> > > > On Wed, Mar 14, 2018 at 11:21:38AM +0530, Sravanthi Kollukuduru wrote:
> > > > > This change adds the hardware catalog information in driver source
> > > > > for SDM845. This removes the current logic of dt based parsing
> > > > > of target catalog information.
> > > > >
> > > > > Signed-off-by: Sravanthi Kollukuduru <skoll...@codeaurora.org>
> > 
> > 
> > 
> > > > > +{
> > > > > + /* Layer capability */
> > > > > + static const struct dpu_sspp_sub_blks vig_sblk_0 = {
> > > > > + .maxlinewidth = 2560,
> > > > > + .pixel_ram_size = 50 * 1024,
> > > > > + .maxdwnscale = 4,
> > > > > + .maxupscale = 20,
> > > > > + .maxhdeciexp = DECIMATION_40X_MAX_H,
> > > > > + .maxvdeciexp = DECIMATION_40X_MAX_V,
> > > > > + .smart_dma_priority = 5,
> > > > > + .src_blk = {.name = "sspp_src_0", .id = DPU_SSPP_SRC,
> > > > > + .base = 0x00, .len = 0x150,},
> > > > > + .scaler_blk = {.name = "sspp_scaler0",
> > > > > + .id = DPU_SSPP_SCALER_QSEED3,
> > > > > + .base = 0xa00, .len = 0xa0,},
> > > > > + .csc_blk = {.name = "sspp_csc0", .id = 
> > > > > DPU_SSPP_CSC_10BIT,
> > > > > + .base = 0x1a00, .len = 0x100,},
> > > > > + .format_list = plane_formats_yuv,
> > > > > + .virt_format_list = plane_formats,
> > > > > + };
> > > >
> > > > Instead of locating all of these parameters in one file, these should be
> > > > located in their respective driver file. It also seems like you could
> > > > separate
> > > > out the common stuff such as line width, ram size, scaling, format, etc
> > > > parameters from the pipeline setup.
> > > >
> > > > The same comments apply to the other blocks. Move things into the
> > > > drivers,
> > > > use compatibility string to determine the version, and then associate
> > > > the common
> > > > parameters with of_device_id.data.
> > > >
> > > > Sean
> > > >
> > > > 
> > > 
> > > Thanks Sean for the feedback.
> > > The idea behind this approach is to maintain a one point access for
> > > all the
> > > target specific information, analogous to the current dpu dtsi file.
> > > This also ensures easy maintenance for different hardware versions,
> > > as all
> > > it
> > > takes is to add another file instead of updating across individual
> > > sub block
> > > files.
> > 
> > I am not convinced this is what we should optimize for. This file is
> > basically
> > unreadable, and it's abstracting relevant details away from the block
> > code. There
> > are also a TON of duplicated parameters/values which is error-prone.
> > Lastly,
> > this is not the type of file that you want to copy/paste multiple
> > times, it would
> > be much better to simply add the new structs to the block drivers
> > where applicable.
> > 
> > > 
> > > Also, i'm not quite clear on how compatibility strings is applicable
> > > to sub
> > > blocks.
> > 
> > Consider the following example from rockchip:
> > https://gitlab.freedesktop.org/seanpaul/dpu-staging/blob/for-next/drivers/gpu/drm/rockchip/rockchip_vop_reg.c#L538
> > 
> > Each time the vop is changed, it gets a new compatible string in the
> > dt bindings.
> > This compatible string is tied to a parameters that describe the
> > features of
> > that version of vop. This data is tied to the driver data during probe
> > and used
> > whe needed throughout the driver.
> > 
> > So all of your catalog data should be broken up into structs specific to
> > the
> > various sub-blocks of the dpu driver and associated with compatible
> > strings.
> > When a new chip comes out with different parameters, a new struct should
> > be
> > defined

Re: [Freedreno] [DPU PATCH 2/2] drm/msm: Add hardware catalog file for SDM845

[Sean Paul]

On Tue, Mar 20, 2018 at 07:13:38PM +0530, skoll...@codeaurora.org wrote:
> On 2018-03-19 19:29, Sean Paul wrote:
> > On Wed, Mar 14, 2018 at 11:21:38AM +0530, Sravanthi Kollukuduru wrote:
> > > This change adds the hardware catalog information in driver source
> > > for SDM845. This removes the current logic of dt based parsing
> > > of target catalog information.
> > > 
> > > Signed-off-by: Sravanthi Kollukuduru <skoll...@codeaurora.org>



> > > +{
> > > + /* Layer capability */
> > > + static const struct dpu_sspp_sub_blks vig_sblk_0 = {
> > > + .maxlinewidth = 2560,
> > > + .pixel_ram_size = 50 * 1024,
> > > + .maxdwnscale = 4,
> > > + .maxupscale = 20,
> > > + .maxhdeciexp = DECIMATION_40X_MAX_H,
> > > + .maxvdeciexp = DECIMATION_40X_MAX_V,
> > > + .smart_dma_priority = 5,
> > > + .src_blk = {.name = "sspp_src_0", .id = DPU_SSPP_SRC,
> > > + .base = 0x00, .len = 0x150,},
> > > + .scaler_blk = {.name = "sspp_scaler0",
> > > + .id = DPU_SSPP_SCALER_QSEED3,
> > > + .base = 0xa00, .len = 0xa0,},
> > > + .csc_blk = {.name = "sspp_csc0", .id = DPU_SSPP_CSC_10BIT,
> > > + .base = 0x1a00, .len = 0x100,},
> > > + .format_list = plane_formats_yuv,
> > > + .virt_format_list = plane_formats,
> > > + };
> > 
> > Instead of locating all of these parameters in one file, these should be
> > located in their respective driver file. It also seems like you could
> > separate
> > out the common stuff such as line width, ram size, scaling, format, etc
> > parameters from the pipeline setup.
> > 
> > The same comments apply to the other blocks. Move things into the
> > drivers,
> > use compatibility string to determine the version, and then associate
> > the common
> > parameters with of_device_id.data.
> > 
> > Sean
> > 
> > 
> 
> Thanks Sean for the feedback.
> The idea behind this approach is to maintain a one point access for all the
> target specific information, analogous to the current dpu dtsi file.
> This also ensures easy maintenance for different hardware versions, as all
> it
> takes is to add another file instead of updating across individual sub block
> files.

I am not convinced this is what we should optimize for. This file is basically
unreadable, and it's abstracting relevant details away from the block code. 
There
are also a TON of duplicated parameters/values which is error-prone. Lastly,
this is not the type of file that you want to copy/paste multiple times, it 
would
be much better to simply add the new structs to the block drivers where 
applicable.

> 
> Also, i'm not quite clear on how compatibility strings is applicable to sub
> blocks.

Consider the following example from rockchip:
https://gitlab.freedesktop.org/seanpaul/dpu-staging/blob/for-next/drivers/gpu/drm/rockchip/rockchip_vop_reg.c#L538

Each time the vop is changed, it gets a new compatible string in the dt 
bindings.
This compatible string is tied to a parameters that describe the features of
that version of vop. This data is tied to the driver data during probe and used
whe needed throughout the driver.

So all of your catalog data should be broken up into structs specific to the
various sub-blocks of the dpu driver and associated with compatible strings.
When a new chip comes out with different parameters, a new struct should be
defined along with a new compatible string.

Make sense?

Sean

> Please clarify.
> 
> Thanks,
> Sravanthi

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Re: [Freedreno] [DPU PATCH 06/11] drm/msm: Remove msm_commit/kthread, use atomic helper commit

[Sean Paul]

On Mon, Mar 12, 2018 at 04:23:10PM -0400, Sean Paul wrote:
> On Thu, Mar 08, 2018 at 05:08:03PM -0800, Jeykumar Sankaran wrote:
> > On 2018-03-02 06:56, Sean Paul wrote:
> > > On Thu, Mar 01, 2018 at 07:37:10PM -0500, Rob Clark wrote:
> > > > On Thu, Mar 1, 2018 at 3:37 PM,  <jsa...@codeaurora.org> wrote:
> > > > > On 2018-03-01 07:27, Sean Paul wrote:
> > > > >>
> > > > >> On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org
> > > wrote:
> > > > >>>
> > > > >>> On 2018-02-28 11:19, Sean Paul wrote:
> > > > >>> > Moving further towards switching fully to the the atomic helpers,
> > > this
> > > > >>> > patch removes the hand-rolled kthread nonblock commit code and
> > > uses
> > > > >>
> > > > >> the
> > > > >>>
> > > > >>> > atomic helpers commit_work model.
> > > > >>> >
> > > > >>> > There's still a lot of copypasta here, but it's still needed to
> > > > >>> > facilitate the swap_state and prepare_fence private functions.
> > > These
> > > > >>> > will be sorted out in a follow-on patch.
> > > > >>> >
> > > > >>> > Change-Id: I9fcba27824ba63d3fab96cb2bc194bfa6f3475b7
> > > > >>> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > > > >>> > ---



> > > > >>
> > > > >>> > - /* only return zero if work
> > > is
> > > > >>> > -  * queued successfully.
> > > > >>> > -  */
> > > > >>> > - ret = 0;
> > > > >>> > - } else {
> > > > >>> > -     DRM_ERROR(" Error for
> > > crtc_id:
> > > > >>> > %d\n",
> > > > >>> > -
> > > > >>> > priv->disp_thread[j].crtc_id);
> > > > >>> > - }
> > > > >>> > - break;
> > > > >>> > - }
> > > > >>> > - }
> > 
> > Care to remove priv->disp_thread and all its references as a part of this
> > change?
> 
> Definitely! Will revise.
> 

Now that I look at it, disp_thread doesn't seem relevant to this change. It
seems like it's used for deferred cleanup. So perhaps we could get rid of it,
but IMO that would be a different patch.

> Sean
> 
> > 
> > - Jeykumar S



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Re: [Freedreno] [DPU PATCH 2/2] drm/msm: Add hardware catalog file for SDM845

[Sean Paul]

On Wed, Mar 14, 2018 at 11:21:38AM +0530, Sravanthi Kollukuduru wrote:
> This change adds the hardware catalog information in driver source
> for SDM845. This removes the current logic of dt based parsing
> of target catalog information.
> 
> Signed-off-by: Sravanthi Kollukuduru <skoll...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/Makefile   |1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3071 
> +---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   17 +-
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog_sdm845.c  |  744 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|2 +-
>  5 files changed, 767 insertions(+), 3068 deletions(-)

Hi Sravanthi,
Thank you for the patch, it's great to see diffstats like this :)



> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_sdm845.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_sdm845.c
> new file mode 100644
> index 000..3ca5dc7
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_sdm845.c
> @@ -0,0 +1,744 @@
> +/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.

We should be using SPDX license tags from now on.

> + */
> +
> +#include "dpu_hw_catalog.h"
> +#include "dpu_hw_catalog_format.h"
> +#include "dpu_hw_mdss.h"
> +#include "dpu_hwio.h"
> +
> +/* VIG layer capability */
> +#define VIG_40X_MASK \
> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\
> + BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\
> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
> +
> +/* DMA layer capability */
> +#define DMA_40X_MASK \
> + (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> + BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
> +
> +#define MIXER_40X_MASK \
> + (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
> +
> +#define DSPP_40X_MASK \
> + (BIT(DPU_DSPP_IGC) | BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) |\
> + BIT(DPU_DSPP_HSIC) | BIT(DPU_DSPP_GAMUT) | BIT(DPU_DSPP_HIST) |\
> + BIT(DPU_DSPP_MEMCOLOR) | BIT(DPU_DSPP_SIXZONE) | BIT(DPU_DSPP_VLUT))
> +
> +#define DSPP_AD_40X_MASK \
> + (DSPP_40X_MASK | BIT(DPU_DSPP_AD))
> +
> +#define PINGPONG_40X_MASK BIT(DPU_PINGPONG_DITHER)
> +
> +#define PINGPONG_40X_SPLIT_MASK \
> + (PINGPONG_40X_MASK | BIT(DPU_PINGPONG_SPLIT) | BIT(DPU_PINGPONG_TE2))
> +
> +#define WB2_40X_MASK \
> + (BIT(DPU_WB_LINE_MODE) | BIT(DPU_WB_TRAFFIC_SHAPER) | BIT(DPU_WB_CDP) |\
> + BIT(DPU_WB_YUV_CONFIG) | BIT(DPU_WB_QOS_8LVL) | BIT(DPU_WB_UBWC))
> +
> +#define DECIMATION_40X_MAX_H 4
> +#define DECIMATION_40X_MAX_V 4
> +
> +/*
> + * set_cfg_xxx_init(): populate dpu sub-blocks reg offsets
> + * and instance counts.
> + */
> +static inline int set_cfg_40X_init(struct dpu_mdss_cfg *dpu_cfg)
> +{
> + /* Layer capability */
> + static const struct dpu_sspp_sub_blks vig_sblk_0 = {
> + .maxlinewidth = 2560,
> + .pixel_ram_size = 50 * 1024,
> + .maxdwnscale = 4,
> + .maxupscale = 20,
> + .maxhdeciexp = DECIMATION_40X_MAX_H,
> + .maxvdeciexp = DECIMATION_40X_MAX_V,
> + .smart_dma_priority = 5,
> + .src_blk = {.name = "sspp_src_0", .id = DPU_SSPP_SRC,
> + .base = 0x00, .len = 0x150,},
> + .scaler_blk = {.name = "sspp_scaler0",
> + .id = DPU_SSPP_SCALER_QSEED3,
> + .base = 0xa00, .len = 0xa0,},
> + .csc_blk = {.name = "sspp_csc0", .id = DPU_SSPP_CSC_10BIT,
> + .base = 0x1a00, .len = 0x100,},
> + .format_list = plane_formats_yuv,
> + .virt_format_list = plane_formats,
> + };

Instead of locating all of these parameters in one file, these should be
located in their respective driver file. It also seems like you could separate
out the common stuff such as line width, ram size, scaling, format, etc
parameters from the pipeline setup.

The same comments apply to the other blocks. Move things into the drivers,
use compatibility string to determine the version, and then associate the common
parameters with of_device_id.data.

Sean


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[Freedreno] [DPU PATCH v2] drm/msm: Don't duplicate modeset_enables atomic helper

[Sean Paul]

Instead, shuffle things around so we kickoff crtc after enabling encoder
during modesets. Also moves the vblank wait to after the frame.

Changes in v2:
- Remove the encoder.commit hack, it's not required (Jeykumar)

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c |   9 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |   8 +-
 drivers/gpu/drm/msm/msm_atomic.c | 132 ++-
 3 files changed, 19 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index a3ab6ed2bf1d..94fab2dcca5b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -3525,6 +3525,12 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
DPU_EVT32_VERBOSE(DRMID(crtc));
dpu_crtc = to_dpu_crtc(crtc);
 
+   if (msm_is_mode_seamless(>state->adjusted_mode) ||
+   msm_is_mode_seamless_vrr(>state->adjusted_mode)) {
+   DPU_DEBUG("Skipping crtc enable, seamless mode\n");
+   return;
+   }
+
pm_runtime_get_sync(crtc->dev->dev);
 
drm_for_each_encoder(encoder, crtc->dev) {
@@ -3572,6 +3578,9 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE |
DPU_POWER_EVENT_PRE_DISABLE,
dpu_crtc_handle_power_event, crtc, dpu_crtc->name);
+
+   if (msm_needs_vblank_pre_modeset(>state->adjusted_mode))
+   drm_crtc_wait_one_vblank(crtc);
 }
 
 struct plane_state {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5ba345395b82..2c4c7fe1affe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -422,14 +422,14 @@ static void dpu_kms_prepare_commit(struct msm_kms *kms,
dpu_encoder_prepare_commit(encoder);
 }
 
-static void dpu_kms_commit(struct msm_kms *kms,
-   struct drm_atomic_state *old_state)
+static void dpu_kms_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 {
struct drm_crtc *crtc;
-   struct drm_crtc_state *old_crtc_state;
+   struct drm_crtc_state *crtc_state;
+   struct dpu_crtc_state *cstate;
int i;
 
-   for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
if (crtc->state->active) {
DPU_EVT32(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 5cfb80345052..f5794dce25dd 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -84,131 +84,6 @@ static void msm_atomic_wait_for_commit_done(
}
 }
 
-/**
- * msm_atomic_helper_commit_modeset_enables - modeset commit to enable outputs
- * @dev: DRM device
- * @old_state: atomic state object with old state structures
- *
- * This function enables all the outputs with the new configuration which had 
to
- * be turned off for the update.
- *
- * For compatibility with legacy crtc helpers this should be called after
- * drm_atomic_helper_commit_planes(), which is what the default commit function
- * does. But drivers with different needs can group the modeset commits 
together
- * and do the plane commits at the end. This is useful for drivers doing 
runtime
- * PM since planes updates then only happen when the CRTC is actually enabled.
- */
-static void msm_atomic_helper_commit_modeset_enables(struct drm_device *dev,
-   struct drm_atomic_state *old_state)
-{
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *old_crtc_state;
-   struct drm_crtc_state *new_crtc_state;
-   struct drm_connector *connector;
-   struct drm_connector_state *new_conn_state;
-   struct msm_drm_private *priv = dev->dev_private;
-   struct msm_kms *kms = priv->kms;
-   int bridge_enable_count = 0;
-   int i;
-
-   for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state,
-   new_crtc_state, i) {
-   const struct drm_crtc_helper_funcs *funcs;
-
-   /* Need to filter out CRTCs where only planes change. */
-   if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
-   continue;
-
-   if (!new_crtc_state->active)
-   continue;
-
-   if (msm_is_mode_seamless(_crtc_state->mode) ||
-   msm_is_mode_seamless_vrr(
-   _crtc_state->adjusted_mode))
-   continue;
-
-   funcs = crtc->helper_private;
-
-   if (crtc->

Re: [Freedreno] [DPU PATCH 02/11] drm/msm: Don't duplicate modeset_enables atomic helper

[Sean Paul]

On Tue, Mar 13, 2018 at 04:57:35PM -0700, Jeykumar Sankaran wrote:
> On 2018-03-12 13:21, Sean Paul wrote:
> > On Thu, Mar 08, 2018 at 04:56:01PM -0800, Jeykumar Sankaran wrote:
> > > On 2018-02-28 11:18, Sean Paul wrote:
> > > > Instead, shuffle things around so we kickoff crtc after enabling
> > encoder
> > > > during modesets. Also moves the vblank wait to after the frame.
> > > >
> > > > Change-Id: I16c7b7f9390d04f6050aa20e17a5335fbf49eba3
> > > > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > > > ---
> > > >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|   9 ++
> > > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |   5 +-
> > > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  31 -
> > > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |   2 +
> > > >  drivers/gpu/drm/msm/msm_atomic.c| 132
> > +---
> > > >  5 files changed, 48 insertions(+), 131 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > > index a3ab6ed2bf1d..94fab2dcca5b 100644
> > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > > @@ -3525,6 +3525,12 @@ static void dpu_crtc_enable(struct drm_crtc
> > > > *crtc,
> > > > DPU_EVT32_VERBOSE(DRMID(crtc));
> > > > dpu_crtc = to_dpu_crtc(crtc);
> > > >
> > > > +   if (msm_is_mode_seamless(>state->adjusted_mode) ||
> > > > +   msm_is_mode_seamless_vrr(>state->adjusted_mode)) {
> > > > +   DPU_DEBUG("Skipping crtc enable, seamless mode\n");
> > > > +   return;
> > > > +   }
> > > > +
> > > > pm_runtime_get_sync(crtc->dev->dev);
> > > >
> > > > drm_for_each_encoder(encoder, crtc->dev) {
> > > > @@ -3572,6 +3578,9 @@ static void dpu_crtc_enable(struct drm_crtc
> > *crtc,
> > > > DPU_POWER_EVENT_POST_ENABLE | 
> > > > DPU_POWER_EVENT_POST_DISABLE
> > > > |
> > > > DPU_POWER_EVENT_PRE_DISABLE,
> > > > dpu_crtc_handle_power_event, crtc, dpu_crtc->name);
> > > > +
> > > > +   if (msm_needs_vblank_pre_modeset(>state->adjusted_mode))
> > > > +   drm_crtc_wait_one_vblank(crtc);
> > > >  }
> > > >
> > > >  struct plane_state {
> > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > index 28ceb589ee40..4d1e3652dbf4 100644
> > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > > @@ -3693,8 +3693,11 @@ static void
> > dpu_encoder_frame_done_timeout(struct
> > > > timer_list *t)
> > > >  static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs
> > =
> > > > {
> > > > .mode_set = dpu_encoder_virt_mode_set,
> > > > .disable = dpu_encoder_virt_disable,
> > > > -   .enable = dpu_encoder_virt_enable,
> > > > +   .enable = dpu_kms_encoder_enable,
> > > > .atomic_check = dpu_encoder_virt_atomic_check,
> > > > +
> > > > +   /* This is called by dpu_kms_encoder_enable */
> > > > +   .commit = dpu_encoder_virt_enable,
> > > >  };
> > > >
> > > >  static const struct drm_encoder_funcs dpu_encoder_funcs = {
> > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > > index 81fd3a429e9f..3d83037e8305 100644
> > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > > @@ -425,14 +425,37 @@ static void dpu_kms_prepare_commit(struct
> > msm_kms
> > > > *kms,
> > > > dpu_encoder_prepare_commit(encoder);
> > > >  }
> > > >
> > > > -static void dpu_kms_commit(struct msm_kms *kms,
> > > > -   struct drm_atomic_state *old_state)
> > > > +/*
> > > > + * Override the encoder enable since we need to setup the inline
> > > > rotator
> > > > 

[Freedreno] [DPU PATCH] drm/msm: Add pm_runtime_get/put calls to dpu

[Sean Paul]

Ensure that pm_runtime is properly referenced/unreferenced when we need
it.

Signed-off-by: Sean Paul <seanp...@chromium.org>
---

Didn't get a response to my suggestion, so wrote the patch anyways.
Thoughts?


 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c |  3 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  2 ++
 drivers/gpu/drm/msm/dpu_power_handle.c   | 12 
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f1642d72469e..df6cbeb15cf5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -3497,6 +3497,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
/* disable clk & bw control until clk & bw properties are set */
cstate->bw_control = false;
cstate->bw_split_vote = false;
+   pm_runtime_put_sync(crtc->dev->dev);
 
mutex_unlock(_crtc->crtc_lock);
 }
@@ -3523,6 +3524,8 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
DPU_EVT32_VERBOSE(DRMID(crtc));
dpu_crtc = to_dpu_crtc(crtc);
 
+   pm_runtime_get_sync(crtc->dev->dev);
+
drm_for_each_encoder(encoder, crtc->dev) {
if (encoder->crtc != crtc)
continue;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fb4de59d8ed1..90608a303aec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -346,12 +346,14 @@ static void _dpu_debugfs_destroy(struct dpu_kms *dpu_kms)
 
 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 {
+   pm_runtime_get_sync(crtc->dev->dev);
return dpu_crtc_vblank(crtc, true);
 }
 
 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 {
dpu_crtc_vblank(crtc, false);
+   pm_runtime_put_sync(crtc->dev->dev);
 }
 
 static void dpu_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
diff --git a/drivers/gpu/drm/msm/dpu_power_handle.c 
b/drivers/gpu/drm/msm/dpu_power_handle.c
index 477ea9f2778c..a52be861117f 100644
--- a/drivers/gpu/drm/msm/dpu_power_handle.c
+++ b/drivers/gpu/drm/msm/dpu_power_handle.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -857,6 +858,9 @@ int dpu_power_resource_enable(struct dpu_power_handle 
*phandle,
return -EINVAL;
}
 
+   if (enable)
+   pm_runtime_get_sync(phandle->dev);
+
mp = >mp;
 
mutex_lock(>phandle_lock);
@@ -963,10 +967,6 @@ int dpu_power_resource_enable(struct dpu_power_handle 
*phandle,
DPU_POWER_EVENT_POST_DISABLE);
}
 
-end:
-   mutex_unlock(>phandle_lock);
-   return rc;
-
 clk_err:
dpu_power_rsc_update(phandle, false);
 rsc_err:
@@ -979,7 +979,11 @@ int dpu_power_resource_enable(struct dpu_power_handle 
*phandle,
dpu_power_data_bus_update(>data_bus_handle[i], 0);
 data_bus_hdl_err:
phandle->current_usecase_ndx = prev_usecase_ndx;
+
+end:
mutex_unlock(>phandle_lock);
+   if (!enable)
+   pm_runtime_put_sync(phandle->dev);
return rc;
 }
 
-- 
Sean Paul, Software Engineer, Google / Chromium OS

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Re: [Freedreno] [DPU PATCH 07/11] drm/msm: Use atomic private_obj instead of subclassing

[Sean Paul]

On Thu, Mar 08, 2018 at 05:59:11PM -0800, Jeykumar Sankaran wrote:
> On 2018-02-28 11:19, Sean Paul wrote:
> > Instead of subclassing atomic state, store driver private data in
> > private_obj/state. This allows us to remove the swap_state driver hook
> > for mdp5 and get closer to using the atomic helpers entirely.
> > 
> > Change-Id: I65a4a2887593ae257d584e00b352b5daf00e4e61
> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > ---
> >  drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 37 ++
> >  drivers/gpu/drm/msm/msm_atomic.c | 30 ---
> >  drivers/gpu/drm/msm/msm_drv.c| 65 ++--
> >  drivers/gpu/drm/msm/msm_drv.h|  4 +-
> >  drivers/gpu/drm/msm/msm_kms.h| 28 +-
> >  5 files changed, 95 insertions(+), 69 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> > b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> > index 6d8e3a9a6fc0..f1a248419655 100644
> > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
> > @@ -74,36 +74,32 @@ struct mdp5_state *mdp5_get_state(struct
> > drm_atomic_state *s)
> >  {
> > struct msm_drm_private *priv = s->dev->dev_private;
> > struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
> > -   struct msm_kms_state *state = to_kms_state(s);
> > -   struct mdp5_state *new_state;
> > +   struct msm_kms_state *kms_state;
> > int ret;
> > 
> > -   if (state->state)
> > -   return state->state;
> > -
> > ret = drm_modeset_lock(_kms->state_lock, s->acquire_ctx);
> > if (ret)
> > return ERR_PTR(ret);
> > 
> > -   new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
> > -   if (!new_state)
> > -   return ERR_PTR(-ENOMEM);
> > +   kms_state = msm_kms_get_state(s);
> > +   if (IS_ERR_OR_NULL(kms_state))
> > +   return (struct mdp5_state *)kms_state; /* casting ERR_PTR
> > */
> > 
> > -   /* Copy state: */
> > -   new_state->hwpipe = mdp5_kms->state->hwpipe;
> > -   new_state->hwmixer = mdp5_kms->state->hwmixer;
> > -   if (mdp5_kms->smp)
> > -   new_state->smp = mdp5_kms->state->smp;
> > +   return kms_state->state;
> > +}
> > 
> > -   state->state = new_state;
> > +static void *mdp5_duplicate_state(void *state)
> > +{
> > +   if (!state)
> > +   return kzalloc(sizeof(struct mdp5_state), GFP_KERNEL);
> > 
> > -   return new_state;
> > +   return kmemdup(state, sizeof(struct mdp5_state), GFP_KERNEL);
> >  }
> > 
> > -static void mdp5_swap_state(struct msm_kms *kms, struct
> > drm_atomic_state
> > *state)
> > +static void mdp5_destroy_state(void *state)
> >  {
> > -   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
> > -   swap(to_kms_state(state)->state, mdp5_kms->state);
> > +   struct mdp5_state *mdp_state = state;
> > +   kfree(mdp_state);
> >  }
> > 
> >  static void mdp5_prepare_commit(struct msm_kms *kms, struct
> > drm_atomic_state *state)
> > @@ -229,7 +225,8 @@ static const struct mdp_kms_funcs kms_funcs = {
> > .irq = mdp5_irq,
> > .enable_vblank   = mdp5_enable_vblank,
> > .disable_vblank  = mdp5_disable_vblank,
> > -   .swap_state  = mdp5_swap_state,
> > +   .duplicate_state = mdp5_duplicate_state,
> > +   .destroy_state   = mdp5_destroy_state,
> > .prepare_commit  = mdp5_prepare_commit,
> > .complete_commit = mdp5_complete_commit,
> > .wait_for_crtc_commit_done =
> > mdp5_wait_for_crtc_commit_done,
> > @@ -726,8 +723,6 @@ static void mdp5_destroy(struct platform_device
> > *pdev)
> > 
> > if (mdp5_kms->rpm_enabled)
> > pm_runtime_disable(>dev);
> > -
> > -   kfree(mdp5_kms->state);
> >  }
> > 
> >  static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
> > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> > b/drivers/gpu/drm/msm/msm_atomic.c
> > index 7e54eb65d096..1f53262ea46b 100644
> > --- a/drivers/gpu/drm/msm/msm_atomic.c
> > +++ b/drivers/gpu/drm/msm/msm_atomic.c
> > @@ -169,9 +169,6 @@ int msm_atomic_commit(struct drm_device *dev,
> >  */
> > BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
> > 
> > -   if (to_kms_state(state)->state)
> > -   p

Re: [Freedreno] [DPU PATCH 06/11] drm/msm: Remove msm_commit/kthread, use atomic helper commit

[Sean Paul]

On Thu, Mar 08, 2018 at 05:08:03PM -0800, Jeykumar Sankaran wrote:
> On 2018-03-02 06:56, Sean Paul wrote:
> > On Thu, Mar 01, 2018 at 07:37:10PM -0500, Rob Clark wrote:
> > > On Thu, Mar 1, 2018 at 3:37 PM,  <jsa...@codeaurora.org> wrote:
> > > > On 2018-03-01 07:27, Sean Paul wrote:
> > > >>
> > > >> On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org
> > wrote:
> > > >>>
> > > >>> On 2018-02-28 11:19, Sean Paul wrote:
> > > >>> > Moving further towards switching fully to the the atomic helpers,
> > this
> > > >>> > patch removes the hand-rolled kthread nonblock commit code and
> > uses
> > > >>
> > > >> the
> > > >>>
> > > >>> > atomic helpers commit_work model.
> > > >>> >
> > > >>> > There's still a lot of copypasta here, but it's still needed to
> > > >>> > facilitate the swap_state and prepare_fence private functions.
> > These
> > > >>> > will be sorted out in a follow-on patch.
> > > >>> >
> > > >>> > Change-Id: I9fcba27824ba63d3fab96cb2bc194bfa6f3475b7
> > > >>> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > > >>> > ---
> > > >>> >  drivers/gpu/drm/msm/msm_atomic.c | 199
> > > >>
> > > >> ++-
> > > >>>
> > > >>> >  drivers/gpu/drm/msm/msm_drv.c|   1 -
> > > >>> >  drivers/gpu/drm/msm/msm_drv.h|   4 -
> > > >>> >  3 files changed, 35 insertions(+), 169 deletions(-)
> > > >>> >
> > > >>> > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> > > >>> > b/drivers/gpu/drm/msm/msm_atomic.c
> > > >>> > index 3a18bd3dc215..7e54eb65d096 100644
> > > >>> > --- a/drivers/gpu/drm/msm/msm_atomic.c
> > > >>> > +++ b/drivers/gpu/drm/msm/msm_atomic.c
> > > >>> > @@ -21,51 +21,6 @@
> > > >>> >  #include "msm_gem.h"
> > > >>> >  #include "msm_fence.h"
> > > >>> >
> > > >>> > -struct msm_commit {
> > > >>> > - struct drm_device *dev;
> > > >>> > - struct drm_atomic_state *state;
> > > >>> > - uint32_t crtc_mask;
> > > >>> > - bool nonblock;
> > > >>> > - struct kthread_work commit_work;
> > > >>> > -};
> > > >>> > -
> > > >>> > -/* block until specified crtcs are no longer pending update, and
> > > >>> > - * atomically mark them as pending update
> > > >>> > - */
> > > >>> > -static int start_atomic(struct msm_drm_private *priv, uint32_t
> > > >>> > crtc_mask)
> > > >>> > -{
> > > >>> > - int ret;
> > > >>> > -
> > > >>> > - spin_lock(>pending_crtcs_event.lock);
> > > >>> > - ret =
> > wait_event_interruptible_locked(priv->pending_crtcs_event,
> > > >>> > - !(priv->pending_crtcs & crtc_mask));
> > > >>> > - if (ret == 0) {
> > > >>> > - DBG("start: %08x", crtc_mask);
> > > >>> > - priv->pending_crtcs |= crtc_mask;
> > > >>> > - }
> > > >>> > - spin_unlock(>pending_crtcs_event.lock);
> > > >>> > -
> > > >>> > - return ret;
> > > >>> > -}
> > > >>> > -
> > > >>> > -/* clear specified crtcs (no longer pending update)
> > > >>> > - */
> > > >>> > -static void end_atomic(struct msm_drm_private *priv, uint32_t
> > > >>> > crtc_mask)
> > > >>> > -{
> > > >>> > - spin_lock(>pending_crtcs_event.lock);
> > > >>> > - DBG("end: %08x", crtc_mask);
> > > >>> > - priv->pending_crtcs &= ~crtc_mask;
> > > >>> > - wake_up_all_locked(>pending_crtcs_event);
> > > >>> > - spin_unlock(>pending_crtcs_event.lock);
> > > >>> > -}
> > > >

Re: [Freedreno] [DPU PATCH 02/11] drm/msm: Don't duplicate modeset_enables atomic helper

[Sean Paul]

On Thu, Mar 08, 2018 at 04:56:01PM -0800, Jeykumar Sankaran wrote:
> On 2018-02-28 11:18, Sean Paul wrote:
> > Instead, shuffle things around so we kickoff crtc after enabling encoder
> > during modesets. Also moves the vblank wait to after the frame.
> > 
> > Change-Id: I16c7b7f9390d04f6050aa20e17a5335fbf49eba3
> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > ---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|   9 ++
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |   5 +-
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  31 -
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |   2 +
> >  drivers/gpu/drm/msm/msm_atomic.c| 132 +---
> >  5 files changed, 48 insertions(+), 131 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > index a3ab6ed2bf1d..94fab2dcca5b 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -3525,6 +3525,12 @@ static void dpu_crtc_enable(struct drm_crtc
> > *crtc,
> > DPU_EVT32_VERBOSE(DRMID(crtc));
> > dpu_crtc = to_dpu_crtc(crtc);
> > 
> > +   if (msm_is_mode_seamless(>state->adjusted_mode) ||
> > +   msm_is_mode_seamless_vrr(>state->adjusted_mode)) {
> > +   DPU_DEBUG("Skipping crtc enable, seamless mode\n");
> > +   return;
> > +   }
> > +
> > pm_runtime_get_sync(crtc->dev->dev);
> > 
> > drm_for_each_encoder(encoder, crtc->dev) {
> > @@ -3572,6 +3578,9 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
> > DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE
> > |
> > DPU_POWER_EVENT_PRE_DISABLE,
> > dpu_crtc_handle_power_event, crtc, dpu_crtc->name);
> > +
> > +   if (msm_needs_vblank_pre_modeset(>state->adjusted_mode))
> > +   drm_crtc_wait_one_vblank(crtc);
> >  }
> > 
> >  struct plane_state {
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 28ceb589ee40..4d1e3652dbf4 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -3693,8 +3693,11 @@ static void dpu_encoder_frame_done_timeout(struct
> > timer_list *t)
> >  static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs =
> > {
> > .mode_set = dpu_encoder_virt_mode_set,
> > .disable = dpu_encoder_virt_disable,
> > -   .enable = dpu_encoder_virt_enable,
> > +   .enable = dpu_kms_encoder_enable,
> > .atomic_check = dpu_encoder_virt_atomic_check,
> > +
> > +   /* This is called by dpu_kms_encoder_enable */
> > +   .commit = dpu_encoder_virt_enable,
> >  };
> > 
> >  static const struct drm_encoder_funcs dpu_encoder_funcs = {
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index 81fd3a429e9f..3d83037e8305 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -425,14 +425,37 @@ static void dpu_kms_prepare_commit(struct msm_kms
> > *kms,
> > dpu_encoder_prepare_commit(encoder);
> >  }
> > 
> > -static void dpu_kms_commit(struct msm_kms *kms,
> > -   struct drm_atomic_state *old_state)
> > +/*
> > + * Override the encoder enable since we need to setup the inline
> > rotator
> > and do
> > + * some crtc magic before enabling any bridge that might be present.
> > + */
> > +void dpu_kms_encoder_enable(struct drm_encoder *encoder)
> > +{
> > +   const struct drm_encoder_helper_funcs *funcs =
> > encoder->helper_private;
> > +   struct drm_crtc *crtc = encoder->crtc;
> > +
> > +   /* Forward this enable call to the commit hook */
> > +   if (funcs && funcs->commit)
> > +   funcs->commit(encoder);
> 
> The purpose of this function is not clear. Where are we setting up the
> inline rotator?
> Why do we need a kickoff here?

The reason the code is shuffled is to avoid duplicating the entire atomic helper
function. By moving calls into the ->enable hooks, we can avoid having to hand
roll the helpers.

The kickoff is preserved from the helper copy when you call kms->funcs->commit
in between the encoder enable and bridge enable. If this can be removed, that'd
be even better. I was simply trying to preserve the call order of everything.

Sean

Re: [Freedreno] [DPU PATCH 01/11] drm/msm: Skip seamless disables in crtc/encoder

[Sean Paul]

On Fri, Mar 02, 2018 at 04:04:24PM -0800, jsa...@codeaurora.org wrote:
> On 2018-02-28 11:18, Sean Paul wrote:
> > Instead of duplicating whole swaths of atomic helper functions (which
> > are already out-of-date), just skip the encoder/crtc disables in the
> > .disable hooks.
> > 
> > Change-Id: I7bd9183ae60624204fb1de9550656b776efc7202
> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> 
> Can you consider getting rid of these checks?

Do you mean the Change-Id? Yeah, I forgot to strip them out before sending, I'll
make sure I clean it up before I apply.

> 
> > ---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|   8 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |   8 +
> >  drivers/gpu/drm/msm/msm_atomic.c| 185 +---
> >  3 files changed, 17 insertions(+), 184 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > index 3cdf1e3d9d96..a3ab6ed2bf1d 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -3393,6 +3393,7 @@ static void dpu_crtc_disable(struct drm_crtc
> > *crtc)
> >  {
> > struct dpu_crtc *dpu_crtc;
> > struct dpu_crtc_state *cstate;
> > +   struct drm_display_mode *mode;
> > struct drm_encoder *encoder;
> > struct msm_drm_private *priv;
> > unsigned long flags;
> > @@ -3407,8 +3408,15 @@ static void dpu_crtc_disable(struct drm_crtc
> > *crtc)
> > }
> > dpu_crtc = to_dpu_crtc(crtc);
> > cstate = to_dpu_crtc_state(crtc->state);
> > +   mode = >base.adjusted_mode;
> > priv = crtc->dev->dev_private;
> > 
> > +   if (msm_is_mode_seamless(mode) || msm_is_mode_seamless_vrr(mode)
> > ||
> > +   msm_is_mode_seamless_dms(mode)) {
> > +   DPU_DEBUG("Seamless mode is being applied, skip
> > disable\n");
> > +   return;
> > +   }
> > +
> Another topic of discussion which should be brought up with dri-devel.
> 
> May not be common in PC world, but there are a handful of mobile OEM's
> using panels which supports more than one resolution. Primary use cases
> involve "seamless" switching to optimized display resolution when
> streaming content changes resolutions or rendering lossless data.

Yeah, I think we can do this under the covers if the hardware supports it such
as this patch. We could probably do a better job of making this useful for other
drivers, but I was really just trying to get the seamless stuff out of the way
so we don't need to roll our own atomic commit.

Sean

> 
> Jeykumar S.
> 
> > DPU_DEBUG("crtc%d\n", crtc->base.id);
> > 
> > if (dpu_kms_is_suspend_state(crtc->dev))
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 3d168fa09f3f..28ceb589ee40 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -2183,6 +2183,7 @@ static void dpu_encoder_virt_disable(struct
> > drm_encoder *drm_enc)
> > struct dpu_encoder_virt *dpu_enc = NULL;
> > struct msm_drm_private *priv;
> > struct dpu_kms *dpu_kms;
> > +   struct drm_display_mode *mode;
> > int i = 0;
> > 
> > if (!drm_enc) {
> > @@ -2196,6 +2197,13 @@ static void dpu_encoder_virt_disable(struct
> > drm_encoder *drm_enc)
> > return;
> > }
> > 
> > +   mode = _enc->crtc->state->adjusted_mode;
> > +   if (msm_is_mode_seamless(mode) || msm_is_mode_seamless_vrr(mode)
> > ||
> > +   msm_is_mode_seamless_dms(mode)) {
> > +   DPU_DEBUG("Seamless mode is being applied, skip
> > disable\n");
> > +   return;
> > +   }
> > +
> > dpu_enc = to_dpu_encoder_virt(drm_enc);
> > DPU_DEBUG_ENC(dpu_enc, "\n");
> > 
> > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> > b/drivers/gpu/drm/msm/msm_atomic.c
> > index 46536edb72ee..5cfb80345052 100644
> > --- a/drivers/gpu/drm/msm/msm_atomic.c
> > +++ b/drivers/gpu/drm/msm/msm_atomic.c
> > @@ -84,189 +84,6 @@ static void msm_atomic_wait_for_commit_done(
> > }
> >  }
> > 
> > -static void
> > -msm_disable_outputs(struct drm_device *dev, struct drm_atomic_state
> > *old_state)
> > -{
> > -   struct drm_connector *connector;
> > -   struct drm_connector_state *old_conn_state, *new_conn_state;
> > -   struct drm_

Re: [Freedreno] [DPU PATCH] msm/hdcp: Remove redundant stubs/CONFIG

[Sean Paul]

On Tue, Feb 27, 2018 at 11:24:31AM -0500, Sean Paul wrote:
> On Mon, Feb 26, 2018 at 03:01:14PM -0800, abhin...@codeaurora.org wrote:
> > The change itself is okay. 

So, Reviewed-by?

Sean

> > However I am planning to do a bigger cleanup here
> > ( removing the entire hdmi_hdcp.c ).
> > 
> > We dont use this file as we have our equivalent sde_hdcp_1x.c.
> 
> Yes, we definitely need to rationalize the 2 versions. 
> 
> There's going to be a fair amount of work to get the sde/dpu version working
> with the mainline property, backwards compatible with the hdmi version that
> exists, as well as figuring out what key injection is going look like. So 
> let's
> not disable the current thing before the next thing is ready :-)
> 
> > 
> > Was planning this cleanup as part of the HDCP 1x requirements.
> > 
> > If we want to push this as as separate change, I am okay with it but would
> > prefer to wait ...
> 
> git revert is cheap, we can always overturn it, no need to wait.
> 
> Sean
> 
> 
> 
> > 
> > Abhinav
> > On 2018-02-26 12:48, Sean Paul wrote:
> > > We already have CONFIG_DRM_MSM_HDMI_HDCP, with accompanying stubs in
> > > hdmi/hdmi.h.
> > > 
> > > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > > ---
> > >  drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c | 24 
> > >  1 file changed, 24 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
> > > b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
> > > index d24527468284..87e3acb3a259 100644
> > > --- a/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
> > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
> > > @@ -14,7 +14,6 @@
> > >  #include "hdmi.h"
> > >  #include 
> > > 
> > > -#ifdef CONFIG_DRM_MSM_HDCP
> > >  #define HDCP_REG_ENABLE 0x01
> > >  #define HDCP_REG_DISABLE 0x00
> > >  #define HDCP_PORT_ADDR 0x74
> > > @@ -1436,26 +1435,3 @@ void msm_hdmi_hdcp_destroy(struct hdmi *hdmi)
> > >   hdmi->hdcp_ctrl = NULL;
> > >   }
> > >  }
> > > -
> > > -#else
> > > -struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
> > > -{
> > > - return NULL;
> > > -}
> > > -
> > > -void msm_hdmi_hdcp_destroy(struct hdmi *hdmi)
> > > -{
> > > -}
> > > -
> > > -void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
> > > -{
> > > -}
> > > -
> > > -void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
> > > -{
> > > -}
> > > -
> > > -void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
> > > -{
> > > -}
> > > -#endif
> 
> -- 
> Sean Paul, Software Engineer, Google / Chromium OS

-- 
Sean Paul, Software Engineer, Google / Chromium OS
___
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Re: [Freedreno] [DPU PATCH] drm/msm: Remove dpu_edid_parser

[Sean Paul]

On Mon, Feb 26, 2018 at 02:23:40PM -0800, abhin...@codeaurora.org wrote:
> On 2018-02-26 07:36, Sean Paul wrote:
> > On Fri, Feb 23, 2018 at 05:48:48PM -0500, Rob Clark wrote:
> > > On Fri, Feb 23, 2018 at 5:31 PM,  <abhin...@codeaurora.org> wrote:
> > > > The bitmaps in drm_hdmi_info dont seem to be exposed to userspace.
> > > >
> > > > Our mode selection logic is in userspace at the moment which means its
> > > > better userspace knows which modes support what.
> > > >
> > > > If we decide to move mode validation entirely to the driver, we can use
> > > > these bitmaps to validate.
> > > >
> > > > But this is again a fundamental question then.
> > > >
> > > > Is there no use-case so far where userspace has had to know which modes
> > > > support which formats?
> > > >
> > > 
> > > I think historically a lot more of the focus upstream so far has been
> > > "desktop style" use cases, where RGB to the sink makes more sense.
> > > That doesn't mean there isn't a use-case for YUV.  I'm not sure, and
> > > haven't really given much thought into, how to expose this to
> > > userspace.  But I guess the same thing comes up w/ HDR and higher
> > > bit-depth RGB modes (like 10_10_10 formats, etc), and people are
> > > giving thought to those things these days.  I haven't been following
> > > the HDR work *that* closely, but I guess if you want to use HDR, you
> > > want to know what modes support it at the sink.
> > > 
> > > Either way, I think this is something which should be supported in drm
> > > core with a standardized UAPI, rather than by driver rolling it's own
> > > edid parsing and custom UAPI.
> > > 
> > > (I guess extending the modeinfo struct might be difficult, but perhaps
> > > a blob property w/ supplemental info might make sense??  Or maybe
> > > someone already has some other ideas?)
> > 
> > 
> > Yeah, in conjunction with hdr support, some type of modeinfo
> > supplementary data
> > seems appropriate.
> > 
> > We have some space left in modeinfo->flags, but that doesn't scale so
> > well.
> > Adding a property would be easiest since we could just expose the bitmap
> > to
> > userspace (more or less). We could also change "pad" in
> > drm_mode_get_connector
> > to flags and allow userspace to request enhanced mode info.
> > 
> > Sean
> > 
> Yes, we had been using flags so long as per our earlier discussion with Rob
> on this.
> It works well so far and thats pretty much what the EDID parser was doing.
> Thats why I mentioned
> that we can keep some part of the parser and get rid of most of it.

Given that we don't have a userspace implementation for this, and it doesn't
seem likely that we will have one soon, I'd recommend we keep this patch as-is
and expose drm_hdmi_info with a property when the need arises.

Sean

> 
> If we want to move over to another property, we will explore this option
> moving forward.
> 
> Abhinav
> > 
> > > 
> > > BR,
> > > -R
> > > 
> > > > Thanks
> > > >
> > > > Abhinav
> > > >
> > > >
> > > > On 2018-02-23 13:51, Sean Paul wrote:
> > > >>
> > > >> On Fri, Feb 23, 2018 at 01:29:03PM -0800, abhin...@codeaurora.org 
> > > >> wrote:
> > > >>>
> > > >>> I am OK with removing some parts of the parser but not entirely.
> > > >>>
> > > >>> Fundamentally, we went ahead with the parser for a couple of reasons:
> > > >>>
> > > >>> -> We would like to be able to associate the color format with the 
> > > >>> mode.
> > > >>> This helps us decide that if the same mode supports both RGB/YUV then
> > > >>> which
> > > >>> one we can pick.
> > > >>>
> > > >>> -> The upstream parser currently just adds it to the supported 
> > > >>> formats of
> > > >>> the sink info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; However the
> > > >>> link
> > > >>> between the mode and the format itself is unclear
> > > >>>
> > > >>> I would like to know if any of the above have been addressed so far
> > > >>> before
> > > >>> reverting this.
> > > >

Re: [Freedreno] [PATCH RESEND 08/10] drm/msm: Sprinkle pm_runtime calls around

[Sean Paul]

On Thu, Mar 08, 2018 at 04:14:38PM -0800, Jeykumar Sankaran wrote:
> On 2018-02-21 07:18, Sean Paul wrote:
> > Adding missing pm_runtime references where appropriate.
> > 
> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > ---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c |  3 +++
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  | 10 +-
> >  2 files changed, 12 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > index f1642d72469e..df6cbeb15cf5 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -3497,6 +3497,7 @@ static void dpu_crtc_disable(struct drm_crtc
> > *crtc)
> > /* disable clk & bw control until clk & bw properties are set */
> > cstate->bw_control = false;
> > cstate->bw_split_vote = false;
> > +   pm_runtime_put_sync(crtc->dev->dev);
> > 
> > mutex_unlock(_crtc->crtc_lock);
> >  }
> > @@ -3523,6 +3524,8 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
> > DPU_EVT32_VERBOSE(DRMID(crtc));
> > dpu_crtc = to_dpu_crtc(crtc);
> > 
> > +   pm_runtime_get_sync(crtc->dev->dev);
> > +
> > drm_for_each_encoder(encoder, crtc->dev) {
> > if (encoder->crtc != crtc)
> > continue;
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index fb4de59d8ed1..b919c9a6a463 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -114,6 +114,7 @@ static int _dpu_danger_signal_status(struct seq_file
> > *s,
> > priv = kms->dev->dev_private;
> > memset(, 0, sizeof(struct dpu_danger_safe_status));
> > 
> > +   pm_runtime_get_sync(kms->dev->dev);
> > dpu_power_resource_enable(>phandle, kms->core_client, true);
> > if (danger_status) {
> > seq_puts(s, "\nDanger signal status:\n");
> > @@ -127,6 +128,7 @@ static int _dpu_danger_signal_status(struct seq_file
> > *s,
> > );
> > }
> > dpu_power_resource_enable(>phandle, kms->core_client, false);
> > +   pm_runtime_put_sync(kms->dev->dev);
> > 
> > seq_printf(s, "MDP :  0x%x\n", status.mdp);
> > 
> > @@ -346,12 +348,14 @@ static void _dpu_debugfs_destroy(struct dpu_kms
> > *dpu_kms)
> > 
> >  static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc
> > *crtc)
> >  {
> > +   pm_runtime_get_sync(crtc->dev->dev);
> > return dpu_crtc_vblank(crtc, true);
> >  }
> > 
> >  static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc
> > *crtc)
> >  {
> > dpu_crtc_vblank(crtc, false);
> > +   pm_runtime_put_sync(crtc->dev->dev);
> >  }
> > 
> >  static void dpu_kms_wait_for_frame_transfer_complete(struct msm_kms
> > *kms,
> > @@ -413,6 +417,7 @@ static void dpu_kms_prepare_commit(struct msm_kms
> > *kms,
> > if (!dev || !dev->dev_private)
> > return;
> > priv = dev->dev_private;
> > +   pm_runtime_get_sync(dev->dev);
> 
> CONFIG_DEBUG_FS is not enabled yet. Do we need this change here? If yes, we
> need
> to add pm_runtime calls in other files as well e.g:
> sde_plane_danger_read/write in dpu_plane.c.

Hmm, yeah good catch. Aside from the question of debugfs (which I think we
should probably do a deep review of what's being exposed), perhaps we should
move the pm_runtime_(get|put)_sync calls in dpu_power_resource_enable, then we
don't need to worry about adding the calls everywhere.

Thoughts?

Sean


> 
> > dpu_power_resource_enable(>phandle, dpu_kms->core_client, true);
> > 
> > list_for_each_entry(encoder, >mode_config.encoder_list, head)
> > @@ -471,6 +476,7 @@ static void dpu_kms_complete_commit(struct msm_kms
> > *kms,
> > }
> > 
> > dpu_power_resource_enable(>phandle, dpu_kms->core_client,
> > false);
> > +   pm_runtime_put_sync(dpu_kms->dev->dev);
> > 
> > DPU_EVT32_VERBOSE(DPU_EVTLOG_FUNC_EXIT);
> >  }
> > @@ -1896,7 +1902,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
> > dpu_kms->core_client = NULL;
> > goto error;
> > }
> > -
> > +   pm_runtime_get_sync(dev->dev);
> > rc = dpu_power_re

Re: [Freedreno] [DPU PATCH v3 2/2] drm/msm: remove partial update support

[Sean Paul]

On Thu, Mar 01, 2018 at 04:52:35PM -0800, Jeykumar Sankaran wrote:
> Implementation of partial update in DPU DRM is heavily
> dependent on custom properties and dsi hooks. Removing the
> support for now. We may need to revisit the support in the
> future.
> 
> changes since v1:
>   - get away with unwanted parameter validation
>   - code style fixes
>   - remove header file definitions for partial update
> 
> changes since v2:
>   - remove compilation flag for DPU_AD4.
> 
> Signed-off-by: Jeykumar Sankaran 

Thanks for the revised patches. I've applied them to both for-next and
mtp-testing staging branches. I had some trouble applying this patch cleanly, I
resolved the conflicts for this one, but  probably a good idea to update your
local branch.

Sean

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 139 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h |   7 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 544 
> +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  18 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 277 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |   8 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c |  42 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |  13 -
>  drivers/gpu/drm/msm/msm_drv.h |  56 ---
>  9 files changed, 87 insertions(+), 1017 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> index 57b8627..c5e6c53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> @@ -424,8 +424,7 @@ int dpu_connector_pre_kickoff(struct drm_connector 
> *connector)
>  {
>   struct dpu_connector *c_conn;
>   struct dpu_connector_state *c_state;
> - struct msm_display_kickoff_params params;
> - int idx, rc;
> + int idx, rc = 0;
>  
>   if (!connector) {
>   DPU_ERROR("invalid argument\n");
> @@ -462,15 +461,8 @@ int dpu_connector_pre_kickoff(struct drm_connector 
> *connector)
>   }
>   }
>  
> - if (!c_conn->ops.pre_kickoff)
> - return 0;
> -
> - params.rois = _state->rois;
> -
>   DPU_EVT32_VERBOSE(connector->base.id);
>  
> - rc = c_conn->ops.pre_kickoff(connector, c_conn->display, );
> -
>   return rc;
>  }
>  
> @@ -645,122 +637,6 @@ static void dpu_connector_atomic_reset(struct 
> drm_connector *connector)
>   return _state->base;
>  }
>  
> -static int _dpu_connector_roi_v1_check_roi(
> - struct dpu_connector *c_conn,
> - struct drm_clip_rect *roi_conn,
> - const struct msm_roi_caps *caps)
> -{
> - const struct msm_roi_alignment *align = >align;
> - int w = roi_conn->x2 - roi_conn->x1;
> - int h = roi_conn->y2 - roi_conn->y1;
> -
> - if (w <= 0 || h <= 0) {
> - DPU_ERROR_CONN(c_conn, "invalid conn roi w %d h %d\n", w, h);
> - return -EINVAL;
> - }
> -
> - if (w < align->min_width || w % align->width_pix_align) {
> - DPU_ERROR_CONN(c_conn,
> - "invalid conn roi width %d min %d align %d\n",
> - w, align->min_width, align->width_pix_align);
> - return -EINVAL;
> - }
> -
> - if (h < align->min_height || h % align->height_pix_align) {
> - DPU_ERROR_CONN(c_conn,
> - "invalid conn roi height %d min %d align %d\n",
> - h, align->min_height, align->height_pix_align);
> - return -EINVAL;
> - }
> -
> - if (roi_conn->x1 % align->xstart_pix_align) {
> - DPU_ERROR_CONN(c_conn, "invalid conn roi x1 %d align %d\n",
> - roi_conn->x1, align->xstart_pix_align);
> - return -EINVAL;
> - }
> -
> - if (roi_conn->y1 % align->ystart_pix_align) {
> - DPU_ERROR_CONN(c_conn, "invalid conn roi y1 %d align %d\n",
> - roi_conn->y1, align->ystart_pix_align);
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -static int _dpu_connector_set_roi_v1(
> - struct dpu_connector *c_conn,
> - struct dpu_connector_state *c_state,
> - void *usr_ptr)
> -{
> - struct dpu_drm_roi_v1 roi_v1;
> - struct msm_display_info display_info;
> - struct msm_roi_caps *caps;
> - int i, rc;
> -
> - if (!c_conn || !c_state) {
> - DPU_ERROR("invalid args\n");
> - return -EINVAL;
> - }
> -
> - rc = dpu_connector_get_info(_conn->base, _info);
> - if (rc) {
> - DPU_ERROR_CONN(c_conn, "display get info error: %d\n", rc);
> - return rc;
> - }
> -
> - caps = _info.roi_caps;
> - if (!caps->enabled) {
> - DPU_ERROR_CONN(c_conn, "display roi capability is disabled\n");
> - return 

Re: [Freedreno] [DPU PATCH 06/11] drm/msm: Remove msm_commit/kthread, use atomic helper commit

[Sean Paul]

On Thu, Mar 01, 2018 at 07:37:10PM -0500, Rob Clark wrote:
> On Thu, Mar 1, 2018 at 3:37 PM,  <jsa...@codeaurora.org> wrote:
> > On 2018-03-01 07:27, Sean Paul wrote:
> >>
> >> On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org wrote:
> >>>
> >>> On 2018-02-28 11:19, Sean Paul wrote:
> >>> > Moving further towards switching fully to the the atomic helpers, this
> >>> > patch removes the hand-rolled kthread nonblock commit code and uses
> >>
> >> the
> >>>
> >>> > atomic helpers commit_work model.
> >>> >
> >>> > There's still a lot of copypasta here, but it's still needed to
> >>> > facilitate the swap_state and prepare_fence private functions. These
> >>> > will be sorted out in a follow-on patch.
> >>> >
> >>> > Change-Id: I9fcba27824ba63d3fab96cb2bc194bfa6f3475b7
> >>> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> >>> > ---
> >>> >  drivers/gpu/drm/msm/msm_atomic.c | 199
> >>
> >> ++-
> >>>
> >>> >  drivers/gpu/drm/msm/msm_drv.c|   1 -
> >>> >  drivers/gpu/drm/msm/msm_drv.h|   4 -
> >>> >  3 files changed, 35 insertions(+), 169 deletions(-)
> >>> >
> >>> > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> >>> > b/drivers/gpu/drm/msm/msm_atomic.c
> >>> > index 3a18bd3dc215..7e54eb65d096 100644
> >>> > --- a/drivers/gpu/drm/msm/msm_atomic.c
> >>> > +++ b/drivers/gpu/drm/msm/msm_atomic.c
> >>> > @@ -21,51 +21,6 @@
> >>> >  #include "msm_gem.h"
> >>> >  #include "msm_fence.h"
> >>> >
> >>> > -struct msm_commit {
> >>> > - struct drm_device *dev;
> >>> > - struct drm_atomic_state *state;
> >>> > - uint32_t crtc_mask;
> >>> > - bool nonblock;
> >>> > - struct kthread_work commit_work;
> >>> > -};
> >>> > -
> >>> > -/* block until specified crtcs are no longer pending update, and
> >>> > - * atomically mark them as pending update
> >>> > - */
> >>> > -static int start_atomic(struct msm_drm_private *priv, uint32_t
> >>> > crtc_mask)
> >>> > -{
> >>> > - int ret;
> >>> > -
> >>> > - spin_lock(>pending_crtcs_event.lock);
> >>> > - ret = wait_event_interruptible_locked(priv->pending_crtcs_event,
> >>> > - !(priv->pending_crtcs & crtc_mask));
> >>> > - if (ret == 0) {
> >>> > - DBG("start: %08x", crtc_mask);
> >>> > - priv->pending_crtcs |= crtc_mask;
> >>> > - }
> >>> > - spin_unlock(>pending_crtcs_event.lock);
> >>> > -
> >>> > - return ret;
> >>> > -}
> >>> > -
> >>> > -/* clear specified crtcs (no longer pending update)
> >>> > - */
> >>> > -static void end_atomic(struct msm_drm_private *priv, uint32_t
> >>> > crtc_mask)
> >>> > -{
> >>> > - spin_lock(>pending_crtcs_event.lock);
> >>> > - DBG("end: %08x", crtc_mask);
> >>> > - priv->pending_crtcs &= ~crtc_mask;
> >>> > - wake_up_all_locked(>pending_crtcs_event);
> >>> > - spin_unlock(>pending_crtcs_event.lock);
> >>> > -}
> >>> > -
> >>> > -static void commit_destroy(struct msm_commit *c)
> >>> > -{
> >>> > - end_atomic(c->dev->dev_private, c->crtc_mask);
> >>> > - if (c->nonblock)
> >>> > - kfree(c);
> >>> > -}
> >>> > -
> >>> >  static void msm_atomic_wait_for_commit_done(
> >>> >   struct drm_device *dev,
> >>> >   struct drm_atomic_state *old_state)
> >>> > @@ -118,6 +73,10 @@ static void msm_atomic_commit_tail(struct
> >>> > drm_atomic_state *state)
> >>> >
> >>> >   msm_atomic_wait_for_commit_done(dev, state);
> >>> >
> >>> > + drm_atomic_helper_commit_hw_done(state);
> >>> > +
> >>> > + drm_atomic_helper_

Re: [Freedreno] [[RFC]DPU PATCH] drm/msm/dsi: Use one connector for dual DSI mode

[Sean Paul]

atic int dsi_mgr_connector_get_modes(struct 
> drm_connector *connector)
>   if (!panel)
>   return 0;
>  
> - /* Since we have 2 connectors, but only 1 drm_panel in dual DSI mode,
> -  * panel should not attach to any connector.
> -  * Only temporarily attach panel to the current connector here,
> -  * to let panel set mode to this connector.
> + /*
> +  * In dual DSI mode, we have one connector that can be
> +  * attached to the drm_panel.
>*/
>   drm_panel_attach(panel, connector);
>   num = drm_panel_get_modes(panel);
> - drm_panel_detach(panel);
>   if (!num)
>   return 0;
>  
> - if (IS_DUAL_DSI()) {
> - /* report half resolution to user */
> - dsi_dual_connector_fix_modes(connector);
> - ret = dsi_dual_connector_tile_init(connector, id);
> - if (ret)
> - return ret;
> - ret = drm_mode_connector_set_tile_property(connector);
> - if (ret) {
> - pr_err("%s: set tile property failed, %d\n",
> - __func__, ret);
> - return ret;
> - }
> - }
> -
>   return num;
>  }
>  
> @@ -689,6 +612,23 @@ struct drm_connector *msm_dsi_manager_connector_init(u8 
> id)
>   return connector;
>  }
>  
> +bool msm_dsi_manager_validate_current_config(u8 id)
> +{
> + bool is_dual_dsi = IS_DUAL_DSI();
> +
> + /*
> +  * For dual DSI, we only have one drm panel. For this
> +  * use case, we register only one bridge/connector.
> +  * Skip bridge/connector initialisation if it is
> +  * DSI 1 in case of dual DSI.

I think the other dual-dsi implementations take the master/slave cues from
device tree as opposed to hard-coding one or the other (I know of at least one
case where DSI_1 was connected to the panel's first channel, whereas DSI_0 was
connected to the second channel.

Sean

> +  */
> + if (is_dual_dsi && (DSI_1 == id)) {
> + DBG("Skip DSI_1 bridge registration for dual DSI.\n");
> + return false;
> + }
> + return true;
> +}
> +
>  /* initialize bridge */
>  struct drm_bridge *msm_dsi_manager_bridge_init(u8 id)
>  {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [DPU PATCH v2 1/2] drm/msm/dsi-staging: remove support for partial update

[Sean Paul]

On Tue, Feb 27, 2018 at 06:55:10PM -0800, Jeykumar Sankaran wrote:
> Remove support partial update and related changes from dsi-staging
> since the DPU dependencies are getting cleaned up.
> 

Can you please add a "Changes in v2:" section to the commit message 
summarizing what you've changed since the last version? This is super
helpful for reviewers.

> Change-Id: I02462f520cdf99c8445b18e60212ca46155f9710

I forgot this during my last patchset too, but please try to strip the Change-Id
tag.

With the commit message changes,

Reviewed-by: Sean Paul <seanp...@chromium.org>


> Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 104 
> +-
>  drivers/gpu/drm/msm/dsi-staging/dsi_display.h |   5 +-
>  drivers/gpu/drm/msm/dsi-staging/dsi_drm.c |  26 +--
>  drivers/gpu/drm/msm/dsi-staging/dsi_drm.h |   4 +-
>  drivers/gpu/drm/msm/dsi-staging/dsi_panel.c   |  85 -
>  drivers/gpu/drm/msm/dsi-staging/dsi_panel.h   |   2 -
>  6 files changed, 7 insertions(+), 219 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c 
> b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
> index 72055dc..31b7d7e 100644
> --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
> +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
> @@ -3414,9 +3414,6 @@ int dsi_display_get_info(struct msm_display_info *info, 
> void *disp)
>   break;
>   }
>  
> - memcpy(>roi_caps, >panel->roi_caps,
> - sizeof(info->roi_caps));
> -
>  error:
>   mutex_unlock(>display_lock);
>   return rc;
> @@ -3941,104 +3938,7 @@ int dsi_display_prepare(struct dsi_display *display)
>   return rc;
>  }
>  
> -static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
> - const struct dsi_display_ctrl *ctrl,
> - const struct msm_roi_list *req_rois,
> - struct dsi_rect *out_roi)
> -{
> - const struct dsi_rect *bounds = >ctrl->mode_bounds;
> - struct dsi_rect req_roi = { 0 };
> - int rc = 0;
> -
> - if (req_rois->num_rects > display->panel->roi_caps.num_roi) {
> - pr_err("request for %d rois greater than max %d\n",
> - req_rois->num_rects,
> - display->panel->roi_caps.num_roi);
> - rc = -EINVAL;
> - goto exit;
> - }
> -
> - /**
> -  * if no rois, user wants to reset back to full resolution
> -  * note: h_active is already divided by ctrl_count
> -  */
> - if (!req_rois->num_rects) {
> - *out_roi = *bounds;
> - goto exit;
> - }
> -
> - /* intersect with the bounds */
> - req_roi.x = req_rois->roi[0].x1;
> - req_roi.y = req_rois->roi[0].y1;
> - req_roi.w = req_rois->roi[0].x2 - req_rois->roi[0].x1;
> - req_roi.h = req_rois->roi[0].y2 - req_rois->roi[0].y1;
> - dsi_rect_intersect(_roi, bounds, out_roi);
> -
> -exit:
> - /* adjust the ctrl origin to be top left within the ctrl */
> - out_roi->x = out_roi->x - bounds->x;
> -
> - pr_debug("ctrl%d:%d: req (%d,%d,%d,%d) bnd (%d,%d,%d,%d) out 
> (%d,%d,%d,%d)\n",
> - ctrl->dsi_ctrl_idx, ctrl->ctrl->cell_index,
> - req_roi.x, req_roi.y, req_roi.w, req_roi.h,
> - bounds->x, bounds->y, bounds->w, bounds->h,
> - out_roi->x, out_roi->y, out_roi->w, out_roi->h);
> -
> - return rc;
> -}
> -
> -static int dsi_display_set_roi(struct dsi_display *display,
> - struct msm_roi_list *rois)
> -{
> - int rc = 0;
> - int i;
> -
> - if (!display || !rois || !display->panel)
> - return -EINVAL;
> -
> - if (!display->panel->roi_caps.enabled)
> - return 0;
> -
> - for (i = 0; i < display->ctrl_count; i++) {
> - struct dsi_display_ctrl *ctrl = >ctrl[i];
> - struct dsi_rect ctrl_roi;
> - bool changed = false;
> -
> - rc = dsi_display_calc_ctrl_roi(display, ctrl, rois, _roi);
> - if (rc) {
> - pr_err("dsi_display_calc_ctrl_roi failed rc %d\n", rc);
> - return rc;
> - }
> -
> - rc = dsi_ctrl_set_roi(ctrl->ctrl, _roi, );
> - if (rc) {
> - pr_err("dsi_ctrl_set_roi failed rc %d\n", rc);
> - retur

Re: [Freedreno] [DPU PATCH v2 2/2] drm/msm: remove partial update support

[Sean Paul]

p.x2  && clip.y2) {
> - result->x = clip.x1;
> - result->y = clip.y1;
> - result->w = clip.x2 - clip.x1;
> - result->h = clip.y2 - clip.y1;
> - }
> -}
> -
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 834dcc0..9e9c9d2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -3243,7 +3243,6 @@ static int dpu_plane_sspp_atomic_update(struct 
> drm_plane *plane,
>   struct drm_crtc *crtc;
>   struct drm_framebuffer *fb;
>   struct dpu_rect src, dst;
> - const struct dpu_rect *crtc_roi;
>   bool q16_data = true;
>   int idx;
>  
> @@ -3357,11 +3356,6 @@ static int dpu_plane_sspp_atomic_update(struct 
> drm_plane *plane,
>   _dpu_plane_sspp_atomic_check_mode_changed(pdpu, state,
>   old_state);
>  
> - /* re-program the output rects always in the case of partial update */
> - dpu_crtc_get_crtc_roi(crtc->state, _roi);
> - if (!dpu_kms_rect_is_null(crtc_roi))
> - pstate->dirty |= DPU_PLANE_DIRTY_RECTS;
> -
>   if (pstate->dirty & DPU_PLANE_DIRTY_RECTS)
>   memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg));
>  
> @@ -3399,13 +3393,6 @@ static int dpu_plane_sspp_atomic_update(struct 
> drm_plane *plane,
>   src.y &= ~0x1;
>   }
>  
> - /*
> -  * adjust layer mixer position of the sspp in the presence
> -  * of a partial update to the active lm origin
> -  */
> - dst.x -= crtc_roi->x;
> - dst.y -= crtc_roi->y;
> -
>   pdpu->pipe_cfg.src_rect = src;
>   pdpu->pipe_cfg.dst_rect = dst;
>  
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d8e090f..8574f30 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -144,7 +144,6 @@ enum msm_mdp_crtc_property {
>   CRTC_PROP_DRAM_IB,
>   CRTC_PROP_ROT_PREFILL_BW,
>   CRTC_PROP_ROT_CLK,
> - CRTC_PROP_ROI_V1,
>   CRTC_PROP_IDLE_TIMEOUT,
>   CRTC_PROP_DEST_SCALER,
>  
> @@ -168,7 +167,6 @@ enum msm_mdp_conn_property {
>   CONNECTOR_PROP_DST_Y,
>   CONNECTOR_PROP_DST_W,
>   CONNECTOR_PROP_DST_H,
> - CONNECTOR_PROP_ROI_V1,
>   CONNECTOR_PROP_BL_SCALE,
>   CONNECTOR_PROP_AD_BL_SCALE,
>  
> @@ -228,38 +226,6 @@ enum msm_event_wait {
>  };
>  
>  /**
> - * struct msm_roi_alignment - region of interest alignment restrictions
> - * @xstart_pix_align: left x offset alignment restriction
> - * @width_pix_align: width alignment restriction
> - * @ystart_pix_align: top y offset alignment restriction
> - * @height_pix_align: height alignment restriction
> - * @min_width: minimum width restriction
> - * @min_height: minimum height restriction
> - */
> -struct msm_roi_alignment {
> - uint32_t xstart_pix_align;
> - uint32_t width_pix_align;
> - uint32_t ystart_pix_align;
> - uint32_t height_pix_align;
> - uint32_t min_width;
> - uint32_t min_height;
> -};
> -
> -/**
> - * struct msm_roi_caps - display's region of interest capabilities
> - * @enabled: true if some region of interest is supported
> - * @merge_rois: merge rois before sending to display
> - * @num_roi: maximum number of rois supported
> - * @align: roi alignment restrictions
> - */
> -struct msm_roi_caps {
> - bool enabled;
> - bool merge_rois;
> - uint32_t num_roi;
> - struct msm_roi_alignment align;
> -};
> -
> -/**
>   * struct msm_display_dsc_info - defines dsc configuration
>   * @version: DSC version.
>   * @scr_rev: DSC revision.
> @@ -427,7 +393,6 @@ struct msm_mode_info {
>   * @is_primary: Set to true if display is primary display
>   * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
>   *used instead of panel TE in cmd mode panels
> - * @roi_caps:   Region of interest capability info
>   */
>  struct msm_display_info {
>   int intf_type;
> @@ -446,27 +411,6 @@ struct msm_display_info {
>  
>   bool is_primary;
>   bool is_te_using_watchdog_timer;
> - struct msm_roi_caps roi_caps;
> -};
> -
> -#define MSM_MAX_ROI  4
> -
> -/**
> - * struct msm_roi_list - list of regions of interest for a drm object
> - * @num_rects: number of valid rectangles in the roi array
> - * @roi: list of roi rectangles
> - */
> -struct msm_roi_list {
> - uint32_t num_rects;
> - struct drm_clip_rect roi[MSM_MAX_ROI];
> -};
> -
> -/**
> - * struct - msm_display_kickoff_params - info for display features at kickoff
> - * @rois: Regions of interest structure for mapping CRTC to Connector output
> - */
> -struct msm_display_kickoff_params {
> - struct msm_roi_list *rois;
>  };
>  
>  /**
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [DPU PATCH 06/11] drm/msm: Remove msm_commit/kthread, use atomic helper commit

[Sean Paul]

On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org wrote:
> On 2018-02-28 11:19, Sean Paul wrote:
> > Moving further towards switching fully to the the atomic helpers, this
> > patch removes the hand-rolled kthread nonblock commit code and uses the
> > atomic helpers commit_work model.
> > 
> > There's still a lot of copypasta here, but it's still needed to
> > facilitate the swap_state and prepare_fence private functions. These
> > will be sorted out in a follow-on patch.
> > 
> > Change-Id: I9fcba27824ba63d3fab96cb2bc194bfa6f3475b7
> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > ---
> >  drivers/gpu/drm/msm/msm_atomic.c | 199 ++-
> >  drivers/gpu/drm/msm/msm_drv.c|   1 -
> >  drivers/gpu/drm/msm/msm_drv.h|   4 -
> >  3 files changed, 35 insertions(+), 169 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> > b/drivers/gpu/drm/msm/msm_atomic.c
> > index 3a18bd3dc215..7e54eb65d096 100644
> > --- a/drivers/gpu/drm/msm/msm_atomic.c
> > +++ b/drivers/gpu/drm/msm/msm_atomic.c
> > @@ -21,51 +21,6 @@
> >  #include "msm_gem.h"
> >  #include "msm_fence.h"
> > 
> > -struct msm_commit {
> > -   struct drm_device *dev;
> > -   struct drm_atomic_state *state;
> > -   uint32_t crtc_mask;
> > -   bool nonblock;
> > -   struct kthread_work commit_work;
> > -};
> > -
> > -/* block until specified crtcs are no longer pending update, and
> > - * atomically mark them as pending update
> > - */
> > -static int start_atomic(struct msm_drm_private *priv, uint32_t
> > crtc_mask)
> > -{
> > -   int ret;
> > -
> > -   spin_lock(>pending_crtcs_event.lock);
> > -   ret = wait_event_interruptible_locked(priv->pending_crtcs_event,
> > -   !(priv->pending_crtcs & crtc_mask));
> > -   if (ret == 0) {
> > -   DBG("start: %08x", crtc_mask);
> > -   priv->pending_crtcs |= crtc_mask;
> > -   }
> > -   spin_unlock(>pending_crtcs_event.lock);
> > -
> > -   return ret;
> > -}
> > -
> > -/* clear specified crtcs (no longer pending update)
> > - */
> > -static void end_atomic(struct msm_drm_private *priv, uint32_t
> > crtc_mask)
> > -{
> > -   spin_lock(>pending_crtcs_event.lock);
> > -   DBG("end: %08x", crtc_mask);
> > -   priv->pending_crtcs &= ~crtc_mask;
> > -   wake_up_all_locked(>pending_crtcs_event);
> > -   spin_unlock(>pending_crtcs_event.lock);
> > -}
> > -
> > -static void commit_destroy(struct msm_commit *c)
> > -{
> > -   end_atomic(c->dev->dev_private, c->crtc_mask);
> > -   if (c->nonblock)
> > -   kfree(c);
> > -}
> > -
> >  static void msm_atomic_wait_for_commit_done(
> > struct drm_device *dev,
> > struct drm_atomic_state *old_state)
> > @@ -118,6 +73,10 @@ static void msm_atomic_commit_tail(struct
> > drm_atomic_state *state)
> > 
> > msm_atomic_wait_for_commit_done(dev, state);
> > 
> > +   drm_atomic_helper_commit_hw_done(state);
> > +
> > +   drm_atomic_helper_wait_for_vblanks(dev, state);
> > +
> > drm_atomic_helper_cleanup_planes(dev, state);
> > 
> > kms->funcs->complete_commit(kms, state);
> > @@ -126,109 +85,25 @@ static void msm_atomic_commit_tail(struct
> > drm_atomic_state *state)
> >  /* The (potentially) asynchronous part of the commit.  At this point
> >   * nothing can fail short of armageddon.
> >   */
> > -static void complete_commit(struct msm_commit *c)
> > +static void commit_tail(struct drm_atomic_state *state)
> >  {
> > -   struct drm_atomic_state *state = c->state;
> > -   struct drm_device *dev = state->dev;
> > +   drm_atomic_helper_wait_for_fences(state->dev, state, false);
> > 
> > -   drm_atomic_helper_wait_for_fences(dev, state, false);
> > +   drm_atomic_helper_wait_for_dependencies(state);
> > 
> > msm_atomic_commit_tail(state);
> > 
> > -   drm_atomic_state_put(state);
> > -}
> > -
> > -static void _msm_drm_commit_work_cb(struct kthread_work *work)
> > -{
> > -   struct msm_commit *commit =  NULL;
> > -
> > -   if (!work) {
> > -   DRM_ERROR("%s: Invalid commit work data!\n", __func__);
> > -   return;
> > -   }
> > -
> > -   commit = container_of(work, struct msm_commit, commit_work);
> > -
> > -