[Freedreno] [PATCH v3 2/3] drm/msm/dpu: Integrate interconnect API in MDSS
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one of the interconnect consumers which uses the
interconnect APIs to get the path between endpoints and
set its bandwidth/latency/QoS requirements for the given
interconnected path.
Changes in v2:
- Remove error log and unnecessary check (Jordan Crouse)
Changes in v3:
- Code clean involving variable name change, removal
of extra paranthesis and variables (Matthias Kaehlcke)
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49
1 file changed, 44 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 38576f8b90b6..1387a6b1b39e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -4,10 +4,12 @@
*/
#include "dpu_kms.h"
+#include
#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
-#define HW_INTR_STATUS 0x0010
+#define HW_INTR_STATUS 0x0010
+#define MAX_BW 680
struct dpu_mdss {
struct msm_mdss base;
@@ -16,8 +18,30 @@ struct dpu_mdss {
u32 hwversion;
struct dss_module_power mp;
struct dpu_irq_controller irq_controller;
+ struct icc_path *path[2];
+ u32 num_paths;
};
+static int dpu_mdss_parse_data_bus_icc_path(
+ struct drm_device *dev, struct dpu_mdss *dpu_mdss)
+{
+ struct icc_path *path0 = of_icc_get(dev->dev, "port0");
+ struct icc_path *path1 = of_icc_get(dev->dev, "port1");
+
+ if (IS_ERR(path0))
+ return PTR_ERR(path0);
+
+ dpu_mdss->path[0] = path0;
+ dpu_mdss->num_paths = 1;
+
+ if (!IS_ERR(path1)) {
+ dpu_mdss->path[1] = path1;
+ dpu_mdss->num_paths++;
+ }
+
+ return 0;
+}
+
static irqreturn_t dpu_mdss_irq(int irq, void *arg)
{
struct dpu_mdss *dpu_mdss = arg;
@@ -127,7 +151,11 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
+ u64 avg_bw = dpu_mdss->num_paths ? MAX_BW/dpu_mdss->num_paths : 0;
+
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set(dpu_mdss->path[i], avg_bw, MAX_BW);
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
if (ret)
@@ -140,12 +168,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
if (ret)
DPU_ERROR("clock disable failed, ret:%d\n", ret);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set(dpu_mdss->path[i], 0, 0);
+
return ret;
}
@@ -155,6 +186,7 @@ static void dpu_mdss_destroy(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
struct dss_module_power *mp = _mdss->mp;
+ int i;
pm_runtime_disable(dev->dev);
_dpu_mdss_irq_domain_fini(dpu_mdss);
@@ -162,6 +194,9 @@ static void dpu_mdss_destroy(struct drm_device *dev)
msm_dss_put_clk(mp->clk_config, mp->num_clk);
devm_kfree(>dev, mp->clk_config);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_put(dpu_mdss->path[i]);
+
if (dpu_mdss->mmio)
devm_iounmap(>dev, dpu_mdss->mmio);
dpu_mdss->mmio = NULL;
@@ -200,6 +235,10 @@ int dpu_mdss_init(struct drm_device *dev)
}
dpu_mdss->mmio_len = resource_size(res);
+ ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
+ if (ret)
+ return ret;
+
mp = _mdss->mp;
ret = msm_dss_parse_clock(pdev, mp);
if (ret) {
@@ -221,14 +260,14 @@ int dpu_mdss_init(struct drm_device *dev)
goto irq_error;
}
+ priv->mdss = _mdss->base;
+
pm_runtime_enable(dev->dev);
pm_runtime_get_sync(dev->dev);
dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
pm_runtime_put_sync(dev->dev);
- priv->mdss = _mdss->base;
-
return ret;
irq_error:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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[Freedreno] [PATCH v3 0/3] Use interconnect API in MDSS on SDM845
The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the appropriate power/performance profile. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth requirements for the given interconnected path. Subsequently, there is a clean up patch to remove all the references of the DPU custom bus scaling. There is corresponding DT patch with the source and destination ports defined for display driver which will be sent separately. Changes in v2: - Remove error log and unnecessary check (Jordan Crouse) - Fixed build error due to partial clean up Changes in v3: - Remove common property definitions (Rob Herring) - Code clean up involving variable name change, removal of extra paranthesis and variables (Matthias Kaehlcke) - Condense multiple lines into a single line (Sean Paul) Sravanthi Kollukuduru (3): drm/msm/dpu: clean up references of DPU custom bus scaling drm/msm/dpu: Integrate interconnect API in MDSS dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845 .../devicetree/bindings/display/msm/dpu.txt| 9 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 174 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 22 +-- 8 files changed, 142 insertions(+), 244 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v3 1/3] drm/msm/dpu: clean up references of DPU custom bus scaling
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single line (Sean Paul)
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c| 174 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 22 +--
6 files changed, 89 insertions(+), 239 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 22e84b3d7f98..c75536ece3ed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -84,7 +84,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
struct dpu_core_perf_params *perf)
{
struct dpu_crtc_state *dpu_cstate;
- int i;
if (!kms || !kms->catalog || !crtc || !state || !perf) {
DPU_ERROR("invalid parameters\n");
@@ -95,35 +94,24 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
memset(perf, 0, sizeof(struct dpu_core_perf_params));
if (!dpu_cstate->bw_control) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
+ perf->bw_ctl = kms->catalog->perf.max_bw_high *
1000ULL;
- perf->max_per_pipe_ib[i] = perf->bw_ctl[i];
- }
+ perf->max_per_pipe_ib = perf->bw_ctl;
perf->core_clk_rate = kms->perf.max_core_clk_rate;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = 0;
- perf->max_per_pipe_ib[i] = 0;
- }
+ perf->bw_ctl = 0;
+ perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->perf.fix_core_ab_vote;
- perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote;
- }
+ perf->bw_ctl = kms->perf.fix_core_ab_vote;
+ perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
}
DPU_DEBUG(
- "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu
llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
+ "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
crtc->base.id, perf->core_clk_rate,
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]);
+ perf->max_per_pipe_ib, perf->bw_ctl);
}
int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
@@ -136,7 +124,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
struct dpu_crtc_state *dpu_cstate;
struct drm_crtc *tmp_crtc;
struct dpu_kms *kms;
- int i;
if (!crtc || !state) {
DPU_ERROR("invalid crtc\n");
@@ -158,31 +145,25 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
/* obtain new values */
_dpu_core_perf_calc_crtc(kms, crtc, state, _cstate->new_perf);
- for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
- i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i];
- curr_client_type = dpu_crtc_get_client_type(crtc);
+ bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
+ curr_client_type = dpu_crtc_get_client_type(crtc);
- drm_for_each_crtc(tmp_crtc, crtc->dev) {
- if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
- (dpu_crtc_get_client_type(tmp_crtc) ==
- curr_client_type)
[Freedreno] [PATCH v2 3/3] dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845
Add interconnect properties such as interconnect provider specifier , the edge source and destination ports which are required by the interconnect API to configure interconnect path for MDSS. Changes in v2: -none Signed-off-by: Sravanthi Kollukuduru --- Documentation/devicetree/bindings/display/msm/dpu.txt | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index ad2e8830324e..abd4d99b5030 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -28,6 +28,11 @@ Required properties: - #address-cells: number of address cells for the MDSS children. Should be 1. - #size-cells: Should be 1. - ranges: parent bus address space is the same as the child bus address space. +- interconnects : pairs of phandles and interconnect provider specifier to + denote the edge source and destination ports of the interconnect path. +- interconnect-names : list of interconnect path name strings sorted in the + same order as the interconnects property. Consumers drivers will use + interconnect-names to match interconnect paths with interconnect specifiers. Optional properties: - assigned-clocks: list of clock specifiers for clocks needing rate assignment @@ -86,6 +91,9 @@ Example: interrupt-controller; #interrupt-cells = <1>; + interconnects = < 38 512>; + interconnect-names = "port0"; + iommus = <_iommu 0>; #address-cells = <2>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 1/3] drm/msm/dpu: clean up references of DPU custom bus scaling
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c| 157 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 --
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 21 +--
6 files changed, 86 insertions(+), 224 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 41c5191f9056..4ee6f0dd14f7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -90,7 +90,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
struct dpu_core_perf_params *perf)
{
struct dpu_crtc_state *dpu_cstate;
- int i;
if (!kms || !kms->catalog || !crtc || !state || !perf) {
DPU_ERROR("invalid parameters\n");
@@ -101,35 +100,24 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
memset(perf, 0, sizeof(struct dpu_core_perf_params));
if (!dpu_cstate->bw_control) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
+ perf->bw_ctl = kms->catalog->perf.max_bw_high *
1000ULL;
- perf->max_per_pipe_ib[i] = perf->bw_ctl[i];
- }
+ perf->max_per_pipe_ib = perf->bw_ctl;
perf->core_clk_rate = kms->perf.max_core_clk_rate;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = 0;
- perf->max_per_pipe_ib[i] = 0;
- }
+ perf->bw_ctl = 0;
+ perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->perf.fix_core_ab_vote;
- perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote;
- }
+ perf->bw_ctl = kms->perf.fix_core_ab_vote;
+ perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
}
DPU_DEBUG(
- "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu
llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
+ "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
crtc->base.id, perf->core_clk_rate,
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]);
+ perf->max_per_pipe_ib, perf->bw_ctl);
}
int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
@@ -142,7 +130,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
struct dpu_crtc_state *dpu_cstate;
struct drm_crtc *tmp_crtc;
struct dpu_kms *kms;
- int i;
if (!crtc || !state) {
DPU_ERROR("invalid crtc\n");
@@ -164,31 +151,28 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
/* obtain new values */
_dpu_core_perf_calc_crtc(kms, crtc, state, _cstate->new_perf);
- for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
- i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i];
- curr_client_type = dpu_crtc_get_client_type(crtc);
+ bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
+ curr_client_type = dpu_crtc_get_client_type(crtc);
- drm_for_each_crtc(tmp_crtc, crtc->dev) {
- if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
- (dpu_crtc_get_client_type(tmp_crtc) ==
- curr_client_type) &&
- (tmp_crtc != crtc)) {
-
[Freedreno] [PATCH v2 0/3] Use interconnect API in MDSS on SDM845
The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the appropriate power/performance profile. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth requirements for the given interconnected path. Subsequently, there is a clean up patch to remove all the references of the DPU custom bus scaling. There is corresponding DT patch with the source and destination ports defined for display driver which will be sent separately. Changes in v2: - Remove error log and unnecessary check (Jordan Crouse) - Fixed build error due to partial clean up Sravanthi Kollukuduru (3): drm/msm/dpu: clean up references of DPU custom bus scaling drm/msm/dpu: Integrate interconnect API in MDSS dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845 .../devicetree/bindings/display/msm/dpu.txt| 8 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 157 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 50 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 21 +-- 8 files changed, 140 insertions(+), 228 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 2/3] drm/msm/dpu: Integrate interconnect API in MDSS
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one of the interconnect consumers which uses the
interconnect APIs to get the path between endpoints and
set its bandwidth/latency/QoS requirements for the given
interconnected path.
Changes in v2:
- Remove error log and unnecessary check (Jordan Crouse)
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 50 +---
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 2235ef8129f4..27c2594e5133 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -4,6 +4,7 @@
*/
#include "dpu_kms.h"
+#include
#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
@@ -16,8 +17,33 @@ struct dpu_mdss {
u32 hwversion;
struct dss_module_power mp;
struct dpu_irq_controller irq_controller;
+ struct icc_path *path[2];
+ u32 num_paths;
};
+static int dpu_mdss_parse_data_bus_icc_path(
+ struct drm_device *dev, struct dpu_mdss *dpu_mdss)
+{
+ struct icc_path *path0 = of_icc_get(dev->dev, "port0");
+ struct icc_path *path1 = of_icc_get(dev->dev, "port1");
+ int total_num_paths = 0;
+
+ if (IS_ERR(path0))
+ return PTR_ERR(path0);
+
+ dpu_mdss->path[0] = path0;
+ total_num_paths = 1;
+
+ if (!IS_ERR(path1)) {
+ dpu_mdss->path[1] = path1;
+ total_num_paths++;
+ }
+
+ dpu_mdss->num_paths = total_num_paths;
+
+ return 0;
+}
+
static irqreturn_t dpu_mdss_irq(int irq, void *arg)
{
struct dpu_mdss *dpu_mdss = arg;
@@ -127,7 +153,12 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
+ u64 ab = (dpu_mdss->num_paths) ? 68/dpu_mdss->num_paths : 0;
+ u64 ib = 68;
+
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set(dpu_mdss->path[i], ab, ib);
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
if (ret)
@@ -140,12 +171,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
if (ret)
DPU_ERROR("clock disable failed, ret:%d\n", ret);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set(dpu_mdss->path[i], 0, 0);
+
return ret;
}
@@ -155,6 +189,7 @@ static void dpu_mdss_destroy(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
struct dss_module_power *mp = _mdss->mp;
+ int i;
_dpu_mdss_irq_domain_fini(dpu_mdss);
@@ -163,6 +198,9 @@ static void dpu_mdss_destroy(struct drm_device *dev)
msm_dss_put_clk(mp->clk_config, mp->num_clk);
devm_kfree(>dev, mp->clk_config);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_put(dpu_mdss->path[i]);
+
if (dpu_mdss->mmio)
devm_iounmap(>dev, dpu_mdss->mmio);
dpu_mdss->mmio = NULL;
@@ -203,6 +241,10 @@ int dpu_mdss_init(struct drm_device *dev)
}
dpu_mdss->mmio_len = resource_size(res);
+ ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
+ if (ret)
+ return ret;
+
mp = _mdss->mp;
ret = msm_dss_parse_clock(pdev, mp);
if (ret) {
@@ -224,14 +266,14 @@ int dpu_mdss_init(struct drm_device *dev)
goto irq_error;
}
+ priv->mdss = _mdss->base;
+
pm_runtime_enable(dev->dev);
pm_runtime_get_sync(dev->dev);
dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
pm_runtime_put_sync(dev->dev);
- priv->mdss = _mdss->base;
-
return ret;
irq_error:
--
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[Freedreno] [PATCH 3/3] dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845
Add interconnect properties such as interconnect provider specifier , the edge source and destination ports which are required by the interconnect API to configure interconnect path for MDSS. Signed-off-by: Sravanthi Kollukuduru --- Documentation/devicetree/bindings/display/msm/dpu.txt | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index ad2e8830324e..abd4d99b5030 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -28,6 +28,11 @@ Required properties: - #address-cells: number of address cells for the MDSS children. Should be 1. - #size-cells: Should be 1. - ranges: parent bus address space is the same as the child bus address space. +- interconnects : pairs of phandles and interconnect provider specifier to + denote the edge source and destination ports of the interconnect path. +- interconnect-names : list of interconnect path name strings sorted in the + same order as the interconnects property. Consumers drivers will use + interconnect-names to match interconnect paths with interconnect specifiers. Optional properties: - assigned-clocks: list of clock specifiers for clocks needing rate assignment @@ -86,6 +91,9 @@ Example: interrupt-controller; #interrupt-cells = <1>; + interconnects = < 38 512>; + interconnect-names = "port0"; + iommus = <_iommu 0>; #address-cells = <2>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 0/3] Use interconnect API in MDSS on SDM845
The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the appropriate power/performance profile. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth requirements for the given interconnected path. Subsequently, there is a clean up patch to remove all the references of the DPU custom bus scaling. There is corresponding DT patch with the source and destination ports defined for display driver which will be sent separately. Sravanthi Kollukuduru (3): drm/msm/dpu: clean up references of DPU custom bus scaling drm/msm/dpu: Integrate interconnect API in MDSS dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845 .../devicetree/bindings/display/msm/dpu.txt| 8 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 157 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 56 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 21 +-- 8 files changed, 143 insertions(+), 219 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 1/2] drm/msm/dpu: enable cursor plane on dpu
Reserve DMA pipe for cursor plane and attach it to the
crtc during the initialization.
Changes in V2:
None
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 35 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 9 +
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
6 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 80cbf75bc2ff..0cd9456a6c4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2082,7 +2082,8 @@ static const struct drm_crtc_helper_funcs
dpu_crtc_helper_funcs = {
};
/* initialize crtc */
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor)
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -2119,7 +2120,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
struct drm_plane *plane)
dpu_crtc_frame_event_work);
}
- drm_crtc_init_with_planes(dev, crtc, plane, NULL, _crtc_funcs,
+ drm_crtc_init_with_planes(dev, crtc, plane, cursor, _crtc_funcs,
NULL);
drm_crtc_helper_add(crtc, _crtc_helper_funcs);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index e87109e608e9..a89679160237 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -375,9 +375,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
* dpu_crtc_init - create a new crtc object
* @dev: dpu device
* @plane: base plane
+ * @cursor: cursor plane
* @Return: new crtc object or error
*/
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
*plane);
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor);
/**
* dpu_crtc_register_custom_event - api for enabling/disabling crtc event
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 44ee06398b1d..c04f3f3acae4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -29,6 +29,9 @@
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
+#define DMA_CURSOR_SDM845_MASK \
+ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
+
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -174,45 +177,35 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 =
_DMA_SBLK("9", 2);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
-#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x1c8, \
- .features = VIG_SDM845_MASK, \
- .sblk = &_sblk, \
- .xin_id = _xinid, \
- .type = SSPP_TYPE_VIG, \
- .clk_ctrl = _clkctrl \
- }
-
-#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
+#define SSPP_BLK(_name, _id, _base, _features, \
+ _sblk, _xinid, _type, _clkctrl) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x1c8, \
- .features = DMA_SDM845_MASK, \
+ .features = _features, \
.sblk = &_sblk, \
.xin_id = _xinid, \
- .type = SSPP_TYPE_DMA, \
+ .type = _type, \
.clk_ctrl = _clkctrl \
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
- sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
- sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
- sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
- sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
- sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
- sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
- sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
-
[Freedreno] [PATCH v2 2/2] drm/msm/dpu: fix for cursor blend issue
The current driver has the opaque blend mode set as the
default causing the black box effect around the cursor.
The fix enables choosing a different blend mode for alpha
enabled formats.
Changes in V2:
- Use drm_get_format_name() in the logs (Sean)
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 0cd9456a6c4c..07c2d15b45f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -297,14 +297,29 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate)
+ struct dpu_plane_state *pstate, struct dpu_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
+ uint32_t blend_op;
+ struct drm_format_name_buf format_name;
/* default to opaque blending */
- lm->ops.setup_blend_config(lm, pstate->stage, 0XFF, 0,
- DPU_BLEND_FG_ALPHA_FG_CONST |
- DPU_BLEND_BG_ALPHA_BG_CONST);
+ blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
+ DPU_BLEND_BG_ALPHA_BG_CONST;
+
+ if (format->alpha_enable) {
+ /* coverage blending */
+ blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
+ DPU_BLEND_BG_ALPHA_FG_PIXEL |
+ DPU_BLEND_BG_INV_ALPHA;
+ }
+
+ lm->ops.setup_blend_config(lm, pstate->stage,
+ 0xFF, 0, blend_op);
+
+ DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n",
+ drm_get_format_name(format->base.pixel_format, _name),
+ format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -401,7 +416,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
/* blend config update */
for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
- _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);
+ _dpu_crtc_setup_blend_cfg(mixer + lm_idx,
+ pstate, format);
mixer[lm_idx].flush_mask |= flush_mask;
--
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[Freedreno] [PATCH v2 0/2] Enable cursor plane on DPU
s patchset adds the cursor plane support on DPU driver. It also includes the fix for the black box artifacts seen around the cursor when enabled. Changes in V2: - Minor comments in logging in blend config function (Sean) Sravanthi Kollukuduru (2): drm/msm/dpu: enable cursor plane on dpu drm/msm/dpu: fix for cursor blend issue drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 31 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 35 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 9 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +- 6 files changed, 76 insertions(+), 60 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH 2/2] drm/msm/dpu: fix for cursor blend issue
The current driver has the opaque blend mode set as the
default causing the black box effect around the cursor.
The fix enables choosing a different blend mode for alpha
enabled formats.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 0cd9456a6c4c..fc6200c74614 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -297,14 +297,29 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate)
+ struct dpu_plane_state *pstate, struct dpu_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
+ uint32_t blend_op;
/* default to opaque blending */
- lm->ops.setup_blend_config(lm, pstate->stage, 0XFF, 0,
- DPU_BLEND_FG_ALPHA_FG_CONST |
- DPU_BLEND_BG_ALPHA_BG_CONST);
+ blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
+ DPU_BLEND_BG_ALPHA_BG_CONST;
+
+ if (format->alpha_enable) {
+ /* coverage blending */
+ blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
+ DPU_BLEND_BG_ALPHA_FG_PIXEL |
+ DPU_BLEND_BG_INV_ALPHA;
+ }
+
+ lm->ops.setup_blend_config(lm, pstate->stage,
+ 0xFF, 0, blend_op);
+
+ DPU_DEBUG(
+ "format:%4.4s, alpha_en(%u) blend_op:0x%x\n",
+ (char *) >base.pixel_format,
+ format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -401,7 +416,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
/* blend config update */
for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
- _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);
+ _dpu_crtc_setup_blend_cfg(mixer + lm_idx,
+ pstate, format);
mixer[lm_idx].flush_mask |= flush_mask;
--
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[Freedreno] [PATCH 1/2] drm/msm/dpu: enable cursor plane on dpu
Reserve DMA pipe for cursor plane and attach it to the
crtc during the initialization.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 35 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 9 +
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
6 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 80cbf75bc2ff..0cd9456a6c4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2082,7 +2082,8 @@ static const struct drm_crtc_helper_funcs
dpu_crtc_helper_funcs = {
};
/* initialize crtc */
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor)
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -2119,7 +2120,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
struct drm_plane *plane)
dpu_crtc_frame_event_work);
}
- drm_crtc_init_with_planes(dev, crtc, plane, NULL, _crtc_funcs,
+ drm_crtc_init_with_planes(dev, crtc, plane, cursor, _crtc_funcs,
NULL);
drm_crtc_helper_add(crtc, _crtc_helper_funcs);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index e87109e608e9..a89679160237 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -375,9 +375,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
* dpu_crtc_init - create a new crtc object
* @dev: dpu device
* @plane: base plane
+ * @cursor: cursor plane
* @Return: new crtc object or error
*/
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
*plane);
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor);
/**
* dpu_crtc_register_custom_event - api for enabling/disabling crtc event
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 44ee06398b1d..c04f3f3acae4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -29,6 +29,9 @@
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
+#define DMA_CURSOR_SDM845_MASK \
+ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
+
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -174,45 +177,35 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 =
_DMA_SBLK("9", 2);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
-#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x1c8, \
- .features = VIG_SDM845_MASK, \
- .sblk = &_sblk, \
- .xin_id = _xinid, \
- .type = SSPP_TYPE_VIG, \
- .clk_ctrl = _clkctrl \
- }
-
-#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
+#define SSPP_BLK(_name, _id, _base, _features, \
+ _sblk, _xinid, _type, _clkctrl) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x1c8, \
- .features = DMA_SDM845_MASK, \
+ .features = _features, \
.sblk = &_sblk, \
.xin_id = _xinid, \
- .type = SSPP_TYPE_DMA, \
+ .type = _type, \
.clk_ctrl = _clkctrl \
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
- sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
- sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
- sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
- sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
- sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
- sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
- sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
- SSPP_DMA_BLK("sspp_11",
[Freedreno] [PATCH 0/2] Enable cursor plane on DPU
This patchset adds the cursor plane support on DPU driver. It also includes the fix for the black box artifacts seen around the cursor when enabled. Sravanthi Kollukuduru (2): drm/msm/dpu: enable cursor plane on dpu drm/msm/dpu: fix for cursor blend issue drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 31 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 35 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 9 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +- 6 files changed, 76 insertions(+), 60 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH] drm/msm/dpu: enable cursor plane on dpu
Reserve DMA pipe for cursor plane and attach it to the
crtc during the initialization.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 35 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 9 +
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
6 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 7ac0e0d..25eba80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2456,7 +2456,8 @@ static int _dpu_crtc_init_events(struct dpu_crtc
*dpu_crtc)
}
/* initialize crtc */
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor)
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -2493,7 +2494,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
struct drm_plane *plane)
dpu_crtc_frame_event_work);
}
- drm_crtc_init_with_planes(dev, crtc, plane, NULL, _crtc_funcs,
+ drm_crtc_init_with_planes(dev, crtc, plane, cursor, _crtc_funcs,
NULL);
drm_crtc_helper_add(crtc, _crtc_helper_funcs);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 4a97ba1..a7e3173 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -396,9 +396,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
* dpu_crtc_init - create a new crtc object
* @dev: dpu device
* @plane: base plane
+ * @cursor: cursor plane
* @Return: new crtc object or error
*/
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
*plane);
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor);
/**
* dpu_crtc_register_custom_event - api for enabling/disabling crtc event
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1793cfd..f53e42d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -29,6 +29,9 @@
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
+#define DMA_CURSOR_SDM845_MASK \
+ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
+
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -174,45 +177,35 @@
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
-#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x1c8, \
- .features = VIG_SDM845_MASK, \
- .sblk = &_sblk, \
- .xin_id = _xinid, \
- .type = SSPP_TYPE_VIG, \
- .clk_ctrl = _clkctrl \
- }
-
-#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
+#define SSPP_BLK(_name, _id, _base, _features, \
+ _sblk, _xinid, _type, _clkctrl) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x1c8, \
- .features = DMA_SDM845_MASK, \
+ .features = _features, \
.sblk = &_sblk, \
.xin_id = _xinid, \
- .type = SSPP_TYPE_DMA, \
+ .type = _type, \
.clk_ctrl = _clkctrl \
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
- sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
- sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
- sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
- sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
- sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
- sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
- sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
- SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
- sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
+ SSPP_BLK("sspp_0", SSPP_VIG
[Freedreno] [DPU PATCH 2/5] drm/msm/dpu: enable cursor plane for primary crtc
Reserve one DMA pipe as cursor plane and also, update crtc
support of cursor in crtc_init.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 53 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 7 +++-
4 files changed, 34 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f0aafec..56f6576 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2027,7 +2027,8 @@ static int _dpu_crtc_init_events(struct dpu_crtc
*dpu_crtc)
}
/* initialize crtc */
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane)
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor_plane)
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -2061,8 +2062,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
struct drm_plane *plane)
dpu_crtc_frame_event_work);
}
- drm_crtc_init_with_planes(dev, crtc, plane, NULL, _crtc_funcs,
- NULL);
+ drm_crtc_init_with_planes(dev, crtc, plane,
+ cursor_plane, _crtc_funcs, NULL);
drm_crtc_helper_add(crtc, _crtc_helper_funcs);
plane->crtc = crtc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 50c3d4b..b44750d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -366,7 +366,8 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
* @plane: base plane
* @Return: new crtc object or error
*/
-struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
*plane);
+struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
+ struct drm_plane *cursor_plane);
/**
* dpu_crtc_cancel_pending_flip - complete flip for clients on lastclose
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index f0c2881..c0b8116 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -29,6 +29,9 @@
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
+#define DMA_CURSOR_SDM845_MASK \
+ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
+
#define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
@@ -169,45 +172,35 @@
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10");
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11");
-#define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
- { \
- .name = _name, .id = _id, \
- .base = _base, .len = 0x1c8, \
- .features = VIG_SDM845_MASK, \
- .sblk = &_sblk, \
- .xin_id = _xinid, \
- .type = SSPP_TYPE_VIG, \
- .clk_ctrl = _clkctrl \
- }
-
-#define SSPP_DMA_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \
+#define SSPP_BLK(_name, _id, _base, _features, \
+ _sblk, _xinid, _type, _clkctrl) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x1c8, \
- .features = DMA_SDM845_MASK, \
+ .features = _features, \
.sblk = &_sblk, \
.xin_id = _xinid, \
- .type = SSPP_TYPE_DMA, \
+ .type = _type, \
.clk_ctrl = _clkctrl \
}
static struct dpu_sspp_cfg sdm845_sspp[] = {
- SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
- sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
- SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
- sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
- SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
- sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
- SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
- sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
- SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
- sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
- SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
- sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
- SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
- sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
- SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
- sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
+ sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP
[Freedreno] [DPU PATCH 5/5] drm/msm/dpu: dynamic assignment of hw pipe to plane
Currently, there exists a static binding of hw pipe to
plane. This restricts wide plane support where plane width
exceeds the pipe's maximum width.
To enable such use cases, the hw pipes are dynamically
(re)allocated to a plane during atomic check based on the
plane capabilities.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 45 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 670 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 +-
3 files changed, 414 insertions(+), 305 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 56f6576..afb8c79 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -175,7 +175,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
struct dpu_rect plane_crtc_roi;
u32 flush_mask;
- uint32_t stage_idx, lm_idx;
+ uint32_t stage_idx = 0, lm_idx;
+ int i;
int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
bool bg_alpha_enable = false;
@@ -204,11 +205,11 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
dpu_plane_get_ctl_flush(plane, ctl, _mask);
- DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
- crtc->base.id,
- pstate->stage,
- plane->base.id,
- dpu_plane_pipe(plane) - SSPP_VIG0,
+ DPU_DEBUG("crtc %d stage%d: plane%d ssppmode%d[%d %d] fb%d\n",
+ crtc->base.id, pstate->stage,
+ plane->base.id, pstate->num_pipes,
+ dpu_plane_pipe(pstate->pipe_hw[0]) - SSPP_VIG0,
+ dpu_plane_pipe(pstate->pipe_hw[1]) - SSPP_VIG0,
state->fb ? state->fb->base.id : -1);
format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
@@ -221,19 +222,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
bg_alpha_enable = true;
DPU_EVT32(DRMID(crtc), DRMID(plane),
- state->fb ? state->fb->base.id : -1,
- state->src_x >> 16, state->src_y >> 16,
- state->src_w >> 16, state->src_h >> 16,
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h);
-
- stage_idx = zpos_cnt[pstate->stage]++;
- stage_cfg->stage[pstate->stage][stage_idx] =
- dpu_plane_pipe(plane);
-
- DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
- dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- format->base.pixel_format, fb ? fb->modifier : 0);
+ state->fb ? state->fb->base.id : -1,
+ state->src_x >> 16, state->src_y >> 16,
+ state->src_w >> 16, state->src_h >> 16,
+ state->crtc_x, state->crtc_y,
+ state->crtc_w, state->crtc_h);
+
+ for (i = 0; i < pstate->num_pipes; i++) {
+ stage_idx = zpos_cnt[pstate->stage]++;
+ if (stage_idx >= PIPES_PER_STAGE)
+ break;
+
+ stage_cfg->stage[pstate->stage][stage_idx] =
+ dpu_plane_pipe(pstate->pipe_hw[i]);
+
+ DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
+ dpu_plane_pipe(pstate->pipe_hw[i]) - SSPP_VIG0,
+ pstate->stage, format->base.pixel_format,
+ fb ? fb->modifier : 0);
+ }
/* blend config update */
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index be40a2c..2c6960e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -81,40 +81,26 @@ enum dpu_plane_qos {
/*
* struct dpu_plane - local dpu plane structure
- * @aspace: address space pointer
* @csc_ptr: Points to dpu_csc_cfg structure to use for current
- * @catalog: Points to dpu catalog structure
- * @revalidate: force revalidation of all the plane properties
*/
struct dpu_plane {
struct drm_plane base;
struct mutex lock;
- enum dpu_sspp pipe;
- uint32_t features; /* capabilities
[Freedreno] [DPU PATCH 3/5] drm/msm/dpu: remove static binding of hw pipe to plane
Expose all planes with superset of formats and with no
hw pipe static binding. Accordingly, remove checks from
atomic_check reflecting the decoupling.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 26 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 50 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 17 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 158 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 5 +-
5 files changed, 56 insertions(+), 200 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c0b8116..c2a7c64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -44,13 +44,6 @@
#define DEFAULT_DPU_LINE_WIDTH 2048
#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
-#define MAX_HORZ_DECIMATION4
-#define MAX_VERT_DECIMATION4
-
-#define MAX_UPSCALE_RATIO 20
-#define MAX_DOWNSCALE_RATIO4
-#define SSPP_UNITY_SCALE 1
-
#define STRCAT(X, Y) (X Y)
/*
@@ -58,9 +51,12 @@
*/
/* DPU top level caps */
static const struct dpu_caps sdm845_dpu_caps = {
+ .max_sspp_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_sspp_pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .csc_type = DPU_SSPP_CSC_10BIT,
.ubwc_version = DPU_HW_UBWC_VER_20,
.has_src_split = true,
.has_dim_layer = true,
@@ -128,19 +124,8 @@
* SSPP sub blocks config
*/
-/* SSPP common configuration */
-static const struct dpu_sspp_blks_common sdm845_sspp_common = {
- .maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
- .maxhdeciexp = MAX_HORZ_DECIMATION,
- .maxvdeciexp = MAX_VERT_DECIMATION,
-};
-
#define _VIG_SBLK(num) \
{ \
- .common = _sspp_common, \
- .maxdwnscale = MAX_DOWNSCALE_RATIO, \
- .maxupscale = MAX_UPSCALE_RATIO, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
@@ -149,17 +134,12 @@
.csc_blk = {.name = STRCAT("sspp_csc", num), \
.id = DPU_SSPP_CSC_10BIT, \
.base = 0x1a00, .len = 0x100,}, \
- .format_list = plane_formats_yuv, \
}
#define _DMA_SBLK(num) \
{ \
- .common = _sspp_common, \
- .maxdwnscale = SSPP_UNITY_SCALE, \
- .maxupscale = SSPP_UNITY_SCALE, \
.src_blk = {.name = STRCAT("sspp_src_", num), \
.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
- .format_list = plane_formats, \
}
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 1b04448..68644db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -63,6 +63,10 @@
#define CRTC_DUAL_MIXERS 2
+#define MAX_UPSCALE_RATIO 20
+#define MAX_DOWNSCALE_RATIO4
+#define SSPP_UNITY_SCALE 1
+
#define MAX_XIN_COUNT 16
/**
@@ -290,19 +294,26 @@ struct dpu_qos_lut_tbl {
/**
* struct dpu_caps - define DPU capabilities
- * @max_mixer_widthmax layer mixer line width support.
- * @max_mixer_blendstages max layer mixer blend stages or
+ * @max_sspp_width max: pixelwidth supported by this pipe
+ * @max_sspp_pixel_ram_size: size of latency hiding and
+ * de-tiling buffer in bytes
+ * @max_mixer_width: max layer mixer line width support
+ * @max_mixer_blendstages: max layer mixer blend stages or
* supported z order
- * @qseed_type qseed2 or qseed3 support.
- * @ubwc_version UBWC feature version (0x0 for not supported)
- * @has_src_split source split feature status
- * @has_dim_layer dim layer feature status
- * @has_idle_pcindicate if idle power collapse feature is supported
+ * @qseed_type: qseed2 or qseed3 support
+ * @csc_type: csc or csc_10bit support
+ * @ubwc_version: UBWC feature version (0x0 for not supported)
+ * @has_src_split: source split feature status
+ * @has_dim_layer: dim layer feature status
+ * @has_idle_pc:indicate if idle power collapse feature is supported
*/
struct dpu_caps {
+ u32 max_sspp_width;
+ u32 max_sspp_pixel_ram_size;
u32 max_mixer_width;
u32 max_mixer_blendstages;
[Freedreno] [DPU PATCH 4/5] drm/msm/dpu: introduce state based plane resource management
A plane can be attached to a maximum of two hw pipes
in case of wide resolution greater than pipe's max width limit.
This mapping of hw pipe(s) to plane and number of pipes will be
maintained in the plane state.
Resource manager (RM) will handle the SSPP blocks reservation
for a given plane.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 11 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c| 156 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h| 20
3 files changed, 172 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index e0688895..4eb929b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -25,6 +25,8 @@
#include "dpu_hw_mdss.h"
#include "dpu_hw_sspp.h"
+#define PLANE_DUAL_PIPES 2
+
/**
* struct dpu_plane_state: Define dpu extension of drm plane state object
* @base: base drm plane state object
@@ -36,6 +38,8 @@
* @multirect_index: index of the rectangle of SSPP
* @multirect_mode: parallel or time multiplex multirect mode
* @pending: whether the current update is still pending
+ * @num_pipes: number of pipes attached to plane
+ * @pipe_hw: array of pointers to hardware pipes reserved for plane
* @scaler3_cfg: configuration data for scaler3
* @pixel_ext: configuration data for pixel extensions
* @scaler_check_state: indicates status of user provided pixel extension data
@@ -48,6 +52,10 @@ struct dpu_plane_state {
enum dpu_stage stage;
bool pending;
+ /* HW pipe config */
+ u32 num_pipes;
+ struct dpu_hw_pipe *pipe_hw[PLANE_DUAL_PIPES];
+
/* scaler configuration */
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
@@ -58,6 +66,9 @@ struct dpu_plane_state {
#define to_dpu_plane_state(x) \
container_of(x, struct dpu_plane_state, base)
+/* get plane id from dpu plane state */
+#define get_plane_id(x) ((x->base.plane)->base.id)
+
/**
* dpu_plane_pipe - return sspp identifier for the given plane
* @plane: Pointer to DRM plane object
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 018d01a..5387600 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -14,6 +14,7 @@
#define pr_fmt(fmt)"[drm:%s] " fmt, __func__
#include "dpu_kms.h"
+#include "dpu_hw_sspp.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_cdm.h"
@@ -22,10 +23,13 @@
#include "dpu_encoder.h"
#include "dpu_rm.h"
+#define RESERVED_BY_OTHER(drm_map_id, drm_id) \
+ (drm_map_id && (drm_map_id != drm_id))
+
/**
* struct dpu_rm_hw_blk - hardware block tracking list member
* @type: Type of hardware block this structure tracks
- * @drm_id:DRM component ID associated with the HW block
+ * @rm_id: DRM component ID associated with the HW block
* @id:Hardware ID number, within it's own space, ie. LM_X
* @hw:Pointer to the hardware register access object for this
block
*/
@@ -157,7 +161,8 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type,
void *hw)
dpu_hw_intf_destroy(hw);
break;
case DPU_HW_BLK_SSPP:
- /* SSPPs are not managed by the resource manager */
+ dpu_hw_sspp_destroy(hw);
+ break;
case DPU_HW_BLK_TOP:
/* Top is a singleton, not managed in hw_blks list */
case DPU_HW_BLK_MAX:
@@ -229,7 +234,8 @@ static int _dpu_rm_hw_blk_create(
hw = dpu_hw_intf_init(id, mmio, cat);
break;
case DPU_HW_BLK_SSPP:
- /* SSPPs are not managed by the resource manager */
+ hw = dpu_hw_sspp_init(id, mmio, cat);
+ break;
case DPU_HW_BLK_TOP:
/* Top is a singleton, not managed in hw_blks list */
case DPU_HW_BLK_MAX:
@@ -281,6 +287,15 @@ int dpu_rm_init(struct dpu_rm *rm,
}
/* Interrogate HW catalog and create tracking items for hw blocks */
+ for (i = 0; i < cat->sspp_count; i++) {
+ rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_SSPP,
+ cat->sspp[i].id, >sspp[i]);
+ if (rc) {
+ DPU_ERROR("failed: sspp hw not available\n");
+ goto fail;
+ }
+ }
+
for (i = 0; i < cat->mixer_count; i++) {
struct dpu_lm_cfg *lm = >mixer[i];
@@ -570,12 +585,10 @@ static int _dpu_rm_reserve_intf_related_hw(
}
static int _dpu_rm_release_hw_blk(
- struct dpu_rm *rm,
- struct dpu_crtc_state *st
[Freedreno] [DPU PATCH 1/5] drm/msm/dpu: remove smart dma support
Removing the smart dma feature implementation as it is
currently not enabled on dpu driver.
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 51 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 25 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 19 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 76 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 159 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h| 56 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 26 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 265 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 38 +---
drivers/gpu/drm/msm/msm_drv.h | 2 +-
11 files changed, 84 insertions(+), 637 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 6c78c11c3..f0aafec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -230,12 +230,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
stage_idx = zpos_cnt[pstate->stage]++;
stage_cfg->stage[pstate->stage][stage_idx] =
dpu_plane_pipe(plane);
- stage_cfg->multirect_index[pstate->stage][stage_idx] =
- pstate->multirect_index;
DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage,
- pstate->multirect_index, pstate->multirect_mode,
format->base.pixel_format, fb ? fb->modifier : 0);
/* blend config update */
@@ -1334,14 +1331,13 @@ struct plane_state {
struct dpu_plane_state *dpu_pstate;
const struct drm_plane_state *drm_pstate;
int stage;
- u32 pipe_id;
};
static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct dpu_crtc *dpu_crtc;
- struct plane_state pstates[DPU_STAGE_MAX * 4];
+ struct plane_state pstates[DPU_STAGE_MAX * 2];
struct dpu_crtc_state *cstate;
const struct drm_plane_state *pstate;
@@ -1351,10 +1347,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct dpu_private_state *dpu_priv_state;
int cnt = 0, rc = 0, mixer_width, i, z_pos;
-
- struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
- int multirect_count = 0;
- const struct drm_plane_state *pipe_staged[SSPP_MAX];
int left_zpos_cnt = 0, right_zpos_cnt = 0;
if (!crtc) {
@@ -1378,8 +1370,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (state->active_changed)
state->mode_changed = true;
- memset(pipe_staged, 0, sizeof(pipe_staged));
-
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
_dpu_crtc_setup_lm_bounds(crtc, state);
@@ -1398,18 +1388,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
pstates[cnt].drm_pstate = pstate;
pstates[cnt].stage = pstate->normalized_zpos;
- pstates[cnt].pipe_id = dpu_plane_pipe(plane);
-
- if (pipe_staged[pstates[cnt].pipe_id]) {
- multirect_plane[multirect_count].r0 =
- pipe_staged[pstates[cnt].pipe_id];
- multirect_plane[multirect_count].r1 = pstate;
- multirect_count++;
-
- pipe_staged[pstates[cnt].pipe_id] = NULL;
- } else {
- pipe_staged[pstates[cnt].pipe_id] = pstate;
- }
cnt++;
@@ -1426,20 +1404,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
}
}
- for (i = 1; i < SSPP_MAX; i++) {
- if (pipe_staged[i]) {
- dpu_plane_clear_multirect(pipe_staged[i]);
-
- if (is_dpu_plane_virtual(pipe_staged[i]->plane)) {
- DPU_ERROR(
- "r1 only virt plane:%d not supported\n",
- pipe_staged[i]->plane->base.id);
- rc = -EINVAL;
- goto end;
- }
- }
- }
-
z_pos = -1;
for (i = 0; i < cnt; i++) {
/* reset counts at every new blend stage */
@@ -1478,17 +1442,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos);
}
- for (i = 0; i < m
[Freedreno] [DPU PATCH 0/5] Introduce plane virtualization in DPU driver
Currently, each drm plane controls a single HW pipe. For all use cases where plane width exceeds the maximum pipe width, the DPU driver will require more than one HW pipe. This patchset enables virtualization of planes through the following changes: (1) Expose all the planes with the superset of formats and without any static binding of HW pipe during the initialization. (2) Introduce the state based plane resource management. (3) Dynamically assign a maximum of two pipes per plane based on plane capabilities in atomic check. This patchset is based on https://patchwork.kernel.org/patch/10471479/ Sravanthi Kollukuduru (5): drm/msm/dpu: remove smart dma support drm/msm/dpu: enable cursor plane for primary crtc drm/msm/dpu: remove static binding of hw pipe to plane drm/msm/dpu: introduce state based plane resource management drm/msm/dpu: dynamic assignment of hw pipe to plane drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 103 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 104 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 69 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 76 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |4 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 159 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h| 56 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 48 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1063 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 58 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 156 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 20 + drivers/gpu/drm/msm/msm_drv.h |2 +- 14 files changed, 744 insertions(+), 1177 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH v2 13/14] drm/msm/dpu: add atomic private object to dpu kms
From: Jeykumar Sankaran
Subclass drm private state for DPU for handling driver
specific data. Adds atomic private object and private object
lock to dpu kms. Provides helper function to retrieve DPU
private data from current atomic state.
changes in v2:
- fix return value while retrieving dpu priv state (Jordan)
- avoid error on kzalloc failure(Jordan)
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 65 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 15
2 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fe614c0..b3eaf3f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1076,6 +1076,10 @@ static void dpu_kms_destroy(struct msm_kms *kms)
dpu_kms = to_dpu_kms(kms);
_dpu_kms_hw_destroy(dpu_kms);
+
+ drm_atomic_private_obj_fini(_kms->priv_obj);
+ drm_modeset_lock_fini(_kms->priv_obj_lock);
+
}
static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file *file)
@@ -1618,10 +1622,59 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
return rc;
}
+struct dpu_private_state *dpu_get_private_state(struct drm_atomic_state *state)
+{
+ struct msm_drm_private *priv = state->dev->dev_private;
+ struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
+ struct drm_private_state *priv_state;
+ int rc = 0;
+
+ rc = drm_modeset_lock(_kms->priv_obj_lock, state->acquire_ctx);
+ if (rc)
+ return ERR_PTR(rc);
+
+ priv_state = drm_atomic_get_private_obj_state(state,
+ _kms->priv_obj);
+ if (IS_ERR(priv_state))
+ return ERR_PTR(-ENOMEM);
+
+ return to_dpu_private_state(priv_state);
+}
+
+static struct drm_private_state *
+dpu_private_obj_duplicate_state(struct drm_private_obj *obj)
+{
+ struct dpu_private_state *dpu_priv_state;
+
+ dpu_priv_state = kmemdup(obj->state,
+ sizeof(*dpu_priv_state), GFP_KERNEL);
+ if (!dpu_priv_state)
+ return NULL;
+
+ __drm_atomic_helper_private_obj_duplicate_state(obj,
+ _priv_state->base);
+
+ return _priv_state->base;
+}
+
+static void dpu_private_obj_destroy_state(struct drm_private_obj *obj,
+ struct drm_private_state *state)
+{
+ struct dpu_private_state *dpu_priv_state = to_dpu_private_state(state);
+
+ kfree(dpu_priv_state);
+}
+
+static const struct drm_private_state_funcs priv_obj_funcs = {
+ .atomic_duplicate_state = dpu_private_obj_duplicate_state,
+ .atomic_destroy_state = dpu_private_obj_destroy_state,
+};
+
struct msm_kms *dpu_kms_init(struct drm_device *dev)
{
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
+ struct dpu_private_state *dpu_priv_state;
int irq;
if (!dev || !dev->dev_private) {
@@ -1639,6 +1692,18 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev)
}
dpu_kms->base.irq = irq;
+ /* Initialize private obj's */
+ drm_modeset_lock_init(_kms->priv_obj_lock);
+
+ dpu_priv_state = kzalloc(sizeof(*dpu_priv_state), GFP_KERNEL);
+ if (!dpu_priv_state)
+ return ERR_PTR(-ENOMEM);
+
+
+ drm_atomic_private_obj_init(_kms->priv_obj,
+ _priv_state->base,
+ _obj_funcs);
+
return _kms->base;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 046e6f7..924d8967 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -190,6 +190,9 @@ struct dpu_kms {
struct dpu_hw_vbif *hw_vbif[VBIF_MAX];
struct dpu_hw_mdp *hw_mdp;
+ struct drm_modeset_lock priv_obj_lock;
+ struct drm_private_obj priv_obj;
+
bool has_danger_ctrl;
struct platform_device *pdev;
@@ -197,12 +200,24 @@ struct dpu_kms {
struct dss_module_power mp;
};
+struct dpu_private_state {
+ struct drm_private_state base;
+};
+
struct vsync_info {
u32 frame_count;
u32 line_count;
};
#define to_dpu_kms(x) container_of(x, struct dpu_kms, base)
+#define to_dpu_private_state(x) container_of(x, struct dpu_private_state, base)
+
+/**
+ * dpu_get_private_state - get dpu private state from atomic state
+ * @state: drm atomic state
+ * Return: pointer to dpu private state object
+ */
+struct dpu_private_state *dpu_get_private_state(struct drm_atomic_state
*state);
/**
* dpu_is_custom_client - whether or not to enable non-standard customizations
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
__
[Freedreno] [DPU PATCH v2 14/14] drm/msm/dpu: use private obj to track hw resources
From: Jeykumar Sankaran
Switch to state based resource management. This patch
overhauls the resource manager and HW allocation methods by
maintaining the global resource pool and allocated hw
blocks in respective drm component states.
Global resource manager(RM) is tracked in private object.
Allocation strategy is switched from single point allocation
of HW resources for the display pipeline to per component
based allocation, where each drm component allocates HW
blocks mapped to it's domain and tracks them in their respective
state objects.
Fix resource contention due to race conditions between
user space and display thread by reserving resources
only in atomic check.
changes in v2:
- split irrelevant changes to separate patches(Sean)
- validate dpu priv state before using(Jordan)
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 159 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 32 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 134 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 22 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 19 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 792 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 140 ++--
9 files changed, 445 insertions(+), 863 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 317dd2e..6c78c11c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,6 +47,8 @@
#define RIGHT_MIXER 1
#define MISR_BUFF_SIZE 256
+#define MAX_VDISPLAY_SPLIT 1080
+
static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
{
@@ -276,16 +278,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
DPU_DEBUG("%s\n", dpu_crtc->name);
- if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
- DPU_ERROR("invalid number mixers: %d\n", cstate->num_mixers);
- return;
- }
-
for (i = 0; i < cstate->num_mixers; i++) {
- if (!mixer[i].hw_lm || !mixer[i].lm_ctl) {
- DPU_ERROR("invalid lm or ctl assigned to mixer\n");
- return;
- }
mixer[i].mixer_op_mode = 0;
mixer[i].flush_mask = 0;
if (mixer[i].lm_ctl->ops.clear_all_blendstages)
@@ -579,75 +572,27 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc,
DPU_EVT32_VERBOSE(DRMID(crtc));
}
-static void _dpu_crtc_setup_mixer_for_encoder(
- struct drm_crtc *crtc,
- struct drm_encoder *enc)
+static void _dpu_crtc_setup_mixers(struct drm_crtc_state *crtc_state)
{
- struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
- struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
- struct dpu_rm *rm = _kms->rm;
+ struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
struct dpu_crtc_mixer *mixer;
- struct dpu_hw_ctl *last_valid_ctl = NULL;
int i;
- struct dpu_rm_hw_iter lm_iter, ctl_iter;
-
- dpu_rm_init_hw_iter(_iter, enc->base.id, DPU_HW_BLK_LM);
- dpu_rm_init_hw_iter(_iter, enc->base.id, DPU_HW_BLK_CTL);
-
- /* Set up all the mixers and ctls reserved by this encoder */
- for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
- mixer = >mixers[i];
-
- if (!dpu_rm_get_hw(rm, _iter))
- break;
- mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw;
-
- /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
- if (!dpu_rm_get_hw(rm, _iter)) {
- DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
- mixer->hw_lm->idx - LM_0);
- mixer->lm_ctl = last_valid_ctl;
- } else {
- mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
- last_valid_ctl = mixer->lm_ctl;
- }
-
- /* Shouldn't happen, mixers are always >= ctls */
- if (!mixer->lm_ctl) {
- DPU_ERROR("no valid ctls found for lm %d\n",
- mixer->hw_lm->idx - LM_0);
- return;
- }
- mixer->encoder = enc;
-
- cstate->num_mixers++;
- DPU_DEBUG("setup mixer %d: lm %d\n",
- i, mixer->hw_lm->idx - LM_0);
- DPU_DEBUG("setup mixer
[Freedreno] [DPU PATCH v2 05/14] drm/msm/dpu: use kms stored hw mdp block
From: Jeykumar Sankaran
Avoid querying RM for hw mdp block. Use the one
stored in KMS during initialization.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +
2 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 388de38..b9f7d95 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -830,7 +830,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
{
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_cmd *cmd_enc = NULL;
- struct dpu_hw_mdp *hw_mdp;
struct dpu_encoder_irq *irq;
int i, ret = 0;
@@ -843,14 +842,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
goto fail;
}
phys_enc = _enc->base;
-
- hw_mdp = dpu_rm_get_mdp(>dpu_kms->rm);
- if (IS_ERR_OR_NULL(hw_mdp)) {
- ret = PTR_ERR(hw_mdp);
- DPU_ERROR("failed to get mdptop\n");
- goto fail_mdp_init;
- }
- phys_enc->hw_mdptop = hw_mdp;
+ phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
dpu_encoder_phys_cmd_init_ops(_enc->ops);
@@ -905,8 +897,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
return phys_enc;
-fail_mdp_init:
- kfree(cmd_enc);
fail:
return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 73e5938..e9b346c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -835,7 +835,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_vid *vid_enc = NULL;
struct dpu_rm_hw_iter iter;
- struct dpu_hw_mdp *hw_mdp;
struct dpu_encoder_irq *irq;
int i, ret = 0;
@@ -852,13 +851,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
phys_enc = _enc->base;
- hw_mdp = dpu_rm_get_mdp(>dpu_kms->rm);
- if (IS_ERR_OR_NULL(hw_mdp)) {
- ret = PTR_ERR(hw_mdp);
- DPU_ERROR("failed to get mdptop\n");
- goto fail;
- }
- phys_enc->hw_mdptop = hw_mdp;
+ phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
/**
--
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[Freedreno] [DPU PATCH v2 10/14] drm/msm/dpu: rename hw_ctl to lm_ctl
From: Jeykumar Sankaran
Prep change for state based resource management.
Rename hw_ctl to lm_ctl to mean the ctl associated
with the hw layer mixer block.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 4 ++--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index bed67cd..317dd2e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -182,7 +182,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
return;
}
- ctl = mixer->hw_ctl;
+ ctl = mixer->lm_ctl;
lm = mixer->hw_lm;
stage_cfg = _crtc->stage_cfg;
cstate = to_dpu_crtc_state(crtc->state);
@@ -282,15 +282,15 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
}
for (i = 0; i < cstate->num_mixers; i++) {
- if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
+ if (!mixer[i].hw_lm || !mixer[i].lm_ctl) {
DPU_ERROR("invalid lm or ctl assigned to mixer\n");
return;
}
mixer[i].mixer_op_mode = 0;
mixer[i].flush_mask = 0;
- if (mixer[i].hw_ctl->ops.clear_all_blendstages)
- mixer[i].hw_ctl->ops.clear_all_blendstages(
- mixer[i].hw_ctl);
+ if (mixer[i].lm_ctl->ops.clear_all_blendstages)
+ mixer[i].lm_ctl->ops.clear_all_blendstages(
+ mixer[i].lm_ctl);
}
/* initialize stage cfg */
@@ -299,7 +299,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
for (i = 0; i < cstate->num_mixers; i++) {
- ctl = mixer[i].hw_ctl;
+ ctl = mixer[i].lm_ctl;
lm = mixer[i].hw_lm;
lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
@@ -606,14 +606,14 @@ static void _dpu_crtc_setup_mixer_for_encoder(
if (!dpu_rm_get_hw(rm, _iter)) {
DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
mixer->hw_lm->idx - LM_0);
- mixer->hw_ctl = last_valid_ctl;
+ mixer->lm_ctl = last_valid_ctl;
} else {
- mixer->hw_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
- last_valid_ctl = mixer->hw_ctl;
+ mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
+ last_valid_ctl = mixer->lm_ctl;
}
/* Shouldn't happen, mixers are always >= ctls */
- if (!mixer->hw_ctl) {
+ if (!mixer->lm_ctl) {
DPU_ERROR("no valid ctls found for lm %d\n",
mixer->hw_lm->idx - LM_0);
return;
@@ -625,7 +625,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
DPU_DEBUG("setup mixer %d: lm %d\n",
i, mixer->hw_lm->idx - LM_0);
DPU_DEBUG("setup mixer %d: ctl %d\n",
- i, mixer->hw_ctl->idx - CTL_0);
+ i, mixer->lm_ctl->idx - CTL_0);
}
}
@@ -1660,11 +1660,11 @@ static int _dpu_debugfs_status_show(struct seq_file *s,
void *data)
m = >mixers[i];
if (!m->hw_lm)
seq_printf(s, "\tmixer[%d] has no lm\n", i);
- else if (!m->hw_ctl)
+ else if (!m->lm_ctl)
seq_printf(s, "\tmixer[%d] has no ctl\n", i);
else
seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
- m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
+ m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
out_width, mode->vdisplay);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index e7cc1ef..f3edff3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -83,14 +83,14 @@ struct dpu_crtc_smmu_state_data {
/**
* struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
* @hw_lm: LM HW Driver context
- * @hw_ctl:CTL Path HW driver context
+ * @lm_ctl:CTL Path HW driver con
[Freedreno] [DPU PATCH v2 04/14] drm/msm/dpu: program master-slave encoders explicitly
From: Jeykumar Sankaran
Identify slave-master encoders and program them explicitly.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 41 -
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 11a1045..e98cf70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -184,6 +184,7 @@ struct dpu_encoder_virt {
unsigned int num_phys_encs;
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
+ struct dpu_encoder_phys *cur_slave;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
bool intfs_swapped;
@@ -1170,35 +1171,48 @@ void dpu_encoder_virt_restore(struct drm_encoder
*drm_enc)
static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc = NULL;
+ struct dpu_encoder_phys *phys = NULL;
int i, ret = 0;
- struct drm_display_mode *cur_mode = NULL;
if (!drm_enc) {
DPU_ERROR("invalid encoder\n");
return;
}
dpu_enc = to_dpu_encoder_virt(drm_enc);
- cur_mode = _enc->base.crtc->state->adjusted_mode;
DPU_DEBUG_ENC(dpu_enc, "\n");
- DPU_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
dpu_enc->cur_master = NULL;
+ dpu_enc->cur_slave = NULL;
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+ phys = dpu_enc->phys_encs[i];
+
+ if (!phys || !phys->ops.is_master)
+ continue;
- if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
- DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n", i);
+ if (phys->ops.is_master(phys)) {
+ DPU_DEBUG_ENC(dpu_enc, "master is at idx %d\n", i);
dpu_enc->cur_master = phys;
- break;
+ } else {
+ DPU_DEBUG_ENC(dpu_enc, "slave is at idx %d\n", i);
+ dpu_enc->cur_slave = phys;
}
}
if (!dpu_enc->cur_master) {
- DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
+ DPU_ERROR("virt encoder has no master identified\n");
return;
}
+ /* always enable slave encoder before master */
+ phys = dpu_enc->cur_slave;
+ if (phys && phys->ops.enable)
+ phys->ops.enable(phys);
+
+ phys = dpu_enc->cur_master;
+ if (phys && phys->ops.enable)
+ phys->ops.enable(phys);
+
ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
if (ret) {
DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
@@ -1207,25 +1221,16 @@ static void dpu_encoder_virt_enable(struct drm_encoder
*drm_enc)
}
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
+ phys = dpu_enc->phys_encs[i];
if (!phys)
continue;
- if (phys != dpu_enc->cur_master) {
- if (phys->ops.enable)
- phys->ops.enable(phys);
- }
-
if (dpu_enc->misr_enable && (dpu_enc->disp_info.capabilities &
MSM_DISPLAY_CAP_VID_MODE) && phys->ops.setup_misr)
phys->ops.setup_misr(phys, true,
dpu_enc->misr_frame_count);
}
- if (dpu_enc->cur_master->ops.enable)
- dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
-
_dpu_encoder_virt_enable_helper(drm_enc);
}
--
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[Freedreno] [DPU PATCH v2 12/14] drm/msm/dpu: remove display H_TILE from encoder
From: Jeykumar Sankaran
Encoder H_TILE values are not used for allocating the hw blocks.
no. of hw_intf blocks provides the info.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 3 +--
3 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index c9e2dce..5e820bc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -179,8 +179,6 @@ struct dpu_encoder_virt {
spinlock_t enc_spinlock;
uint32_t bus_scaling_client;
- uint32_t display_num_of_h_tiles;
-
unsigned int num_phys_encs;
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
@@ -469,7 +467,6 @@ void dpu_encoder_get_hw_resources(struct drm_encoder
*drm_enc,
/* Query resources used by phys encs, expected to be without overlap */
memset(hw_res, 0, sizeof(*hw_res));
- hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles;
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -2295,8 +2292,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
WARN_ON(disp_info->num_of_h_tiles < 1);
- dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
-
DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index ce92901..a9f49b2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -33,14 +33,10 @@
* Encoder functions and data types
* @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused
* @needs_cdm: Encoder requests a CDM based on pixel format conversion needs
- * @display_num_of_h_tiles: Number of horizontal tiles in case of split
- * interface
- * @topology: Topology of the display
*/
struct dpu_encoder_hw_resources {
enum dpu_intf_mode intfs[INTF_MAX];
bool needs_cdm;
- u32 display_num_of_h_tiles;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index b65f386..ef945d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -818,8 +818,7 @@ static int _dpu_rm_populate_requirements(
conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI)
reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DS);
- DPU_DEBUG("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
- reqs->hw_res.display_num_of_h_tiles);
+ DPU_DEBUG("top_ctrl: 0x%llX\n", reqs->top_ctrl);
DPU_DEBUG("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
reqs->topology->num_lm, reqs->topology->num_ctl,
reqs->topology->top_name,
--
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[Freedreno] [DPU PATCH v2 09/14] drm/msm/dpu: move hw resource tracking to crtc state
From: Jeykumar Sankaran
Prep changes for state based resource management.
Moves all the hw block tracking for the crtc to the state
object.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 76 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 26 +--
2 files changed, 53 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 426e2ad..bed67cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -142,9 +142,9 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc
*crtc)
crtc_state = to_dpu_crtc_state(crtc->state);
lm_horiz_position = 0;
- for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+ for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
const struct dpu_rect *lm_roi = _state->lm_bounds[lm_idx];
- struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm;
+ struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
struct dpu_hw_mixer_cfg cfg;
if (dpu_kms_rect_is_null(lm_roi))
@@ -237,7 +237,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
format->base.pixel_format, fb ? fb->modifier : 0);
/* blend config update */
- for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);
mixer[lm_idx].flush_mask |= flush_mask;
@@ -260,7 +260,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
{
struct dpu_crtc *dpu_crtc;
- struct dpu_crtc_state *dpu_crtc_state;
+ struct dpu_crtc_state *cstate;
struct dpu_crtc_mixer *mixer;
struct dpu_hw_ctl *ctl;
struct dpu_hw_mixer *lm;
@@ -271,17 +271,17 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
return;
dpu_crtc = to_dpu_crtc(crtc);
- dpu_crtc_state = to_dpu_crtc_state(crtc->state);
- mixer = dpu_crtc->mixers;
+ cstate = to_dpu_crtc_state(crtc->state);
+ mixer = cstate->mixers;
DPU_DEBUG("%s\n", dpu_crtc->name);
- if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
- DPU_ERROR("invalid number mixers: %d\n", dpu_crtc->num_mixers);
+ if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
+ DPU_ERROR("invalid number mixers: %d\n", cstate->num_mixers);
return;
}
- for (i = 0; i < dpu_crtc->num_mixers; i++) {
+ for (i = 0; i < cstate->num_mixers; i++) {
if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
DPU_ERROR("invalid lm or ctl assigned to mixer\n");
return;
@@ -298,7 +298,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
- for (i = 0; i < dpu_crtc->num_mixers; i++) {
+ for (i = 0; i < cstate->num_mixers; i++) {
ctl = mixer[i].hw_ctl;
lm = mixer[i].hw_lm;
@@ -583,7 +583,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
struct drm_crtc *crtc,
struct drm_encoder *enc)
{
- struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
+ struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
struct dpu_rm *rm = _kms->rm;
struct dpu_crtc_mixer *mixer;
@@ -595,8 +595,8 @@ static void _dpu_crtc_setup_mixer_for_encoder(
dpu_rm_init_hw_iter(_iter, enc->base.id, DPU_HW_BLK_CTL);
/* Set up all the mixers and ctls reserved by this encoder */
- for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers); i++) {
- mixer = _crtc->mixers[i];
+ for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
+ mixer = >mixers[i];
if (!dpu_rm_get_hw(rm, _iter))
break;
@@ -621,7 +621,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
mixer->encoder = enc;
- dpu_crtc->num_mixers++;
+ cstate->num_mixers++;
DPU_DEBUG("setup mixer %d: lm %d\n",
i, mixer->hw_lm->idx - LM_0);
DPU_DEBUG("setup mixer %d: ctl %d\n",
@@ -632,11 +632,11 @@ static void _dpu_crtc_setup_mixer_for_encoder(
static
[Freedreno] [DPU PATCH v2 11/14] drm/msm/dpu: remove topology name
From: Jeykumar Sankaran
Strip down the support for topology enums. It
can be replaced with simple hw count checks.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 9 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 9 -
5 files changed, 10 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6d32a0b..c9e2dce 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1036,7 +1036,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
struct drm_connector *conn = NULL, *conn_iter;
struct dpu_rm_hw_iter pp_iter, ctl_iter;
struct msm_display_topology topology;
- enum dpu_rm_topology_name topology_name;
struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC];
int i = 0, ret;
@@ -1094,7 +1093,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
}
- topology_name = dpu_rm_get_topology_name(topology);
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -1114,7 +1112,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
phys->hw_ctl = hw_ctl[i];
phys->connector = conn->state->connector;
- phys->topology_name = topology_name;
if (phys->ops.mode_set)
phys->ops.mode_set(phys, mode, adj_mode);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 71a037b..35ce88a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -24,6 +24,7 @@
#include "dpu_hw_top.h"
#include "dpu_hw_cdm.h"
#include "dpu_encoder.h"
+#include "dpu_crtc.h"
#define DPU_ENCODER_NAME_MAX 16
@@ -219,7 +220,6 @@ struct dpu_encoder_irq {
* @split_role:Role to play in a split-panel configuration
* @intf_mode: Interface mode
* @intf_idx: Interface index on dpu hardware
- * @topology_name: topology selected for the display
* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
* @enable_state: Enable state tracking
* @vblank_refcount: Reference count of vblank request
@@ -249,7 +249,6 @@ struct dpu_encoder_phys {
enum dpu_enc_split_role split_role;
enum dpu_intf_mode intf_mode;
enum dpu_intf intf_idx;
- enum dpu_rm_topology_name topology_name;
spinlock_t *enc_spinlock;
enum dpu_enc_enable_state enable_state;
atomic_t vblank_refcount;
@@ -381,11 +380,15 @@ int dpu_encoder_helper_wait_event_timeout(
static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
struct dpu_encoder_phys *phys_enc)
{
+ struct dpu_crtc_state *dpu_cstate;
+
if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
return BLEND_3D_NONE;
+ dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
+
if (phys_enc->split_role == ENC_ROLE_SOLO &&
- phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
+ (dpu_cstate->num_mixers == 2))
return BLEND_3D_H_ROW_INT;
return BLEND_3D_NONE;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 3adc491..c74f4c4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -355,13 +355,14 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg,
int irq_idx)
static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
{
+ struct dpu_crtc_state *dpu_cstate;
+
if (!phys_enc)
return false;
- if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
- return true;
+ dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
- return false;
+ return (dpu_cstate->num_ctls > 1);
}
static bool dpu_encoder_phys_vid_needs_single_flush(
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index eff316b..b65f386 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu
[Freedreno] [DPU PATCH v2 08/14] drm/msm/dpu: avoid querying for hw intf before assignment
From: Jeykumar Sankaran
hw intf blocks are needed only during encoder enable to program
timing engines(for video panels). encoder->enable is triggered
only after atomic_modeset at which point we assign the
resources for the display pipeline. This patch defers the
hw_intf look-up until encoder enable.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 53 +++---
1 file changed, 16 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index f0b5762..3adc491 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -468,7 +468,7 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
{
struct msm_drm_private *priv;
struct dpu_encoder_phys_vid *vid_enc;
- struct dpu_hw_intf *intf;
+ struct dpu_rm_hw_iter iter;
struct dpu_hw_ctl *ctl;
u32 flush_mask = 0;
@@ -480,11 +480,20 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
priv = phys_enc->parent->dev->dev_private;
vid_enc = to_dpu_encoder_phys_vid(phys_enc);
- intf = vid_enc->hw_intf;
ctl = phys_enc->hw_ctl;
- if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
- DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
- vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
+
+ dpu_rm_init_hw_iter(, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
+ while (dpu_rm_get_hw(_enc->dpu_kms->rm, )) {
+ struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
+
+ if (hw_intf->idx == phys_enc->intf_idx) {
+ vid_enc->hw_intf = hw_intf;
+ break;
+ }
+ }
+
+ if (!vid_enc->hw_intf) {
+ DPU_ERROR("hw_intf not assigned\n");
return;
}
@@ -506,7 +515,7 @@ static void dpu_encoder_phys_vid_enable(struct
dpu_encoder_phys *phys_enc)
!dpu_encoder_phys_vid_is_master(phys_enc))
goto skip_flush;
- ctl->ops.get_bitmask_intf(ctl, _mask, intf->idx);
+ ctl->ops.get_bitmask_intf(ctl, _mask, vid_enc->hw_intf->idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
skip_flush:
@@ -537,22 +546,13 @@ static void dpu_encoder_phys_vid_get_hw_resources(
struct dpu_encoder_hw_resources *hw_res,
struct drm_connector_state *conn_state)
{
- struct dpu_encoder_phys_vid *vid_enc;
-
if (!phys_enc || !hw_res) {
DPU_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
phys_enc != 0, hw_res != 0, conn_state != 0);
return;
}
- vid_enc = to_dpu_encoder_phys_vid(phys_enc);
- if (!vid_enc->hw_intf) {
- DPU_ERROR("invalid arg(s), hw_intf\n");
- return;
- }
-
- DPU_DEBUG_VIDENC(vid_enc, "\n");
- hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO;
+ hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
}
static int _dpu_encoder_phys_vid_wait_for_vblank(
@@ -815,7 +815,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
{
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_vid *vid_enc = NULL;
- struct dpu_rm_hw_iter iter;
struct dpu_encoder_irq *irq;
int i, ret = 0;
@@ -835,26 +834,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
- /**
-* hw_intf resource permanently assigned to this encoder
-* Other resources allocated at atomic commit time by use case
-*/
- dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_INTF);
- while (dpu_rm_get_hw(>dpu_kms->rm, )) {
- struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
-
- if (hw_intf->idx == p->intf_idx) {
- vid_enc->hw_intf = hw_intf;
- break;
- }
- }
-
- if (!vid_enc->hw_intf) {
- ret = -EINVAL;
- DPU_ERROR("failed to get hw_intf\n");
- goto fail;
- }
-
DPU_DEBUG_VIDENC(vid_enc, "\n");
dpu_encoder_phys_vid_init_ops(_enc->ops);
--
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a Linux Foundation Collaborative Project
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[Freedreno] [DPU PATCH v2 07/14] drm/msm/dpu: iterate for assigned hw ctl in virtual encoder
From: Jeykumar Sankaran
Instead of iterating for hw ctrl per physical encoder, this
patch moves the iterations and assignment to the virtual encoder.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 22 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 19 ---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 19 ---
3 files changed, 20 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9f2bd47..6d32a0b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1034,9 +1034,11 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
struct dpu_kms *dpu_kms;
struct list_head *connector_list;
struct drm_connector *conn = NULL, *conn_iter;
- struct dpu_rm_hw_iter pp_iter;
+ struct dpu_rm_hw_iter pp_iter, ctl_iter;
struct msm_display_topology topology;
enum dpu_rm_topology_name topology_name;
+ struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC];
+
int i = 0, ret;
if (!drm_enc) {
@@ -1084,6 +1086,14 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
}
+ dpu_rm_init_hw_iter(_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+ hw_ctl[i] = NULL;
+ if (!dpu_rm_get_hw(_kms->rm, _iter))
+ break;
+ hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
+ }
+
topology_name = dpu_rm_get_topology_name(topology);
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -1091,10 +1101,18 @@ static void dpu_encoder_virt_mode_set(struct
drm_encoder *drm_enc,
if (phys) {
if (!dpu_enc->hw_pp[i]) {
DPU_ERROR_ENC(dpu_enc,
- "invalid pingpong block for the encoder\n");
+ "no pp block assigned at idx: %d\n", i);
return;
}
phys->hw_pp = dpu_enc->hw_pp[i];
+
+ if (!hw_ctl[i]) {
+ DPU_ERROR_ENC(dpu_enc,
+ "no ctl block assigned at idx: %d\n", i);
+ return;
+ }
+ phys->hw_ctl = hw_ctl[i];
+
phys->connector = conn->state->connector;
phys->topology_name = topology_name;
if (phys->ops.mode_set)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b9f7d95..2d974e3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -195,9 +195,6 @@ static void dpu_encoder_phys_cmd_mode_set(
{
struct dpu_encoder_phys_cmd *cmd_enc =
to_dpu_encoder_phys_cmd(phys_enc);
- struct dpu_rm *rm = _enc->dpu_kms->rm;
- struct dpu_rm_hw_iter iter;
- int i, instance;
if (!phys_enc || !mode || !adj_mode) {
DPU_ERROR("invalid args\n");
@@ -207,22 +204,6 @@ static void dpu_encoder_phys_cmd_mode_set(
DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
drm_mode_debug_printmodeline(adj_mode);
- instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
-
- /* Retrieve previously allocated HW Resources. Shouldn't fail */
- dpu_rm_init_hw_iter(, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
- for (i = 0; i <= instance; i++) {
- if (dpu_rm_get_hw(rm, ))
- phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
- }
-
- if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
- DPU_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
- PTR_ERR(phys_enc->hw_ctl));
- phys_enc->hw_ctl = NULL;
- return;
- }
-
_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e9b346c..f0b5762 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -395,9 +395,6 @@ static void dpu_encoder_phys_vid_mode_set(
struct drm_display_mode *mode,
st
[Freedreno] [DPU PATCH v2 06/14] drm/msm/dpu: remove stale encoder code
From: Jeykumar Sankaran
Remove helper function used only by writeback
connectors to trigger final flush before disabling.
Now that write back connectors are stripped down,
the helper is not used.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 64
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 9
2 files changed, 73 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index e98cf70..9f2bd47 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1927,70 +1927,6 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
DPU_ATRACE_END("encoder_kickoff");
}
-int dpu_encoder_helper_hw_release(struct dpu_encoder_phys *phys_enc,
- struct drm_framebuffer *fb)
-{
- struct drm_encoder *drm_enc;
- struct dpu_hw_mixer_cfg mixer;
- struct dpu_rm_hw_iter lm_iter;
- bool lm_valid = false;
-
- if (!phys_enc || !phys_enc->parent) {
- DPU_ERROR("invalid encoder\n");
- return -EINVAL;
- }
-
- drm_enc = phys_enc->parent;
- memset(, 0, sizeof(mixer));
-
- /* reset associated CTL/LMs */
- if (phys_enc->hw_ctl->ops.clear_pending_flush)
- phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
- if (phys_enc->hw_ctl->ops.clear_all_blendstages)
- phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
-
- dpu_rm_init_hw_iter(_iter, drm_enc->base.id, DPU_HW_BLK_LM);
- while (dpu_rm_get_hw(_enc->dpu_kms->rm, _iter)) {
- struct dpu_hw_mixer *hw_lm = (struct dpu_hw_mixer *)lm_iter.hw;
-
- if (!hw_lm)
- continue;
-
- /* need to flush LM to remove it */
- if (phys_enc->hw_ctl->ops.get_bitmask_mixer &&
- phys_enc->hw_ctl->ops.update_pending_flush)
- phys_enc->hw_ctl->ops.update_pending_flush(
- phys_enc->hw_ctl,
- phys_enc->hw_ctl->ops.get_bitmask_mixer(
- phys_enc->hw_ctl, hw_lm->idx));
-
- if (fb) {
- /* assume a single LM if targeting a frame buffer */
- if (lm_valid)
- continue;
-
- mixer.out_height = fb->height;
- mixer.out_width = fb->width;
-
- if (hw_lm->ops.setup_mixer_out)
- hw_lm->ops.setup_mixer_out(hw_lm, );
- }
-
- lm_valid = true;
-
- /* only enable border color on LM */
- if (phys_enc->hw_ctl->ops.setup_blendstage)
- phys_enc->hw_ctl->ops.setup_blendstage(
- phys_enc->hw_ctl, hw_lm->idx, NULL);
- }
-
- if (!lm_valid) {
- DPU_DEBUG_ENC(to_dpu_encoder_virt(drm_enc), "lm not found\n");
- return -EFAULT;
- }
- return 0;
-}
-
void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 15459be..71a037b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -403,15 +403,6 @@ void dpu_encoder_helper_split_config(
enum dpu_intf interface);
/**
- * dpu_encoder_helper_hw_release - prepare for h/w reset during disable
- * @phys_enc: Pointer to physical encoder structure
- * @fb: Optional fb for specifying new mixer output resolution, may be NULL
- * Return: Zero on success
- */
-int dpu_encoder_helper_hw_release(struct dpu_encoder_phys *phys_enc,
- struct drm_framebuffer *fb);
-
-/**
* dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
* timed out, including reporting frame error event to crtc and debug dump
* @phys_enc: Pointer to physical encoder structure
--
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a Linux Foundation Collaborative Project
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[Freedreno] [DPU PATCH v2 03/14] drm/msm/dpu: remove ping pong split topology variables
From: Jeykumar Sankaran
Remove left out variables of previous ping pong
split topology cleanup.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 8e6b6c7..916615d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -242,7 +242,6 @@ struct dpu_crtc {
* @base: Base drm crtc state structure
* @connectors: Currently associated drm connectors
* @num_connectors: Number of associated drm connectors
- * @is_ppsplit: Whether current topology requires PPSplit special handling
* @bw_control: true if bw/clk controlled by core bw/clk properties
* @bw_split_vote : true if bw controlled by llcc/dram bw properties
* @lm_bounds : LM boundaries based on current mode full resolution, no
ROI.
@@ -260,7 +259,6 @@ struct dpu_crtc_state {
bool bw_control;
bool bw_split_vote;
- bool is_ppsplit;
struct dpu_rect lm_bounds[CRTC_DUAL_MIXERS];
uint64_t input_fence_timeout_ns;
--
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[Freedreno] [DPU PATCH v2 02/14] drm/msm/dpu: remove resource pool manager
From: Jeykumar Sankaran
resource pool manager utility was introduced to manage
rotator sessions. Removing the support as the rotator
feature doesn't exist.
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 494 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 86 --
2 files changed, 580 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9ca8325..426e2ad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -98,476 +98,6 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc
*dpu_crtc, bool enable)
return 0;
}
-/**
- * _dpu_crtc_rp_to_crtc - get crtc from resource pool object
- * @rp: Pointer to resource pool
- * return: Pointer to drm crtc if success; null otherwise
- */
-static struct drm_crtc *_dpu_crtc_rp_to_crtc(struct dpu_crtc_respool *rp)
-{
- if (!rp)
- return NULL;
-
- return container_of(rp, struct dpu_crtc_state, rp)->base.crtc;
-}
-
-/**
- * _dpu_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool
- * @rp: Pointer to resource pool
- * @force: True to reclaim all resources; otherwise, reclaim only unused ones
- * return: None
- */
-static void _dpu_crtc_rp_reclaim(struct dpu_crtc_respool *rp, bool force)
-{
- struct dpu_crtc_res *res, *next;
- struct drm_crtc *crtc;
-
- crtc = _dpu_crtc_rp_to_crtc(rp);
- if (!crtc) {
- DPU_ERROR("invalid crtc\n");
- return;
- }
-
- DPU_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id,
- force ? "destroy" : "free_unused");
-
- list_for_each_entry_safe(res, next, >res_list, list) {
- if (!force && !(res->flags & DPU_CRTC_RES_FLAG_FREE))
- continue;
- DPU_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n",
- crtc->base.id, rp->sequence_id,
- res->type, res->tag, res->val,
- atomic_read(>refcount));
- list_del(>list);
- if (res->ops.put)
- res->ops.put(res->val);
- kfree(res);
- }
-}
-
-/**
- * _dpu_crtc_rp_free_unused - free unused resource in pool
- * @rp: Pointer to resource pool
- * return: none
- */
-static void _dpu_crtc_rp_free_unused(struct dpu_crtc_respool *rp)
-{
- mutex_lock(rp->rp_lock);
- _dpu_crtc_rp_reclaim(rp, false);
- mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_rp_destroy - destroy resource pool
- * @rp: Pointer to resource pool
- * return: None
- */
-static void _dpu_crtc_rp_destroy(struct dpu_crtc_respool *rp)
-{
- mutex_lock(rp->rp_lock);
- list_del_init(>rp_list);
- _dpu_crtc_rp_reclaim(rp, true);
- mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_hw_blk_get - get callback for hardware block
- * @val: Resource handle
- * @type: Resource type
- * @tag: Search tag for given resource
- * return: Resource handle
- */
-static void *_dpu_crtc_hw_blk_get(void *val, u32 type, u64 tag)
-{
- DPU_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val);
- return dpu_hw_blk_get(val, type, tag);
-}
-
-/**
- * _dpu_crtc_hw_blk_put - put callback for hardware block
- * @val: Resource handle
- * return: None
- */
-static void _dpu_crtc_hw_blk_put(void *val)
-{
- DPU_DEBUG("res://%pK\n", val);
- dpu_hw_blk_put(val);
-}
-
-/**
- * _dpu_crtc_rp_duplicate - duplicate resource pool and reset reference count
- * @rp: Pointer to original resource pool
- * @dup_rp: Pointer to duplicated resource pool
- * return: None
- */
-static void _dpu_crtc_rp_duplicate(struct dpu_crtc_respool *rp,
- struct dpu_crtc_respool *dup_rp)
-{
- struct dpu_crtc_res *res, *dup_res;
- struct drm_crtc *crtc;
-
- if (!rp || !dup_rp || !rp->rp_head) {
- DPU_ERROR("invalid resource pool\n");
- return;
- }
-
- crtc = _dpu_crtc_rp_to_crtc(rp);
- if (!crtc) {
- DPU_ERROR("invalid crtc\n");
- return;
- }
-
- DPU_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id);
-
- mutex_lock(rp->rp_lock);
- dup_rp->sequence_id = rp->sequence_id + 1;
- INIT_LIST_HEAD(_rp->res_list);
- dup_rp->ops = rp->ops;
- list_for_each_entry(res, >res_list, list) {
- dup_res = kzalloc(sizeof(struct dpu_crtc_res), GFP_KERNEL);
- if (!dup_res) {
- mutex_unlock(rp->rp_lock);
- return;
- }
-
[Freedreno] [DPU PATCH v2 01/14] drm/msm/dpu: remove scalar config definitions
From: Jeykumar Sankaran
cleans up left out scalar config definitions from headers
changes in v2:
- none
Signed-off-by: Jeykumar Sankaran
Signed-off-by: Sravanthi Kollukuduru
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 10 --
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 39def93..2c3857b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -183,7 +183,6 @@ struct dpu_crtc_event {
* @cur_perf : current performance committed to clock/bandwidth driver
* @rp_lock : serialization lock for resource pool
* @rp_head : list of active resource pool
- * @scl3_cfg_lut : qseed3 lut config
*/
struct dpu_crtc {
struct drm_crtc base;
@@ -194,7 +193,6 @@ struct dpu_crtc {
u32 num_mixers;
bool mixers_swapped;
struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
- struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
struct drm_pending_vblank_event *event;
u32 vsync_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 42f1b22..71e8dd1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -148,16 +148,6 @@ struct dpu_hw_scaler3_cfg {
struct dpu_hw_scaler3_de_cfg de;
};
-struct dpu_hw_scaler3_lut_cfg {
- bool is_configured;
- u32 *dir_lut;
- size_t dir_len;
- u32 *cir_lut;
- size_t cir_len;
- u32 *sep_lut;
- size_t sep_len;
-};
-
/**
* struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
* @num_ext_pxls_lr: Number of total horizontal pixels
--
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[Freedreno] [DPU PATCH v2 00/14] Atomic resource management
This patchset introduces drm private object in KMS to manage HW resource management. It modifies the resource manager by introducing API's to do per DRM object resource allocation/cleanups. The patchset is based on: https://patchwork.kernel.org/patch/10461375/ major changes in v2: - Fix return values in kms (Jordan) - Split irrelevant changes from master patch into separate patches (Sean) Jeykumar Sankaran (14): drm/msm/dpu: remove scalar config definitions drm/msm/dpu: remove resource pool manager drm/msm/dpu: remove ping pong split topology variables drm/msm/dpu: program master-slave encoders explicitly drm/msm/dpu: use kms stored hw mdp block drm/msm/dpu: remove stale encoder code drm/msm/dpu: iterate for assigned hw ctl in virtual encoder drm/msm/dpu: avoid querying for hw intf before assignment drm/msm/dpu: move hw resource tracking to crtc state drm/msm/dpu: rename hw_ctl to lm_ctl drm/msm/dpu: remove topology name drm/msm/dpu: remove display H_TILE from encoder drm/msm/dpu: add atomic private object to dpu kms drm/msm/dpu: use private obj to track hw resources drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 711 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 150 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 229 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 4 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 18 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 31 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 88 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h| 10 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 84 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h| 23 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 805 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++-- 12 files changed, 609 insertions(+), 1693 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH v2 0/2] Add hardware catalog information in driver source for SDM845
This patch series aims at adding the target specific hardware catalog information in driver source. As a result, the current logic of dt based parsing is removed. The DT clean up patch corresponding to this driver change will be posted separately. [V2] * Addressed Rob Herring's comment to update the commit message. * Addressed Sean's comment to restructure the catalog data in a way that different hardware versions can reuse. - Removed the target specific catalog file and moved the initialization logic to the main catalog file. Updated the driver patch title to reflect the same. - Added config handler structure to define the mapping between the hardware versions read from the register and the respective config init functions. - Added new structures for various sub blocks of the dpu driver and also, for any common configuration shared by the different blocks. Sravanthi Kollukuduru (2): dt-bindings: msm/disp: Remove hw block offset DT entries for SDM845 drm/msm: Add hardware catalog data in driver source for SDM845 .../devicetree/bindings/display/msm/dpu.txt| 530 --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3542 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 124 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c|2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c |2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 24 +- 10 files changed, 636 insertions(+), 3617 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH 1/2] dt-bindings: msm/disp: Remove hw block offset DT entries for SDM845
Remove DT entries of hw block offsets and other target specific catalog information for SDM845. Signed-off-by: Sravanthi Kollukuduru <skoll...@codeaurora.org> --- .../devicetree/bindings/display/msm/dpu.txt| 530 - 1 file changed, 530 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index 136f0d3..90cd3e0 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -19,61 +19,6 @@ Required properties - interrupt-controller: Mark the device node as an interrupt controller. - #interrupt-cells: Should be one. The first cell is interrupt number. - iommus: Specifies the SID's used by this context bank. -- qcom,dpu-sspp-type: Array of strings for DPU source surface pipes type information. - A source pipe can be "vig", "rgb", "dma" or "cursor" type. - Number of xin ids defined should match the number of offsets - defined in property: qcom,dpu-sspp-off. -- qcom,dpu-sspp-off: Array of offset for DPU source surface pipes. The offsets - are calculated from register "mdp_phys" defined in - reg property + "dpu-off". The number of offsets defined here should - reflect the amount of pipes that can be active in DPU for - this configuration. -- qcom,dpu-sspp-xin-id:Array of VBIF clients ids (xins) corresponding - to the respective source pipes. Number of xin ids - defined should match the number of offsets - defined in property: qcom,dpu-sspp-off. -- qcom,dpu-ctl-off:Array of offset addresses for the available ctl - hw blocks within DPU, these offsets are - calculated from register "mdp_phys" defined in - reg property. The number of ctl offsets defined - here should reflect the number of control paths - that can be configured concurrently on DPU for - this configuration. -- qcom,dpu-wb-off: Array of offset addresses for the programmable - writeback blocks within DPU. -- qcom,dpu-wb-xin-id: Array of VBIF clients ids (xins) corresponding - to the respective writeback. Number of xin ids - defined should match the number of offsets - defined in property: qcom,dpu-wb-off. -- qcom,dpu-mixer-off: Array of offset addresses for the available - mixer blocks that can drive data to panel - interfaces. These offsets are be calculated from - register "mdp_phys" defined in reg property. - The number of offsets defined should reflect the - amount of mixers that can drive data to a panel - interface. -- qcom,dpu-dspp-top-off: Offset address for the dspp top block. - The offset is calculated from register "mdp_phys" - defined in reg property. -- qcom,dpu-dspp-off: Array of offset addresses for the available dspp - blocks. These offsets are calculated from - register "mdp_phys" defined in reg property. -- qcom,dpu-pp-off: Array of offset addresses for the available - pingpong blocks. These offsets are calculated - from register "mdp_phys" defined in reg property. -- qcom,dpu-pp-slave: Array of flags indicating whether each ping pong - block may be configured as a pp slave. -- qcom,dpu-intf-off: Array of offset addresses for the available DPU - interface blocks that can drive data to a - panel controller. The offsets are calculated - from "mdp_phys" defined in reg property. The number - of offsets defined should reflect the number of - programmable interface blocks available in hardware. -- qcom,dpu-mixer-blend-op-off Array of offset addresses for the available - blending stages. The offsets are relative to
[Freedreno] [DPU PATCH 0/2] Add hardware catalog information in driver source for SDM845
This patch series aims at adding the target specific hardware catalog information in driver source. As a result, the current logic of dt based parsing is removed. The DT clean up patch corresponding to this driver change will be posted separately. Sravanthi Kollukuduru (2): dt-bindings: msm/disp: Remove hw block offset DT entries for SDM845 drm/msm: Add hardware catalog file for SDM845 .../devicetree/bindings/display/msm/dpu.txt| 530 drivers/gpu/drm/msm/Makefile |1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3071 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog_sdm845.c | 744 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|2 +- 6 files changed, 767 insertions(+), 3598 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_sdm845.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [DPU PATCH] drm/msm: fix compilation warnings in display driver
Fix the compilation warnings flagged in display driver.
Signed-off-by: Sravanthi Kollukuduru <skoll...@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 36a4795..ccf25a3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -592,15 +592,12 @@ void dpu_core_perf_crtc_update(struct drm_crtc *crtc,
DPU_EVT32(kms->dev, stop_req, clk_rate);
- /* Temp change to avoid crash in clk_set_rate API. */
-#ifdef QCOM_DPU_SET_CLK
if (dpu_power_clk_set_rate(>phandle,
kms->perf.clk_name, clk_rate)) {
DPU_ERROR("failed to set %s clock rate %llu\n",
kms->perf.clk_name, clk_rate);
return;
}
-#endif
kms->perf.core_clk_rate = clk_rate;
DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
index bb45477..e0d46c5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
@@ -374,7 +374,7 @@ static int validate_dma_cfg(struct
dpu_reg_dma_setup_ops_cfg *cfg)
}
if (cfg->dma_buf->iova & GUARD_BYTES || !cfg->dma_buf->vaddr) {
- DRM_ERROR("iova not aligned to %zx iova %x kva %pK",
+ DRM_ERROR("iova not aligned to %zx iova %llx kva %pK",
ADDR_ALIGN, cfg->dma_buf->iova,
cfg->dma_buf->vaddr);
return -EINVAL;
@@ -433,7 +433,7 @@ static int validate_kick_off_v1(struct
dpu_reg_dma_kickoff_cfg *cfg)
(WRITE_TRIGGER);
if (cfg->dma_buf->iova & GUARD_BYTES) {
- DRM_ERROR("Address is not aligned to %zx iova %x", ADDR_ALIGN,
+ DRM_ERROR("Address is not aligned to %zx iova %llx", ADDR_ALIGN,
cfg->dma_buf->iova);
return -EINVAL;
}
--
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