Re: [Freedreno] [PATCH 3/4] drm/msm/dpu: Add SC8180x to hw catalog

2021-05-17 Thread Rob Herring 
On Mon, May 10, 2021 at 11:18:51PM -0500, Bjorn Andersson wrote:
> From: Rob Clark 
> 
> Add SC8180x to the hardware catalog, for initial support for the
> platform. Due to limitations in the DP driver only one of the four DP
> interfaces is left enabled.
> 
> The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
> the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
> is flagged appropriately to ensure widebus is disabled - for now.
> 
> Signed-off-by: Rob Clark 
> Signed-off-by: Bjorn Andersson 
> ---
>  .../devicetree/bindings/display/msm/dpu.txt   |   4 +-

This is getting converted to schema. Please help that along (it needs 
it).

>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 121 ++
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   3 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   1 +
>  drivers/gpu/drm/msm/msm_drv.c |   1 +
>  5 files changed, 128 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt 
> b/Documentation/devicetree/bindings/display/msm/dpu.txt
> index 586e6eac5b08..b98258374a60 100644
> --- a/Documentation/devicetree/bindings/display/msm/dpu.txt
> +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
> @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
>  
>  MDSS:
>  Required properties:
> -- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss"
> +- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sc8180x-mdss"
>  - reg: physical base address and length of controller's registers.
>  - reg-names: register region names. The following region is required:
>* "mdss"
> @@ -41,7 +41,7 @@ Optional properties:
>  
>  MDP:
>  Required properties:
> -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
> +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sc8180x-dpu"
>  - reg: physical base address and length of controller's registers.
>  - reg-names : register region names. The following region is required:
>* "mdp"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b569030a0847..81c429ce94a9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -56,6 +56,10 @@
>  
>  #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
>  
> +#define INTF_SC8180X_MASK BIT(DPU_INTF_INPUT_CTRL) | \
> +   BIT(DPU_INTF_TE) | \
> +   BIT(DPU_INTF_WIDEBUS)
> +
>  #define INTR_SC7180_MASK \
>   (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
>   BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
> @@ -197,6 +201,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
>   .max_vdeci_exp = MAX_VERT_DECIMATION,
>  };
>  
> +static const struct dpu_caps sc8180_dpu_caps = {
> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> + .max_mixer_blendstages = 0xb,
> + .qseed_type = DPU_SSPP_SCALER_QSEED3,
> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> + .ubwc_version = DPU_HW_UBWC_VER_30,
> + .has_src_split = true,
> + .has_dim_layer = true,
> + .has_idle_pc = true,
> + .has_3d_merge = false,   /* I think? */
> + .max_linewidth = 4096,
> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> + .max_hdeci_exp = MAX_HORZ_DECIMATION,
> + .max_vdeci_exp = MAX_VERT_DECIMATION,
> +};
> +
>  static const struct dpu_caps sm8250_dpu_caps = {
>   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
>   .max_mixer_blendstages = 0xb,
> @@ -265,6 +285,35 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
>   },
>  };
>  
> +static const struct dpu_mdp_cfg sc8180_mdp[] = {
> + {
> + .name = "top_0", .id = MDP_TOP,
> + // TODO check len
> + .base = 0x0, .len = 0x45C,
> + .features = 0,
> + .highest_bank_bit = 0x3,
> + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> + .reg_off = 0x2AC, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> + .reg_off = 0x2B4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> + .reg_off = 0x2BC, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> + .reg_off = 0x2C4, .bit_off = 0},
> + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> + .reg_off = 0x2AC, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> + .reg_off = 0x2B4, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> + .reg_off = 0x2BC, .bit_off = 8},
> + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> + .reg_off = 0x2C4, .bit_off = 8},
> +// TODO ???
> +//   .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> +//   .reg_off = 0x2BC, .bit_off = 20},
> + },
> +};
> +
>  static const struct dpu_mdp_cfg sm8250_mdp[] = {
>   {
>   .name = "top_0", .id = MDP_TOP,
> @@ -789,6 +838,15 @@ static const struct dpu_intf_cfg sc7280_i

Re: [Freedreno] [PATCH 3/4] drm/msm/dpu: Add SC8180x to hw catalog

2021-05-15 Thread Bjorn Andersson 
On Wed 12 May 17:58 CDT 2021, Dmitry Baryshkov wrote:

> On Tue, 11 May 2021 at 07:19, Bjorn Andersson
>  wrote:
> >
> > From: Rob Clark 
> >
> > Add SC8180x to the hardware catalog, for initial support for the
> > platform. Due to limitations in the DP driver only one of the four DP
> > interfaces is left enabled.
> >
> > The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
> > the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
> > is flagged appropriately to ensure widebus is disabled - for now.
> >
> > Signed-off-by: Rob Clark 
> > Signed-off-by: Bjorn Andersson 
> > ---
> >  .../devicetree/bindings/display/msm/dpu.txt   |   4 +-
> >  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 121 ++
> >  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   3 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   1 +
> >  drivers/gpu/drm/msm/msm_drv.c |   1 +
> >  5 files changed, 128 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt 
> > b/Documentation/devicetree/bindings/display/msm/dpu.txt
> > index 586e6eac5b08..b98258374a60 100644
> > --- a/Documentation/devicetree/bindings/display/msm/dpu.txt
> > +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
> > @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
> >
> >  MDSS:
> >  Required properties:
> > -- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss"
> > +- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sc8180x-mdss"
> >  - reg: physical base address and length of controller's registers.
> >  - reg-names: register region names. The following region is required:
> >* "mdss"
> > @@ -41,7 +41,7 @@ Optional properties:
> >
> >  MDP:
> >  Required properties:
> > -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
> > +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sc8180x-dpu"
> >  - reg: physical base address and length of controller's registers.
> >  - reg-names : register region names. The following region is required:
> >* "mdp"
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index b569030a0847..81c429ce94a9 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -56,6 +56,10 @@
> >
> >  #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
> >
> > +#define INTF_SC8180X_MASK BIT(DPU_INTF_INPUT_CTRL) | \
> > + BIT(DPU_INTF_TE) | \
> > + BIT(DPU_INTF_WIDEBUS)
> > +
> >  #define INTR_SC7180_MASK \
> > (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
> > BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
> > @@ -197,6 +201,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
> > .max_vdeci_exp = MAX_VERT_DECIMATION,
> >  };
> >
> > +static const struct dpu_caps sc8180_dpu_caps = {
> > +   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > +   .max_mixer_blendstages = 0xb,
> > +   .qseed_type = DPU_SSPP_SCALER_QSEED3,
> 
> Is it qseed3 or qseed3lite?
> 
> > +   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > +   .ubwc_version = DPU_HW_UBWC_VER_30,
> > +   .has_src_split = true,
> > +   .has_dim_layer = true,
> > +   .has_idle_pc = true,
> > +   .has_3d_merge = false,   /* I think? */
> 
> Hmm. Are you sure? Judging from two DSI interfaces you might have merge3d.
> 
> > +   .max_linewidth = 4096,
> > +   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > +   .max_hdeci_exp = MAX_HORZ_DECIMATION,
> > +   .max_vdeci_exp = MAX_VERT_DECIMATION,
> > +};
> > +
> >  static const struct dpu_caps sm8250_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0xb,
> > @@ -265,6 +285,35 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
> > },
> >  };
> >
> > +static const struct dpu_mdp_cfg sc8180_mdp[] = {
> > +   {
> > +   .name = "top_0", .id = MDP_TOP,
> > +   // TODO check len
> > +   .base = 0x0, .len = 0x45C,
> > +   .features = 0,
> > +   .highest_bank_bit = 0x3,
> > +   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > +   .reg_off = 0x2AC, .bit_off = 0},
> > +   .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > +   .reg_off = 0x2B4, .bit_off = 0},
> > +   .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > +   .reg_off = 0x2BC, .bit_off = 0},
> > +   .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > +   .reg_off = 0x2C4, .bit_off = 0},
> > +   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > +   .reg_off = 0x2AC, .bit_off = 8},
> > +   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > +   .reg_off = 0x2B4, .bit_off = 8},
> > +   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > +   .reg_off = 0x2BC, .bit_off = 8},
> > +   .clk_ctrls[DPU_CLK_CTR

Re: [Freedreno] [PATCH 3/4] drm/msm/dpu: Add SC8180x to hw catalog

2021-05-12 Thread Dmitry Baryshkov 
On Tue, 11 May 2021 at 07:19, Bjorn Andersson
 wrote:
>
> From: Rob Clark 
>
> Add SC8180x to the hardware catalog, for initial support for the
> platform. Due to limitations in the DP driver only one of the four DP
> interfaces is left enabled.
>
> The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
> the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
> is flagged appropriately to ensure widebus is disabled - for now.
>
> Signed-off-by: Rob Clark 
> Signed-off-by: Bjorn Andersson 
> ---
>  .../devicetree/bindings/display/msm/dpu.txt   |   4 +-
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 121 ++
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   3 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   1 +
>  drivers/gpu/drm/msm/msm_drv.c |   1 +
>  5 files changed, 128 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt 
> b/Documentation/devicetree/bindings/display/msm/dpu.txt
> index 586e6eac5b08..b98258374a60 100644
> --- a/Documentation/devicetree/bindings/display/msm/dpu.txt
> +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
> @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
>
>  MDSS:
>  Required properties:
> -- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss"
> +- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sc8180x-mdss"
>  - reg: physical base address and length of controller's registers.
>  - reg-names: register region names. The following region is required:
>* "mdss"
> @@ -41,7 +41,7 @@ Optional properties:
>
>  MDP:
>  Required properties:
> -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
> +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sc8180x-dpu"
>  - reg: physical base address and length of controller's registers.
>  - reg-names : register region names. The following region is required:
>* "mdp"
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b569030a0847..81c429ce94a9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -56,6 +56,10 @@
>
>  #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
>
> +#define INTF_SC8180X_MASK BIT(DPU_INTF_INPUT_CTRL) | \
> + BIT(DPU_INTF_TE) | \
> + BIT(DPU_INTF_WIDEBUS)
> +
>  #define INTR_SC7180_MASK \
> (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
> BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
> @@ -197,6 +201,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
> .max_vdeci_exp = MAX_VERT_DECIMATION,
>  };
>
> +static const struct dpu_caps sc8180_dpu_caps = {
> +   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> +   .max_mixer_blendstages = 0xb,
> +   .qseed_type = DPU_SSPP_SCALER_QSEED3,

Is it qseed3 or qseed3lite?

> +   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> +   .ubwc_version = DPU_HW_UBWC_VER_30,
> +   .has_src_split = true,
> +   .has_dim_layer = true,
> +   .has_idle_pc = true,
> +   .has_3d_merge = false,   /* I think? */

Hmm. Are you sure? Judging from two DSI interfaces you might have merge3d.

> +   .max_linewidth = 4096,
> +   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> +   .max_hdeci_exp = MAX_HORZ_DECIMATION,
> +   .max_vdeci_exp = MAX_VERT_DECIMATION,
> +};
> +
>  static const struct dpu_caps sm8250_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .max_mixer_blendstages = 0xb,
> @@ -265,6 +285,35 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
> },
>  };
>
> +static const struct dpu_mdp_cfg sc8180_mdp[] = {
> +   {
> +   .name = "top_0", .id = MDP_TOP,
> +   // TODO check len
> +   .base = 0x0, .len = 0x45C,
> +   .features = 0,
> +   .highest_bank_bit = 0x3,
> +   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> +   .reg_off = 0x2AC, .bit_off = 0},
> +   .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> +   .reg_off = 0x2B4, .bit_off = 0},
> +   .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> +   .reg_off = 0x2BC, .bit_off = 0},
> +   .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> +   .reg_off = 0x2C4, .bit_off = 0},
> +   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> +   .reg_off = 0x2AC, .bit_off = 8},
> +   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> +   .reg_off = 0x2B4, .bit_off = 8},
> +   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> +   .reg_off = 0x2BC, .bit_off = 8},
> +   .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> +   .reg_off = 0x2C4, .bit_off = 8},
> +// TODO ???
> +// .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
> +// .reg_off = 0x2BC, .bit_off = 20},
> +   },
> +};
> +
>  static const struct dpu_mdp_cfg sm8250_mdp[] = {
> {
>

[Freedreno] [PATCH 3/4] drm/msm/dpu: Add SC8180x to hw catalog

2021-05-10 Thread Bjorn Andersson 
From: Rob Clark 

Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.

The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
is flagged appropriately to ensure widebus is disabled - for now.

Signed-off-by: Rob Clark 
Signed-off-by: Bjorn Andersson 
---
 .../devicetree/bindings/display/msm/dpu.txt   |   4 +-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 121 ++
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   3 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   1 +
 drivers/gpu/drm/msm/msm_drv.c |   1 +
 5 files changed, 128 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt 
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index 586e6eac5b08..b98258374a60 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
 
 MDSS:
 Required properties:
-- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss"
+- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sc8180x-mdss"
 - reg: physical base address and length of controller's registers.
 - reg-names: register region names. The following region is required:
   * "mdss"
@@ -41,7 +41,7 @@ Optional properties:
 
 MDP:
 Required properties:
-- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sc8180x-dpu"
 - reg: physical base address and length of controller's registers.
 - reg-names : register region names. The following region is required:
   * "mdp"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b569030a0847..81c429ce94a9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -56,6 +56,10 @@
 
 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
 
+#define INTF_SC8180X_MASK BIT(DPU_INTF_INPUT_CTRL) | \
+ BIT(DPU_INTF_TE) | \
+ BIT(DPU_INTF_WIDEBUS)
+
 #define INTR_SC7180_MASK \
(BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
@@ -197,6 +201,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
.max_vdeci_exp = MAX_VERT_DECIMATION,
 };
 
+static const struct dpu_caps sc8180_dpu_caps = {
+   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+   .max_mixer_blendstages = 0xb,
+   .qseed_type = DPU_SSPP_SCALER_QSEED3,
+   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+   .ubwc_version = DPU_HW_UBWC_VER_30,
+   .has_src_split = true,
+   .has_dim_layer = true,
+   .has_idle_pc = true,
+   .has_3d_merge = false,   /* I think? */
+   .max_linewidth = 4096,
+   .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+   .max_hdeci_exp = MAX_HORZ_DECIMATION,
+   .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
 static const struct dpu_caps sm8250_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -265,6 +285,35 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
},
 };
 
+static const struct dpu_mdp_cfg sc8180_mdp[] = {
+   {
+   .name = "top_0", .id = MDP_TOP,
+   // TODO check len
+   .base = 0x0, .len = 0x45C,
+   .features = 0,
+   .highest_bank_bit = 0x3,
+   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+   .reg_off = 0x2AC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+   .reg_off = 0x2B4, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+   .reg_off = 0x2BC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+   .reg_off = 0x2C4, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+   .reg_off = 0x2AC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+   .reg_off = 0x2BC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+   .reg_off = 0x2C4, .bit_off = 8},
+// TODO ???
+// .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+// .reg_off = 0x2BC, .bit_off = 20},
+   },
+};
+
 static const struct dpu_mdp_cfg sm8250_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -789,6 +838,15 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK),
 };
 
+static const struct dpu_intf_cfg sc8180x_intf[] = {
+// INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC8180X_MASK),
+   INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0,