Re: [Freedreno] [PATCH v1 3/3] drm/msm/dpu: simplify interrupt managing
On 16/05/2021 08:24, Bjorn Andersson wrote:
On Sun 11 Apr 19:09 CDT 2021, Dmitry Baryshkov wrote:
Change huge lookup table to contain just sensible entries. IRQ index is
now not an index in the table, but just register id (multiplied by 32,
the amount of IRQs in the register) plus offset in the register. This
allows us to remove all the "reserved" entries from dpu_irq_map. The
table is now only used for lookups, individual functions calculate
register and mask using the irq_idx.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 10 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1151 +++--
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |4 +-
3 files changed, 196 insertions(+), 969 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index fd11a2aeab6c..4e2ad03df903 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -70,7 +70,7 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int
irq_idx)
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -133,7 +133,7 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms,
int irq_idx)
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -208,7 +208,7 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms,
int irq_idx,
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -243,7 +243,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms
*dpu_kms, int irq_idx,
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -328,7 +328,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
spin_lock_init(&dpu_kms->irq_obj.cb_lock);
/* Create irq callbacks for all possible irq_idx */
- dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
+ dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
sizeof(struct list_head), GFP_KERNEL);
dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 8bd22e060437..2cb6800047c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -32,142 +32,142 @@
/**
* WB interrupt status bit definitions
*/
-#define DPU_INTR_WB_0_DONE BIT(0)
-#define DPU_INTR_WB_1_DONE BIT(1)
-#define DPU_INTR_WB_2_DONE BIT(4)
+#define DPU_INTR_WB_0_DONE 0
+#define DPU_INTR_WB_1_DONE 1
+#define DPU_INTR_WB_2_DONE 4
/**
* WDOG timer interrupt status bit definitions
*/
-#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
-#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
-#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
-#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
-#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
+#define DPU_INTR_WD_TIMER_0_DONE 2
+#define DPU_INTR_WD_TIMER_1_DONE 3
+#define DPU_INTR_WD_TIMER_2_DONE 5
+#define DPU_INTR_WD_TIMER_3_DONE 6
+#define DPU_INTR_WD_TIMER_4_DONE 7
/**
* Pingpong interrupt status bit definitions
*/
-#define DPU_INTR_PING_PONG_0_DONE BIT(8)
-#define DPU_INTR_PING_PONG_1_DONE BIT(9)
-#define DPU_INTR_PING_PONG_2_DONE BIT(10)
-#define DPU_INTR_PING_PONG_3_DONE BIT(11)
-#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
-#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
-#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
-#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
-#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
-#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
-#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
-#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
-#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
-#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
-#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
-#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
+#define DPU_INTR_PING_PONG_0_DONE 8
+#define D
Re: [Freedreno] [PATCH v1 3/3] drm/msm/dpu: simplify interrupt managing
On Sun, 16 May 2021 at 08:24, Bjorn Andersson
wrote:
>
> On Sun 11 Apr 19:09 CDT 2021, Dmitry Baryshkov wrote:
>
> > Change huge lookup table to contain just sensible entries. IRQ index is
> > now not an index in the table, but just register id (multiplied by 32,
> > the amount of IRQs in the register) plus offset in the register. This
> > allows us to remove all the "reserved" entries from dpu_irq_map. The
> > table is now only used for lookups, individual functions calculate
> > register and mask using the irq_idx.
> >
> > Signed-off-by: Dmitry Baryshkov
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 10 +-
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1151 +++--
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |4 +-
> > 3 files changed, 196 insertions(+), 969 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> > index fd11a2aeab6c..4e2ad03df903 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> > @@ -70,7 +70,7 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms,
> > int irq_idx)
> > return -EINVAL;
> > }
> >
> > - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> > + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> > DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> > return -EINVAL;
> > }
> > @@ -133,7 +133,7 @@ static int _dpu_core_irq_disable(struct dpu_kms
> > *dpu_kms, int irq_idx)
> > return -EINVAL;
> > }
> >
> > - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> > + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> > DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> > return -EINVAL;
> > }
> > @@ -208,7 +208,7 @@ int dpu_core_irq_register_callback(struct dpu_kms
> > *dpu_kms, int irq_idx,
> > return -EINVAL;
> > }
> >
> > - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> > + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> > DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> > return -EINVAL;
> > }
> > @@ -243,7 +243,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms
> > *dpu_kms, int irq_idx,
> > return -EINVAL;
> > }
> >
> > - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> > + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> > DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> > return -EINVAL;
> > }
> > @@ -328,7 +328,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
> > spin_lock_init(&dpu_kms->irq_obj.cb_lock);
> >
> > /* Create irq callbacks for all possible irq_idx */
> > - dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
> > + dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
> > dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
> > sizeof(struct list_head), GFP_KERNEL);
> > dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > index 8bd22e060437..2cb6800047c3 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > @@ -32,142 +32,142 @@
> > /**
> > * WB interrupt status bit definitions
> > */
> > -#define DPU_INTR_WB_0_DONE BIT(0)
> > -#define DPU_INTR_WB_1_DONE BIT(1)
> > -#define DPU_INTR_WB_2_DONE BIT(4)
> > +#define DPU_INTR_WB_0_DONE 0
> > +#define DPU_INTR_WB_1_DONE 1
> > +#define DPU_INTR_WB_2_DONE 4
> >
> > /**
> > * WDOG timer interrupt status bit definitions
> > */
> > -#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
> > -#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
> > -#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
> > -#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
> > -#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
> > +#define DPU_INTR_WD_TIMER_0_DONE 2
> > +#define DPU_INTR_WD_TIMER_1_DONE 3
> > +#define DPU_INTR_WD_TIMER_2_DONE 5
> > +#define DPU_INTR_WD_TIMER_3_DONE 6
> > +#define DPU_INTR_WD_TIMER_4_DONE 7
> >
> > /**
> > * Pingpong interrupt status bit definitions
> > */
> > -#define DPU_INTR_PING_PONG_0_DONE BIT(8)
> > -#define DPU_INTR_PING_PONG_1_DONE BIT(9)
> > -#define DPU_INTR_PING_PONG_2_DONE BIT(10)
> > -#define DPU_INTR_PING_PONG_3_DONE BIT(11)
> > -#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
> > -#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
> > -#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
> > -#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
> > -#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
> > -#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
> > -#
Re: [Freedreno] [PATCH v1 3/3] drm/msm/dpu: simplify interrupt managing
On Sun 11 Apr 19:09 CDT 2021, Dmitry Baryshkov wrote:
> Change huge lookup table to contain just sensible entries. IRQ index is
> now not an index in the table, but just register id (multiplied by 32,
> the amount of IRQs in the register) plus offset in the register. This
> allows us to remove all the "reserved" entries from dpu_irq_map. The
> table is now only used for lookups, individual functions calculate
> register and mask using the irq_idx.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 10 +-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1151 +++--
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |4 +-
> 3 files changed, 196 insertions(+), 969 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index fd11a2aeab6c..4e2ad03df903 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -70,7 +70,7 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms,
> int irq_idx)
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -133,7 +133,7 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms,
> int irq_idx)
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -208,7 +208,7 @@ int dpu_core_irq_register_callback(struct dpu_kms
> *dpu_kms, int irq_idx,
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -243,7 +243,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms
> *dpu_kms, int irq_idx,
> return -EINVAL;
> }
>
> - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> return -EINVAL;
> }
> @@ -328,7 +328,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
> spin_lock_init(&dpu_kms->irq_obj.cb_lock);
>
> /* Create irq callbacks for all possible irq_idx */
> - dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
> + dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
> dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
> sizeof(struct list_head), GFP_KERNEL);
> dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 8bd22e060437..2cb6800047c3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -32,142 +32,142 @@
> /**
> * WB interrupt status bit definitions
> */
> -#define DPU_INTR_WB_0_DONE BIT(0)
> -#define DPU_INTR_WB_1_DONE BIT(1)
> -#define DPU_INTR_WB_2_DONE BIT(4)
> +#define DPU_INTR_WB_0_DONE 0
> +#define DPU_INTR_WB_1_DONE 1
> +#define DPU_INTR_WB_2_DONE 4
>
> /**
> * WDOG timer interrupt status bit definitions
> */
> -#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
> -#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
> -#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
> -#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
> -#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
> +#define DPU_INTR_WD_TIMER_0_DONE 2
> +#define DPU_INTR_WD_TIMER_1_DONE 3
> +#define DPU_INTR_WD_TIMER_2_DONE 5
> +#define DPU_INTR_WD_TIMER_3_DONE 6
> +#define DPU_INTR_WD_TIMER_4_DONE 7
>
> /**
> * Pingpong interrupt status bit definitions
> */
> -#define DPU_INTR_PING_PONG_0_DONE BIT(8)
> -#define DPU_INTR_PING_PONG_1_DONE BIT(9)
> -#define DPU_INTR_PING_PONG_2_DONE BIT(10)
> -#define DPU_INTR_PING_PONG_3_DONE BIT(11)
> -#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
> -#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
> -#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
> -#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
> -#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
> -#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
> -#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
> -#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
> -#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
> -#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
> -#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
> -#de
[Freedreno] [PATCH v1 3/3] drm/msm/dpu: simplify interrupt managing
Change huge lookup table to contain just sensible entries. IRQ index is
now not an index in the table, but just register id (multiplied by 32,
the amount of IRQs in the register) plus offset in the register. This
allows us to remove all the "reserved" entries from dpu_irq_map. The
table is now only used for lookups, individual functions calculate
register and mask using the irq_idx.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 10 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1151 +++--
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |4 +-
3 files changed, 196 insertions(+), 969 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index fd11a2aeab6c..4e2ad03df903 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -70,7 +70,7 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int
irq_idx)
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -133,7 +133,7 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms,
int irq_idx)
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -208,7 +208,7 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms,
int irq_idx,
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -243,7 +243,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms
*dpu_kms, int irq_idx,
return -EINVAL;
}
- if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+ if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
}
@@ -328,7 +328,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
spin_lock_init(&dpu_kms->irq_obj.cb_lock);
/* Create irq callbacks for all possible irq_idx */
- dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
+ dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
sizeof(struct list_head), GFP_KERNEL);
dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 8bd22e060437..2cb6800047c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -32,142 +32,142 @@
/**
* WB interrupt status bit definitions
*/
-#define DPU_INTR_WB_0_DONE BIT(0)
-#define DPU_INTR_WB_1_DONE BIT(1)
-#define DPU_INTR_WB_2_DONE BIT(4)
+#define DPU_INTR_WB_0_DONE 0
+#define DPU_INTR_WB_1_DONE 1
+#define DPU_INTR_WB_2_DONE 4
/**
* WDOG timer interrupt status bit definitions
*/
-#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
-#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
-#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
-#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
-#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
+#define DPU_INTR_WD_TIMER_0_DONE 2
+#define DPU_INTR_WD_TIMER_1_DONE 3
+#define DPU_INTR_WD_TIMER_2_DONE 5
+#define DPU_INTR_WD_TIMER_3_DONE 6
+#define DPU_INTR_WD_TIMER_4_DONE 7
/**
* Pingpong interrupt status bit definitions
*/
-#define DPU_INTR_PING_PONG_0_DONE BIT(8)
-#define DPU_INTR_PING_PONG_1_DONE BIT(9)
-#define DPU_INTR_PING_PONG_2_DONE BIT(10)
-#define DPU_INTR_PING_PONG_3_DONE BIT(11)
-#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
-#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
-#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
-#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
-#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
-#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
-#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
-#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
-#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
-#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
-#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
-#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
+#define DPU_INTR_PING_PONG_0_DONE 8
+#define DPU_INTR_PING_PONG_1_DONE 9
+#define DPU_INTR_PING_PONG_2_DONE 10
+#define DPU_INTR_PING_PO
