Re: [Freedreno] [PATCH v2 1/4] dt-bindings: display: msm: Convert GMU bindings to YAML
On Thu, Feb 20, 2020 at 11:26:53AM -0700, Jordan Crouse wrote:
> Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
> text bindings.
>
> Signed-off-by: Jordan Crouse
> ---
>
> .../devicetree/bindings/display/msm/gmu.txt| 116 --
> .../devicetree/bindings/display/msm/gmu.yaml | 130
> +
> 2 files changed, 130 insertions(+), 116 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
> create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml
> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
> b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> new file mode 100644
> index 000..776ff92
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
> +%YAML 1.2
> +---
> +
> +$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Devicetree bindings for the GMU attached to certain Adreno GPUs
> +
> +maintainers:
> + - Rob Clark
> +
> +description: |
> + These bindings describe the Graphics Management Unit (GMU) that is attached
> + to members of the Adreno A6xx GPU family. The GMU provides on-device power
> + management and support to improve power efficiency and reduce the load on
> + the CPU.
> +
> +properties:
> + compatible:
> +items:
> + - enum:
> + - qcom,adreno-gmu-630.2
> + - const: qcom,adreno-gmu
> +
> + reg:
> +items:
> + - description: Core GMU registers
> + - description: GMU PDC registers
> + - description: GMU PDC sequence registers
> +
> + reg-names:
> +items:
> + - const: gmu
> + - const: gmu_pdc
> + - const: gmu_pdc_seq
> +
> + clocks:
> +items:
> + - description: GMU clock
> + - description: GPU CX clock
> + - description: GPU AXI clock
> + - description: GPU MEMNOC clock
> +
> + clock-names:
> +items:
> + - const: gmu
> + - const: cxo
> + - const: axi
> + - const: memnoc
> +
> + interrupts:
> +items:
> + - description: GMU HFI interrupt
> + - description: GMU interrupt
> +
> +
> + interrupt-names:
> +items:
> + - const: hfi
> + - const: gmu
> +
> + power-domains:
> + items:
> + - description: CX power domain
> + - description: GX power domain
> +
> + power-domain-names:
> + items:
> + - const: cx
> + - const: gx
> +
> + iommus:
> +$ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type. Just need to define how many entries (maxItems).
> +description:
> + Phandle to a IOMMU device and stream ID. Refer to
> ../../iommu/iommu.txt
> + for more information.
Drop. That's all iommus entries.
> +
> + operating-points-v2:
> +$ref: /schemas/types.yaml#/definitions/phandle
> +description:
> + Phandle to the OPP table for the available GMU frequencies. Refer to
> + ../../opp/opp.txt for more information.
Just 'true' is enough here.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - power-domains
> + - power-domain-names
> + - iommus
> + - operating-points-v2
> +
> +examples:
> + - |
> + #include
> + #include
> + #include
> + #include
> +
> + gmu: gmu@506a000 {
> +compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
> +
> +reg = <0x506a000 0x3>,
> + <0xb28 0x1>,
> + <0xb48 0x1>;
> +reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
> +
> +clocks = < GPU_CC_CX_GMU_CLK>,
> + < GPU_CC_CXO_CLK>,
> + < GCC_DDRSS_GPU_AXI_CLK>,
> + < GCC_GPU_MEMNOC_GFX_CLK>;
> +clock-names = "gmu", "cxo", "axi", "memnoc";
> +
> +interrupts = ,
> + ;
> +interrupt-names = "hfi", "gmu";
> +
> +power-domains = < GPU_CX_GDSC>,
> +< GPU_GX_GDSC>;
> +power-domain-names = "cx", "gx";
> +
> +iommus = <_smmu 5>;
> +operating-points-v2 = <_opp_table>;
> + };
> --
> 2.7.4
>
___
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[Freedreno] [PATCH v2 1/4] dt-bindings: display: msm: Convert GMU bindings to YAML
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 --
.../devicetree/bindings/display/msm/gmu.yaml | 130 +
2 files changed, 130 insertions(+), 116 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt
b/Documentation/devicetree/bindings/display/msm/gmu.txt
deleted file mode 100644
index bf9c7a2..000
--- a/Documentation/devicetree/bindings/display/msm/gmu.txt
+++ /dev/null
@@ -1,116 +0,0 @@
-Qualcomm adreno/snapdragon GMU (Graphics management unit)
-
-The GMU is a programmable power controller for the GPU. the CPU controls the
-GMU which in turn handles power controls for the GPU.
-
-Required properties:
-- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
-for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
- Note that you need to list the less specific "qcom,adreno-gmu"
- for generic matches and the more specific identifier to identify
- the specific device.
-- reg: Physical base address and length of the GMU registers.
-- reg-names: Matching names for the register regions
- * "gmu"
- * "gmu_pdc"
- * "gmu_pdc_seg"
-- interrupts: The interrupt signals from the GMU.
-- interrupt-names: Matching names for the interrupts
- * "hfi"
- * "gmu"
-- clocks: phandles to the device clocks
-- clock-names: Matching names for the clocks
- * "gmu"
- * "cxo"
- * "axi"
- * "mnoc"
-- power-domains: should be:
- <_gpucc GPU_CX_GDSC>
- <_gpucc GPU_GX_GDSC>
-- power-domain-names: Matching names for the power domains
-- iommus: phandle to the adreno iommu
-- operating-points-v2: phandle to the OPP operating points
-
-Optional properties:
-- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
-SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
-
-Example:
-
-/ {
- ...
-
- gmu: gmu@506a000 {
- compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
-
- reg = <0x506a000 0x3>,
- <0xb28 0x1>,
- <0xb48 0x1>;
- reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
-
- interrupts = ,
-;
- interrupt-names = "hfi", "gmu";
-
- clocks = < GPU_CC_CX_GMU_CLK>,
- < GPU_CC_CXO_CLK>,
- < GCC_DDRSS_GPU_AXI_CLK>,
- < GCC_GPU_MEMNOC_GFX_CLK>;
- clock-names = "gmu", "cxo", "axi", "memnoc";
-
- power-domains = < GPU_CX_GDSC>,
- < GPU_GX_GDSC>;
- power-domain-names = "cx", "gx";
-
- iommus = <_smmu 5>;
-
- operating-points-v2 = <_opp_table>;
- };
-};
-
-a3xx example with OCMEM support:
-
-/ {
- ...
-
- gpu: adreno@fdb0 {
- compatible = "qcom,adreno-330.2",
-"qcom,adreno";
- reg = <0xfdb0 0x1>;
- reg-names = "kgsl_3d0_reg_memory";
- interrupts = ;
- interrupt-names = "kgsl_3d0_irq";
- clock-names = "core",
- "iface",
- "mem_iface";
- clocks = < OXILI_GFX3D_CLK>,
-< OXILICX_AHB_CLK>,
-< OXILICX_AXI_CLK>;
- sram = <_sram>;
- power-domains = < OXILICX_GDSC>;
- operating-points-v2 = <_opp_table>;
- iommus = <_iommu 0>;
- };
-
- ocmem@fdd0 {
- compatible = "qcom,msm8974-ocmem";
-
- reg = <0xfdd0 0x2000>,
- <0xfec0 0x18>;
- reg-names = "ctrl",
-"mem";
-
- clocks = < RPM_SMD_OCMEMGX_CLK>,
-< OCMEMCX_OCMEMNOC_CLK>;
- clock-names = "core",
- "iface";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- gmu_sram: gmu-sram@0 {
- reg = <0x0 0x10>;
- ranges = <0 0 0xfec0 0x10>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
new file mode 100644
index 000..776ff92
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
+%YAML 1.2
+---
+
+$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#;
+$schema:
