Re: [Freedreno] [PATCH v2 4/4] arm64: dts: qcom: sc7280: add edp display dt nodes
On 2021-10-21 11:44, Stephen Boyd wrote:
Quoting Krishna Manikandan (2021-10-20 06:58:53)
From: Sankeerth Billakanti
Add edp controller and phy DT nodes for sc7280.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Krishna Manikandan
Some comments below
Reviewed-by: Stephen Boyd
Changes in v2:
- Move regulator definitions to board file (Matthias Kaehlcke)
- Move the gpio definitions to board file (Matthias Kaehlcke)
- Move the pinconf to board file (Matthias Kaehlcke)
- Move status property (Stephen Boyd)
- Drop flags from interrupts (Stephen Boyd)
- Add clock names one per line for readability (Stephen Boyd)
- Rename edp-opp-table (Stephen Boyd)
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 107
++-
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index dd35882..4450277 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2575,7 +2575,7 @@
reg = <0 0xaf0 0 0x2>;
clocks = < RPMH_CXO_CLK>,
< GCC_DISP_GPLL0_CLK_SRC>,
-<0>, <0>, <0>, <0>, <0>, <0>;
+<0>, <0>, <0>, <0>, <_phy 0>,
<_phy 1>;
I can already tell this is going to be a merge mess! Can this also be
one cell per line?
where are dsi phy? (<_phy 0>, <_phy 1>)
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
@@ -2777,6 +2784,103 @@
status = "disabled";
};
+
+ msm_edp: edp@aea {
+ compatible = "qcom,sc7280-edp";
+
+ reg = <0 0xaea 0 0x200>,
+ <0 0xaea0200 0 0x200>,
+ <0 0xaea0400 0 0xc00>,
+ <0 0xaea1000 0 0x400>;
+
+ interrupt-parent = <>;
+ interrupts = <14>;
+
+ clocks = < RPMH_CXO_CLK>,
+< GCC_EDP_CLKREF_EN>,
+<
DISP_CC_MDSS_AHB_CLK>,
+<
DISP_CC_MDSS_EDP_AUX_CLK>,
+<
DISP_CC_MDSS_EDP_LINK_CLK>,
+<
DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
+<
DISP_CC_MDSS_EDP_PIXEL_CLK>;
+ clock-names = "core_xo",
+ "core_ref",
+ "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <
DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
+ <
DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
+ phys = <_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 =
<_opp_table>;
+ power-domains = < SC7280_CX>;
+
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+
remote-endpoint = <_intf5_out>;
+ };
+ };
+ };
+
+ edp_opp_table: opp-table {
+ compatible =
"operating-points-v2";
+
+ opp-16000 {
+ opp-hz = /bits/ 64
<16000>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-27000 {
+ opp-hz = /bits/ 64
<27000>;
+
Re: [Freedreno] [PATCH v2 4/4] arm64: dts: qcom: sc7280: add edp display dt nodes
Quoting Krishna Manikandan (2021-10-20 06:58:53)
> From: Sankeerth Billakanti
>
> Add edp controller and phy DT nodes for sc7280.
>
> Signed-off-by: Sankeerth Billakanti
> Signed-off-by: Krishna Manikandan
>
Some comments below
Reviewed-by: Stephen Boyd
> Changes in v2:
> - Move regulator definitions to board file (Matthias Kaehlcke)
> - Move the gpio definitions to board file (Matthias Kaehlcke)
> - Move the pinconf to board file (Matthias Kaehlcke)
> - Move status property (Stephen Boyd)
> - Drop flags from interrupts (Stephen Boyd)
> - Add clock names one per line for readability (Stephen Boyd)
> - Rename edp-opp-table (Stephen Boyd)
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 107
> ++-
> 1 file changed, 106 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index dd35882..4450277 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2575,7 +2575,7 @@
> reg = <0 0xaf0 0 0x2>;
> clocks = < RPMH_CXO_CLK>,
> < GCC_DISP_GPLL0_CLK_SRC>,
> -<0>, <0>, <0>, <0>, <0>, <0>;
> +<0>, <0>, <0>, <0>, <_phy 0>, <_phy
> 1>;
I can already tell this is going to be a merge mess! Can this also be
one cell per line?
> clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
> "dsi0_phy_pll_out_byteclk",
> "dsi0_phy_pll_out_dsiclk",
> @@ -2777,6 +2784,103 @@
>
> status = "disabled";
> };
> +
> + msm_edp: edp@aea {
> + compatible = "qcom,sc7280-edp";
> +
> + reg = <0 0xaea 0 0x200>,
> + <0 0xaea0200 0 0x200>,
> + <0 0xaea0400 0 0xc00>,
> + <0 0xaea1000 0 0x400>;
> +
> + interrupt-parent = <>;
> + interrupts = <14>;
> +
> + clocks = < RPMH_CXO_CLK>,
> +< GCC_EDP_CLKREF_EN>,
> +< DISP_CC_MDSS_AHB_CLK>,
> +< DISP_CC_MDSS_EDP_AUX_CLK>,
> +< DISP_CC_MDSS_EDP_LINK_CLK>,
> +<
> DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
> +< DISP_CC_MDSS_EDP_PIXEL_CLK>;
> + clock-names = "core_xo",
> + "core_ref",
> + "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> + #clock-cells = <1>;
> + assigned-clocks = <
> DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
> + <
> DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <_phy 0>,
> <_phy 1>;
> +
> + phys = <_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + edp_in: endpoint {
> + remote-endpoint =
> <_intf5_out>;
> + };
> + };
> + };
> +
> + edp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-16000 {
> + opp-hz = /bits/ 64
> <16000>;
> + required-opps =
> <_opp_low_svs>;
> + };
> +
> +
[Freedreno] [PATCH v2 4/4] arm64: dts: qcom: sc7280: add edp display dt nodes
From: Sankeerth Billakanti
Add edp controller and phy DT nodes for sc7280.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Krishna Manikandan
Changes in v2:
- Move regulator definitions to board file (Matthias Kaehlcke)
- Move the gpio definitions to board file (Matthias Kaehlcke)
- Move the pinconf to board file (Matthias Kaehlcke)
- Move status property (Stephen Boyd)
- Drop flags from interrupts (Stephen Boyd)
- Add clock names one per line for readability (Stephen Boyd)
- Rename edp-opp-table (Stephen Boyd)
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 ++-
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index dd35882..4450277 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2575,7 +2575,7 @@
reg = <0 0xaf0 0 0x2>;
clocks = < RPMH_CXO_CLK>,
< GCC_DISP_GPLL0_CLK_SRC>,
-<0>, <0>, <0>, <0>, <0>, <0>;
+<0>, <0>, <0>, <0>, <_phy 0>, <_phy 1>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
@@ -2662,6 +2662,13 @@
remote-endpoint =
<_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ dpu_intf5_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
};
mdp_opp_table: opp-table {
@@ -2777,6 +2784,103 @@
status = "disabled";
};
+
+ msm_edp: edp@aea {
+ compatible = "qcom,sc7280-edp";
+
+ reg = <0 0xaea 0 0x200>,
+ <0 0xaea0200 0 0x200>,
+ <0 0xaea0400 0 0xc00>,
+ <0 0xaea1000 0 0x400>;
+
+ interrupt-parent = <>;
+ interrupts = <14>;
+
+ clocks = < RPMH_CXO_CLK>,
+< GCC_EDP_CLKREF_EN>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_EDP_AUX_CLK>,
+< DISP_CC_MDSS_EDP_LINK_CLK>,
+<
DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
+< DISP_CC_MDSS_EDP_PIXEL_CLK>;
+ clock-names = "core_xo",
+ "core_ref",
+ "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <
DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
+ <
DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <_phy 0>,
<_phy 1>;
+
+ phys = <_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SC7280_CX>;
+
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ edp_in: endpoint {
+ remote-endpoint =
<_intf5_out>;
+ };
+ };
+ };
+
+ edp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-16000 {
+
