Re: [Freedreno] [PATCH v3 6/8] drm/msm/dpu: drop DPU_INTF_TE feature flag

[Stephen Boyd]

Quoting Dmitry Baryshkov (2023-09-03 19:04:52)
> Replace the only user of the DPU_INTF_TE feature flag with the direct
> DPU version comparison.
>
> Reviewed-by: Marijn Suijten 
> Signed-off-by: Dmitry Baryshkov 
> ---

Reviewed-by: Stephen Boyd 

[Freedreno] [PATCH v3 6/8] drm/msm/dpu: drop DPU_INTF_TE feature flag

[Dmitry Baryshkov]

Replace the only user of the DPU_INTF_TE feature flag with the direct
DPU version comparison.

Reviewed-by: Marijn Suijten 
Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 5 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   | 2 --
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index df88358e7037..e03b2075639d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -776,8 +776,9 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
phys_enc->intf_mode = INTF_MODE_CMD;
cmd_enc->stream_sel = 0;
 
-   phys_enc->has_intf_te = test_bit(DPU_INTF_TE,
-_enc->hw_intf->cap->features);
+   /* DPU before 5.0 use PINGPONG for TE handling */
+   if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
+   phys_enc->has_intf_te = true;
 
atomic_set(_enc->pending_vblank_cnt, 0);
init_waitqueue_head(_enc->pending_vblank_wq);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d89bdd0dd27a..a1aada630780 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -100,7 +100,6 @@
 
 #define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
-BIT(DPU_INTF_TE) | \
 BIT(DPU_INTF_STATUS_SUPPORTED) | \
 BIT(DPU_DATA_HCTL_EN))
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 9aac937285b1..e5add4384830 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -158,7 +158,6 @@ enum {
  * INTF sub-blocks
  * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
  *  pixel data arrives to this INTF
- * @DPU_INTF_TE INTF block has TE configuration support
  * @DPU_DATA_HCTL_ENAllows data to be transferred at different 
rate
  *  than video timing
  * @DPU_INTF_STATUS_SUPPORTED   INTF block has INTF_STATUS register
@@ -166,7 +165,6 @@ enum {
  */
 enum {
DPU_INTF_INPUT_CTRL = 0x1,
-   DPU_INTF_TE,
DPU_DATA_HCTL_EN,
DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
-- 
2.39.2