Re: [Freedreno] [PATCH v5 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2023-01-19 Thread Bjorn Andersson 
On Wed, Jan 18, 2023 at 04:58:26AM +0200, Dmitry Baryshkov wrote:
> On 08/12/2022 00:00, Bjorn Andersson wrote:
> > From: Bjorn Andersson 
> > 
> > Define the display clock controllers, the MDSS instances, the DP phys
> > and connect these together.
> > 
> > Signed-off-by: Bjorn Andersson 
> > Signed-off-by: Bjorn Andersson 
> > ---
> > 
> > Changes since v4:
> > - None
> > 
> >   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
> >   1 file changed, 838 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi 
> > b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index 9f3132ac2857..c2f186495506 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -4,6 +4,7 @@
> >* Copyright (c) 2022, Linaro Limited
> >*/
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 {
> > status = "disabled";
> > };
> > +   mdss1_dp0_phy: phy@8909a00 {
> > +   compatible = "qcom,sc8280xp-dp-phy";
> > +   reg = <0 0x08909a00 0 0x19c>,
> > + <0 0x08909200 0 0xec>,
> > + <0 0x08909600 0 0xec>,
> > + <0 0x08909000 0 0x1c8>;
> > +
> > +   clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > +<&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> > +   clock-names = "aux", "cfg_ahb";
> > +
> > +   power-domains = <&rpmhpd SC8280XP_MX>;
> > +
> > +   #clock-cells = <1>;
> > +   #phy-cells = <0>;
> > +
> > +   status = "disabled";
> > +   };
> > +
> > +   mdss1_dp1_phy: phy@890ca00 {
> > +   compatible = "qcom,sc8280xp-dp-phy";
> > +   reg = <0 0x0890ca00 0 0x19c>,
> > + <0 0x0890c200 0 0xec>,
> > + <0 0x0890c600 0 0xec>,
> > + <0 0x0890c000 0 0x1c8>;
> > +
> > +   clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
> > +<&dispcc1 DISP_CC_MDSS_AHB_CLK>;
> > +   clock-names = "aux", "cfg_ahb";
> > +
> > +   power-domains = <&rpmhpd SC8280XP_MX>;
> > +
> > +   #clock-cells = <1>;
> > +   #phy-cells = <0>;
> > +
> > +   status = "disabled";
> > +   };
> > +
> > system-cache-controller@920 {
> > compatible = "qcom,sc8280xp-llcc";
> > reg = <0 0x0920 0 0x58000>, <0 0x0960 0 
> > 0x58000>;
> > @@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a80 {
> > };
> > };
> > +   mdss0: display-subsystem@ae0 {
> > +   compatible = "qcom,sc8280xp-mdss";
> > +   reg = <0 0x0ae0 0 0x1000>;
> > +   reg-names = "mdss";
> > +
> > +   power-domains = <&dispcc0 MDSS_GDSC>;
> > +
> > +   clocks = <&gcc GCC_DISP_AHB_CLK>,
> > +<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> > +<&dispcc0 DISP_CC_MDSS_MDP_CLK>;
> > +   clock-names = "iface",
> > + "ahb",
> > + "core";
> > +
> > +   resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
> > +
> > +   interrupts = ;
> > +   interrupt-controller;
> > +   #interrupt-cells = <1>;
> > +
> > +   interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt 
> > SLAVE_EBI1 0>,
> > +   <&mmss_noc MASTER_MDP1 0 &mc_virt 
> > SLAVE_EBI1 0>;
> > +   interconnect-names = "mdp0-mem", "mdp1-mem";
> > +
> > +   iommus = <&apps_smmu 0x1000 0x402>;
> > +
> > +   status = "disabled";
> > +
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   ranges;
> > +
> > +   mdss0_mdp: display-controller@ae01000 {
> > +   compatible = "qcom,sc8280xp-dpu";
> > +   reg = <0 0x0ae01000 0 0x8f000>,
> > + <0 0x0aeb 0 0x2008>;
> > +   reg-names = "mdp", "vbif";
> > +
> > +   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > +<&gcc GCC_DISP_SF_AXI_CLK>,
> > +<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> > +<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
> > +<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
> > +<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
> > +   clock-names = "bus",
> > +

Re: [Freedreno] [PATCH v5 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2023-01-17 Thread Dmitry Baryshkov 

On 08/12/2022 00:00, Bjorn Andersson wrote:

From: Bjorn Andersson 

Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.

Signed-off-by: Bjorn Andersson 
Signed-off-by: Bjorn Andersson 
---

Changes since v4:
- None

  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
  1 file changed, 838 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi 
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 9f3132ac2857..c2f186495506 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4,6 +4,7 @@
   * Copyright (c) 2022, Linaro Limited
   */
  
+#include 

  #include 
  #include 
  #include 
@@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 {
status = "disabled";
};
  
+		mdss1_dp0_phy: phy@8909a00 {

+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x08909a00 0 0x19c>,
+ <0 0x08909200 0 0xec>,
+ <0 0x08909600 0 0xec>,
+ <0 0x08909000 0 0x1c8>;
+
+   clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
+<&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = <&rpmhpd SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
+   mdss1_dp1_phy: phy@890ca00 {
+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x0890ca00 0 0x19c>,
+ <0 0x0890c200 0 0xec>,
+ <0 0x0890c600 0 0xec>,
+ <0 0x0890c000 0 0x1c8>;
+
+   clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
+<&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = <&rpmhpd SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
system-cache-controller@920 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x0920 0 0x58000>, <0 0x0960 0 
0x58000>;
@@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a80 {
};
};
  
+		mdss0: display-subsystem@ae0 {

+   compatible = "qcom,sc8280xp-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   power-domains = <&dispcc0 MDSS_GDSC>;
+
+   clocks = <&gcc GCC_DISP_AHB_CLK>,
+<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0 DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface",
+ "ahb",
+ "core";
+
+   resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt 
SLAVE_EBI1 0>,
+   <&mmss_noc MASTER_MDP1 0 &mc_virt 
SLAVE_EBI1 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   iommus = <&apps_smmu 0x1000 0x402>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss0_mdp: display-controller@ae01000 {
+   compatible = "qcom,sc8280xp-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
+<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+   assigned-clocks =

Re: [Freedreno] [PATCH v5 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2022-12-09 Thread Johan Hovold 
On Wed, Dec 07, 2022 at 02:00:10PM -0800, Bjorn Andersson wrote:
> From: Bjorn Andersson 
> 
> Define the display clock controllers, the MDSS instances, the DP phys
> and connect these together.
> 
> Signed-off-by: Bjorn Andersson 
> Signed-off-by: Bjorn Andersson 
> ---
> 
> Changes since v4:
> - None
> 
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
>  1 file changed, 838 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi 
> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 9f3132ac2857..c2f186495506 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
 
> + mdss0: display-subsystem@ae0 {
> + compatible = "qcom,sc8280xp-mdss";
> + reg = <0 0x0ae0 0 0x1000>;
> + reg-names = "mdss";
> +
> + power-domains = <&dispcc0 MDSS_GDSC>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> +  <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
> +  <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> +   "ahb",
> +   "core";
> +
> + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
> +
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt 
> SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt 
> SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + iommus = <&apps_smmu 0x1000 0x402>;
> +
> + status = "disabled";

Please move status last.

> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss0_mdp: display-controller@ae01000 {

[...]

> + mdss1: display-subsystem@2200 {
> + compatible = "qcom,sc8280xp-mdss";
> + reg = <0 0x2200 0 0x1000>;
> + reg-names = "mdss";
> +
> + power-domains = <&dispcc1 MDSS_GDSC>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> +  <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
> +  <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface",
> +   "ahb",
> +   "core";
> +
> + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
> +
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 
> &mc_virt SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP_CORE1_1 0 
> &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + iommus = <&apps_smmu 0x1800 0x402>;
> +
> + status = "disabled";

Same here.

> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss1_mdp: display-controller@22001000 {

Johan

[Freedreno] [PATCH v5 10/12] arm64: dts: qcom: sc8280xp: Define some of the display blocks

2022-12-07 Thread Bjorn Andersson 
From: Bjorn Andersson 

Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.

Signed-off-by: Bjorn Andersson 
Signed-off-by: Bjorn Andersson 
---

Changes since v4:
- None

 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
 1 file changed, 838 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi 
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 9f3132ac2857..c2f186495506 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4,6 +4,7 @@
  * Copyright (c) 2022, Linaro Limited
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 {
status = "disabled";
};
 
+   mdss1_dp0_phy: phy@8909a00 {
+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x08909a00 0 0x19c>,
+ <0 0x08909200 0 0xec>,
+ <0 0x08909600 0 0xec>,
+ <0 0x08909000 0 0x1c8>;
+
+   clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
+<&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = <&rpmhpd SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
+   mdss1_dp1_phy: phy@890ca00 {
+   compatible = "qcom,sc8280xp-dp-phy";
+   reg = <0 0x0890ca00 0 0x19c>,
+ <0 0x0890c200 0 0xec>,
+ <0 0x0890c600 0 0xec>,
+ <0 0x0890c000 0 0x1c8>;
+
+   clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
+<&dispcc1 DISP_CC_MDSS_AHB_CLK>;
+   clock-names = "aux", "cfg_ahb";
+
+   power-domains = <&rpmhpd SC8280XP_MX>;
+
+   #clock-cells = <1>;
+   #phy-cells = <0>;
+
+   status = "disabled";
+   };
+
system-cache-controller@920 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x0920 0 0x58000>, <0 0x0960 0 
0x58000>;
@@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a80 {
};
};
 
+   mdss0: display-subsystem@ae0 {
+   compatible = "qcom,sc8280xp-mdss";
+   reg = <0 0x0ae0 0 0x1000>;
+   reg-names = "mdss";
+
+   power-domains = <&dispcc0 MDSS_GDSC>;
+
+   clocks = <&gcc GCC_DISP_AHB_CLK>,
+<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0 DISP_CC_MDSS_MDP_CLK>;
+   clock-names = "iface",
+ "ahb",
+ "core";
+
+   resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
+
+   interrupts = ;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt 
SLAVE_EBI1 0>,
+   <&mmss_noc MASTER_MDP1 0 &mc_virt 
SLAVE_EBI1 0>;
+   interconnect-names = "mdp0-mem", "mdp1-mem";
+
+   iommus = <&apps_smmu 0x1000 0x402>;
+
+   status = "disabled";
+
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   mdss0_mdp: display-controller@ae01000 {
+   compatible = "qcom,sc8280xp-dpu";
+   reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+   reg-names = "mdp", "vbif";
+
+   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&gcc GCC_DISP_SF_AXI_CLK>,
+<&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc0 DISP_CC_MDSS_MDP_CLK>,
+<&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
+   clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+   assigned-clocks = <&dispcc0 
DISP_CC_MDSS_MDP_CLK>,