Re: [PATCH v2 1/4] dt-bindings: display/msm: document MDSS on X1E80100
On Wed, Feb 14, 2024 at 11:24:30PM +0200, Abel Vesa wrote:
> Document the MDSS hardware found on the Qualcomm X1E80100 platform.
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Abel Vesa
> ---
> .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 252
> +
> 1 file changed, 252 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> new file mode 100644
> index ..c3e38afab76e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
> @@ -0,0 +1,252 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm X1E80100 Display MDSS
> +
> +maintainers:
> + - Abel Vesa
> +
> +description:
> + X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
> like
> + DPU display controller, DP interfaces, etc.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> +const: qcom,x1e80100-mdss
> +
> + clocks:
> +items:
> + - description: Display AHB
> + - description: Display hf AXI
> + - description: Display core
> +
> + iommus:
> +maxItems: 1
> +
> + interconnects:
> +maxItems: 3
> +
> + interconnect-names:
> +maxItems: 3
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> +type: object
additionalProperties: true
> +properties:
> + compatible:
> +const: qcom,x1e80100-dpu
> +
> + "^displayport-controller@[0-9a-f]+$":
> +type: object
additionalProperties: true
> +properties:
> + compatible:
> +const: qcom,x1e80100-dp
> +
> + "^phy@[0-9a-f]+$":
> +type: object
additionalProperties: true
> +properties:
> + compatible:
> +const: qcom,x1e80100-dp-phy
> +
> +required:
> + - compatible
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +display-subsystem@ae0 {
> +compatible = "qcom,x1e80100-mdss";
> +reg = <0x0ae0 0x1000>;
> +reg-names = "mdss";
> +
> +interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
> +<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
> +<&gem_noc MASTER_APPSS_PROC 0 &config_noc
> SLAVE_DISPLAY_CFG 0>;
> +interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
> +
> +resets = <&dispcc_core_bcr>;
> +
> +power-domains = <&dispcc_gdsc>;
> +
> +clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +clock-names = "bus", "nrt_bus", "core";
> +
> +interrupts = ;
> +interrupt-controller;
> +#interrupt-cells = <1>;
> +
> +iommus = <&apps_smmu 0x1c00 0x2>;
> +
> +#address-cells = <1>;
> +#size-cells = <1>;
> +ranges;
> +
> +display-controller@ae01000 {
> +compatible = "qcom,x1e80100-dpu";
> +reg = <0x0ae01000 0x8f000>,
> + <0x0aeb 0x2008>;
> +reg-names = "mdp", "vbif";
> +
> +clocks = <&gcc_axi_clk>,
> + <&dispcc_ahb_clk>,
> + <&dispcc_mdp_lut_clk>,
> + <&dispcc_mdp_clk>,
> + <&dispcc_mdp_vsync_clk>;
> +clock-names = "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> +assigned-clocks = <&dispcc_mdp_vsync_clk>;
> +assigned-clock-rates = <1920>;
> +
> +operating-points-v2 = <&mdp_opp_table>;
> +power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> +interrupt-parent = <&mdss>;
> +interrupts = <0>;
> +
> +ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> +reg = <0>;
> +dpu_intf1_out: endpoint {
> +remote-endpoint = <&dsi0_in>;
> +};
> +};
> +
> +port@1 {
> +reg = <1>;
> +dpu_intf2_out: endpoint {
> +remote-endpoint = <&dsi1_in>;
> +};
> +};
> +};
> +
> +mdp_opp_table: opp-table {
> +compatible = "operating-points-v2";
> +
> +opp-2 {
> +opp-hz = /bits/ 64 <2>;
> +required-opps = <&
Re: [PATCH v2 1/4] dt-bindings: display/msm: document MDSS on X1E80100
On Wed, 14 Feb 2024 23:24:30 +0200, Abel Vesa wrote: > Document the MDSS hardware found on the Qualcomm X1E80100 platform. > > Reviewed-by: Krzysztof Kozlowski > Signed-off-by: Abel Vesa > --- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 252 > + > 1 file changed, 252 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.example.dts:24:18: fatal error: dt-bindings/clock/qcom,x1e80100-dispcc.h: No such file or directory 24 | #include | ^~ compilation terminated. make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1428: dt_binding_check] Error 2 make: *** [Makefile:240: __sub-make] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240214-x1e80100-display-v2-1-cf05ba887...@linaro.org The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
[PATCH v2 1/4] dt-bindings: display/msm: document MDSS on X1E80100
Document the MDSS hardware found on the Qualcomm X1E80100 platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Abel Vesa
---
.../bindings/display/msm/qcom,x1e80100-mdss.yaml | 252 +
1 file changed, 252 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
new file mode 100644
index ..c3e38afab76e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 Display MDSS
+
+maintainers:
+ - Abel Vesa
+
+description:
+ X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces, etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,x1e80100-mdss
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 3
+
+ interconnect-names:
+maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,x1e80100-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,x1e80100-dp
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,x1e80100-dp-phy
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,x1e80100-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
+<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
+<&gem_noc MASTER_APPSS_PROC 0 &config_noc
SLAVE_DISPLAY_CFG 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
+
+resets = <&dispcc_core_bcr>;
+
+power-domains = <&dispcc_gdsc>;
+
+clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+clock-names = "bus", "nrt_bus", "core";
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <&apps_smmu 0x1c00 0x2>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,x1e80100-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc_axi_clk>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_mdp_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+
+port@1 {
+reg = <1>;
+dpu_intf2_out: endpoint {
+remote-endpoint = <&dsi1_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <&rpmhpd_opp_low_svs>;
+};
+
+opp-32500 {
+opp-hz = /bits/ 64 <32500>;
+required-opps = <&rpmhpd_opp_svs>;
+};
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-51400 {
+opp-hz = /bits/ 64 <51400>;
+required-opps = <&rpmhpd_
