Re: [PATCH v3 6/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1

2024-04-08 Thread Jun Nie
Dmitry Baryshkov  于2024年4月3日周三 18:51写道:
>
> On Wed, 3 Apr 2024 at 12:11, Jun Nie  wrote:
> >
> > From: Jonathan Marek 
> >
> > Support slice_per_pkt in msm driver.
> >
> > Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
> > comment is incorrect.
> >
> > Also trim the code to simplify the dsc reference.
> >
> > Signed-off-by: Jonathan Marek 
> > Signed-off-by: Jun Nie 
> > ---
> >  drivers/gpu/drm/msm/dsi/dsi_host.c | 35 ++-
> >  1 file changed, 14 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
> > b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > index b0507a42ee6a..0c6f40dbd25c 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -866,17 +866,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host 
> > *msm_host, bool is_cmd_mod
> > slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
> >
> > total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
> > -   bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
> > -
> > +   bytes_per_pkt = dsc->slice_chunk_size * dsc->slice_per_pkt;
>
> Please don't mix cleanup and functional changes.

OK. Will fix this.


Re: [PATCH v3 6/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1

2024-04-03 Thread Dmitry Baryshkov
On Wed, 3 Apr 2024 at 12:11, Jun Nie  wrote:
>
> From: Jonathan Marek 
>
> Support slice_per_pkt in msm driver.
>
> Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
> comment is incorrect.
>
> Also trim the code to simplify the dsc reference.
>
> Signed-off-by: Jonathan Marek 
> Signed-off-by: Jun Nie 
> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c | 35 ++-
>  1 file changed, 14 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
> b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index b0507a42ee6a..0c6f40dbd25c 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -866,17 +866,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host 
> *msm_host, bool is_cmd_mod
> slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
>
> total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
> -   bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
> -
> +   bytes_per_pkt = dsc->slice_chunk_size * dsc->slice_per_pkt;

Please don't mix cleanup and functional changes.

> eol_byte_num = total_bytes_per_intf % 3;
>
> -   /*
> -* Typically, pkt_per_line = slice_per_intf * slice_per_pkt.
> -*
> -* Since the current driver only supports slice_per_pkt = 1,
> -* pkt_per_line will be equal to slice per intf for now.
> -*/
> -   pkt_per_line = slice_per_intf;
> +   pkt_per_line = slice_per_intf / dsc->slice_per_pkt;
>
> if (is_cmd_mode) /* packet data type */
> reg = 
> DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
> @@ -916,6 +909,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host 
> *msm_host, bool is_cmd_mod
>  static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool 
> is_bonded_dsi)
>  {
> struct drm_display_mode *mode = msm_host->mode;
> +   struct drm_dsc_config *dsc = msm_host->dsc;

And here too. Please pull msm_host->dsc change to a separate patch.

> u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
> u32 h_total = mode->htotal;
> u32 v_total = mode->vtotal;
> @@ -947,8 +941,7 @@ static void dsi_timing_setup(struct msm_dsi_host 
> *msm_host, bool is_bonded_dsi)
> hdisplay /= 2;
> }
>
> -   if (msm_host->dsc) {
> -   struct drm_dsc_config *dsc = msm_host->dsc;
> +   if (dsc) {
> u32 bytes_per_pclk;
>
> /* update dsc params with timing params */
> @@ -988,14 +981,14 @@ static void dsi_timing_setup(struct msm_dsi_host 
> *msm_host, bool is_bonded_dsi)
> else
> bytes_per_pclk = 3;
>
> -   hdisplay = 
> DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk);
> +   hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(dsc), 
> bytes_per_pclk);
>
> h_total += hdisplay;
> ha_end = ha_start + hdisplay;
> }
>
> if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> -   if (msm_host->dsc)
> +   if (dsc)
> dsi_update_dsc_timing(msm_host, false, 
> mode->hdisplay);
>
> dsi_write(msm_host, REG_DSI_ACTIVE_H,
> @@ -1016,21 +1009,17 @@ static void dsi_timing_setup(struct msm_dsi_host 
> *msm_host, bool is_bonded_dsi)
> DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> } else {/* command mode */
> -   if (msm_host->dsc)
> +   if (dsc)
> dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
>
> /* image data and 1 byte write_memory_start cmd */
> -   if (!msm_host->dsc)
> +   if (!dsc)
> wc = hdisplay * 
> mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1;
> else
> /*
>  * When DSC is enabled, WC = slice_chunk_size * 
> slice_per_pkt + 1.
> -* Currently, the driver only supports default value 
> of slice_per_pkt = 1
> -*
> -* TODO: Expand mipi_dsi_device struct to hold 
> slice_per_pkt info
> -*   and adjust DSC math to account for 
> slice_per_pkt.
>  */
> -   wc = msm_host->dsc->slice_chunk_size + 1;
> +   wc = dsc->slice_chunk_size * dsc->slice_per_pkt + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
> @@ -1657,8 +1646,12 @@ static int dsi_host_attach(struct mipi_dsi_host *host,
> msm_host->lanes = dsi->lanes;
> msm_host->format = dsi->format;
> msm_host->mode_flags = dsi->mode_flags;
> 

[PATCH v3 6/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1

2024-04-03 Thread Jun Nie
From: Jonathan Marek 

Support slice_per_pkt in msm driver.

Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
comment is incorrect.

Also trim the code to simplify the dsc reference.

Signed-off-by: Jonathan Marek 
Signed-off-by: Jun Nie 
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 35 ++-
 1 file changed, 14 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b0507a42ee6a..0c6f40dbd25c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -866,17 +866,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host 
*msm_host, bool is_cmd_mod
slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
 
total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
-   bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */
-
+   bytes_per_pkt = dsc->slice_chunk_size * dsc->slice_per_pkt;
eol_byte_num = total_bytes_per_intf % 3;
 
-   /*
-* Typically, pkt_per_line = slice_per_intf * slice_per_pkt.
-*
-* Since the current driver only supports slice_per_pkt = 1,
-* pkt_per_line will be equal to slice per intf for now.
-*/
-   pkt_per_line = slice_per_intf;
+   pkt_per_line = slice_per_intf / dsc->slice_per_pkt;
 
if (is_cmd_mode) /* packet data type */
reg = 
DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
@@ -916,6 +909,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host 
*msm_host, bool is_cmd_mod
 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
 {
struct drm_display_mode *mode = msm_host->mode;
+   struct drm_dsc_config *dsc = msm_host->dsc;
u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
u32 h_total = mode->htotal;
u32 v_total = mode->vtotal;
@@ -947,8 +941,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, 
bool is_bonded_dsi)
hdisplay /= 2;
}
 
-   if (msm_host->dsc) {
-   struct drm_dsc_config *dsc = msm_host->dsc;
+   if (dsc) {
u32 bytes_per_pclk;
 
/* update dsc params with timing params */
@@ -988,14 +981,14 @@ static void dsi_timing_setup(struct msm_dsi_host 
*msm_host, bool is_bonded_dsi)
else
bytes_per_pclk = 3;
 
-   hdisplay = 
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk);
+   hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(dsc), 
bytes_per_pclk);
 
h_total += hdisplay;
ha_end = ha_start + hdisplay;
}
 
if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
-   if (msm_host->dsc)
+   if (dsc)
dsi_update_dsc_timing(msm_host, false, mode->hdisplay);
 
dsi_write(msm_host, REG_DSI_ACTIVE_H,
@@ -1016,21 +1009,17 @@ static void dsi_timing_setup(struct msm_dsi_host 
*msm_host, bool is_bonded_dsi)
DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
} else {/* command mode */
-   if (msm_host->dsc)
+   if (dsc)
dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
 
/* image data and 1 byte write_memory_start cmd */
-   if (!msm_host->dsc)
+   if (!dsc)
wc = hdisplay * 
mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1;
else
/*
 * When DSC is enabled, WC = slice_chunk_size * 
slice_per_pkt + 1.
-* Currently, the driver only supports default value of 
slice_per_pkt = 1
-*
-* TODO: Expand mipi_dsi_device struct to hold 
slice_per_pkt info
-*   and adjust DSC math to account for 
slice_per_pkt.
 */
-   wc = msm_host->dsc->slice_chunk_size + 1;
+   wc = dsc->slice_chunk_size * dsc->slice_per_pkt + 1;
 
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
@@ -1657,8 +1646,12 @@ static int dsi_host_attach(struct mipi_dsi_host *host,
msm_host->lanes = dsi->lanes;
msm_host->format = dsi->format;
msm_host->mode_flags = dsi->mode_flags;
-   if (dsi->dsc)
+   if (dsi->dsc) {
msm_host->dsc = dsi->dsc;
+   /* for backwards compatibility, assume 1 if not set */
+   if (!dsi->dsc->slice_per_pkt)
+   dsi->dsc->slice_per_pkt = 1;
+   }
 
/* Some gpios defined in panel DT need to be controlled by host */
ret =