Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On 28/05/2024 02:15, Dmitry Baryshkov wrote:
> In the end, msm8998 uses what looks like QMP v3 with a different TX
> register set
Patch diff currently looks like this:
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c| 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h| 8 +
drivers/gpu/drm/msm/hdmi/hdmi_phy.c| 5 +
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 795 +
drivers/gpu/drm/msm/registers/display/hdmi.xml | 89 +++
6 files changed, 899 insertions(+)
I'll post hdmi_phy_8998.c below for easy reference,
but Arnaud might want me to have a closer look at
pll_get_post_div()
Though I must confess, if the code works as it is now,
why look for a different solution, especially if it's
going to be factorized again in a few weeks?
pll_get_cpctrl() and pll_get_rctrl() looks a bit odd.
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2024 Freebox SAS
*/
#include
#include
#include "hdmi.h"
#define HDMI_VCO_MAX_FREQ 120UL
#define HDMI_VCO_MIN_FREQ 80UL
#define HDMI_PCLK_MAX_FREQ 6
#define HDMI_PCLK_MIN_FREQ 2500
#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD34UL
#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 15UL
#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 75000UL
#define HDMI_CORECLK_DIV5
#define HDMI_DEFAULT_REF_CLOCK 1920
#define HDMI_PLL_CMP_CNT1024
#define HDMI_PLL_POLL_MAX_READS 100
#define HDMI_PLL_POLL_TIMEOUT_US150
#define HDMI_NUM_TX_CHANNEL 4
struct hdmi_pll_8998 {
struct platform_device *pdev;
struct clk_hw clk_hw;
unsigned long rate;
/* pll mmio base */
void __iomem *mmio_qserdes_com;
/* tx channel base */
void __iomem *mmio_qserdes_tx[HDMI_NUM_TX_CHANNEL];
};
#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8998, clk_hw)
struct hdmi_8998_phy_pll_reg_cfg {
u32 com_svs_mode_clk_sel;
u32 com_hsclk_sel;
u32 com_pll_cctrl_mode0;
u32 com_pll_rctrl_mode0;
u32 com_cp_ctrl_mode0;
u32 com_dec_start_mode0;
u32 com_div_frac_start1_mode0;
u32 com_div_frac_start2_mode0;
u32 com_div_frac_start3_mode0;
u32 com_integloop_gain0_mode0;
u32 com_integloop_gain1_mode0;
u32 com_lock_cmp_en;
u32 com_lock_cmp1_mode0;
u32 com_lock_cmp2_mode0;
u32 com_lock_cmp3_mode0;
u32 com_core_clk_en;
u32 com_coreclk_div_mode0;
u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_tx_drv_lvl[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_tx_emp_post1_lvl[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_pre_driver_1[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_pre_driver_2[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_res_code_offset[HDMI_NUM_TX_CHANNEL];
u32 phy_mode;
};
struct hdmi_8998_post_divider {
u64 vco_freq;
int hsclk_divsel;
int vco_ratio;
int tx_band_sel;
int half_rate_mode;
};
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll)
{
return platform_get_drvdata(pll->pdev);
}
static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset,
u32 data)
{
writel(data, pll->mmio_qserdes_com + offset);
}
static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset)
{
return readl(pll->mmio_qserdes_com + offset);
}
static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel,
int offset, int data)
{
writel(data, pll->mmio_qserdes_tx[channel] + offset);
}
static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x8;
return 0x30;
}
static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x16;
return 0x18;
}
static inline u32 pll_get_cctrl(u64 frac_start, bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x34;
return 0x2;
}
static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,
bool gen_ssc)
{
int digclk_divsel = bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2;
u64 base;
if ((frac_start != 0) || gen_ssc)
base = 0x3F;
else
base = 0xC4;
base <<= (digclk_divsel == 2 ? 1 : 0);
return (base <= 2046 ? base : 2046);
}
static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk)
{
u64
[RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
From: Arnaud Vrac
Ported from the downstream driver.
Signed-off-by: Arnaud Vrac
Signed-off-by: Marc Gonzalez
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
6 files changed, 1118 insertions(+)
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index b21ae2880c715..5b5d6aded5233 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi_phy.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8996.o \
+ hdmi/hdmi_phy_8998.o \
hdmi/hdmi_phy_8x60.o \
hdmi/hdmi_phy_8x74.o \
hdmi/hdmi_pll_8960.o \
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c8ebd75176bba..2a2ce49ef5aa3 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct platform_device
*pdev)
}
static const struct of_device_id msm_hdmi_dt_match[] = {
+ { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8996", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8994", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = _tx_8974_config },
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index ec57864403915..cad0d50c82fbc 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -137,6 +137,7 @@ enum hdmi_phy_type {
MSM_HDMI_PHY_8960,
MSM_HDMI_PHY_8x74,
MSM_HDMI_PHY_8996,
+ MSM_HDMI_PHY_8998,
MSM_HDMI_PHY_MAX,
};
@@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
+extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
struct hdmi_phy {
struct platform_device *pdev;
@@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
#ifdef CONFIG_COMMON_CLK
int msm_hdmi_pll_8960_init(struct platform_device *pdev);
int msm_hdmi_pll_8996_init(struct platform_device *pdev);
+int msm_hdmi_pll_8998_init(struct platform_device *pdev);
#else
static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
{
@@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
platform_device *pdev)
{
return -ENODEV;
}
+
+static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
+{
+ return -ENODEV;
+}
#endif
/*
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 973b460486a5a..c9ca1101b5ad4 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -1396,4 +1396,166 @@ static inline uint32_t
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x0110
+#define REG_HDMI_8998_PHY_CFG 0x
+
+#define REG_HDMI_8998_PHY_PD_CTL 0x0004
+
+#define REG_HDMI_8998_PHY_MODE 0x0010
+
+#define REG_HDMI_8998_PHY_CLOCK
0x005c
+
+#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
+
+#define REG_HDMI_8998_PHY_STATUS 0x00b4
+
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE 0x0008
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_BG_TIMER 0x000c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_EN_CENTER0x0010
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER1 0x001c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER2 0x0020
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_DIV 0x002c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_DIV_MUX 0x0030
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0034
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_CLK_ENABLE1 0x0038
+
+#define
Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On Mon, May 27, 2024 at 02:39:35PM +0200, Arnaud Vrac wrote:
> On 27/05/2024 14:11, Dmitry Baryshkov wrote:
> > On Thu, 23 May 2024 at 18:14, Marc Gonzalez wrote:
> > >
> > > From: Arnaud Vrac
> > >
> > > Ported from the downstream driver.
> > >
> > > Signed-off-by: Arnaud Vrac
> > > Signed-off-by: Marc Gonzalez
> > > ---
> > > drivers/gpu/drm/msm/Makefile | 1 +
> > > drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
> > > drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
> > > drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
> > > drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
> > > drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
> > > 6 files changed, 1118 insertions(+)
> > > create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
> > >
> > > diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> > > index b21ae2880c715..5b5d6aded5233 100644
> > > --- a/drivers/gpu/drm/msm/Makefile
> > > +++ b/drivers/gpu/drm/msm/Makefile
> > > @@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
> > > hdmi/hdmi_phy.o \
> > > hdmi/hdmi_phy_8960.o \
> > > hdmi/hdmi_phy_8996.o \
> > > + hdmi/hdmi_phy_8998.o \
> > > hdmi/hdmi_phy_8x60.o \
> > > hdmi/hdmi_phy_8x74.o \
> > > hdmi/hdmi_pll_8960.o \
> > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > b/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > index c8ebd75176bba..2a2ce49ef5aa3 100644
> > > --- a/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
> > > @@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct
> > > platform_device *pdev)
> > > }
> > >
> > > static const struct of_device_id msm_hdmi_dt_match[] = {
> > > + { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config
> > > },
> >
> > Missing DT bindings.
> >
> > > { .compatible = "qcom,hdmi-tx-8996", .data =
> > > _tx_8974_config },
> > > { .compatible = "qcom,hdmi-tx-8994", .data =
> > > _tx_8974_config },
> > > { .compatible = "qcom,hdmi-tx-8084", .data =
> > > _tx_8974_config },
> > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > b/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > index ec57864403915..cad0d50c82fbc 100644
> > > --- a/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
> > > @@ -137,6 +137,7 @@ enum hdmi_phy_type {
> > > MSM_HDMI_PHY_8960,
> > > MSM_HDMI_PHY_8x74,
> > > MSM_HDMI_PHY_8996,
> > > + MSM_HDMI_PHY_8998,
> > > MSM_HDMI_PHY_MAX,
> > > };
> > >
> > > @@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg
> > > msm_hdmi_phy_8x60_cfg;
> > > extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
> > > extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
> > > extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
> > > +extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
> > >
> > > struct hdmi_phy {
> > > struct platform_device *pdev;
> > > @@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
> > > #ifdef CONFIG_COMMON_CLK
> > > int msm_hdmi_pll_8960_init(struct platform_device *pdev);
> > > int msm_hdmi_pll_8996_init(struct platform_device *pdev);
> > > +int msm_hdmi_pll_8998_init(struct platform_device *pdev);
> > > #else
> > > static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
> > > {
> > > @@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
> > > platform_device *pdev)
> > > {
> > > return -ENODEV;
> > > }
> > > +
> > > +static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
> > > +{
> > > + return -ENODEV;
> > > +}
> > > #endif
> > >
> > > /*
> > > diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > index 973b460486a5a..c9ca1101b5ad4 100644
> > > --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> > > @@ -1396,4 +1396,166 @@ static inline uint32_t
> > > HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
> > > #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV
> > > 0x0110
> > >
> > >
> > > +#define REG_HDMI_8998_PHY_CFG 0x
> > > +
> > > +#define REG_HDMI_8998_PHY_PD_CTL 0x0004
> > > +
> > > +#define REG_HDMI_8998_PHY_MODE 0x0010
> > > +
> > > +#define REG_HDMI_8998_PHY_CLOCK
> > > 0x005c
> > > +
> > > +#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
> > > +
> > > +#define REG_HDMI_8998_PHY_STATUS 0x00b4
> > > +
> > > +
> > > +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
> > > +
> > > +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
> > > +
> > > +#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE
Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On 27/05/2024 14:11, Dmitry Baryshkov wrote:
On Thu, 23 May 2024 at 18:14, Marc Gonzalez wrote:
From: Arnaud Vrac
Ported from the downstream driver.
Signed-off-by: Arnaud Vrac
Signed-off-by: Marc Gonzalez
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
6 files changed, 1118 insertions(+)
create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index b21ae2880c715..5b5d6aded5233 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi_phy.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8996.o \
+ hdmi/hdmi_phy_8998.o \
hdmi/hdmi_phy_8x60.o \
hdmi/hdmi_phy_8x74.o \
hdmi/hdmi_pll_8960.o \
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c8ebd75176bba..2a2ce49ef5aa3 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct platform_device
*pdev)
}
static const struct of_device_id msm_hdmi_dt_match[] = {
+ { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config },
Missing DT bindings.
{ .compatible = "qcom,hdmi-tx-8996", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8994", .data = _tx_8974_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = _tx_8974_config },
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index ec57864403915..cad0d50c82fbc 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -137,6 +137,7 @@ enum hdmi_phy_type {
MSM_HDMI_PHY_8960,
MSM_HDMI_PHY_8x74,
MSM_HDMI_PHY_8996,
+ MSM_HDMI_PHY_8998,
MSM_HDMI_PHY_MAX,
};
@@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
+extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
struct hdmi_phy {
struct platform_device *pdev;
@@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
#ifdef CONFIG_COMMON_CLK
int msm_hdmi_pll_8960_init(struct platform_device *pdev);
int msm_hdmi_pll_8996_init(struct platform_device *pdev);
+int msm_hdmi_pll_8998_init(struct platform_device *pdev);
#else
static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
{
@@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
platform_device *pdev)
{
return -ENODEV;
}
+
+static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
+{
+ return -ENODEV;
+}
#endif
/*
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 973b460486a5a..c9ca1101b5ad4 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -1396,4 +1396,166 @@ static inline uint32_t
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x0110
+#define REG_HDMI_8998_PHY_CFG 0x
+
+#define REG_HDMI_8998_PHY_PD_CTL 0x0004
+
+#define REG_HDMI_8998_PHY_MODE 0x0010
+
+#define REG_HDMI_8998_PHY_CLOCK
0x005c
+
+#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
+
+#define REG_HDMI_8998_PHY_STATUS 0x00b4
+
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE 0x0008
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_BG_TIMER 0x000c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_EN_CENTER0x0010
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER1 0x001c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER2 0x0020
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_DIV 0x002c
+
+#define REG_HDMI_8998_PHY_QSERDES_COM_POST_DIV_MUX 0x0030
+
+#define
Re: [RFC PATCH v1] drm/msm: add msm8998 hdmi phy/pll support
On Thu, 23 May 2024 at 18:14, Marc Gonzalez wrote:
>
> From: Arnaud Vrac
>
> Ported from the downstream driver.
>
> Signed-off-by: Arnaud Vrac
> Signed-off-by: Marc Gonzalez
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> drivers/gpu/drm/msm/hdmi/hdmi.c | 1 +
> drivers/gpu/drm/msm/hdmi/hdmi.h | 8 +
> drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 162
> drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 5 +
> drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 941 +++
> 6 files changed, 1118 insertions(+)
> create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index b21ae2880c715..5b5d6aded5233 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -26,6 +26,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
> hdmi/hdmi_phy.o \
> hdmi/hdmi_phy_8960.o \
> hdmi/hdmi_phy_8996.o \
> + hdmi/hdmi_phy_8998.o \
> hdmi/hdmi_phy_8x60.o \
> hdmi/hdmi_phy_8x74.o \
> hdmi/hdmi_pll_8960.o \
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
> index c8ebd75176bba..2a2ce49ef5aa3 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi.c
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
> @@ -549,6 +549,7 @@ static void msm_hdmi_dev_remove(struct platform_device
> *pdev)
> }
>
> static const struct of_device_id msm_hdmi_dt_match[] = {
> + { .compatible = "qcom,hdmi-tx-8998", .data = _tx_8974_config },
Missing DT bindings.
> { .compatible = "qcom,hdmi-tx-8996", .data = _tx_8974_config },
> { .compatible = "qcom,hdmi-tx-8994", .data = _tx_8974_config },
> { .compatible = "qcom,hdmi-tx-8084", .data = _tx_8974_config },
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
> index ec57864403915..cad0d50c82fbc 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi.h
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
> @@ -137,6 +137,7 @@ enum hdmi_phy_type {
> MSM_HDMI_PHY_8960,
> MSM_HDMI_PHY_8x74,
> MSM_HDMI_PHY_8996,
> + MSM_HDMI_PHY_8998,
> MSM_HDMI_PHY_MAX,
> };
>
> @@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
> extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
> extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
> extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
> +extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
>
> struct hdmi_phy {
> struct platform_device *pdev;
> @@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
> #ifdef CONFIG_COMMON_CLK
> int msm_hdmi_pll_8960_init(struct platform_device *pdev);
> int msm_hdmi_pll_8996_init(struct platform_device *pdev);
> +int msm_hdmi_pll_8998_init(struct platform_device *pdev);
> #else
> static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
> {
> @@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct
> platform_device *pdev)
> {
> return -ENODEV;
> }
> +
> +static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
> +{
> + return -ENODEV;
> +}
> #endif
>
> /*
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> index 973b460486a5a..c9ca1101b5ad4 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
> @@ -1396,4 +1396,166 @@ static inline uint32_t
> HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
> #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x0110
>
>
> +#define REG_HDMI_8998_PHY_CFG 0x
> +
> +#define REG_HDMI_8998_PHY_PD_CTL 0x0004
> +
> +#define REG_HDMI_8998_PHY_MODE 0x0010
> +
> +#define REG_HDMI_8998_PHY_CLOCK
> 0x005c
> +
> +#define REG_HDMI_8998_PHY_CMN_CTRL 0x0068
> +
> +#define REG_HDMI_8998_PHY_STATUS 0x00b4
> +
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL1 0x
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_ATB_SEL2 0x0004
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_FREQ_UPDATE 0x0008
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_BG_TIMER 0x000c
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_EN_CENTER0x0010
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER1 0x001c
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_PER2 0x0020
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
> +
> +#define REG_HDMI_8998_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
> +
> +#define
