Re: [Freedreno] [PATCH v1 3/4] arm64: dts: qcom: sc7280: Add DSI display nodes

[Stephen Boyd]

Quoting Krishna Manikandan (2021-08-18 03:27:03)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index fd7ff1c..aadf55d 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1507,6 +1519,95 @@
> };
> };
> };
> +
> +   dsi0: dsi@ae94000 {
> +   compatible = "qcom,mdss-dsi-ctrl";
> +   reg = <0 0x0ae94000 0 0x400>;
> +   reg-names = "dsi_ctrl";
> +
> +   interrupt-parent = <>;
> +   interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

Drop flags as the #interrupt-cells is 0 for mdss

> +
> +   clocks = < DISP_CC_MDSS_BYTE0_CLK>,
> +< 
> DISP_CC_MDSS_BYTE0_INTF_CLK>,
> +< DISP_CC_MDSS_PCLK0_CLK>,
> +< DISP_CC_MDSS_ESC0_CLK>,
> +< DISP_CC_MDSS_AHB_CLK>,
> +< GCC_DISP_HF_AXI_CLK>;
> +   clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> +   operating-points-v2 = <_opp_table>;
> +   power-domains = < SC7280_CX>;
> +
> +   phys = <_phy>;
> +   phy-names = "dsi";
> +
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +
> +   status = "disabled";
> +
> +   ports {
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +
> +   port@0 {
> +   reg = <0>;
> +   dsi0_in: endpoint {
> +   remote-endpoint = 
> <_intf1_out>;
> +   };
> +   };
> +
> +   port@1 {
> +   reg = <1>;
> +   dsi0_out: endpoint {
> +   };
> +   };
> +   };
> +
> +   dsi_opp_table: dsi-opp-table {

dsi_opp_table: opp-table {

> +   compatible = "operating-points-v2";
> +
> +   opp-18750 {
> +   opp-hz = /bits/ 64 
> <18750>;
> +   required-opps = 
> <_opp_low_svs>;
> +   };
> +
> +   opp-3 {
> +   opp-hz = /bits/ 64 
> <3>;
> +   required-opps = 
> <_opp_svs>;
> +   };
> +
> +   opp-35800 {
> +   opp-hz = /bits/ 64 
> <35800>;
> +   required-opps = 
> <_opp_svs_l1>;
> +   };
> +   };
> +   };
> +
> +   dsi_phy: dsi-phy@ae94400 {

phy@ae94400

> +   compatible = "qcom,sc7280-dsi-phy-7nm";
> +   reg = <0 0x0ae94400 0 0x200>,
> + <0 0x0ae94600 0 0x280>,
> + <0 0x0ae94900 0 0x280>;
> +   reg-names = "dsi_phy",
> +   "dsi_phy_lane",
> +   "dsi_pll";
> +
> +   #clock-cells = <1>;
> +   #phy-cells = <0>;
> +
> +   clocks = < DISP_CC_MDSS_AHB_CLK>,
> +< RPMH_CXO_CLK>;
> +   clock-names = "iface", "ref";
> +
> +   status = "disabled";
> +   };

Re: [Freedreno] [PATCH v1 3/4] arm64: dts: qcom: sc7280: Add DSI display nodes

[Matthias Kaehlcke]

On Wed, Aug 18, 2021 at 03:57:03PM +0530, Krishna Manikandan wrote:
> From: Rajeev Nandan 
> 
> Add DSI controller and PHY nodes for sc7280.
> 
> Signed-off-by: Rajeev Nandan 

You should sign off patches you send, even if you aren't the original author.

> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 101 
> +++
>  1 file changed, 101 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index fd7ff1c..aadf55d 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1483,6 +1483,18 @@
>  
>   status = "disabled";
>  
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = 
> <_in>;
> + };
> + };
> + };
> +
>   mdp_opp_table: mdp-opp-table {
>   compatible = "operating-points-v2";
>  
> @@ -1507,6 +1519,95 @@
>   };
>   };
>   };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <>;
> + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = < DISP_CC_MDSS_BYTE0_CLK>,
> +  < DISP_CC_MDSS_BYTE0_INTF_CLK>,
> +  < DISP_CC_MDSS_PCLK0_CLK>,
> +  < DISP_CC_MDSS_ESC0_CLK>,
> +  < DISP_CC_MDSS_AHB_CLK>,
> +  < GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> +   "byte_intf",
> +   "pixel",
> +   "core",
> +   "iface",
> +   "bus";
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SC7280_CX>;
> +
> + phys = <_phy>;
> + phy-names = "dsi";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = 
> <_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> +
> + dsi_opp_table: dsi-opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-18750 {
> + opp-hz = /bits/ 64 <18750>;
> + required-opps = 
> <_opp_low_svs>;
> + };
> +
> + opp-3 {
> + opp-hz = /bits/ 64 <3>;
> + required-opps = 
> <_opp_svs>;
> + };
> +
> + opp-35800 {
> + opp-hz = /bits/ 64 <35800>;
> + required-opps = 
> <_opp_svs_l1>;
> + };
> + };
> + };
> +
> + dsi_phy: dsi-phy@ae94400 {
> + compatible = "qcom,sc7280-dsi-phy-7nm";
>