GNU Tools Cauldron 2017, Prague, September 8-10

2017-04-03 Thread Jan Hubicka 
Hi,
we are very pleased to invite you all the GNU Tools Cauldron on 8-10 September
2017.  This year we will meet again in Prague, at Charles University.  Details
are here:

  https://gcc.gnu.org/wiki/cauldron2017

As usual, please register (capacity is limited), send abstracts and ask
administrivia questions to tools-cauldron-ad...@googlegroups.com.

I plan to contact GCC, GDB, binutils, CGEN, DejaGnu, newlib and glibc mailing
lists. Please feel free to share with any other groups that are appropriate.

Looking forward to see you in Prague,
Honza Hubicka

About global var reg optimization

2017-04-03 Thread Aurelien Buhrig 
Hello !

I would like to use a fixed global register (here, as an applicative
stack pointer) and would like gcc (6.3 / private backend) to actually
optimize the following code using postinc/predec addressing mode on this
global fixed reg itself (a4 here) :

register int *ptr asm ("a4");
void  pushint (int a) {  *ptr++ = a; }

- The optimized tree looks like:
pushint (int a)
{
  int * ptr.0_2;
  int * _3;

  :
  ptr.0_2 = ptr;
  _3 = ptr.0_2 + 2;
  ptr = _3;
  *ptr.0_2 = a_5(D);
  return;
}

- And the RTL expand looks like:
(set (reg/v:HI 26 [ a ]) (reg:HI 0 r0 [ a ]))
(set (reg/f:SI 24 [ ptr.0_2 ]) (reg/v:SI 12 a4 [ ptr ]))
(set (reg/v:SI 12 a4 [ ptr ]) (plus:SI (reg/f:SI 24 [ ptr.0_2 ])
(const_int 2)))
(set (mem:HI (reg/f:SI 24 [ ptr.0_2 ])) (reg/v:HI 26 [ a ]))

Firstly, the global fixed reg (a4) is flagged volatile, but maybe it is
normal for a user var? May the volatile flag prevent the autoincdec pass
to use a4 as postinc reg?
Then, ptr is spilled into pseudo reg 24 which is used as base reg, which
seems to prevent the autoincdec pass to use a4.

Any idea how I could optimize such a code ?

Thank you in advance,
Cheers,
Aurélien

Re: About global var reg optimization

2017-04-03 Thread Jeff Law 

On 04/03/2017 09:42 AM, Aurelien Buhrig wrote:

Hello !

I would like to use a fixed global register (here, as an applicative
stack pointer) and would like gcc (6.3 / private backend) to actually
optimize the following code using postinc/predec addressing mode on this
global fixed reg itself (a4 here) :

register int *ptr asm ("a4");
void  pushint (int a) {  *ptr++ = a; }

- The optimized tree looks like:
pushint (int a)
{
  int * ptr.0_2;
  int * _3;

  :
  ptr.0_2 = ptr;
  _3 = ptr.0_2 + 2;
  ptr = _3;
  *ptr.0_2 = a_5(D);
  return;
}

- And the RTL expand looks like:
(set (reg/v:HI 26 [ a ]) (reg:HI 0 r0 [ a ]))
(set (reg/f:SI 24 [ ptr.0_2 ]) (reg/v:SI 12 a4 [ ptr ]))
(set (reg/v:SI 12 a4 [ ptr ]) (plus:SI (reg/f:SI 24 [ ptr.0_2 ])
(const_int 2)))
(set (mem:HI (reg/f:SI 24 [ ptr.0_2 ])) (reg/v:HI 26 [ a ]))

Firstly, the global fixed reg (a4) is flagged volatile, but maybe it is
normal for a user var?
On a reg the /v flag means it is a user variable.  The meaning of the 
various flags is documented in the developer manual.



May the volatile flag prevent the autoincdec pass

to use a4 as postinc reg?

Nope.  Again, the volatile flag really means it's a user variable.


Then, ptr is spilled into pseudo reg 24 which is used as base reg, which
seems to prevent the autoincdec pass to use a4.

Any idea how I could optimize such a code ?
You'd have to dig into the auto-inc pass to see why it doesn't see the 
autoincrement opportunity.  This looks like a pre-inc to me.


Jeff