Updating @gcc.gnu.org email forwarding
Hi, I'm looking to update the forwarding address for my @gcc.gnu.org email address, but appear to have lost (if I ever had) my private key. Could someone point me in the right direction for fixing this? Thanks, Stu
[PATCH] Avoid HOST cflags polluting BUILD cflags
Hi, I noticed a Canadian cross failure in 4.8 which was down to BUILD_CXXFLAGS being set to ALL_FLAGS even when build != host. Obviously this has only become apparent with 4.8. Thanks, Stu 2013-11-14 Stuart Henderson shend...@gcc.gnu.org * configure (BUILD_CXXFLAGS): Set appropriately when build != host. * configure.ac (BUILD_CXXFLAGS): Likewise diff --git a/gcc/configure b/gcc/configure index fbdcd89..a2791a3 100755 --- a/gcc/configure +++ b/gcc/configure @@ -11704,6 +11704,7 @@ STMP_FIXINC=stmp-fixinc if test x$build != x$host || test x$coverage_flags != x then BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)' +BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)' BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)' fi diff --git a/gcc/configure.ac b/gcc/configure.ac index 773cb5d..5d7d18b 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -1887,6 +1887,7 @@ STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC) if test x$build != x$host || test x$coverage_flags != x then BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)' +BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)' BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)' fi upstream.patch Description: upstream.patch
RE: spill failure after IF-CASE-2 transformation
I think this is a fairly reasonable minimal fix. For 4.8 we could
experiment whether to always do this, regardless of s_r_c_f_m_p.
Ok if bootstrapped and tested on a primary target (i.e. linux) and
tested on Blackfin.
Bernd
Thanks again, Bernd.
Forwarding to gcc-patches to give people a couple of days to object.
Tested on linux and bfin.
Stu
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index 8d81c89..e4e13ab 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -2295,7 +2295,9 @@ noce_get_condition (rtx jump, rtx *earliest, bool
then_else_reversed)
cond = XEXP (SET_SRC (set), 0);
tmp = XEXP (cond, 0);
- if (REG_P (tmp) GET_MODE_CLASS (GET_MODE (tmp)) == MODE_INT)
+ if (REG_P (tmp) GET_MODE_CLASS (GET_MODE (tmp)) == MODE_INT
+ (GET_MODE (tmp) != BImode
+ || !targetm.small_register_classes_for_mode_p (BImode)))
{
*earliest = jump;
upstream2.patch
Description: upstream2.patch
RE: spill failure after IF-CASE-2 transformation
Not really. I think in dead_or_predicable you need to check in the /* Try the NCE path if the CE path did not result in any changes. */ block (I assume this is where we end up in this testcase) that none of the live hard regs at the point where we are going to insert the insns are in small register classes. small_register_classes_for_mode_p is unfortunately not a good interface to answer that question. It looks like noce_get_condition probably didn't find the instruction setting CC? Maybe you can paper over the problem for the moment by making sure it does. The problem with noce_get_condition is that if the condition variable is a MODE_INT register it will return it and set earliest as the jump insn itself. I'm not sure why this is the case, but it seems like something we don't want to be doing in this situation. Is there a reasonable check that should be made to avoid noce_get_condition doing this? e.g. if the condition var is a reg and !small_register_classes_for_mode_p. Thanks, Stu
RE: spill failure after IF-CASE-2 transformation
Make an exception for BImode and small_register_classes_for_mode_p
(BImode).
Thanks Bernd.
Would this be acceptable:
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index 8d81c89..e4e13ab 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -2295,7 +2295,9 @@ noce_get_condition (rtx jump, rtx *earliest, bool
then_else_reversed)
cond = XEXP (SET_SRC (set), 0);
tmp = XEXP (cond, 0);
- if (REG_P (tmp) GET_MODE_CLASS (GET_MODE (tmp)) == MODE_INT)
+ if (REG_P (tmp) GET_MODE_CLASS (GET_MODE (tmp)) == MODE_INT
+ (GET_MODE (tmp) != BImode
+ || !targetm.small_register_classes_for_mode_p (BImode)))
{
*earliest = jump;
RE: spill failure after IF-CASE-2 transformation
Ping. looks like an invalid transformation, but I suspect rather than setting the CC register, the (*) insn is setting a pseudo (more accurate RTL would be useful). There are some cases in ifcvt.c which check targetm.small_register_classes_for_mode already, this is probably what should be done to prevent this transformation. You suspect correctly, cc=x sets CC whereas cc=y is a pseudo which can only match CC. Presumably I must check all instructions in the else_bb for modifications to small_register_classes_for_mode_p? e.g. see below. Does this seem reasonable? Patch here: http://gcc.gnu.org/ml/gcc/2012-02/msg00296.html Thanks, Stu
RE: spill failure after IF-CASE-2 transformation
Ping. looks like an invalid transformation, but I suspect rather than setting the CC register, the (*) insn is setting a pseudo (more accurate RTL would be useful). There are some cases in ifcvt.c which check targetm.small_register_classes_for_mode already, this is probably what should be done to prevent this transformation. You suspect correctly, cc=x sets CC whereas cc=y is a pseudo which can only match CC. Presumably I must check all instructions in the else_bb for modifications to small_register_classes_for_mode_p? e.g. see below. Does this seem reasonable? Patch here: http://gcc.gnu.org/ml/gcc/2012-02/msg00296.html Thanks, Stu
RE: spill failure after IF-CASE-2 transformation
spill_failure does return for asms since we don't want to ICE on bad
user code. That's all that's going on here.
ahh, thanks.
It sounds like ifcvt needs to be fixed. Your example:
block 44:
set cc = x;
set cc = y; (*)
if cc jump;
looks like an invalid transformation, but I suspect rather than setting
the CC register, the (*) insn is setting a pseudo (more accurate RTL
would be useful). There are some cases in ifcvt.c which check
targetm.small_register_classes_for_mode already, this is probably what
should be done to prevent this transformation.
You suspect correctly, cc=x sets CC whereas cc=y is a pseudo which can only
match CC.
Presumably I must check all instructions in the else_bb for modifications to
small_register_classes_for_mode_p? e.g. see below.
Does this seem reasonable?
Thanks,
Stu
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index 8d81c89..b605a63 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -3924,6 +3924,7 @@ find_if_case_2 (basic_block test_bb, edge then_edge, edge
else_edge)
basic_block else_bb = else_edge-dest;
edge else_succ;
int then_prob, else_prob;
+ rtx insn;
/* If we are partitioning hot/cold basic blocks, we don't want to
mess up unconditional or indirect jumps that cross between hot
@@ -3957,6 +3958,25 @@ find_if_case_2 (basic_block test_bb, edge then_edge,
edge else_edge)
/* ELSE has one predecessor. */
if (!single_pred_p (else_bb))
return FALSE;
+
+ /* Avoid small_register_classes_for_mode_p dests. */
+ FOR_BB_INSNS (else_bb, insn)
+{
+ rtx set, dest;
+
+ if (!NONDEBUG_INSN_P (insn) || JUMP_P (insn))
+continue;
+ set = single_set (insn);
+ if (!set)
+return FALSE;
+
+ dest = SET_DEST (set);
+ if (!REG_P (dest))
+continue;
+ if (targetm.small_register_classes_for_mode_p (GET_MODE (dest)))
+return FALSE;
+}
/* THEN is not EXIT. */
if (then_bb-index NUM_FIXED_BLOCKS)
spill failure after IF-CASE-2 transformation
Hi,
I'm investigating the following ICE building the Blackfin compiler from trunk:
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:
In function ÃâËeoshift1Ãââ:
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:250:1:
error: unable to find a register to spill in class ÃâËCCREGSÃââ
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:250:1:
error: this is the insn:
(insn 546 540 479 46 (set (reg:BI 455)
(le:BI (reg/v:SI 6 R6 [orig:122 size ] [122])
(const_int 0 [0])))
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:212
119 {compare_le}
(nil))
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:250:1:
internal compiler error: in spill_failure, at reload1.c:2123
The problem occurs when the ce2 pass does an IF-CASE-2 transformation, moving
an instruction which sets the condition code register into a block between
another instruction which sets the condition code register and its conditional
jump.
e.g.
block 44:
set cc = x;
if cc jump;
...
block 49:
set cc = y;
block 51:
if cc jump;
gets transformed into...
block 44:
set cc = x;
set cc = y;
if cc jump;
...
block 51:
if cc jump;
When we reach cc=y in
reload1.c:reload()-select_reload_regs()-find_reload_regs(), find_reg() fails
and we call spill_failure(), which doesn't return. However, right after the
call to spill_failure, we set the failure flag, which is checked for right
after select_reload_regs returns. I'm a little confused as to what the
intention of this code was. It seems like the idea was to note the
spill_failure and then try and fix it by jumping to the failed: label, but
obviously this never happens due to the call to spill_failure. A spill failure
like this looks very fixable and I would expect the previously live register
(cc=x) to be spilled. Is there a reason this isn't attempted here?
Thanks,
Stu
RE: ICE building compiler
Whilst investigating an ICE with the Blackfin compiler, I bumped in to a bit of code which seems questionable: in reload1.c:reload() we call select_reload_regs() and then check if failure was set. However, looking at find_reload_regs() (called via select_reload_regs()), the only time we set failure is immediately after a call to spill_failure() which doesn't return. Is spill_failure the correct function to be using here? It seems like the intention of the code was to note the spill_failure and then try and fix it by jumping to the failed: label. any feedback on this? Thanks, Stu
RE: ICE building compiler
Hi, Whilst investigating an ICE with the Blackfin compiler, I bumped in to a bit of code which seems questionable: in reload1.c:reload() we call select_reload_regs() and then check if failure was set. However, looking at find_reload_regs() (called via select_reload_regs()), the only time we set failure is immediately after a call to spill_failure() which doesn't return. Is spill_failure the correct function to be using here? It seems like the intention of the code was to note the spill_failure and then try and then try and fix it by jumping to the failed: label. Cheers, Stu
ICE building compiler
Hi,
I'm investigating an ICE building the Blackfin compiler from trunk.
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:
In function ‘eoshift1’:
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:250:1:
error: unable to find a register to spill in class ‘CCREGS’
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:250:1:
error: this is the insn:
(insn 546 540 479 46 (set (reg:BI 455)
(le:BI (reg/v:SI 6 R6 [orig:122 size ] [122])
(const_int 0 [0])))
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:212
119 {compare_le}
(nil))
/home/shender/gnu-upstream/toolchain/gcc-4.7/libgfortran/generated/eoshift1_4.c:250:1:
internal compiler error: in spill_failure, at reload1.c:2123
The problem occurs when the ce2 pass does an IF-CASE-2 transformation, moving
an instruction which sets the condition code register into a block between
another instruction which sets the condition code register and its conditional
jump.
e.g.
block 44:
set cc = x;
if cc jump;
...
block 49:
set cc = y;
block 51:
if cc jump;
gets transformed into...
block 44:
set cc = x;
set cc = y;
if cc jump;
...
block 51:
if cc jump;
When we reach cc=y in the reload pass the CC reg is already in use from cc=x,
find_reg fails to find an alternative and we bomb out.
This seems like something IF-CASE-2 could do a lot, so is it supposed to avoid
such scenarios? or should reload handle the situation by finding the previous
use of CC and spilling it to memory?
Any pointers would be appreciated.
Thanks,
Stu
RE: GCC 4.7 Status Report for *-rtems
bfin - REGRESSION - ICE - http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51003 This looks like a known, general issue which Bernd had a fix for, but it doesn't appear to have been checked in yet: http://gcc.gnu.org/ml/gcc-patches/2011-11/msg01524.html Stu
Re: [PATCH] Optimize in RTL vector AND { -1, -1, ... }, IOR { -1, -1, ... } and XOR { -1, -1, ... } (take 2)
2011-09-26 Jakub Jelinek ja...@redhat.com * rtl.h (const_tiny_rtx): Change into array of 4 x MAX_MACHINE_MODE from 3 x MAX_MACHINE_MODE. (CONSTM1_RTX): Define. * emit-rtl.c (const_tiny_rtx): Change into array of 4 x MAX_MACHINE_MODE from 3 x MAX_MACHINE_MODE. (gen_rtx_CONST_VECTOR): Use CONSTM1_RTX if all inner constants are CONSTM1_RTX. (init_emit_once): Initialize CONSTM1_RTX for MODE_INT and MODE_VECTOR_INT modes. * simplify-rtx.c (simplify_binary_operation_1) case IOR, XOR, AND: Optimize if one operand is CONSTM1_RTX. * config/i386/i386.c (ix86_expand_sse_movcc): Optimize mask ? -1 : x into mask | x. FYI - this patch (179238) breaks the Blackfin compiler build with an internal compiler error during configure of libgcc: conftest.c:1:0: internal compiler error: in gen_const_vector, at emit-rtl.c:5491 which is the: gcc_assert (const_tiny_rtx[constant][(int) inner]); gcc configured with: ../gcc-4.7/configure --build=x86_64-unknown-linux-gnu --host=x86_64-unknown-linux-gnu --target=bfin-elf --prefix=/home/shender/gnu/toolchain/bfin-elf --disable-libstdcxx-pch --enable-languages=c,c++ --with-newlib --enable-clocale=generic --disable-symvers --disable-libssp --disable-libffi --disable-libgcj --enable-version-specific-runtime-libs --enable-__cxa_atexit Stu
RE: [PATCH] Fix PR target/48807
Ping Ping. -Original Message- From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org] On Behalf Of Henderson, Stuart Sent: 19 May 2011 13:39 To: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] Fix PR target/48807 Ping http://gcc.gnu.org/ml/gcc-patches/2011-05/msg00503.html Hi, The attached patch is a fix for PR/48807, which is a segfault when compiling the bfin compiler. The problem appears to be that we're not checking the return value of cgraph_local_info for null before attempting to dereference it. This wasn't a problem before, but now cgraph_local_info calls cgraph_get_node (instead of the old cgraph_node), we cannot assume it will always return non-null. Fix is in bfin specific code. Ok to commit to trunk? Stu 2011-05-06 Stuart Henderson shend...@gcc.gnu.org * config/bfin/bfin.c: Check return value of cgraph_local_info for null before attempting to use it. Index: gcc/config/bfin/bfin.c === --- gcc/config/bfin/bfin.c (revision 173363) +++ gcc/config/bfin/bfin.c (working copy) @@ -2077,6 +2077,8 @@ this_func = cgraph_local_info (current_function_decl); called_func = cgraph_local_info (decl); + if (!called_func || !this_func) +return false; return !called_func-local || this_func-local; }
Re: [PATCH] Fix PR target/48807
Ping http://gcc.gnu.org/ml/gcc-patches/2011-05/msg00503.html Hi, The attached patch is a fix for PR/48807, which is a segfault when compiling the bfin compiler. The problem appears to be that we're not checking the return value of cgraph_local_info for null before attempting to dereference it. This wasn't a problem before, but now cgraph_local_info calls cgraph_get_node (instead of the old cgraph_node), we cannot assume it will always return non-null. Fix is in bfin specific code. Ok to commit to trunk? Stu 2011-05-06 Stuart Henderson shend...@gcc.gnu.org * config/bfin/bfin.c: Check return value of cgraph_local_info for null before attempting to use it. Index: gcc/config/bfin/bfin.c === --- gcc/config/bfin/bfin.c (revision 173363) +++ gcc/config/bfin/bfin.c (working copy) @@ -2077,6 +2077,8 @@ this_func = cgraph_local_info (current_function_decl); called_func = cgraph_local_info (decl); + if (!called_func || !this_func) +return false; return !called_func-local || this_func-local; }
[PATCH 1/2] Add bf592 support
Hi,
The attached patch adds support for the bfin bf592 part.
* doc/invoke.texi (Blackfin Options): -mcpu accepts bf592.
* config/bfin/t-bfin-elf (MULTILIB_MATCHES): Select bf532-none for
bf592-none.
* config/bfin/t-bfin-linux (MULTILIB_MATCHES): Likewise.
* config/bfin/t-bfin-uclinux (MULTILIB_MATCHES): Likewise.
* config/bfin/bfin.c (bfin_cpus): Add bf592.
* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define
__ADSPBF592__ and __ADSPBF59x__ for BFIN_CPU_BF592.
* config/bfin/bfin-opts.h (bfin_cpu_type): Add BFIN_CPU_BF592.
* config/bfin/elf.h (LIB_SPEC): Add bf592.
Ok to add to trunk?
thanks,
Stu
Index: gcc/doc/invoke.texi
===
--- gcc/doc/invoke.texi (revision 173825)
+++ gcc/doc/invoke.texi (working copy)
@@ -10414,7 +10414,7 @@
@samp{bf534}, @samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
@samp{bf542}, @samp{bf544}, @samp{bf547}, @samp{bf548}, @samp{bf549},
@samp{bf542m}, @samp{bf544m}, @samp{bf547m}, @samp{bf548m}, @samp{bf549m},
-@samp{bf561}.
+@samp{bf561}, @samp{bf592}.
The optional @var{sirevision} specifies the silicon revision of the target
Blackfin processor. Any workarounds available for the targeted silicon
revision
will be enabled. If @var{sirevision} is @samp{none}, no workarounds are
enabled.
Index: gcc/config/bfin/t-bfin-elf
===
--- gcc/config/bfin/t-bfin-elf (revision 173825)
+++ gcc/config/bfin/t-bfin-elf (working copy)
@@ -58,6 +58,7 @@
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549m-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf561-none
+MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf592-none
MULTILIB_EXCEPTIONS=mleaf-id-shared-library*
MULTILIB_EXCEPTIONS+=mcpu=bf532-none/mleaf-id-shared-library*
Index: gcc/config/bfin/bfin-opts.h
===
--- gcc/config/bfin/bfin-opts.h (revision 173825)
+++ gcc/config/bfin/bfin-opts.h (working copy)
@@ -53,7 +53,8 @@
BFIN_CPU_BF548M,
BFIN_CPU_BF549,
BFIN_CPU_BF549M,
- BFIN_CPU_BF561
+ BFIN_CPU_BF561,
+ BFIN_CPU_BF592
} bfin_cpu_t;
#endif
Index: gcc/config/bfin/elf.h
===
--- gcc/config/bfin/elf.h (revision 173825)
+++ gcc/config/bfin/elf.h (working copy)
@@ -51,6 +51,7 @@
%{mmulticore:%{mcorea:-T bf561a.ld%s}} \
%{mmulticore:%{mcoreb:-T bf561b.ld%s}} \
%{mmulticore:%{!mcorea:%{!mcoreb:-T bf561m.ld%s \
+ %{mcpu=bf592*:-T bf592.ld%s} \
%{!mcpu=*:%eno processor type specified for linking} \
%{!mcpu=bf561*:-T bfin-common-sc.ld%s} \
%{mcpu=bf561*:%{!mmulticore:-T bfin-common-sc.ld%s} \
Index: gcc/config/bfin/bfin.c
===
--- gcc/config/bfin/bfin.c (revision 173825)
+++ gcc/config/bfin/bfin.c (working copy)
@@ -350,6 +350,11 @@
| WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
| WA_0574},
+ {bf592, BFIN_CPU_BF592, 0x0001,
+ WA_SPECULATIVE_LOADS | WA_0574},
+ {bf592, BFIN_CPU_BF592, 0x,
+ WA_SPECULATIVE_LOADS | WA_0574},
+
{NULL, BFIN_CPU_UNKNOWN, 0, 0}
};
Index: gcc/config/bfin/bfin.h
===
--- gcc/config/bfin/bfin.h (revision 173825)
+++ gcc/config/bfin/bfin.h (working copy)
@@ -140,6 +140,10 @@
case BFIN_CPU_BF561:\
builtin_define (__ADSPBF561__); \
break;\
+ case BFIN_CPU_BF592:\
+ builtin_define (__ADSPBF592__); \
+ builtin_define (__ADSPBF59x__); \
+ break;\
} \
\
if (bfin_si_revision != -1) \
Index: gcc/config/bfin/t-bfin-uclinux
===
--- gcc/config/bfin/t-bfin-uclinux (revision 173825)
+++ gcc/config/bfin/t-bfin-uclinux (working copy)
@@ -58,6 +58,7 @@
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549m-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf561-none
+MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf592-none
MULTILIB_EXCEPTIONS=mleaf-id-shared-library*
MULTILIB_EXCEPTIONS+=mcpu=bf532-none/mleaf-id-shared-library*
Index: gcc/config/bfin/t-bfin-linux
===
--- gcc/config/bfin/t-bfin-linux(revision 173825)
+++ gcc/config/bfin/t-bfin-linux(working copy)
@@ -57,6 +57,7 @@
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549m-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf561-none
+MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf592-none
SHLIB_MAPFILES=$(srcdir)/config/bfin/libgcc-bfin.ver
[PATCH 2/2] Add bf592 support
Hi,
The attached patch adds a new test for the bfin bf592 part.
* gcc.target/bfin/mcpu-bf592.c: New test.
Ok to add to trunk?
thanks,
Stu
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf592.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf592.c (revision 0)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf592.c (revision 0)
@@ -0,0 +1,31 @@
+/* Test for -mcpu=. */
+/* { dg-do preprocess } */
+/* { dg-bfin-options -mcpu=bf592 } */
+
+#ifndef __ADSPBF592__
+#error __ADSPBF592__ is not defined
+#endif
+
+#ifndef __ADSPBF59x__
+#error __ADSPBF59x__ is not defined
+#endif
+
+#if __SILICON_REVISION__ != 0x0001
+#error __SILICON_REVISION__ is not 0x0001
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error __WORKAROUNDS_ENABLED is not defined
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error __WORKAROUND_RETS is defined
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error __WORKAROUND_SPECULATIVE_LOADS is not defined
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error __WORKAROUND_SPECULATIVE_SYNCS is defined
+#endif
[PATCH] Fix PR target/48807
Hi, The attached patch is a fix for PR/48807, which is a segfault when compiling the bfin compiler. The problem appears to be that we're not checking the return value of cgraph_local_info for null before attempting to dereference it. This wasn't a problem before, but now cgraph_local_info calls cgraph_get_node (instead of the old cgraph_node), we cannot assume it will always return non-null. Fix is in bfin specific code. Ok to commit to trunk? Stu 2011-05-06 Stuart Henderson shend...@gcc.gnu.org * config/bfin/bfin.c: Check return value of cgraph_local_info for null before attempting to use it. Index: gcc/config/bfin/bfin.c === --- gcc/config/bfin/bfin.c (revision 173363) +++ gcc/config/bfin/bfin.c (working copy) @@ -2077,6 +2077,8 @@ this_func = cgraph_local_info (current_function_decl); called_func = cgraph_local_info (decl); + if (!called_func || !this_func) +return false; return !called_func-local || this_func-local; }
Re: bf54x support
ping
The attached patch adds support for silicon revision 0.4 of the bf54x family.
2011-02-17 Mike Frysinger michael.frysin...@analog.com
* gcc.target/bfin/mcpu-bf542.c: Check SILICON_REVISION is 0x0004.
* gcc.target/bfin/mcpu-bf544.c, gcc.target/bfin/mcpu-bf547.c,
gcc.target/bfin/mcpu-bf548.c, gcc.target/bfin/mcpu-bf549.c: Likewise.
2011-02-17 Mike Frysinger michael.frysin...@analog.com
* config/bfin/bfin.c (bfin_cpus[]): Add 0.4 for
bf542/bf544/bf547/bf548/bf549.
Thanks,
Stu
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf542.c (revision 5257)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf542.c (revision 5258)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf544.c (revision 5257)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf544.c (revision 5258)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf547.c (revision 5257)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf547.c (revision 5258)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf548.c (revision 5257)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf548.c (revision 5258)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf549.c (revision 5257)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf549.c (revision 5258)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/config/bfin/bfin.c
===
--- gcc/config/bfin/bfin.c (revision 5257)
+++ gcc/config/bfin/bfin.c (revision 5258)
@@ -300,6 +300,8 @@
{bf542m, BFIN_CPU_BF542M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf542, BFIN_CPU_BF542, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf542, BFIN_CPU_BF542, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf542, BFIN_CPU_BF542, 0x0001,
@@ -311,6 +313,8 @@
{bf544m, BFIN_CPU_BF544M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf544, BFIN_CPU_BF544, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf544, BFIN_CPU_BF544, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf544, BFIN_CPU_BF544, 0x0001,
@@ -322,6 +326,8 @@
{bf547m, BFIN_CPU_BF547M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf547, BFIN_CPU_BF547, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf547, BFIN_CPU_BF547, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf547, BFIN_CPU_BF547, 0x0001,
@@ -333,6 +339,8 @@
{bf548m, BFIN_CPU_BF548M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf548, BFIN_CPU_BF548, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf548, BFIN_CPU_BF548, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf548, BFIN_CPU_BF548, 0x0001,
@@ -344,6 +352,8 @@
{bf549m, BFIN_CPU_BF549M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf549, BFIN_CPU_BF549, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf549, BFIN_CPU_BF549, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf549, BFIN_CPU_BF549, 0x0001,
RE: bf54x support
sounds good to me. Thanks. Stu -Original Message- From: Bernd Schmidt [mailto:ber...@codesourcery.com] Sent: 03 May 2011 10:40 To: Henderson, Stuart Cc: gcc-patches@gcc.gnu.org Subject: Re: bf54x support On 05/03/2011 11:23 AM, Henderson, Stuart wrote: ping The attached patch adds support for silicon revision 0.4 of the bf54x family. This is OK. I'll also approve all the patches you posted that were originally from either me or Jie and confined to config/bfin. Could you ping the ones that remain after that? Bernd
FW: [Patch] Update bfin parts to latest silicon revisions
Ping
---
The attached patch adds support for (and changes defaults to) the latest
silicon revisions for Blackfin parts.
2011-05-03 Stuart Henderson stuart.hender...@analog.com
* config/bfin/bfin.c (bfin_cpus): Update silicon revisions.
Thanks,
Stu
Index: gcc/config/bfin/bfin.c
===
--- gcc/config/bfin/bfin.c (revision 171215)
+++ gcc/config/bfin/bfin.c (working copy)
@@ -117,15 +117,32 @@
struct bfin_cpu bfin_cpus[] =
{
+
+ {bf512, BFIN_CPU_BF512, 0x0002,
+ WA_SPECULATIVE_LOADS | WA_0574},
+ {bf512, BFIN_CPU_BF512, 0x0001,
+ WA_SPECULATIVE_LOADS | WA_0574},
{bf512, BFIN_CPU_BF512, 0x,
WA_SPECULATIVE_LOADS | WA_0574},
+ {bf514, BFIN_CPU_BF514, 0x0002,
+ WA_SPECULATIVE_LOADS | WA_0574},
+ {bf514, BFIN_CPU_BF514, 0x0001,
+ WA_SPECULATIVE_LOADS | WA_0574},
{bf514, BFIN_CPU_BF514, 0x,
WA_SPECULATIVE_LOADS | WA_0574},
+ {bf516, BFIN_CPU_BF516, 0x0002,
+ WA_SPECULATIVE_LOADS | WA_0574},
+ {bf516, BFIN_CPU_BF516, 0x0001,
+ WA_SPECULATIVE_LOADS | WA_0574},
{bf516, BFIN_CPU_BF516, 0x,
WA_SPECULATIVE_LOADS | WA_0574},
+ {bf518, BFIN_CPU_BF518, 0x0002,
+ WA_SPECULATIVE_LOADS | WA_0574},
+ {bf518, BFIN_CPU_BF518, 0x0001,
+ WA_SPECULATIVE_LOADS | WA_0574},
{bf518, BFIN_CPU_BF518, 0x,
WA_SPECULATIVE_LOADS | WA_0574},
@@ -273,6 +290,8 @@
{bf542m, BFIN_CPU_BF542M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf542, BFIN_CPU_BF542, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf542, BFIN_CPU_BF542, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf542, BFIN_CPU_BF542, 0x0001,
@@ -284,6 +303,8 @@
{bf544m, BFIN_CPU_BF544M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf544, BFIN_CPU_BF544, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf544, BFIN_CPU_BF544, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf544, BFIN_CPU_BF544, 0x0001,
@@ -295,6 +316,8 @@
{bf547m, BFIN_CPU_BF547M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf547, BFIN_CPU_BF547, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf547, BFIN_CPU_BF547, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf547, BFIN_CPU_BF547, 0x0001,
@@ -306,6 +329,8 @@
{bf548m, BFIN_CPU_BF548M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf548, BFIN_CPU_BF548, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf548, BFIN_CPU_BF548, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf548, BFIN_CPU_BF548, 0x0001,
@@ -317,6 +342,8 @@
{bf549m, BFIN_CPU_BF549M, 0x0003,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
+ {bf549, BFIN_CPU_BF549, 0x0004,
+ WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf549, BFIN_CPU_BF549, 0x0002,
WA_SPECULATIVE_LOADS | WA_INDIRECT_CALLS | WA_0574},
{bf549, BFIN_CPU_BF549, 0x0001,
FW: [Patch] Update bfin part tests to latest silicon revision
Ping
---
The attached testsuite patch updates the blackfin part macro tests to expect
the latest silicon revision, as well as fixing up some duplication in the bf51x
parts.
2011-05-03 Stuart Henderson stuart.hender...@analog.com
* gcc.target/bfin/mcpu-bf542.c: Update to latest silicon revision.
* gcc.target/bfin/mcpu-bf544.c: Likewise.
* gcc.target/bfin/mcpu-bf547.c: Likewise.
* gcc.target/bfin/mcpu-bf548.c: Likewise.
* gcc.target/bfin/mcpu-bf549.c: Likewise.
* gcc.target/bfin/mcpu-bf512.c: Update to latest silicon revision and
remove duplication.
* gcc.target/bfin/mcpu-bf514.c: Likewise.
* gcc.target/bfin/mcpu-bf516.c: Likewise.
* gcc.target/bfin/mcpu-bf518.c: Likewise.
Thanks,
Stu
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf542.c (revision 171215)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf542.c (working copy)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf544.c (revision 171215)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf544.c (working copy)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf547.c (revision 171215)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf547.c (working copy)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf548.c (revision 171215)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf548.c (working copy)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf549.c (revision 171215)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf549.c (working copy)
@@ -10,8 +10,8 @@
#error __ADSPBF54x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x0002
-#error __SILICON_REVISION__ is not 0x0002
+#if __SILICON_REVISION__ != 0x0004
+#error __SILICON_REVISION__ is not 0x0004
#endif
#ifndef __WORKAROUNDS_ENABLED
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf512.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf512.c (revision 171215)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf512.c (working copy)
@@ -10,8 +10,8 @@
#error __ADSPBF51x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x
-#error __SILICON_REVISION__ is not 0x
+#if __SILICON_REVISION__ != 0x0002
+#error __SILICON_REVISION__ is not 0x0002
#endif
#ifndef __WORKAROUNDS_ENABLED
@@ -29,34 +29,3 @@
#ifdef __WORKAROUND_SPECULATIVE_SYNCS
#error __WORKAROUND_SPECULATIVE_SYNCS is defined
#endif
-/* Test for -mcpu=. */
-/* { dg-do preprocess } */
-/* { dg-bfin-options -mcpu=bf512 } */
-
-#ifndef __ADSPBF512__
-#error __ADSPBF512__ is not defined
-#endif
-
-#ifndef __ADSPBF51x__
-#error __ADSPBF51x__ is not defined
-#endif
-
-#if __SILICON_REVISION__ != 0x
-#error __SILICON_REVISION__ is not 0x
-#endif
-
-#ifndef __WORKAROUNDS_ENABLED
-#error __WORKAROUNDS_ENABLED is not defined
-#endif
-
-#ifdef __WORKAROUND_RETS
-#error __WORKAROUND_RETS is defined
-#endif
-
-#ifndef __WORKAROUND_SPECULATIVE_LOADS
-#error __WORKAROUND_SPECULATIVE_LOADS is not defined
-#endif
-
-#ifdef __WORKAROUND_SPECULATIVE_SYNCS
-#error __WORKAROUND_SPECULATIVE_SYNCS is defined
-#endif
Index: gcc/testsuite/gcc.target/bfin/mcpu-bf514.c
===
--- gcc/testsuite/gcc.target/bfin/mcpu-bf514.c (revision 171215)
+++ gcc/testsuite/gcc.target/bfin/mcpu-bf514.c (working copy)
@@ -10,8 +10,8 @@
#error __ADSPBF51x__ is not defined
#endif
-#if __SILICON_REVISION__ != 0x
-#error __SILICON_REVISION__ is not 0x
+#if
FW: [Patch] New bfin divsi/udivsi implementations
Ping --- The attached patch updates the blackfin ___divsi3 and ___udivsi3 implementations (and updates ___umodsi3 to match), as well as adding .size directives to all functions in the file. 2011-03-24 Stuart Henderson stuart.hender...@analog.com * gcc/config/bfin/lib1funcs.asm (___divsi3): New implementation, add .size directive and unguard .text directive. (___udivsi3): New implementation and add .size directive. (___umodsi3): Update to match new ___divsi3/___udivsi3 implementations and add .size directive. (___modsi3): Add .size directive. (___umulsi3_highpart): Likewise. (___smulsi3_highpart): Likewise. Thanks, Stu Index: gcc/config/bfin/lib1funcs.asm === --- gcc/config/bfin/lib1funcs.asm (revision 171215) +++ gcc/config/bfin/lib1funcs.asm (working copy) @@ -23,36 +23,101 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see http://www.gnu.org/licenses/. */ +#if defined(__ELF__) defined(__linux__) +.section .note.GNU-stack,,%progbits +#endif + +.text + #ifdef L_divsi3 -.text .align 2 .global ___divsi3; .type ___divsi3, STT_FUNC; ___divsi3: -[--SP]= RETS; - [--SP] = R7; - R2 = -R0; -CC = R0 0; - IF CC R0 = R2; - R7 = CC; - +.Ls_main_branch: + R3 = R0 ^ R1; + R2 = - R0; + R0 = MAX(R0,R2); R2 = -R1; -CC = R1 0; - IF CC R1 = R2; - R2 = CC; - R7 = R7 ^ R2; + R1 = MAX(R1,R2); + R2 = R0 1; + CC = R2 R1 (IU); + IF CC JUMP .Ls_Q_has_only_one_bit; -CALL ___udivsi3; + P1 = R3; + R3 = R11; + R3.L = SIGNBITS R3; + R1 = LSHIFT R1 BY R3.L; + R2 = R1 15; + CC = R2 == 0; + IF !CC JUMP .Ls_use_sfw_D_has_16bit_or_more; - CC = R7; + R2.L = SIGNBITS R0; + R0 = LSHIFT R0 BY R2.L; + R2.L = R3.L - R2.L (NS); + P2 = R2; + CC = R0 == R1; + IF CC JUMP .Ls_N_is_MIN_D_is_1_bit_set; + + R1 = 17; + +.Ls_use_divq_main_branch: + AQ = CC; + + LOOP(s_lp_use_divq) LC0 = P2; + LOOP_BEGIN s_lp_use_divq; + DIVQ(R0, R1); + LOOP_END s_lp_use_divq; + + R0 = EXTRACT(R0, R2.L) (Z); R1 = -R0; + CC = P10; IF CC R0 = R1; + RTS; - R7 = [SP++]; -RETS = [SP++]; -RTS; +.Ls_N_is_MIN_D_is_1_bit_set: + R0 = 1; + R0 = LSHIFT R0 BY R2.L; + R1 = -R0; + CC = P1 0; + IF CC R0 = R1; + RTS; + +.Ls_use_sfw_D_has_16bit_or_more: + R2 = R0 1; + R2.L = SIGNBITS R2; + R3.H = R3.L - R2.L (NS); + R3 = R3 16; + P2 = R3; + R0 = LSHIFT R0 BY R2.L; + R0 = R0 - R1; + CC = !BITTST(R0, 31); + R1 = 1; + + LOOP(s__use_sfw_loop) LC0 = P2; + LOOP_BEGIN s__use_sfw_loop; + R0 = R0 + R1, R2 = R0 - R1; + IF CC R0 = R2; + R0 = ROT R0 BY 1; + LOOP_END s__use_sfw_loop; + + R0 = EXTRACT(R0, R3.L)(Z); + R0 = ROT R0 BY 1; + R1 = -R0; + CC = P10; + IF CC R0 = R1; + RTS; + +.Ls_Q_has_only_one_bit: + CC = R1 = R0 (IU); + R0 = CC; + R1 = -R0; + CC = R30; + IF CC R0 = R1; + RTS; + .size ___divsi3, .-___divsi3; #endif #ifdef L_modsi3 @@ -71,6 +136,8 @@ R0 = R1 - R2; RETS = [SP++]; RTS; + +.size ___modsi3, .-___modsi3 #endif #ifdef L_udivsi3 @@ -79,26 +146,87 @@ .type ___udivsi3, STT_FUNC; ___udivsi3: -P0 = 32; -LSETUP (0f, 1f) LC0 = P0; - /* upper half of dividend */ -R3 = 0; -0: - /* The first time round in the loop we shift in garbage, but since we - perform 33 shifts, it doesn't matter. */ +.Lu_main_branch: + R2 = R0 1; + CC = R2 R1 (IU); + IF CC JUMP .Lu_Q_has_only_one_bit; + + R3 = R1 1; + R3.L = SIGNBITS R3; + R1 = LSHIFT R1 BY R3.L; + R2 = R1 15; + CC = R2 == 0; + IF !CC JUMP .Lu_use_sfw_D_has_16bit_or_more; + + CC = R0 0; + IF CC JUMP .Lu_MSB_of_N_is_1; + + R1.L = SIGNBITS R0; + R2.L = R3.L - R1.L (NS); + P2 = R2; + R0 = LSHIFT R0 BY R1.L; + R1 = 17; + +.Lu_use_divq_main_branch: + AQ = CC; + + LOOP(u_lp_use_divq_when_MSB_of_N_is_0) LC0 = P2; + LOOP_BEGIN u_lp_use_divq_when_MSB_of_N_is_0; + DIVQ(R0, R1); + LOOP_END u_lp_use_divq_when_MSB_of_N_is_0; + + R0 = EXTRACT(R0, R2.L) (Z); + RTS; + +.Lu_MSB_of_N_is_1: + R3 = R3.L (Z); + P2 = R3; + R0 = R0 - R1; + R1 = 17; + +.Lu_use_divq_when_MSB_of_N_is_1: + R2 = ~R0; + R2 = R2 31; + CC = BITTST(R0, 31); + AQ = CC; + + LOOP(u_lp_use_divq_MSB_of_N_is_1) LC0 = P2; + LOOP_BEGIN u_lp_use_divq_MSB_of_N_is_1; + DIVQ(R0, R1); + LOOP_END u_lp_use_divq_MSB_of_N_is_1; + + R2 = LSHIFT R2 BY R3.L; + R0 =
[Patch, committed] Add myself to MAINTAINERS
Added myself to MAINTAINERS (write after approval), committed as directed. Stu 2011-04-07 Stuart Henderson shend...@gcc.gnu.org * MAINTAINERS (Write After Approval): Add myself. Index: MAINTAINERS === --- MAINTAINERS (revision 172094) +++ MAINTAINERS (revision 172095) @@ -373,6 +373,7 @@ Mark Heffernan meh...@google.com George Helffrich geo...@gcc.gnu.org Fergus Henderson f...@cs.mu.oz.au +Stuart Henderson shend...@gcc.gnu.org Matthew Hiller hil...@redhat.com Manfred Hollstein m...@suse.com Falk Hueffner f...@debian.org
RE: [Patch] bfin: move loop invariants out of loop
Do you mean you plan to implement a generic solution in postreload? I have no objections to dropping this in that case. I'll carry on using the patch in our local 4.5 release (for what it's worth). -Original Message- From: Bernd Schmidt [mailto:ber...@codesourcery.com] Sent: 31 March 2011 16:21 To: Henderson, Stuart Cc: gcc-patches@gcc.gnu.org Subject: Re: [Patch] bfin: move loop invariants out of loop On 03/31/2011 04:16 PM, Henderson, Stuart wrote: The attached patch attempts to move loop invariants out of loops for Blackfin. 2011-03-31 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt * config/bfin/bfin.c (bfin_gen_bundles): Don't try to bundle a jump. (bfin_optimize_loops_1, move_loop_constants): New static functions. (bfin_reorg): Call bfin_optimize_loops_1 if optimizing. I kind of want to do this kind of thing as part of postreload, especially since I recently discovered that we have a cprop pass after loop_invariant that tends to undo all the loop invariant motion. Bernd
RE: [Patch] Bfin: Ensure rotrsi and rotlsi don't accept non-const INTVALS
Yep, I'm seeing this behaviour (getting the error using your patch). But I'm
confused as to why the define_expand is being considered when the predicate
doesn't match. Apologies if this is a dim question, I'm still learning.
-Original Message-
From: Bernd Schmidt [mailto:ber...@codesourcery.com]
Sent: 31 March 2011 17:02
To: Richard Henderson
Cc: Henderson, Stuart; gcc-patches@gcc.gnu.org
Subject: Re: [Patch] Bfin: Ensure rotrsi and rotlsi don't accept non-const
INTVALS
On 03/31/2011 05:42 PM, Richard Henderson wrote:
(rotate:SI (match_operand:SI 1 register_operand )
- (match_operand:SI 2 immediate_operand )))]
+ (match_operand:SI 2 const_int_operand )))]
{
- if (INTVAL (operands[2]) != 16)
+ if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
FAIL;
The point was, that you'd not need the CONST_INT check anymore,
because it's handled by the predicate.
I have a dim memory of the problem being that something didn't check the
predicate. Sure enough, with the patch below applied to a 4.3 tree, I get
/local/src/egcs/gcc-4_3-branch/gcc/testsuite/gcc.c-torture/execute/20020226-1.c:43:
internal compiler error: in gen_rotrsi3, at config/bfin/bfin.md:1632
Please submit a full bug report,
with preprocessed source if appropriate.
See http://gcc.gnu.org/bugs.html for instructions.
compiler exited with status 1
output is:
(reg:SI 193)
Stuart, try to identify whether it still happens. If so, a better fix
would be to change the expanders to honour the predicate.
Bernd
[Patch] bfin: addsi3 alterinative for IREGs.
This patch adds an IREG alternative to the addsi3 insn. 2011-04-04 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt * config/bfin/bfin.md (addsi3): Add an alternative for IREGS. Thanks, Stu Index: gcc/config/bfin/bfin.md === --- gcc/config/bfin/bfin.md (revision 3172) +++ gcc/config/bfin/bfin.md (revision 3173) @@ -1188,22 +1188,21 @@ %0 = %h2 * %h1 (IS,M)%! [(set_attr type dsp32)]) -;; The processor also supports ireg += mreg or ireg -= mreg, but these -;; are unusable if we don't ensure that the corresponding lreg is zero. -;; The same applies to the add/subtract constant versions involving -;; iregs +;; The alternative involving IREGS requires that the corresponding L register +;; is zero. (define_insn addsi3 - [(set (match_operand:SI 0 register_operand =ad,a,d) - (plus:SI (match_operand:SI 1 register_operand %0, a,d) -(match_operand:SI 2 reg_or_7bit_operand Ks7, a,d)))] + [(set (match_operand:SI 0 register_operand =ad,a,d,b) + (plus:SI (match_operand:SI 1 register_operand %0, a,d,0) +(match_operand:SI 2 reg_or_7bit_operand Ks7, a,d,fP2P4)))] @ %0 += %2; %0 = %1 + %2; - %0 = %1 + %2; + %0 = %1 + %2; + %0 += %2; [(set_attr type alu0) - (set_attr length 2,2,2)]) + (set_attr length 2,2,2,2)]) (define_insn ssaddsi3 [(set (match_operand:SI 0 register_operand =d)
RE: [Patch] Bfin: Ensure rotrsi and rotlsi don't accept non-const INTVALS
Seems reasonable to me, thanks! Patch updated.
Stu
2011-03-29 Stuart Henderson stuart.hender...@analog.com
From Bernd Schmidt
* config/bfin/bfin.md (rotrsi, rotlsi): Don't take INTVAL of anything
that's not CONST_INT.
-Original Message-
From: Richard Henderson [mailto:r...@redhat.com]
Sent: 30 March 2011 18:26
To: Henderson, Stuart
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [Patch] Bfin: Ensure rotrsi and rotlsi don't accept non-const
INTVALS
On 03/29/2011 08:49 AM, Henderson, Stuart wrote:
(match_operand:SI 2 immediate_operand )))]
{
- if (INTVAL (operands[2]) != 16)
+ if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
FAIL;
Perhaps use const_int_operand instead of immediate_operand.
r~
upstream.patch
Description: upstream.patch
RE: [Patch] improve bfin conditional move support
e.g. - operands[1] = bfin_gen_compare (operands[1], SImode); + operands[1] = bfin_gen_compare (operands[1], MODEmode); ? Updated patch attached. Thanks, Stu 2011-03-29 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt: * config/bfin/bfin.md (MOVCC): New mode_macro. (movmodecc_insn1, movmodecc_insn2, movmodecc): Renamed from movsicc_insn1, movsicc_insn2 and movsicc and macroized. Remove comments from generated assembly. -Original Message- From: Richard Henderson [mailto:r...@redhat.com] Sent: 30 March 2011 18:29 To: Henderson, Stuart Cc: gcc-patches@gcc.gnu.org Subject: Re: [Patch] improve bfin conditional move support On 03/29/2011 05:57 AM, Henderson, Stuart wrote: - operands[1] = bfin_gen_compare (operands[1], SImode); + operands[1] = bfin_gen_compare (operands[1], GET_MODE (operands[0])); FWIW, you can use MODEmode to get the proper value without having to read it from the operand. r~ upstream.patch Description: upstream.patch
RE: [Patch] bfin: move loop invariants out of loop
New version of previous patch. Apologies. Stu -Original Message- From: Henderson, Stuart Sent: 31 March 2011 12:20 To: gcc-patches@gcc.gnu.org Subject: [Patch] bfin: move loop invariants out of loop The attached patch attempts to move loop invariants out of loops for Blackfin. 2011-03-31 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt * config/bfin/bfin.c (bfin_gen_bundles): Don't try to bundle a jump. (bfin_optimize_loops_1, move_loop_constants): New static functions. (bfin_reorg): Call bfin_optimize_loops_1 if optimizing. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] bfin: fix profiling
The attached patch allows long jumps to __mcount, defines PROFILE_BEFORE_PROLOGUE and ensures ASM_OUTPUT_REG_PUSH pre-decrements the stack pointer. 2011-03-30 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt * config/bfin/bfin.h (FUNCTION_PROFILER): Take TARGET_LONG_CALLS into account and save/restore RETS. (PROFILE_BEFORE_PROLOGUE): Define. (ASM_OUTPUT_REG_PUSH, ASM_OUTPUT_REG_POP): Add tab character. Correct the push insn to use predecrement. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] improve bfin conditional move support
The attached patch improves conditional move mode support for Blackfin. 2011-03-29 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt: * config/bfin/bfin.md (MOVCC): New mode_macro. (movmodecc_insn1, movmodecc_insn2, movmodecc): Renamed from movsicc_insn1, movsicc_insn2 and movsicc and macroized. Remove comments from generated assembly. I don't have write permissions. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] Bfin: Ensure rotrsi and rotlsi don't accept non-const INTVALS
The attached patch ensures rotrsi and rotlsi don't accept non-const INTVALS. 2011-03-29 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt * config/bfin/bfin.md (rotrsi, rotlsi): Don't take INTVAL of anything that's not CONST_INT. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] muldi3 for bfin
The attached patch adds the muldi3 function for bfin. 2011-03-25 Stuart Henderson stuart.hender...@analog.com From Bernd Schmidt * config/bfin/t-bfin (LIB1ASMFUNCS): Add muldi3 and umulsi3_highpart. * config/bfin/t-bfin-elf (LIB1ASMFUNCS): Add muldi3. * config/bfin/t-bfin-linux (LIB1ASMFUNCS): Add muldi3. * config/bfin/t-bfin-uclinux (LIB1ASMFUNCS): Add muldi3. * config/bfin/lib1funcs.asm (___muldi3): New function. I don't have write permissions. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] New bfin divsi/udivsi implementations
The attached patch updates the blackfin ___divsi3 and ___udivsi3 implementations (and updates ___umodsi3 to match), as well as adding .size directives to all functions in the file. 2011-03-24 Stuart Henderson stuart.hender...@analog.com * gcc/config/bfin/lib1funcs.asm (___divsi3): New implementation, add .size directive and unguard .text directive. (___udivsi3): New implementation and add .size directive. (___umodsi3): Update to match new ___divsi3/___udivsi3 implementations and add .size directive. (___modsi3): Add .size directive. (___umulsi3_highpart): Likewise. (___smulsi3_highpart): Likewise. I don't have write permissions. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] Update bfin part tests to latest silicon revision
The attached testsuite patch updates the blackfin part macro tests to expect the latest silicon revision, as well as fixing up some duplication in the bf51x parts. 2011-03-23 Stuart Henderson stuart.hender...@analog.com * gcc.target/bfin/mcpu-bf542.c: Update to latest silicon revision. * gcc.target/bfin/mcpu-bf544.c: Likewise. * gcc.target/bfin/mcpu-bf547.c: Likewise. * gcc.target/bfin/mcpu-bf548.c: Likewise. * gcc.target/bfin/mcpu-bf549.c: Likewise. * gcc.target/bfin/mcpu-bf512.c: Update to latest silicon revision and remove duplication. * gcc.target/bfin/mcpu-bf514.c: Likewise. * gcc.target/bfin/mcpu-bf516.c: Likewise. * gcc.target/bfin/mcpu-bf518.c: Likewise. I don't have write permissions. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] Ensure libbffastfp overrides libgcc
The attached patch ensures libbffastfp overrides libgcc when -mfast-fp is used for bfin-uclinux targets. 2011-03-23 Stuart Henderson stuart.hender...@analog.com From Jie Zhang: * config/bfin/uclinux.h (LINK_GCC_C_SEQUENCE_SPEC): Make sure libbffastfp overrides libgcc when -mfast-fp. I don't have write permissions. Thanks, Stu upstream.patch Description: upstream.patch
RE: Fix for PR target/47779
Thanks. I don't have write permissions. Could someone apply it to trunk/appropriate branches? Stu -Original Message- From: Bernd Schmidt [mailto:ber...@codesourcery.com] Sent: 22 March 2011 16:03 To: Henderson, Stuart Cc: gcc-patches@gcc.gnu.org Subject: Re: Fix for PR target/47779 On 03/22/2011 10:54 AM, Henderson, Stuart wrote: ping. http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00505.html Please can you review the attached patch to fix PR 47779. The register constant names for bfin were clashing with uClibc (sys/ucontext.h) when cross compiling. I've simply changed the naming convention from REG_x to the more common x_REG. 2011-03-10 Stuart Henderson stuart.hender...@analog.com PR target/47779 * config/bfin/predicates.md: Change register constants from REG_x form to x_REG. * config/bfin/bfin.c: Likewise * config/bfin/bfin.h: Likewise * config/bfin/sync.md: Likewise * config/bfin/bfin.md: Likewise I still kind of think this must be a uClibc bug, but OK. Bernd
[Patch] Disable -mfdpic for bfin-uclinux target
-mfdpic is not supported for the bfin-uclinux target. this patch defines a macro in the uclinux header and then adds a check to bfin.c if the macro is defined. 2011-03-21 Stuart Henderson stuart.hender...@analog.com Originally from Bernd Schmidt * config/bfin/uclinux.h (SUBTARGET_FDPIC_NOT_SUPPORTED): New macro. * config/bfin/bfin.c (override_options): Test it and error if TARGET_FDPIC. I don't have write privileges. Thanks, Stu upstream.patch Description: upstream.patch
[Patch] Disable -fstack-limit for bfin -mfdpic
-fstack-limit- is not supported for bfin with -mfdpic and crashes if you try to use it. The attached patch warns the user that -fstack-limit is ignored with the -mfdpic switch for Blackfin and then disables it. 2011-03-17 Stuart Henderson stuart.hender...@analog.com Originally From Bernd Schmidt * config/bfin/bfin.c (override_options): Disable -fstack-limit for FD-PIC. I don't have write permissions. Stu upstream.patch Description: upstream.patch
RE: Fix for PR target/47951
Thanks. I don't have write privileges. If no-one objects, can someone apply the patch to trunk/appropriate branches? 2011-03-16 Stuart Henderson stuart.hender...@analog.com PR target/47951 * config/bfin/bfin.md (loop_end): Update constraints to ensure inputs match output. -Original Message- From: Bernd Schmidt [mailto:ber...@codesourcery.com] Sent: 15 March 2011 10:02 To: Henderson, Stuart Cc: gcc-patches@gcc.gnu.org Subject: Re: Fix for PR target/47951 On 03/14/2011 01:10 PM, Henderson, Stuart wrote: Hi, The attached patch is an attempt to fix PR 47951, however I'm fairly new to GCC and have little confidence in it. I've done some testing with it and it avoids the problem and doesn't appear to cause any new problems, but I'd appreciate more experienced eyes looking over it and giving pointers. Thanks, Stu Looks ok. Bernd
Fix for PR target/47951
Hi, The attached patch is an attempt to fix PR 47951, however I'm fairly new to GCC and have little confidence in it. I've done some testing with it and it avoids the problem and doesn't appear to cause any new problems, but I'd appreciate more experienced eyes looking over it and giving pointers. Thanks, Stu 47951.patch Description: 47951.patch
