[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:1461a33efbfbdff7fe805581db5bf1bc9f3e00f2 commit 1461a33efbfbdff7fe805581db5bf1bc9f3e00f2 Author: Michael Meissner Date: Tue Jul 16 12:07:26 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 88 ++ 1 file changed, 88 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index e2530576840c..1c112f0c0ed6 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,91 @@ + Branch work171-bugs, patch #331 + +Do not add -mvsx when testing the float128 support. + +In the past, we would add -mvsx when building the float128 support in libgcc. +This allowed us to build the float128 support on a big endian system where the +default cpu is power4. While the libgcc support can be built, given there is no +glibc support for float128 available. + +However, adding -mvsx and building the libgcc float128 support causes problems +if you set the default cpu to something like a 7540, which does not have VSX +support. The assembler complains that when the code does a ".machine 7450", you +cannot use VSX instructions. + +This patch changes the GCC tests so that it will only do the IEEE 128-bit tests +if the default compiler enables the VSX instruction set by default. Otherwise +all of the float128 tests will fail because the libgcc support is not available. + +2024-07-16 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + * gcc.target/powerpc/abs128-1.c: Remove -mvsx option. Add explicit + check for the float128 support. + * gcc.target/powerpc/bfp/scalar-insert-exp-16.c: Likewise. + * gcc.target/powerpc/copysign128-1.c: Likewise. + * gcc.target/powerpc/divkc3-1.c: Likewise. + * gcc.target/powerpc/float128-3.c: Likewise. + * gcc.target/powerpc/float128-5.c: Likewise. + * gcc.target/powerpc/float128-complex-2.: Likewise. + * gcc.target/powerpc/float128-math.: Likewise. + * gcc.target/powerpc/inf128-1.: Likewise. + * gcc.target/powerpc/mulkc3-1.c: Likewise. + * gcc.target/powerpc/nan128-1.c: Likewise. + * gcc.target/powerpc/p9-lxvx-stxvx-3.: Likewise. + * gcc.target/powerpc/pr104253.: Likewise. + * gcc.target/powerpc/pr70669.c: Likewise. + * gcc.target/powerpc/pr79004.c: Likewise. + * gcc.target/powerpc/pr79038-1.c: Likewise. + * gcc.target/powerpc/pr81959.c: Likewise. + * gcc.target/powerpc/pr85657-1.: Likewise. + * gcc.target/powerpc/pr85657-2.c: Likewise. + * gcc.target/powerpc/pr99708.: Likewise. + * gcc.target/powerpc/signbit-1.c: Likewise. + * gcc.target/powerpc/signbit-2.c: Likewise. + * lib/target-supports.exp (check_ppc_float128_sw_available): Likewise. + (check_ppc_float128_hw_available): Likewise. + (add_options_for___float128): Likewise. + (check_effective_target___float128): Likewise. + (check_effective_target_base_quadfloat_support): Likewise. + + Branch work171-bugs, patch #330 + +Do not add -mvsx when building libgcc float128 support. + +In the past, we would add -mvsx when building the float128 support in libgcc. +This allowed us to build the float128 support on a big endian system where the +default cpu is power4. While the libgcc support can be built, given there is no +glibc support for float128 available. + +However, adding -mvsx and building the libgcc float128 support causes problems +if you set the default cpu to something like a 7540, which does not have VSX +support. The assembler complains that when the code does a ".machine 7450", you +cannot use VSX instructions. + +With these patches, the float128 libgcc support is only built if the default +compiler has VSX support. If somebody wanted to enable the glibc support for +big endian, they would need to set the base cpu to power8 to enable building the +libgcc float128 libraries. + +2024-07-16 Michael Meissner + +libgcc/ + + PR target/115800 + PR target/113652 + * config.host (powerpc*-*-linux*): Do not add t-float128-hw or + t-float128-p10-hw if the default compiler does not support float128. + * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx when + building the basic float128 support. + * config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise. + * config/rs6000/t-float128-p10-hw (FP128_3_1_CFLAGS_HW): Likewise. + * configure.ac (powerpc*-*-linux*): Do not add -mvsx when testing + whether to build the float128 support. + * configure: Regenerate. + Branch work171-bugs, patch #325 was reverted Branch work171-bugs, patch #324 was reverted Branch work171-bugs, patch #323 was reverted
[gcc(refs/users/meissner/heads/work171-bugs)] Do not add -mvsx when building or testing the float128 support.
https://gcc.gnu.org/g:f36f5b39fac1029515774924f25b837b68fe2a0f
commit f36f5b39fac1029515774924f25b837b68fe2a0f
Author: Michael Meissner
Date: Tue Jul 16 12:01:08 2024 -0400
Do not add -mvsx when building or testing the float128 support.
In the past, we would add -mvsx when building the float128 support in
libgcc.
This allowed us to build the float128 support on a big endian system where
the
default cpu is power4. While the libgcc support can be built, given there
is no
glibc support for float128 available.
However, adding -mvsx and building the libgcc float128 support causes
problems
if you set the default cpu to something like a 7540, which does not have VSX
support. The assembler complains that when the code does a ".machine
7450", you
cannot use VSX instructions.
This patch changes the GCC tests so that it will only do the IEEE 128-bit
tests
if the default compiler enables the VSX instruction set by default.
Otherwise
all of the float128 tests will fail because the libgcc support is not
available.
2024-07-16 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* gcc.target/powerpc/abs128-1.c: Remove -mvsx option. Add explicit
check for the float128 support.
* gcc.target/powerpc/bfp/scalar-insert-exp-16.c: Likewise.
* gcc.target/powerpc/copysign128-1.c: Likewise.
* gcc.target/powerpc/divkc3-1.c: Likewise.
* gcc.target/powerpc/float128-3.c: Likewise.
* gcc.target/powerpc/float128-5.c: Likewise.
* gcc.target/powerpc/float128-complex-2.: Likewise.
* gcc.target/powerpc/float128-math.: Likewise.
* gcc.target/powerpc/inf128-1.: Likewise.
* gcc.target/powerpc/mulkc3-1.c: Likewise.
* gcc.target/powerpc/nan128-1.c: Likewise.
* gcc.target/powerpc/p9-lxvx-stxvx-3.: Likewise.
* gcc.target/powerpc/pr104253.: Likewise.
* gcc.target/powerpc/pr70669.c: Likewise.
* gcc.target/powerpc/pr79004.c: Likewise.
* gcc.target/powerpc/pr79038-1.c: Likewise.
* gcc.target/powerpc/pr81959.c: Likewise.
* gcc.target/powerpc/pr85657-1.: Likewise.
* gcc.target/powerpc/pr85657-2.c: Likewise.
* gcc.target/powerpc/pr99708.: Likewise.
* gcc.target/powerpc/signbit-1.c: Likewise.
* gcc.target/powerpc/signbit-2.c: Likewise.
* lib/target-supports.exp (check_ppc_float128_sw_available):
Likewise.
(check_ppc_float128_hw_available): Likewise.
(add_options_for___float128): Likewise.
(check_effective_target___float128): Likewise.
(check_effective_target_base_quadfloat_support): Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/abs128-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c | 1 +
gcc/testsuite/gcc.target/powerpc/copysign128-1.c| 3 ++-
gcc/testsuite/gcc.target/powerpc/divkc3-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/float128-3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/float128-5.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/float128-complex-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/float128-math.c| 2 +-
gcc/testsuite/gcc.target/powerpc/inf128-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/mulkc3-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/nan128-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr104253.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr70669.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr79004.c | 4 ++--
gcc/testsuite/gcc.target/powerpc/pr79038-1.c| 4 ++--
gcc/testsuite/gcc.target/powerpc/pr81959.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr85657-1.c| 2 +-
gcc/testsuite/gcc.target/powerpc/pr85657-2.c| 2 +-
gcc/testsuite/gcc.target/powerpc/pr99708.c | 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-1.c| 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-2.c| 2 +-
gcc/testsuite/lib/target-supports.exp | 10 +-
23 files changed, 39 insertions(+), 28 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
index fe5206daff8c..ee4c1aa24747 100644
--- a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
@@ -1,5 +1,6 @@
/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
-/* { dg-options "-mfloat128 -mvsx" } */
+/* { dg-options "-mfloat128" } */
+/* { dg-require-effective-target ppc_float128_sw } */
void
[gcc(refs/users/meissner/heads/work171-bugs)] Do not add -mvsx when building or testing the float128 support.
https://gcc.gnu.org/g:1e3d2a86601bea1763bb25bb4e5b23a761ae7d4c
commit 1e3d2a86601bea1763bb25bb4e5b23a761ae7d4c
Author: Michael Meissner
Date: Tue Jul 16 12:00:37 2024 -0400
Do not add -mvsx when building or testing the float128 support.
In the past, we would add -mvsx when building the float128 support in
libgcc.
This allowed us to build the float128 support on a big endian system where
the
default cpu is power4. While the libgcc support can be built, given there
is no
glibc support for float128 available.
However, adding -mvsx and building the libgcc float128 support causes
problems
if you set the default cpu to something like a 7540, which does not have VSX
support. The assembler complains that when the code does a ".machine
7450", you
cannot use VSX instructions.
With these patches, the float128 libgcc support is only built if the default
compiler has VSX support. If somebody wanted to enable the glibc support
for
big endian, they would need to set the base cpu to power8 to enable
building the
libgcc float128 libraries.
2024-07-16 Michael Meissner
libgcc/
PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not add t-float128-hw or
t-float128-p10-hw if the default compiler does not support float128.
* config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx when
building the basic float128 support.
* config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise.
* config/rs6000/t-float128-p10-hw (FP128_3_1_CFLAGS_HW): Likewise.
* configure.ac (powerpc*-*-linux*): Do not add -mvsx when testing
whether to build the float128 support.
* configure: Regenerate.
Diff:
---
libgcc/config.host | 12 ++--
libgcc/config/rs6000/t-float128| 8 +++-
libgcc/config/rs6000/t-float128-hw | 3 +--
libgcc/config/rs6000/t-float128-p10-hw | 3 +--
libgcc/configure | 8 +++-
libgcc/configure.ac| 8 +++-
6 files changed, 29 insertions(+), 13 deletions(-)
diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..261b08859a4d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
- fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
- fi
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
+ fi
+ fi
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index b09b5664af0e..93e78adcd624 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,13 @@ fp128_includes = $(srcdir)/soft-fp/double.h \
$(srcdir)/soft-fp/soft-fp.h
# Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
+#
+# In the past we added -mvsx to build the float128 specific libraries with the
+# VSX instruction set. This allowed the big endian GCC on server platforms to
+# build the float128 support. However, is causes problems when other default
+# cpu targets are used such as the 7450.
+
+FP128_CFLAGS_SW = -Wno-type-limits -mfloat128 \
-mno-float128-hardware -mno-gnu-attribute \
-I$(srcdir)/soft-fp \
-I$(srcdir)/config/rs6000 \
diff --git a/libgcc/config/rs6000/t-float128-hw
b/libgcc/config/rs6000/t-float128-hw
index ed67b572580f..82726c98b983 100644
--- a/libgcc/config/rs6000/t-float128-hw
+++ b/libgcc/config/rs6000/t-float128-hw
@@ -23,8 +23,7 @@ fp128_ifunc_obj = $(fp128_ifunc_static_obj)
$(fp128_ifunc_shared_obj)
fp128_sed_hw = -hw
# Build the hardware support functions with appropriate hardware support
-FP128_CFLAGS_HW = -Wno-type-limits -mvsx -mfloat128 \
- -mcpu=power9 \
+FP128_CFLAGS_HW = -Wno-type-limits -mfloat128 -mcpu=power9 \
-mfloat128-hardware -mno-gnu-attribute \
-I$(srcdir)/soft-fp \
-I$(srcdir)/config/rs6000
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:643ea344d77c82cadd4adcba6e8fa9ac46875f56 commit 643ea344d77c82cadd4adcba6e8fa9ac46875f56 Author: Michael Meissner Date: Tue Jul 16 11:24:54 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 153 ++--- 1 file changed, 5 insertions(+), 148 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 0b0b1bf63356..e2530576840c 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,151 +1,8 @@ - Branch work171-bugs, patch #325 - -Fix last change. - -2024-07-16 Michael Meissner - -gcc/testsuite/ - - PR target/115800 - PR target/113652 - - * gcc.target/powerpc/bfp/scalar-insert-exp-16.c: Require float128 - support. - * lib/target-supports.exp - (check_effective_target_base_quadfloat_support): Add check for explicit - float128. - - Branch work171-bugs, patch #324 - -Fix last change. - -2024-07-16 Michael Meissner - -gcc/testsuite/ - - PR target/115800 - PR target/113652 - - * gcc.target/powerpc/abs128-1.c: Fix typos. - * gcc.target/powerpc/copysign128-1.c: Likewise. - * gcc.target/powerpc/divkc3-1.c: Likewise. - - Branch work171-bugs, patch #323 - -Remove -mfloat128 option. - -2024-07-16 Michael Meissner - -gcc/testsuite/ - - PR target/115800 - PR target/113652 - - * gcc.target/powerpc/abs128-1.c: Remove passing -mfloat128. If needed, - add explicit requires for float128. - * gcc.target/powerpc/copysign128-1.c: Likewise. - * gcc.target/powerpc/divkc3-1.c: Likewise. - * gcc.target/powerpc/float128-3.c: Likewise. - * gcc.target/powerpc/float128-5.c: Likewise. - * gcc.target/powerpc/float128-math.c: Likewise. - * gcc.target/powerpc/inf128-1.c: Likewise. - * gcc.target/powerpc/mulkc3-1.c: Likewise. - * gcc.target/powerpc/nan128-1.c: Likewise. - * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Likewise. - * gcc.target/powerpc/pr104253.c: Likewise. - * gcc.target/powerpc/pr70640.c: Likewise. - * gcc.target/powerpc/pr70669.c: Likewise. - * gcc.target/powerpc/pr79004.c: Likewise. - * gcc.target/powerpc/pr79038-1.c: Likewise. - * gcc.target/powerpc/pr81959.c: Likewise. - * gcc.target/powerpc/pr85657-1.c: Likewise. - * gcc.target/powerpc/pr85657-2.c: Likewise. - * gcc.target/powerpc/pr99708.c: Likewise. - * gcc.target/powerpc/signbit-1.c: Likewise. - * gcc.target/powerpc/signbit-2.c: Likewise. - * gcc.target/powerpc/signbit-3.c: Likewise. - - Branch work171-bugs, patch #322 - -Fix typos. - -2024-07-15 Michael Meissner - -gcc/testsuite/ - - PR target/115800 - PR target/113652 - * lib/target-supports.exp (check_ppc_float128_sw_available): Fix typo in - last change. - (check_effective_target_ppc_ieee128_ok): Likewise. - - Branch work171-bugs, patch #321 - -Do not add -mfloat128 to the tests. - -2024-07-15 Michael Meissner - -gcc/testsuite/ - - PR target/115800 - PR target/113652 - * lib/target-supports.exp (check_ppc_float128_sw_available): Do not add - -mfloat128 on PowerPC tests. - (check_ppc_float128_hw_available): Likewise. - (check_effective_target_ppc_ieee128_ok): Likewise. - (add_options_for___float128): Likewise. - (check_effective_target_power10_ok): Likewise. - (check_effective_target_powerpc_float128_sw_ok): Likewise. - (check_effective_target_powerpc_float128_hw_ok): Likewise. - - Branch work171-bugs, patch #320 - -Do not add -mvsx when building or testing the float128 support. - -In the past, we would add -mvsx when building the float128 support in libgcc. -This allowed us to build the float128 support on a big endian system where the -default cpu is power4. While the libgcc support can be built, given there is no -glibc support for float128 available. - -However, adding -mvsx and building the libgcc float128 support causes problems -if you set the default cpu to something like a 7540, which does not have VSX -support. The assembler complains that when the code does a ".machine 7450", you -cannot use VSX instructions. - -With these patches, the float128 libgcc support is only built if the default -compiler has VSX support. If somebody wanted to enable the glibc support for -big endian, they would need to set the base cpu to power8 to enable building the -libgcc float128 libraries. - -In addition to the changes in libgcc, this patch also changes the GCC tests so -that it will only test float128 if the default compiler enables the VSX -instruction set. Otherwise all of the float128 tests will fail because the -libgcc support is not available.
[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes
https://gcc.gnu.org/g:abb176b702aa3e67dad6d1d724194e144cd85d8e
commit abb176b702aa3e67dad6d1d724194e144cd85d8e
Author: Michael Meissner
Date: Tue Jul 16 11:19:52 2024 -0400
Revert changes
Diff:
---
gcc/testsuite/gcc.target/powerpc/abs128-1.c| 3 +--
.../gcc.target/powerpc/bfp/scalar-insert-exp-16.c | 1 -
gcc/testsuite/gcc.target/powerpc/copysign128-1.c | 3 +--
gcc/testsuite/gcc.target/powerpc/divkc3-1.c| 3 +--
gcc/testsuite/gcc.target/powerpc/float128-3.c | 1 -
gcc/testsuite/gcc.target/powerpc/float128-5.c | 1 -
gcc/testsuite/gcc.target/powerpc/float128-math.c | 3 +--
gcc/testsuite/gcc.target/powerpc/inf128-1.c| 3 +--
gcc/testsuite/gcc.target/powerpc/mulkc3-1.c| 3 +--
gcc/testsuite/gcc.target/powerpc/nan128-1.c| 3 +--
gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr104253.c| 2 +-
gcc/testsuite/gcc.target/powerpc/pr70640.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr70669.c | 3 +--
gcc/testsuite/gcc.target/powerpc/pr79004.c | 3 +--
gcc/testsuite/gcc.target/powerpc/pr79038-1.c | 3 +--
gcc/testsuite/gcc.target/powerpc/pr81959.c | 3 +--
gcc/testsuite/gcc.target/powerpc/pr85657-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr85657-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr99708.c | 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-3.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 24 +-
libgcc/config.host | 12 +--
libgcc/config/rs6000/t-float128| 8 +---
libgcc/config/rs6000/t-float128-hw | 3 ++-
libgcc/config/rs6000/t-float128-p10-hw | 3 ++-
libgcc/configure | 8 +---
libgcc/configure.ac| 8 +---
30 files changed, 47 insertions(+), 73 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
index e8702ec3127a..fe5206daff8c 100644
--- a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
@@ -1,6 +1,5 @@
/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
-/* { dg-options "-mvsx" } */
-/* { dg-require-effective-target ppc_float128_sw } */
+/* { dg-options "-mfloat128 -mvsx" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
index 081fb2e2995f..f0e03c5173d2 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
@@ -2,7 +2,6 @@
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9 -save-temps" } */
-/* { dg-require-effective-target ppc_float128_sw } */
#include
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
index ac8528b53273..429dfc072e3b 100644
--- a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
@@ -1,6 +1,5 @@
/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
-/* { dg-options "-mvsx" } */
-/* { dg-require-effective-target ppc_float128_sw } */
+/* { dg-options "-mfloat128 -mvsx" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
index cb7335f2a755..89bf04f12a97 100644
--- a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
@@ -1,6 +1,5 @@
/* { dg-do run { target { powerpc64*-*-* && p8vector_hw } } } */
-/* { dg-options "-mvsx" } */
-/* { dg-require-effective-target ppc_float128_sw } */
+/* { dg-options "-mfloat128 -mvsx" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-3.c
b/gcc/testsuite/gcc.target/powerpc/float128-3.c
index e58bccdfa159..e62ad5f5247f 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-3.c
@@ -1,7 +1,6 @@
/* { dg-do compile { target { powerpc*-*-linux* } } } */
/* { dg-options "-O2 -mvsx -mno-float128" } */
/* { dg-require-effective-target powerpc_vsx } */
-/* { dg-require-effective-target ppc_float128_sw } */
/* Test that we can use #pragma GCC target to enable -mfloat128. */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-5.c
b/gcc/testsuite/gcc.target/powerpc/float128-5.c
index 8a5d8ceff216..8a9eee971fbc 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-5.c
@@ -1,7 +1,6 @@
/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
/* {
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:9a87fdccc1209cfd436aaad7e3fa3b27049990e6 commit 9a87fdccc1209cfd436aaad7e3fa3b27049990e6 Author: Michael Meissner Date: Tue Jul 16 04:41:11 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 17 + 1 file changed, 17 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index dc2944b781bc..0b0b1bf63356 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,20 @@ + Branch work171-bugs, patch #325 + +Fix last change. + +2024-07-16 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + + * gcc.target/powerpc/bfp/scalar-insert-exp-16.c: Require float128 + support. + * lib/target-supports.exp + (check_effective_target_base_quadfloat_support): Add check for explicit + float128. + Branch work171-bugs, patch #324 Fix last change.
[gcc(refs/users/meissner/heads/work171-bugs)] Fix last change.
https://gcc.gnu.org/g:23b6b57519e181ae6a10a609061a922bb5694aa7
commit 23b6b57519e181ae6a10a609061a922bb5694aa7
Author: Michael Meissner
Date: Tue Jul 16 04:40:06 2024 -0400
Fix last change.
2024-07-16 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* gcc.target/powerpc/bfp/scalar-insert-exp-16.c: Require float128
support.
* lib/target-supports.exp
(check_effective_target_base_quadfloat_support): Add check for
explicit
float128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c | 1 +
gcc/testsuite/lib/target-supports.exp | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
index f0e03c5173d2..081fb2e2995f 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
@@ -2,6 +2,7 @@
/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9 -save-temps" } */
+/* { dg-require-effective-target ppc_float128_sw } */
#include
#include
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 6b460f24cc3a..9e94fd78d925 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3953,7 +3953,7 @@ proc add_options_for___float128 { flags } {
proc check_effective_target_base_quadfloat_support { } {
if { [istarget powerpc*-*-*] } {
- return [check_vsx_hw_available]
+ return [check_effective_target_powerpc_float128_sw_ok]
}
return 1
}
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:33e7ebfe00ba322e5272571682c63aece6276c98 commit 33e7ebfe00ba322e5272571682c63aece6276c98 Author: Michael Meissner Date: Tue Jul 16 03:15:43 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 15 +++ 1 file changed, 15 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 99b0a6a4ec40..dc2944b781bc 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,18 @@ + Branch work171-bugs, patch #324 + +Fix last change. + +2024-07-16 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + + * gcc.target/powerpc/abs128-1.c: Fix typos. + * gcc.target/powerpc/copysign128-1.c: Likewise. + * gcc.target/powerpc/divkc3-1.c: Likewise. + Branch work171-bugs, patch #323 Remove -mfloat128 option.
[gcc(refs/users/meissner/heads/work171-bugs)] Fix last change.
https://gcc.gnu.org/g:d16ee83caaff471d6f202443a66b13780da55f23
commit d16ee83caaff471d6f202443a66b13780da55f23
Author: Michael Meissner
Date: Tue Jul 16 03:14:35 2024 -0400
Fix last change.
2024-07-16 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* gcc.target/powerpc/abs128-1.c: Fix typos.
* gcc.target/powerpc/copysign128-1.c: Likewise.
* gcc.target/powerpc/divkc3-1.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/abs128-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/copysign128-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/divkc3-1.c | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
index 3449c9ca94d8..e8702ec3127a 100644
--- a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
@@ -1,5 +1,6 @@
-/* { dg-do run { target { powerpc64*-*-* && vsx_hw && ppc_float128_sw } } } */
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
/* { dg-options "-mvsx" } */
+/* { dg-require-effective-target ppc_float128_sw } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
index 1e8ae5fa7533..ac8528b53273 100644
--- a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
@@ -1,5 +1,6 @@
-/* { dg-do run { target { powerpc64*-*-* && vsx_hw && ppc_float128_sw } } } */
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
/* { dg-options "-mvsx" } */
+/* { dg-require-effective-target ppc_float128_sw } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
index 2b4f08ecef51..cb7335f2a755 100644
--- a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
@@ -1,5 +1,6 @@
-/* { dg-do run { target { powerpc64*-*-* && p8vector_hw && ppc_float128_sw } }
} */
+/* { dg-do run { target { powerpc64*-*-* && p8vector_hw } } } */
/* { dg-options "-mvsx" } */
+/* { dg-require-effective-target ppc_float128_sw } */
void abort ();
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:fc7d1bdcd0cd73e800030aa4845324ec5071cd55 commit fc7d1bdcd0cd73e800030aa4845324ec5071cd55 Author: Michael Meissner Date: Tue Jul 16 02:39:13 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 35 +++ 1 file changed, 35 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index c2eb08c8f8c2..99b0a6a4ec40 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,38 @@ + Branch work171-bugs, patch #323 + +Remove -mfloat128 option. + +2024-07-16 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + + * gcc.target/powerpc/abs128-1.c: Remove passing -mfloat128. If needed, + add explicit requires for float128. + * gcc.target/powerpc/copysign128-1.c: Likewise. + * gcc.target/powerpc/divkc3-1.c: Likewise. + * gcc.target/powerpc/float128-3.c: Likewise. + * gcc.target/powerpc/float128-5.c: Likewise. + * gcc.target/powerpc/float128-math.c: Likewise. + * gcc.target/powerpc/inf128-1.c: Likewise. + * gcc.target/powerpc/mulkc3-1.c: Likewise. + * gcc.target/powerpc/nan128-1.c: Likewise. + * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Likewise. + * gcc.target/powerpc/pr104253.c: Likewise. + * gcc.target/powerpc/pr70640.c: Likewise. + * gcc.target/powerpc/pr70669.c: Likewise. + * gcc.target/powerpc/pr79004.c: Likewise. + * gcc.target/powerpc/pr79038-1.c: Likewise. + * gcc.target/powerpc/pr81959.c: Likewise. + * gcc.target/powerpc/pr85657-1.c: Likewise. + * gcc.target/powerpc/pr85657-2.c: Likewise. + * gcc.target/powerpc/pr99708.c: Likewise. + * gcc.target/powerpc/signbit-1.c: Likewise. + * gcc.target/powerpc/signbit-2.c: Likewise. + * gcc.target/powerpc/signbit-3.c: Likewise. + Branch work171-bugs, patch #322 Fix typos.
[gcc(refs/users/meissner/heads/work171-bugs)] Remove -mfloat128 option.
https://gcc.gnu.org/g:a05125de6ec8a4d6fe02e3fa88cca3633b95de1a
commit a05125de6ec8a4d6fe02e3fa88cca3633b95de1a
Author: Michael Meissner
Date: Tue Jul 16 02:37:03 2024 -0400
Remove -mfloat128 option.
2024-07-15 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* gcc.target/powerpc/abs128-1.c: Remove passing -mfloat128. If
needed,
add explicit requires for float128.
* gcc.target/powerpc/copysign128-1.c: Likewise.
* gcc.target/powerpc/divkc3-1.c: Likewise.
* gcc.target/powerpc/float128-3.c: Likewise.
* gcc.target/powerpc/float128-5.c: Likewise.
* gcc.target/powerpc/float128-math.c: Likewise.
* gcc.target/powerpc/inf128-1.c: Likewise.
* gcc.target/powerpc/mulkc3-1.c: Likewise.
* gcc.target/powerpc/nan128-1.c: Likewise.
* gcc.target/powerpc/p9-lxvx-stxvx-3.c: Likewise.
* gcc.target/powerpc/pr104253.c: Likewise.
* gcc.target/powerpc/pr70640.c: Likewise.
* gcc.target/powerpc/pr70669.c: Likewise.
* gcc.target/powerpc/pr79004.c: Likewise.
* gcc.target/powerpc/pr79038-1.c: Likewise.
* gcc.target/powerpc/pr81959.c: Likewise.
* gcc.target/powerpc/pr85657-1.c: Likewise.
* gcc.target/powerpc/pr85657-2.c: Likewise.
* gcc.target/powerpc/pr99708.c: Likewise.
* gcc.target/powerpc/signbit-1.c: Likewise.
* gcc.target/powerpc/signbit-2.c: Likewise.
* gcc.target/powerpc/signbit-3.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/abs128-1.c| 4 ++--
gcc/testsuite/gcc.target/powerpc/copysign128-1.c | 4 ++--
gcc/testsuite/gcc.target/powerpc/divkc3-1.c| 4 ++--
gcc/testsuite/gcc.target/powerpc/float128-3.c | 1 +
gcc/testsuite/gcc.target/powerpc/float128-5.c | 1 +
gcc/testsuite/gcc.target/powerpc/float128-math.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/inf128-1.c| 3 ++-
gcc/testsuite/gcc.target/powerpc/mulkc3-1.c| 3 ++-
gcc/testsuite/gcc.target/powerpc/nan128-1.c| 3 ++-
gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr104253.c| 2 +-
gcc/testsuite/gcc.target/powerpc/pr70640.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr70669.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr79004.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr79038-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr81959.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr85657-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr85657-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr99708.c | 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/signbit-3.c | 2 +-
22 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
index fe5206daff8c..3449c9ca94d8 100644
--- a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
@@ -1,5 +1,5 @@
-/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
-/* { dg-options "-mfloat128 -mvsx" } */
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw && ppc_float128_sw } } } */
+/* { dg-options "-mvsx" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
index 429dfc072e3b..1e8ae5fa7533 100644
--- a/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/copysign128-1.c
@@ -1,5 +1,5 @@
-/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
-/* { dg-options "-mfloat128 -mvsx" } */
+/* { dg-do run { target { powerpc64*-*-* && vsx_hw && ppc_float128_sw } } } */
+/* { dg-options "-mvsx" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
index 89bf04f12a97..2b4f08ecef51 100644
--- a/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/divkc3-1.c
@@ -1,5 +1,5 @@
-/* { dg-do run { target { powerpc64*-*-* && p8vector_hw } } } */
-/* { dg-options "-mfloat128 -mvsx" } */
+/* { dg-do run { target { powerpc64*-*-* && p8vector_hw && ppc_float128_sw } }
} */
+/* { dg-options "-mvsx" } */
void abort ();
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-3.c
b/gcc/testsuite/gcc.target/powerpc/float128-3.c
index e62ad5f5247f..e58bccdfa159 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-3.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-linux* } } } */
/* { dg-options "-O2 -mvsx -mno-float128" } */
/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-require-effective-target
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:2cccf2a28a48b07dc553f9b34db1b44377e1ff6c commit 2cccf2a28a48b07dc553f9b34db1b44377e1ff6c Author: Michael Meissner Date: Mon Jul 15 23:17:16 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 14 ++ 1 file changed, 14 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 7a40e702d934..c2eb08c8f8c2 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,17 @@ + Branch work171-bugs, patch #322 + +Fix typos. + +2024-07-15 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + * lib/target-supports.exp (check_ppc_float128_sw_available): Fix typo in + last change. + (check_effective_target_ppc_ieee128_ok): Likewise. + Branch work171-bugs, patch #321 Do not add -mfloat128 to the tests.
[gcc(refs/users/meissner/heads/work171-bugs)] Fix typos.
https://gcc.gnu.org/g:6482b9e47c5ff9557c720eedabdfccfb50b70edd
commit 6482b9e47c5ff9557c720eedabdfccfb50b70edd
Author: Michael Meissner
Date: Mon Jul 15 23:16:02 2024 -0400
Fix typos.
2024-07-15 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* lib/target-supports.exp (check_ppc_float128_sw_available): Fix
typo in
last change.
(check_effective_target_ppc_ieee128_ok): Likewise.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 8ab8f6a10586..6b460f24cc3a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2987,7 +2987,7 @@ proc check_ppc_float128_sw_available { } {
__float128 z = x + y;
return (z != 3.0q);
}
- } $options
+ } ""
}
}]
}
@@ -3035,7 +3035,7 @@ proc check_effective_target_ppc_ieee128_ok { } {
__ieee128 a;
return 0;
}
- } $options
+ } ""
}
}]
}
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:befe8a6d0c46daad90a4c3631c00dd5f40a6b1c4 commit befe8a6d0c46daad90a4c3631c00dd5f40a6b1c4 Author: Michael Meissner Date: Mon Jul 15 19:06:53 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 19 +++ 1 file changed, 19 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 5b1df025f236..7a40e702d934 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,22 @@ + Branch work171-bugs, patch #321 + +Do not add -mfloat128 to the tests. + +2024-07-15 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + * lib/target-supports.exp (check_ppc_float128_sw_available): Do not add + -mfloat128 on PowerPC tests. + (check_ppc_float128_hw_available): Likewise. + (check_effective_target_ppc_ieee128_ok): Likewise. + (add_options_for___float128): Likewise. + (check_effective_target_power10_ok): Likewise. + (check_effective_target_powerpc_float128_sw_ok): Likewise. + (check_effective_target_powerpc_float128_hw_ok): Likewise. + Branch work171-bugs, patch #320 Do not add -mvsx when building or testing the float128 support.
[gcc(refs/users/meissner/heads/work171-bugs)] Do not add -mfloat128 to the tests.
https://gcc.gnu.org/g:9cbff1336d43a8c13fc6d77ee93d165f6bc86de6
commit 9cbff1336d43a8c13fc6d77ee93d165f6bc86de6
Author: Michael Meissner
Date: Mon Jul 15 19:06:08 2024 -0400
Do not add -mfloat128 to the tests.
2024-07-15 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* lib/target-supports.exp (check_ppc_float128_sw_available): Do not
add
-mfloat128 on PowerPC tests.
(check_ppc_float128_hw_available): Likewise.
(check_effective_target_ppc_ieee128_ok): Likewise.
(add_options_for___float128): Likewise.
(check_effective_target_power10_ok): Likewise.
(check_effective_target_powerpc_float128_sw_ok): Likewise.
(check_effective_target_powerpc_float128_hw_ok): Likewise.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ca5276873064..8ab8f6a10586 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2979,7 +2979,6 @@ proc check_ppc_float128_sw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128"
check_runtime_nocache ppc_float128_sw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3005,7 +3004,7 @@ proc check_ppc_float128_hw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128 -mfloat128-hardware -mcpu=power9"
+ set options "-mfloat128-hardware -mcpu=power9"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3030,7 +3029,6 @@ proc check_effective_target_ppc_ieee128_ok { } {
|| [istarget *-*-vxworks*]} {
expr 0
} else {
- set options "-mfloat128"
check_runtime_nocache ppc_ieee128_ok {
int main()
{
@@ -3946,9 +3944,6 @@ proc check_effective_target___float128 { } {
}
proc add_options_for___float128 { flags } {
-if { [istarget powerpc*-*-linux*] } {
- return "$flags -mfloat128"
-}
return "$flags"
}
@@ -7217,8 +7212,9 @@ proc check_effective_target_power10_ok { } {
}
}
-# Return 1 if this is a PowerPC target supporting -mfloat128 via either
-# software emulation on power7/power8 systems or hardware support on power9.
+# Return 1 if this is a PowerPC target supporting IEEE 128-bit floating point
+# via either software emulation on power7/power8 systems or hardware support on
+# power9.
proc check_effective_target_powerpc_float128_sw_ok { } {
if { [istarget powerpc*-*-*]
@@ -7234,14 +7230,14 @@ proc check_effective_target_powerpc_float128_sw_ok { } {
__float128 z = x + y;
return (z == 3.0q);
}
- } "-mfloat128"]
+ }]
} else {
return 0
}
}
-# Return 1 if this is a PowerPC target supporting -mfloat128 via hardware
-# support on power9.
+# Return 1 if this is a PowerPC target supporting IEEE 128-bit floating point
+# via hardware support on power9.
proc check_effective_target_powerpc_float128_hw_ok { } {
if { [istarget powerpc*-*-*]
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:3c3f8727179681e80cf28e57bbdb18f672c2e8d1 commit 3c3f8727179681e80cf28e57bbdb18f672c2e8d1 Author: Michael Meissner Date: Mon Jul 15 13:13:06 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 48 1 file changed, 48 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 076ccebfc45e..5b1df025f236 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,51 @@ + Branch work171-bugs, patch #320 + +Do not add -mvsx when building or testing the float128 support. + +In the past, we would add -mvsx when building the float128 support in libgcc. +This allowed us to build the float128 support on a big endian system where the +default cpu is power4. While the libgcc support can be built, given there is no +glibc support for float128 available. + +However, adding -mvsx and building the libgcc float128 support causes problems +if you set the default cpu to something like a 7540, which does not have VSX +support. The assembler complains that when the code does a ".machine 7450", you +cannot use VSX instructions. + +With these patches, the float128 libgcc support is only built if the default +compiler has VSX support. If somebody wanted to enable the glibc support for +big endian, they would need to set the base cpu to power8 to enable building the +libgcc float128 libraries. + +In addition to the changes in libgcc, this patch also changes the GCC tests so +that it will only test float128 if the default compiler enables the VSX +instruction set. Otherwise all of the float128 tests will fail because the +libgcc support is not available. + +2024-07-15 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + * lib/target-supports.exp (check_ppc_float128_sw_available): Do not add + the -mvsx option. + (check_effective_target___float128): Likewise. + +libgcc/ + + PR target/115800 + PR target/113652 + * config.host (powerpc*-*-linux*): Do not add t-float128-hw or + t-float128-p10-hw if the default compiler does not support float128. + * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx when + building the basic float128 support. + * config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise. + * config/rs6000/t-float128-p10-hw (FP128_3_1_CFLAGS_HW): Likewise. + * configure.ac (powerpc*-*-linux*): Do not add -mvsx when testing + whether to build the float128 support. + * configure: Regenerate. + Branch work171-bugs, patch #311 was reverted Branch work171-bugs, patch #310 was reverted Branch work171-bugs, patch #304 was reverted
[gcc(refs/users/meissner/heads/work171-bugs)] Do not add -mvsx when building or testing the float128 support.
https://gcc.gnu.org/g:5b62b27b2f30b678e2f9ba4f743ce080ea51f1dc
commit 5b62b27b2f30b678e2f9ba4f743ce080ea51f1dc
Author: Michael Meissner
Date: Mon Jul 15 13:11:49 2024 -0400
Do not add -mvsx when building or testing the float128 support.
In the past, we would add -mvsx when building the float128 support in
libgcc.
This allowed us to build the float128 support on a big endian system where
the
default cpu is power4. While the libgcc support can be built, given there
is no
glibc support for float128 available.
However, adding -mvsx and building the libgcc float128 support causes
problems
if you set the default cpu to something like a 7540, which does not have VSX
support. The assembler complains that when the code does a ".machine
7450", you
cannot use VSX instructions.
With these patches, the float128 libgcc support is only built if the default
compiler has VSX support. If somebody wanted to enable the glibc support
for
big endian, they would need to set the base cpu to power8 to enable
building the
libgcc float128 libraries.
In addition to the changes in libgcc, this patch also changes the GCC tests
so
that it will only test float128 if the default compiler enables the VSX
instruction set. Otherwise all of the float128 tests will fail because the
libgcc support is not available.
2024-07-15 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* lib/target-supports.exp (check_ppc_float128_sw_available): Do not
add
the -mvsx option.
(check_effective_target___float128): Likewise.
libgcc/
PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not add t-float128-hw or
t-float128-p10-hw if the default compiler does not support float128.
* config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx when
building the basic float128 support.
* config/rs6000/t-float128-hw (FP128_CFLAGS_HW): Likewise.
* config/rs6000/t-float128-p10-hw (FP128_3_1_CFLAGS_HW): Likewise.
* configure.ac (powerpc*-*-linux*): Do not add -mvsx when testing
whether to build the float128 support.
* configure: Regenerate.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 8
libgcc/config.host | 12 ++--
libgcc/config/rs6000/t-float128| 8 +++-
libgcc/config/rs6000/t-float128-hw | 3 +--
libgcc/config/rs6000/t-float128-p10-hw | 3 +--
libgcc/configure | 8 +++-
libgcc/configure.ac| 8 +++-
7 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index b7df6150bcbd..ca5276873064 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2979,7 +2979,7 @@ proc check_ppc_float128_sw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128 -mvsx"
+ set options "-mfloat128"
check_runtime_nocache ppc_float128_sw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3005,7 +3005,7 @@ proc check_ppc_float128_hw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128 -mvsx -mfloat128-hardware -mcpu=power9"
+ set options "-mfloat128 -mfloat128-hardware -mcpu=power9"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3947,7 +3947,7 @@ proc check_effective_target___float128 { } {
proc add_options_for___float128 { flags } {
if { [istarget powerpc*-*-linux*] } {
- return "$flags -mfloat128 -mvsx"
+ return "$flags -mfloat128"
}
return "$flags"
}
@@ -7234,7 +7234,7 @@ proc check_effective_target_powerpc_float128_sw_ok { } {
__float128 z = x + y;
return (z == 3.0q);
}
- } "-mfloat128 -mvsx"]
+ } "-mfloat128"]
} else {
return 0
}
diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..261b08859a4d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
- fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
- fi
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
-
[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes
https://gcc.gnu.org/g:aa366303d519602bef7b7425d15ce517a31e3291
commit aa366303d519602bef7b7425d15ce517a31e3291
Author: Michael Meissner
Date: Mon Jul 15 12:34:03 2024 -0400
Revert changes
Diff:
---
gcc/ChangeLog.bugs | 22 +-
libgcc/config.host | 16 ++--
libgcc/config/rs6000/t-float128 | 2 +-
libgcc/config/rs6000/t-float128-vsx | 3 ---
libgcc/configure| 29 +
libgcc/configure.ac | 17 +
6 files changed, 18 insertions(+), 71 deletions(-)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index f75ce1a0c83a..076ccebfc45e 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,24 +1,4 @@
- Branch work171-bugs, patch #311
-
-Use -mcpu=power7 if needed and not -mvsx to build float128 support.
-
-2024-07-12 Michael Meissner
-
-libgcc/
-
- PR target/115800
- PR target/113652
- * config.host (powerpc*-*-linux*): Do not enable the float128 hardware
- and float128 power10 hardware support unless the basic float128 support
- is added. Add support for building the float128 support when the default
- compiler does not enable VSX.
- * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not use -mvsx, instead
- use FP128_CFLAGS_VSX to optionally add -mcpu=power7.
- * config/rs6000/t-float128-vsx: New file.
- * configure.ac (powerpc*-*-linux*): Determine if the default powerpc cpu
- includes VSX support.
- * configure: Regenerate.
-
+ Branch work171-bugs, patch #311 was reverted
Branch work171-bugs, patch #310 was reverted
Branch work171-bugs, patch #304 was reverted
Branch work171-bugs, patch #303 was reverted
diff --git a/libgcc/config.host b/libgcc/config.host
index 804d12e8fd6a..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1291,19 +1291,15 @@ powerpc*-*-linux*)
esac
if test $libgcc_cv_powerpc_float128 = yes; then
- if test $libgcc_cv_powerpc_vsx = no; then
- tmake_file="${tmake_file} rs6000/t-float128-vsx"
- fi
-
tmake_file="${tmake_file} rs6000/t-float128"
+ fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
+ fi
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
- fi
- fi
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index 8037a6290a82..b09b5664af0e 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,7 @@ fp128_includes= $(srcdir)/soft-fp/double.h \
$(srcdir)/soft-fp/soft-fp.h
# Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits $(FLOAT128_CFLAGS_VSX)
-mfloat128 \
+FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
-mno-float128-hardware -mno-gnu-attribute \
-I$(srcdir)/soft-fp \
-I$(srcdir)/config/rs6000 \
diff --git a/libgcc/config/rs6000/t-float128-vsx
b/libgcc/config/rs6000/t-float128-vsx
deleted file mode 100644
index c691546242d9..
--- a/libgcc/config/rs6000/t-float128-vsx
+++ /dev/null
@@ -1,3 +0,0 @@
-# Add -mcpu=power7 option if the default compiler does not support VSX
-
-FLOAT128_CFLAGS_VSX= -mabi=altivec -mcpu=power7
diff --git a/libgcc/configure b/libgcc/configure
index ad12baf965f4..a69d314374a3 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,32 +5180,13 @@ esac
esac
case ${host} in
-# Test if the default compiler enables VSX. If it does not, we need to build
-# the float128 bit support using -mcpu=power7 to enable the VSX instruction
set.
-#
-# Also check if a new glibc is being used so that __builtin_cpu_supports can be
-# used.
+# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
+# check if we have VSX (ISA 2.06) support to build the software libraries, and
+# whether the assembler can handle xsaddqp for hardware support. Also check if
+# a new glibc is being used so that __builtin_cpu_supports can be used.
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:de57e5fc86709f9e18d9d56b599d3d13104f94be commit de57e5fc86709f9e18d9d56b599d3d13104f94be Author: Michael Meissner Date: Fri Jul 12 20:59:30 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 21 + 1 file changed, 21 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index dd7b7846d905..f75ce1a0c83a 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,24 @@ + Branch work171-bugs, patch #311 + +Use -mcpu=power7 if needed and not -mvsx to build float128 support. + +2024-07-12 Michael Meissner + +libgcc/ + + PR target/115800 + PR target/113652 + * config.host (powerpc*-*-linux*): Do not enable the float128 hardware + and float128 power10 hardware support unless the basic float128 support + is added. Add support for building the float128 support when the default + compiler does not enable VSX. + * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not use -mvsx, instead + use FP128_CFLAGS_VSX to optionally add -mcpu=power7. + * config/rs6000/t-float128-vsx: New file. + * configure.ac (powerpc*-*-linux*): Determine if the default powerpc cpu + includes VSX support. + * configure: Regenerate. + Branch work171-bugs, patch #310 was reverted Branch work171-bugs, patch #304 was reverted Branch work171-bugs, patch #303 was reverted
[gcc(refs/users/meissner/heads/work171-bugs)] Use -mcpu=power7 if needed and not -mvsx to build float128 support.
https://gcc.gnu.org/g:a92ecfb87c48c9a4c7a7e12d5ec1491198ea0e18
commit a92ecfb87c48c9a4c7a7e12d5ec1491198ea0e18
Author: Michael Meissner
Date: Fri Jul 12 20:58:20 2024 -0400
Use -mcpu=power7 if needed and not -mvsx to build float128 support.
2024-07-12 Michael Meissner
libgcc/
PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not enable the float128
hardware
and float128 power10 hardware support unless the basic float128
support
is added. Add support for building the float128 support when the
default
compiler does not enable VSX.
* config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not use -mvsx,
instead
use FP128_CFLAGS_VSX to optionally add -mcpu=power7.
* config/rs6000/t-float128-vsx: New file.
* configure.ac (powerpc*-*-linux*): Determine if the default
powerpc cpu
includes VSX support.
* configure: Regenerate.
Diff:
---
libgcc/config.host | 16 ++--
libgcc/config/rs6000/t-float128 | 2 +-
libgcc/config/rs6000/t-float128-vsx | 3 +++
libgcc/configure| 29 -
libgcc/configure.ac | 17 -
5 files changed, 50 insertions(+), 17 deletions(-)
diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..804d12e8fd6a 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1291,15 +1291,19 @@ powerpc*-*-linux*)
esac
if test $libgcc_cv_powerpc_float128 = yes; then
+ if test $libgcc_cv_powerpc_vsx = no; then
+ tmake_file="${tmake_file} rs6000/t-float128-vsx"
+ fi
+
tmake_file="${tmake_file} rs6000/t-float128"
- fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
- fi
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
+ fi
+ fi
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index b09b5664af0e..8037a6290a82 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,7 @@ fp128_includes= $(srcdir)/soft-fp/double.h \
$(srcdir)/soft-fp/soft-fp.h
# Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
+FP128_CFLAGS_SW = -Wno-type-limits $(FLOAT128_CFLAGS_VSX)
-mfloat128 \
-mno-float128-hardware -mno-gnu-attribute \
-I$(srcdir)/soft-fp \
-I$(srcdir)/config/rs6000 \
diff --git a/libgcc/config/rs6000/t-float128-vsx
b/libgcc/config/rs6000/t-float128-vsx
new file mode 100644
index ..c691546242d9
--- /dev/null
+++ b/libgcc/config/rs6000/t-float128-vsx
@@ -0,0 +1,3 @@
+# Add -mcpu=power7 option if the default compiler does not support VSX
+
+FLOAT128_CFLAGS_VSX= -mabi=altivec -mcpu=power7
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..ad12baf965f4 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,13 +5180,32 @@ esac
esac
case ${host} in
-# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
-# check if we have VSX (ISA 2.06) support to build the software libraries, and
-# whether the assembler can handle xsaddqp for hardware support. Also check if
-# a new glibc is being used so that __builtin_cpu_supports can be used.
+# Test if the default compiler enables VSX. If it does not, we need to build
+# the float128 bit support using -mcpu=power7 to enable the VSX instruction
set.
+#
+# Also check if a new glibc is being used so that __builtin_cpu_supports can be
+# used.
powerpc*-*-linux*)
saved_CFLAGS="$CFLAGS"
- CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking if VSX is enabled by
default" >&5
+$as_echo_n "checking if VSX is enabled by default... " >&6; }
+if ${libgcc_cv_powerpc_vsx+:} false; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+vector double dadd (vector double a, vector double b) { return a + b; }
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+ libgcc_cv_powerpc_vsx=yes
+else
+ libgcc_cv_powerpc_vsx=no
+fi
+rm -f core conftest.err
[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes
https://gcc.gnu.org/g:78633b506f6673f1b3bfcd39df55933ae4f1d4eb
commit 78633b506f6673f1b3bfcd39df55933ae4f1d4eb
Author: Michael Meissner
Date: Fri Jul 12 20:27:11 2024 -0400
Revert changes
Diff:
---
gcc/ChangeLog.bugs | 24 +-
libgcc/config.host | 12 -
libgcc/configure| 71 +++--
libgcc/configure.ac | 17 ++---
4 files changed, 13 insertions(+), 111 deletions(-)
diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index f2f6f7986da8..dd7b7846d905 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,26 +1,4 @@
- Branch work171-bugs, patch #310
-
-Add checks for building the IEEE 128-bit libgcc support if VSX is not
available.
-
-In the past, we would build libgcc and eable the float128 libraries by adding
--mvsx -mabi=altivec to build the support libraries. However, this causes
-problems if the default cpu is a 7450. This patch checks to see if can link a
-program using the options, and if we can't link the program, do not build the
-float128 libraries.
-
-2024-07-12 Michael Meissner
-
-libgcc/
-
- PR target/115800
- PR target/113652
- * config.host (powerpc*-*-linux*): Do not enable the float128 hardware
- and float128 power10 hardware support unless the basic float128 support
- is added.
- * configure.ac (powerpc*-*-linux*): Check whether the linker and
- assembler will be able to build the float128 libraries.
- * configure: Regenerate.
-
+ Branch work171-bugs, patch #310 was reverted
Branch work171-bugs, patch #304 was reverted
Branch work171-bugs, patch #303 was reverted
Branch work171-bugs, patch #302 was reverted
diff --git a/libgcc/config.host b/libgcc/config.host
index 261b08859a4d..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
+ fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
+ fi
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
- fi
- fi
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index bb196c8e7b84..a69d314374a3 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -1802,52 +1802,6 @@ $as_echo "$ac_res" >&6; }
eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
} # ac_fn_c_check_header_preproc
-
-# ac_fn_c_try_link LINENO
-# ---
-# Try to link conftest.$ac_ext, and return whether this succeeded.
-ac_fn_c_try_link ()
-{
- as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
- rm -f conftest.$ac_objext conftest$ac_exeext
- if { { ac_try="$ac_link"
-case "(($ac_try" in
- *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
- *) ac_try_echo=$ac_try;;
-esac
-eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
-$as_echo "$ac_try_echo"; } >&5
- (eval "$ac_link") 2>conftest.err
- ac_status=$?
- if test -s conftest.err; then
-grep -v '^ *+' conftest.err >conftest.er1
-cat conftest.er1 >&5
-mv -f conftest.er1 conftest.err
- fi
- $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
- test $ac_status = 0; } && {
-test -z "$ac_c_werror_flag" ||
-test ! -s conftest.err
- } && test -s conftest$ac_exeext && {
-test "$cross_compiling" = yes ||
-test -x conftest$ac_exeext
- }; then :
- ac_retval=0
-else
- $as_echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
- ac_retval=1
-fi
- # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information
- # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would
- # interfere with the next link command; also delete a directory that is
- # left behind by Apple's compiler. We do this before executing the actions.
- rm -rf conftest.dSYM conftest_ipa8_conftest.oo
- eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
- as_fn_set_status $ac_retval
-
-} # ac_fn_c_try_link
cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
@@
[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes
https://gcc.gnu.org/g:d317a05ebc91cb1da2a89d9ea9fe5f7dc0747b8a commit d317a05ebc91cb1da2a89d9ea9fe5f7dc0747b8a Author: Michael Meissner Date: Fri Jul 12 20:06:45 2024 -0400 Revert changes Diff: --- gcc/ChangeLog.bugs | 56 -- 1 file changed, 12 insertions(+), 44 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 61066c019ccd..f2f6f7986da8 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,49 +1,14 @@ - Branch work171-bugs, patch #304 + Branch work171-bugs, patch #310 -Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware support. - -2024-07-12 Michael Meissner - -gcc/testsuite/ - - PR target/115800 - PR target/113652 - * lib/target-supports.exp (check_ppc_float128_hw_available): Use - -mcpu=native rather than -mcpu=power9 to check if the machine has - float128 hardware support. - - Branch work171-bugs, patch #303 - -Disable adding -mvsx when checking for float128 support. - -2024-07-12 Michael Meissner - -gcc/testsuite/ - - PR target/115800 - PR target/113652 - * lib/target-supports.exp (check_ppc_float128_sw_available): Do not add - -mvsx when checking for float128 support. - (check_ppc_float128_hw_available): Likewise. - (check_effective_target___float128): Likewise. - - Branch work171-bugs, patch #302 - -Do not build IEEE 128-bit libgcc support if VSX is not available. +Add checks for building the IEEE 128-bit libgcc support if VSX is not available. In the past, we would build libgcc and eable the float128 libraries by adding -mvsx -mabi=altivec to build the support libraries. However, this causes -problems if the default cpu is a 7450. - -With this fix, in order to build the float128 support, the compiler must be -configured to default to at least power7 to enable using the VSX register set, -which is required for passing float128 values. - -If somebody wanted to enable float128 on big endian systems, they would need to -use a compiler that defaults to at least power7. +problems if the default cpu is a 7450. This patch checks to see if can link a +program using the options, and if we can't link the program, do not build the +float128 libraries. - -2024-07-11 Michael Meissner +2024-07-12 Michael Meissner libgcc/ @@ -52,11 +17,14 @@ libgcc/ * config.host (powerpc*-*-linux*): Do not enable the float128 hardware and float128 power10 hardware support unless the basic float128 support is added. - * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx. - * configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC - systems without VSX. + * configure.ac (powerpc*-*-linux*): Check whether the linker and + assembler will be able to build the float128 libraries. * configure: Regenerate. + Branch work171-bugs, patch #304 was reverted + Branch work171-bugs, patch #303 was reverted + Branch work171-bugs, patch #302 was reverted + Branch work171-bugs, patch #301 Do not build IEEE 128-bit libstdc++ support if VSX is not available.
[gcc(refs/users/meissner/heads/work171-bugs)] Add checks for building the IEEE 128-bit libgcc support if VSX is not available.
https://gcc.gnu.org/g:097f2463d8c78602186feb731fd8732dce9f3e7c
commit 097f2463d8c78602186feb731fd8732dce9f3e7c
Author: Michael Meissner
Date: Fri Jul 12 20:04:37 2024 -0400
Add checks for building the IEEE 128-bit libgcc support if VSX is not
available.
In the past, we would build libgcc and eable the float128 libraries by
adding
-mvsx -mabi=altivec to build the support libraries. However, this causes
problems if the default cpu is a 7450. This patch checks to see if can
link a
program using the options, and if we can't link the program, do not build
the
float128 libraries.
2024-07-12 Michael Meissner
libgcc/
PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not enable the float128
hardware
and float128 power10 hardware support unless the basic float128
support
is added.
* configure.ac (powerpc*-*-linux*): Check whether the linker and
assembler will be able to build the float128 libraries.
* configure: Regenerate.
Diff:
---
libgcc/config.host | 12 -
libgcc/configure| 71 ++---
libgcc/configure.ac | 17 +++--
3 files changed, 88 insertions(+), 12 deletions(-)
diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..261b08859a4d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
- fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
- fi
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
+ fi
+ fi
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..bb196c8e7b84 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -1802,6 +1802,52 @@ $as_echo "$ac_res" >&6; }
eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
} # ac_fn_c_check_header_preproc
+
+# ac_fn_c_try_link LINENO
+# ---
+# Try to link conftest.$ac_ext, and return whether this succeeded.
+ac_fn_c_try_link ()
+{
+ as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+ rm -f conftest.$ac_objext conftest$ac_exeext
+ if { { ac_try="$ac_link"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+ (eval "$ac_link") 2>conftest.err
+ ac_status=$?
+ if test -s conftest.err; then
+grep -v '^ *+' conftest.err >conftest.er1
+cat conftest.er1 >&5
+mv -f conftest.er1 conftest.err
+ fi
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; } && {
+test -z "$ac_c_werror_flag" ||
+test ! -s conftest.err
+ } && test -s conftest$ac_exeext && {
+test "$cross_compiling" = yes ||
+test -x conftest$ac_exeext
+ }; then :
+ ac_retval=0
+else
+ $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_retval=1
+fi
+ # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information
+ # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would
+ # interfere with the next link command; also delete a directory that is
+ # left behind by Apple's compiler. We do this before executing the actions.
+ rm -rf conftest.dSYM conftest_ipa8_conftest.oo
+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
+ as_fn_set_status $ac_retval
+
+} # ac_fn_c_try_link
cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
@@ -5184,6 +5230,12 @@ case ${host} in
# check if we have VSX (ISA 2.06) support to build the software libraries, and
# whether the assembler can handle xsaddqp for hardware support. Also check if
# a new glibc is being used so that __builtin_cpu_supports can be used.
+#
+# We use AC_LINK_IFELSE to verify that the assembler will not abort if given
+# the -mvsx -mabi=altivec options to compile the float128 support with VSX.
+# Otherwise if the default CPU is something like the 7450, the assembler will
+# complain when we build the float128 support.
+
powerpc*-*-linux*)
[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes
https://gcc.gnu.org/g:79427fed78d2531db6adc592f63d47ceaf0d5b49
commit 79427fed78d2531db6adc592f63d47ceaf0d5b49
Author: Michael Meissner
Date: Fri Jul 12 19:27:38 2024 -0400
Revert changes
Diff:
---
gcc/testsuite/lib/target-supports.exp | 8
libgcc/config.host| 12 ++--
libgcc/config/rs6000/t-float128 | 2 +-
libgcc/configure | 17 ++---
libgcc/configure.ac | 17 ++---
5 files changed, 23 insertions(+), 33 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ba64a1dbae87..b7df6150bcbd 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2979,7 +2979,7 @@ proc check_ppc_float128_sw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128"
+ set options "-mfloat128 -mvsx"
check_runtime_nocache ppc_float128_sw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3005,7 +3005,7 @@ proc check_ppc_float128_hw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128 -mcpu=native"
+ set options "-mfloat128 -mvsx -mfloat128-hardware -mcpu=power9"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3947,7 +3947,7 @@ proc check_effective_target___float128 { } {
proc add_options_for___float128 { flags } {
if { [istarget powerpc*-*-linux*] } {
- return "$flags -mfloat128"
+ return "$flags -mfloat128 -mvsx"
}
return "$flags"
}
@@ -7234,7 +7234,7 @@ proc check_effective_target_powerpc_float128_sw_ok { } {
__float128 z = x + y;
return (z == 3.0q);
}
- } "-mfloat128"]
+ } "-mfloat128 -mvsx"]
} else {
return 0
}
diff --git a/libgcc/config.host b/libgcc/config.host
index 261b08859a4d..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
+ fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
+ fi
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
- fi
- fi
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index 2d93080f1174..b09b5664af0e 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,7 @@ fp128_includes= $(srcdir)/soft-fp/double.h \
$(srcdir)/soft-fp/soft-fp.h
# Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mfloat128 \
+FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
-mno-float128-hardware -mno-gnu-attribute \
-I$(srcdir)/soft-fp \
-I$(srcdir)/config/rs6000 \
diff --git a/libgcc/configure b/libgcc/configure
index 39193456929a..a69d314374a3 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,18 +5180,13 @@ esac
esac
case ${host} in
-# Check if we can enable float128 support. Some systems (big endian) do not
-# enable float128 by default, but they can enable it if -mfloat128 is used.
-# However, the compiler must be compiled using at least --with-cpu=power7 to
-# enable VSX support. If we build a default big endian system without using
-# --with-cpu=power7, do not build the float128 libraries. VSX support is
-# needed because float128 values are passed in VSX registers.
-#
-# Also check if a new glibc is being used so that __builtin_cpu_supports can be
-# used.
+# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
+# check if we have VSX (ISA 2.06) support to build the software libraries, and
+# whether the assembler can handle xsaddqp for hardware support. Also check if
+# a new glibc is being used so that __builtin_cpu_supports can be used.
powerpc*-*-linux*)
saved_CFLAGS="$CFLAGS"
- CFLAGS="$CFLAGS -mfloat128"
+ CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
{ $as_echo
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:5414c9a058837198fa9da1da672e28dd84da1f1d commit 5414c9a058837198fa9da1da672e28dd84da1f1d Author: Michael Meissner Date: Fri Jul 12 14:13:30 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 14 ++ 1 file changed, 14 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 7ae08f41109b..61066c019ccd 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,17 @@ + Branch work171-bugs, patch #304 + +Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware support. + +2024-07-12 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + * lib/target-supports.exp (check_ppc_float128_hw_available): Use + -mcpu=native rather than -mcpu=power9 to check if the machine has + float128 hardware support. + Branch work171-bugs, patch #303 Disable adding -mvsx when checking for float128 support.
[gcc(refs/users/meissner/heads/work171-bugs)] Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware support.
https://gcc.gnu.org/g:89c9983b9157b8eb443a16561ad9a55d2cb10c66
commit 89c9983b9157b8eb443a16561ad9a55d2cb10c66
Author: Michael Meissner
Date: Fri Jul 12 14:12:28 2024 -0400
Use -mcpu=native instead of -mcpu=power9 when checking for float128
hardware support.
2024-07-12 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* lib/target-supports.exp (check_ppc_float128_hw_available): Use
-mcpu=native rather than -mcpu=power9 to check if the machine has
float128 hardware support.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 86c0913378ed..ba64a1dbae87 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3005,7 +3005,7 @@ proc check_ppc_float128_hw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128 -mcpu=power9"
+ set options "-mfloat128 -mcpu=native"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:a2af9e19c83edeca6fa8a6502fea697715678e95 commit a2af9e19c83edeca6fa8a6502fea697715678e95 Author: Michael Meissner Date: Fri Jul 12 12:01:12 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index a4a6b8aa0f70..7ae08f41109b 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,4 +1,19 @@ - Branch work171-bugs, patch #301 + Branch work171-bugs, patch #303 + +Disable adding -mvsx when checking for float128 support. + +2024-07-12 Michael Meissner + +gcc/testsuite/ + + PR target/115800 + PR target/113652 + * lib/target-supports.exp (check_ppc_float128_sw_available): Do not add + -mvsx when checking for float128 support. + (check_ppc_float128_hw_available): Likewise. + (check_effective_target___float128): Likewise. + + Branch work171-bugs, patch #302 Do not build IEEE 128-bit libgcc support if VSX is not available.
[gcc(refs/users/meissner/heads/work171-bugs)] Disable adding -mvsx when checking for float128 support.
https://gcc.gnu.org/g:0a9e57995990885028fc6af8a53513794890
commit 0a9e57995990885028fc6af8a53513794890
Author: Michael Meissner
Date: Fri Jul 12 12:00:20 2024 -0400
Disable adding -mvsx when checking for float128 support.
2024-07-12 Michael Meissner
gcc/testsuite/
PR target/115800
PR target/113652
* lib/target-supports.exp (check_ppc_float128_sw_available): Do not
add
-mvsx when checking for float128 support.
(check_ppc_float128_hw_available): Likewise.
(check_effective_target___float128): Likewise.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index b7df6150bcbd..86c0913378ed 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2979,7 +2979,7 @@ proc check_ppc_float128_sw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128 -mvsx"
+ set options "-mfloat128"
check_runtime_nocache ppc_float128_sw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3005,7 +3005,7 @@ proc check_ppc_float128_hw_available { } {
|| [istarget *-*-darwin*]} {
expr 0
} else {
- set options "-mfloat128 -mvsx -mfloat128-hardware -mcpu=power9"
+ set options "-mfloat128 -mcpu=power9"
check_runtime_nocache ppc_float128_hw_available {
volatile __float128 x = 1.0q;
volatile __float128 y = 2.0q;
@@ -3947,7 +3947,7 @@ proc check_effective_target___float128 { } {
proc add_options_for___float128 { flags } {
if { [istarget powerpc*-*-linux*] } {
- return "$flags -mfloat128 -mvsx"
+ return "$flags -mfloat128"
}
return "$flags"
}
@@ -7234,7 +7234,7 @@ proc check_effective_target_powerpc_float128_sw_ok { } {
__float128 z = x + y;
return (z == 3.0q);
}
- } "-mfloat128 -mvsx"]
+ } "-mfloat128"]
} else {
return 0
}
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:f4f8f4202017566975f1e2001875876f5cab4cbe commit f4f8f4202017566975f1e2001875876f5cab4cbe Author: Michael Meissner Date: Thu Jul 11 13:01:57 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 738e612fc41a..a4a6b8aa0f70 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -23,6 +23,7 @@ libgcc/ * config.host (powerpc*-*-linux*): Do not enable the float128 hardware and float128 power10 hardware support unless the basic float128 support is added. + * config/rs6000/t-float128 (FP128_CFLAGS_SW): Do not add -mvsx. * configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC systems without VSX. * configure: Regenerate.
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:caad5de45cf2142ddef06b3fd973dee64cba3121 commit caad5de45cf2142ddef06b3fd973dee64cba3121 Author: Michael Meissner Date: Thu Jul 11 12:56:05 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 33 +++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 1b4d99c0e5fb..738e612fc41a 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,8 +1,37 @@ Branch work171-bugs, patch #301 +Do not build IEEE 128-bit libgcc support if VSX is not available. + +In the past, we would build libgcc and eable the float128 libraries by adding +-mvsx -mabi=altivec to build the support libraries. However, this causes +problems if the default cpu is a 7450. + +With this fix, in order to build the float128 support, the compiler must be +configured to default to at least power7 to enable using the VSX register set, +which is required for passing float128 values. + +If somebody wanted to enable float128 on big endian systems, they would need to +use a compiler that defaults to at least power7. + + +2024-07-11 Michael Meissner + +libgcc/ + + PR target/115800 + PR target/113652 + * config.host (powerpc*-*-linux*): Do not enable the float128 hardware + and float128 power10 hardware support unless the basic float128 support + is added. + * configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC + systems without VSX. + * configure: Regenerate. + + Branch work171-bugs, patch #301 + Do not build IEEE 128-bit libstdc++ support if VSX is not available. -2024-07-03 Michael Meissner +2024-07-10 Michael Meissner libstdc++-v3/ @@ -16,7 +45,7 @@ libstdc++-v3/ Do not build IEEE 128-bit libgfortran support if VSX is not available. -2024-07-03 Michael Meissner +2024-07-10 Michael Meissner libgfortran/
[gcc(refs/users/meissner/heads/work171-bugs)] Do not build IEEE 128-bit libgcc support if VSX is not available.
https://gcc.gnu.org/g:aef0a6f0f0df4c1d91e133145540e0f7e7ff171c
commit aef0a6f0f0df4c1d91e133145540e0f7e7ff171c
Author: Michael Meissner
Date: Thu Jul 11 12:54:32 2024 -0400
Do not build IEEE 128-bit libgcc support if VSX is not available.
In the past, we would build libgcc and eable the float128 libraries by
adding
-mvsx -mabi=altivec to build the support libraries. However, this causes
problems if the default cpu is a 7450.
With this fix, in order to build the float128 support, the compiler must be
configured to default to at least power7 to enable using the VSX register
set,
which is required for passing float128 values.
If somebody wanted to enable float128 on big endian systems, they would
need to
use a compiler that defaults to at least power7.
2024-07-11 Michael Meissner
libgcc/
PR target/115800
PR target/113652
* config.host (powerpc*-*-linux*): Do not enable the float128
hardware
and float128 power10 hardware support unless the basic float128
support
is added.
* configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on
PowerPC
systems without VSX.
* configure: Regenerate.
Diff:
---
libgcc/config.host | 12 ++--
libgcc/config/rs6000/t-float128 | 2 +-
libgcc/configure| 17 +++--
libgcc/configure.ac | 17 +++--
4 files changed, 29 insertions(+), 19 deletions(-)
diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..261b08859a4d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1292,14 +1292,14 @@ powerpc*-*-linux*)
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
- fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
- fi
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
+ fi
+ fi
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/config/rs6000/t-float128 b/libgcc/config/rs6000/t-float128
index b09b5664af0e..2d93080f1174 100644
--- a/libgcc/config/rs6000/t-float128
+++ b/libgcc/config/rs6000/t-float128
@@ -74,7 +74,7 @@ fp128_includes= $(srcdir)/soft-fp/double.h \
$(srcdir)/soft-fp/soft-fp.h
# Build the emulator without ISA 3.0 hardware support.
-FP128_CFLAGS_SW = -Wno-type-limits -mvsx -mfloat128 \
+FP128_CFLAGS_SW = -Wno-type-limits -mfloat128 \
-mno-float128-hardware -mno-gnu-attribute \
-I$(srcdir)/soft-fp \
-I$(srcdir)/config/rs6000 \
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..39193456929a 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,13 +5180,18 @@ esac
esac
case ${host} in
-# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
-# check if we have VSX (ISA 2.06) support to build the software libraries, and
-# whether the assembler can handle xsaddqp for hardware support. Also check if
-# a new glibc is being used so that __builtin_cpu_supports can be used.
+# Check if we can enable float128 support. Some systems (big endian) do not
+# enable float128 by default, but they can enable it if -mfloat128 is used.
+# However, the compiler must be compiled using at least --with-cpu=power7 to
+# enable VSX support. If we build a default big endian system without using
+# --with-cpu=power7, do not build the float128 libraries. VSX support is
+# needed because float128 values are passed in VSX registers.
+#
+# Also check if a new glibc is being used so that __builtin_cpu_supports can be
+# used.
powerpc*-*-linux*)
saved_CFLAGS="$CFLAGS"
- CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
+ CFLAGS="$CFLAGS -mfloat128"
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for PowerPC ISA 2.06 to
build __float128 libraries" >&5
$as_echo_n "checking for PowerPC ISA 2.06 to build __float128 libraries... "
>&6; }
if ${libgcc_cv_powerpc_float128+:} false; then :
@@ -5194,7 +5199,7 @@ if ${libgcc_cv_powerpc_float128+:} false; then :
else
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
/* end confdefs.h. */
-vector double dadd (vector double a, vector double b) { return a + b; }
+__float128 f128_add (__float128 a, __float128 b) { return a+b; }
_ACEOF
if
[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:24ecb864d6c40f84d20420c105f6b36e534285f1 commit 24ecb864d6c40f84d20420c105f6b36e534285f1 Author: Michael Meissner Date: Wed Jul 3 23:47:19 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 38 +- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index d2c5d2ab118..1b4d99c0e5f 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,6 +1,42 @@ + Branch work171-bugs, patch #301 + +Do not build IEEE 128-bit libstdc++ support if VSX is not available. + +2024-07-03 Michael Meissner + +libstdc++-v3/ + + * configure.ac (powerpc*-*-linux*): Don't enable IEEE 128-bit on PowerPC + systems without VSX. + * configure: Regenerate. + * numeric_traits.h: Don't enable IEEE 128-bit on PowerPC systems without + VSX. + + Branch work171-bugs, patch #300 + +Do not build IEEE 128-bit libgfortran support if VSX is not available. + +2024-07-03 Michael Meissner + +libgfortran/ + + * configure.ac (powerpc64le*-linux*): Check to see that the compiler + uses VSX before enabling IEEE 128-bit support. + * configure: Regenerate. + * kinds-override.h (GFC_REAL_17): Add check for __VSX__. + * libgfortran.h (POWER_IEEE128): Likewise. + Branch work171-bugs, baseline +Add ChangeLog.bugs and update REVISION. + +2024-06-28 Michael Meissner + +gcc/ + + * ChangeLog.bugs: New file for branch. + * REVISION: Update. + 2024-06-28 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work171-bugs)] Do not build IEEE 128-bit libgfortran support if VSX is not available.
https://gcc.gnu.org/g:e405c7583045f798f26b80432bdf418514efcbaa
commit e405c7583045f798f26b80432bdf418514efcbaa
Author: Michael Meissner
Date: Wed Jul 3 23:42:52 2024 -0400
Do not build IEEE 128-bit libgfortran support if VSX is not available.
2024-07-03 Michael Meissner
libgfortran/
* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
* kinds-override.h (GFC_REAL_17): Add check for __VSX__.
* libgfortran.h (POWER_IEEE128): Likewise.
Diff:
---
libgfortran/configure| 7 +--
libgfortran/configure.ac | 3 +++
libgfortran/kinds-override.h | 2 +-
libgfortran/libgfortran.h| 2 +-
4 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/libgfortran/configure b/libgfortran/configure
index 11a1bc5f070..2708e5c7eca 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -5981,6 +5981,9 @@ if test "x$GCC" = "xyes"; then
#if __SIZEOF_LONG_DOUBLE__ != 16
#error long double is double
#endif
+ #if !defined(__VSX__)
+ #error VSX is not available
+ #endif
int
main ()
{
@@ -12847,7 +12850,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12850 "configure"
+#line 12853 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -12953,7 +12956,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12956 "configure"
+#line 12959 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index cca1ea0ea97..cfaeb9717ab 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -148,6 +148,9 @@ if test "x$GCC" = "xyes"; then
AC_PREPROC_IFELSE(
[AC_LANG_PROGRAM([[#if __SIZEOF_LONG_DOUBLE__ != 16
#error long double is double
+ #endif
+ #if !defined(__VSX__)
+ #error VSX is not available
#endif]],
[[(void) 0;]])],
[AM_FCFLAGS="$AM_FCFLAGS -mabi=ibmlongdouble -mno-gnu-attribute";
diff --git a/libgfortran/kinds-override.h b/libgfortran/kinds-override.h
index f6b4956c5ca..51f440e5323 100644
--- a/libgfortran/kinds-override.h
+++ b/libgfortran/kinds-override.h
@@ -30,7 +30,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If
not, see
#endif
/* Keep these conditions on one line so grep can filter it out. */
-#if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ &&
__SIZEOF_LONG_DOUBLE__ == 16
+#if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ &&
__SIZEOF_LONG_DOUBLE__ == 16 && defined(__VSX__)
typedef _Float128 GFC_REAL_17;
typedef _Complex _Float128 GFC_COMPLEX_17;
#define HAVE_GFC_REAL_17
diff --git a/libgfortran/libgfortran.h b/libgfortran/libgfortran.h
index 5c59ec26e16..23660335243 100644
--- a/libgfortran/libgfortran.h
+++ b/libgfortran/libgfortran.h
@@ -104,7 +104,7 @@ typedef off_t gfc_offset;
#endif
#if defined(__powerpc64__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ \
-&& defined __GLIBC_PREREQ
+&& defined __GLIBC_PREREQ && defined(__VSX__)
#if __GLIBC_PREREQ (2, 32)
#define POWER_IEEE128 1
#endif
[gcc(refs/users/meissner/heads/work171-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:94e5c5ee7f41ea763c4c60cb6e82972a346ad699 commit 94e5c5ee7f41ea763c4c60cb6e82972a346ad699 Author: Michael Meissner Date: Wed Jul 3 19:18:06 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 71 +++ 1 file changed, 51 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 058a06886ea..692ad14da95 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -15,30 +15,61 @@ Remove SPR alternatives for move insns. Branch work171-tar, patch #200 -Restrict SPR to appropriate integer modes. +Add support for the TAR register. -In preparation for the patches to add support for the TAR register, I restricted -the modes that special purpose registers (SPRs) could hold to be appropriate -sized scalar integers. I have discovered occasionally when GCC has run out of -registers, it will use the SPRs to hold values instead of spilling them to the -stack. The LR/CTR registers can hold 8/16/32-bit values and on 64-bit systems, -they can also hold 64-bit values. The VRSAVE and VSCR registers can only hold -32-bit values. - -2024-06-20 Michael Meissner +2024-07-03 Michael Meissner gcc/ - * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict - SPR registers to only hold scalar integer modes of an appropriate size. - * config/rs6000/rs6000.md (movcc_): Remove alternatives that move - values to/from the SPRs. - (movsf_hardfloat): Likewise. - (movsd_hardfloat): Likewise. - (mov_softfloat): Likewise. - (mov_softfloat32): Likewise. - (mov_hardfloat64): Likewise. - (*mov_softfloat64): Likewise. + * config/rs6000/constraints.md (h constraint): Add TAR register to the + documentation. + (wt constraint): New constraint. + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add -mtar. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register support. + (alt_reg_names): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Restrict SPR registers to only + hold scalar integer modes of an appropriate size. Add TAR register + support. + (rs6000_debug_reg_global): Print the register class that wt maps too. + (rs6000_init_hard_regno_mode_ok): Add TAR register support. + (rs6000_conditional_register_usage): Add TAR register support. + (print_operand): Likewise. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Add support for -mtar. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register + support. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Likewise. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (enum r6000_reg_class_enum): Add support for the wt constraint. + * config/rs6000/rs6000.md (TAR_REGNO): New constant. + (call_indirect_nonlocal_sysv): Likewise. + (call_value_indirect_nonlocal_sysv): Likewise. + (call_indirect_aix): Likewise. + (call_value_indirect_aix): Likewise. + (call_indirect_elfv2): Likewise. + (call_indirect_pcrel): Likewise. + (call_value_indirect_elfv2): Likewise. + (call_value_indirect_pcrel): Likewise. + (*sibcall_indirect_nonlocal_sysv): Likewise. + (sibcall_value_indirect_nonlocal_sysv): Likewise. + (indirect_jump): Likewise. + (@indirect_jump_nospec): Likewise. + (@tablejump_insn_normal): Likewise. + (@tablejump_insn_nospec): Likewise. + * config/rs6000/rs6000.opt (-mtar): New option. + +gcc/testsuite/ + + * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register. + * gcc.target/powerpc/pr51513.c: Likewise. + * gcc.target/powerpc/safe-indirect-jump-2.c: Likewise. + * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise. + * gcc.target/powerpc/tar-register.c: New test. Branch work171-tar, baseline
[gcc(refs/users/meissner/heads/work171-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:241891477aab13135aa49e1441abbe6eee44afbb commit 241891477aab13135aa49e1441abbe6eee44afbb Author: Michael Meissner Date: Wed Jul 3 19:11:18 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 15 +++ 1 file changed, 15 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 797d13695e8..058a06886ea 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,18 @@ + Branch work171-tar, patch #201 + +Remove SPR alternatives for move insns. + +2024-07-03 Michael Meissner + + * config/rs6000/rs6000.md (mov_internal): Remove alternatives for + moving values to/from SPR registers. + (movcc_): Likewise. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_softfloat): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + Branch work171-tar, patch #200 Restrict SPR to appropriate integer modes.
[gcc(refs/users/meissner/heads/work171-tar)] Remove SPR alternatives for move insns.
https://gcc.gnu.org/g:dc64c11d40e8a57a665d61eeb5ab50ad5bee1513 commit dc64c11d40e8a57a665d61eeb5ab50ad5bee1513 Author: Michael Meissner Date: Wed Jul 3 19:10:09 2024 -0400 Remove SPR alternatives for move insns. 2024-07-03 Michael Meissner * config/rs6000/rs6000.md (mov_internal): Remove alternatives for moving values to/from SPR registers. (movcc_): Likewise. (movsf_hardfloat): Likewise. (movsd_hardfloat): Likewise. (mov_softfloat): Likewise. (mov_hardfloat64): Likewise. (mov_softfloat64): Likewise. Diff: --- gcc/config/rs6000/rs6000.md | 114 +--- 1 file changed, 44 insertions(+), 70 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 90c3785e7af..8d7f3445c46 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8064,16 +8064,16 @@ ;; MR LHZ/LBZLXSI*ZXSTH/STBSTXSI*XLI ;; XXLOR load 0 load -1VSPLTI*# MFVSRWZ -;; MTVSRWZ MF%1 MT%1 NOP +;; MTVSRWZ (define_insn "*mov_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" "=r,r, wa,m, ?Z,r, wa,wa,wa,v, ?v,r, -wa,r, *c*l, *h") +wa") (match_operand:QHI 1 "input_operand" "r, m, ?Z,r, wa,i, wa,O, wM,wB,wS,wa, -r, *h,r, 0"))] +r"))] "gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode)" "@ @@ -8089,22 +8089,19 @@ vspltis %0,%1 # mfvsrwz %0,%x1 - mtvsrwz %x0,%1 - mf%1 %0 - mt%0 %1 - nop" + mtvsrwz %x0,%1" [(set_attr "type" "*, load, fpload,store, fpstore, *, vecsimple, vecperm, vecperm, vecperm, vecperm, mfvsr, -mtvsr, mfjmpr,mtjmpr,*") +mtvsr") (set_attr "length" "*, *, *, *, *, *, *, *, *, *, 8, *, -*, *, *, *") +*") (set_attr "isa" "*, *, p9v, *, p9v, *, p9v, p9v, p9v, p9v, p9v, p9v, -p9v, *, *, *")]) +p9v")]) ;; Here is how to move condition codes around. When we store CC data in @@ -8120,9 +8117,9 @@ (define_insn "*movcc_" [(set (match_operand:CC_any 0 "nonimmediate_operand" - "=y,x,?y,y,r,r,r,r, r,*c*l,r,m") + "=y,x,?y,y,r,r,r,r,r,m") (match_operand:CC_any 1 "general_operand" - " y,r, r,O,x,y,r,I,*h, r,m,r"))] + " y,r, r,O,x,y,r,I,m,r"))] "register_operand (operands[0], mode) || register_operand (operands[1], mode)" "@ @@ -8134,8 +8131,6 @@ mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf000 mr %0,%1 li %0,%1 - mf%1 %0 - mt%0 %1 lwz%U1%X1 %0,%1 stw%U0%X0 %1,%0" [(set_attr_alternative "type" @@ -8149,11 +8144,9 @@ (const_string "mfcrf") (const_string "mfcr")) (const_string "integer") (const_string "integer") - (const_string "mfjmpr") - (const_string "mtjmpr") (const_string "load") (const_string "store")]) - (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")]) + (set_attr "length" "*,*,12,*,*,8,*,*,*,*")]) ;; For floating-point, we normally deal with the floating-point registers ;; unless -msoft-float is used. The sole exception is that parameter passing @@ -8204,17 +8197,17 @@ ;; ;; LWZ LFSLXSSP LXSSPX STFS STXSSP ;; STXSSPX STWXXLXOR LI FMRXSCPSGNDP -;; MR MT MF NOPXXSPLTIDP +;; MR XXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa,m, wY, Z, m, wa, !r,f, wa, - !r,*c*l, !r, *h,wa") + !r,wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa,r, j, j, f, wa, - r, r, *h, 0, eP"))] + r, eP"))] "(register_operand (operands[0], SFmode) || register_operand
[gcc(refs/users/meissner/heads/work171-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:ec76bc555a845c118fb866ab0cedb6a43b5bd064 commit ec76bc555a845c118fb866ab0cedb6a43b5bd064 Author: Michael Meissner Date: Wed Jul 3 16:04:01 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 37 - 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index dbdff04e2fa..797d13695e8 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,6 +1,41 @@ + Branch work171-tar, patch #200 + +Restrict SPR to appropriate integer modes. + +In preparation for the patches to add support for the TAR register, I restricted +the modes that special purpose registers (SPRs) could hold to be appropriate +sized scalar integers. I have discovered occasionally when GCC has run out of +registers, it will use the SPRs to hold values instead of spilling them to the +stack. The LR/CTR registers can hold 8/16/32-bit values and on 64-bit systems, +they can also hold 64-bit values. The VRSAVE and VSCR registers can only hold +32-bit values. + +2024-06-20 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict + SPR registers to only hold scalar integer modes of an appropriate size. + * config/rs6000/rs6000.md (movcc_): Remove alternatives that move + values to/from the SPRs. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_softfloat): Likewise. + (mov_softfloat32): Likewise. + (mov_hardfloat64): Likewise. + (*mov_softfloat64): Likewise. + Branch work171-tar, baseline +Add ChangeLog.tar and update REVISION. + +2024-06-17 Michael Meissner + +gcc/ + + * ChangeLog.tar: New file for branch. + * REVISION: Update. + 2024-06-28 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work171-tar)] Add support for the TAR register.
https://gcc.gnu.org/g:20ea7e93905d1b23e0507fdb7e4aad8bd2aa9419
commit 20ea7e93905d1b23e0507fdb7e4aad8bd2aa9419
Author: Michael Meissner
Date: Wed Jul 3 16:02:29 2024 -0400
Add support for the TAR register.
2024-07-03 Michael Meissner
gcc/
* config/rs6000/constraints.md (h constraint): Add TAR register to
the
documentation.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register
support.
(alt_reg_names): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Restrict SPR registers to only
hold scalar integer modes of an appropriate size. Add TAR register
support.
(rs6000_debug_reg_global): Print the register class that wt maps
too.
(rs6000_init_hard_regno_mode_ok): Add TAR register support.
(rs6000_conditional_register_usage): Add TAR register support.
(print_operand): Likewise.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Add support for -mtar.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register
support.
(FIXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(enum reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(enum r6000_reg_class_enum): Add support for the wt constraint.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(call_indirect_nonlocal_sysv): Likewise.
(call_value_indirect_nonlocal_sysv): Likewise.
(call_indirect_aix): Likewise.
(call_value_indirect_aix): Likewise.
(call_indirect_elfv2): Likewise.
(call_indirect_pcrel): Likewise.
(call_value_indirect_elfv2): Likewise.
(call_value_indirect_pcrel): Likewise.
(*sibcall_indirect_nonlocal_sysv): Likewise.
(sibcall_value_indirect_nonlocal_sysv): Likewise.
(indirect_jump): Likewise.
(@indirect_jump_nospec): Likewise.
(@tablejump_insn_normal): Likewise.
(@tablejump_insn_nospec): Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
gcc/testsuite/
* gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR
register.
* gcc.target/powerpc/pr51513.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-2.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
* gcc.target/powerpc/tar-register.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 5 +-
gcc/config/rs6000/rs6000-cpus.def | 4 +-
gcc/config/rs6000/rs6000.cc| 58 +++---
gcc/config/rs6000/rs6000.h | 31 +++-
gcc/config/rs6000/rs6000.md| 33 ++--
gcc/config/rs6000/rs6000.opt | 4 ++
gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c| 4 +-
gcc/testsuite/gcc.target/powerpc/pr51513.c | 4 +-
.../gcc.target/powerpc/safe-indirect-jump-2.c | 2 +-
.../gcc.target/powerpc/safe-indirect-jump-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/tar-register.c| 34 +
11 files changed, 138 insertions(+), 43 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042..14f0465d7ae 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91f..4c0b5ca8cb8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -65,7 +65,8 @@
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_MINMAX \
[gcc(refs/users/meissner/heads/work171-vpair)] Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:d25568d1da54417f4aebea618d4ef27dab8325a6 commit d25568d1da54417f4aebea618d4ef27dab8325a6 Merge: d366bcb543d e073a26637a Author: Michael Meissner Date: Wed Jul 3 13:44:06 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work171-vpair Diff:
[gcc(refs/users/meissner/heads/work171-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:d366bcb543d604c108a6f18c135863c35cb7db7c commit d366bcb543d604c108a6f18c135863c35cb7db7c Author: Michael Meissner Date: Fri Jun 28 15:05:36 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..eb6dd427796 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work171-vpair, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..6cef7066a80 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-vpair branch
[gcc/meissner/heads/work171-vpair] (5 commits) Merge commit 'refs/users/meissner/heads/work171-vpair' of g
The branch 'meissner/heads/work171-vpair' was updated to point to: d25568d1da5... Merge commit 'refs/users/meissner/heads/work171-vpair' of g It previously pointed to: e073a26637a... Merge commit 'refs/users/meissner/heads/work171-vpair' of g Diff: Summary of changes (added commits): --- d25568d... Merge commit 'refs/users/meissner/heads/work171-vpair' of g d366bcb... Add ChangeLog.vpair and update REVISION. a80d1d3... Update ChangeLog.* (*) 58db14c... Add -mcpu=power11 tests. (*) 6b86afa... Revert changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-test)] Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:3e791e9d1f1399e4dadb8b32c9d41bd6f2809a76 commit 3e791e9d1f1399e4dadb8b32c9d41bd6f2809a76 Merge: 9b8cccfe5e7 16f55933794 Author: Michael Meissner Date: Wed Jul 3 13:42:50 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work171-test Diff:
[gcc(refs/users/meissner/heads/work171-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:9b8cccfe5e7a9d49509708f67738e204e9c4491a commit 9b8cccfe5e7a9d49509708f67738e204e9c4491a Author: Michael Meissner Date: Fri Jun 28 15:08:09 2024 -0400 Add ChangeLog.test and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..c2893a28120 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work171-test, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..78d94f8c4ae 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-test branch
[gcc/meissner/heads/work171-test] (5 commits) Merge commit 'refs/users/meissner/heads/work171-test' of gi
The branch 'meissner/heads/work171-test' was updated to point to: 3e791e9d1f1... Merge commit 'refs/users/meissner/heads/work171-test' of gi It previously pointed to: 16f55933794... Merge commit 'refs/users/meissner/heads/work171-test' of gi Diff: Summary of changes (added commits): --- 3e791e9... Merge commit 'refs/users/meissner/heads/work171-test' of gi 9b8cccf... Add ChangeLog.test and update REVISION. a80d1d3... Update ChangeLog.* (*) 58db14c... Add -mcpu=power11 tests. (*) 6b86afa... Revert changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-tar)] Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:22640e2b601dcb70040fa7d8118e82bad3166de4 commit 22640e2b601dcb70040fa7d8118e82bad3166de4 Merge: 220389c2c09 e2490ea0551 Author: Michael Meissner Date: Wed Jul 3 13:41:06 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work171-tar Diff:
[gcc(refs/users/meissner/heads/work171-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:220389c2c09c3fc3819db5fb825fb30355d9fc69 commit 220389c2c09c3fc3819db5fb825fb30355d9fc69 Author: Michael Meissner Date: Fri Jun 28 15:06:24 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..dbdff04e2fa --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work171-tar, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..da2e6621959 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-tar branch
[gcc/meissner/heads/work171-tar] (5 commits) Merge commit 'refs/users/meissner/heads/work171-tar' of git
The branch 'meissner/heads/work171-tar' was updated to point to: 22640e2b601... Merge commit 'refs/users/meissner/heads/work171-tar' of git It previously pointed to: e2490ea0551... Merge commit 'refs/users/meissner/heads/work171-tar' of git Diff: Summary of changes (added commits): --- 22640e2... Merge commit 'refs/users/meissner/heads/work171-tar' of git 220389c... Add ChangeLog.tar and update REVISION. a80d1d3... Update ChangeLog.* (*) 58db14c... Add -mcpu=power11 tests. (*) 6b86afa... Revert changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-tar' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-dmf)] Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:2d54858a7bb66c4acbb68dfe109bb761a98be60f commit 2d54858a7bb66c4acbb68dfe109bb761a98be60f Merge: d9c3752bb16 0afd530ede7 Author: Michael Meissner Date: Wed Jul 3 13:39:23 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work171-dmf Diff:
[gcc(refs/users/meissner/heads/work171-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:d9c3752bb16abcaa2ac4527d7df81f802b31234b commit d9c3752bb16abcaa2ac4527d7df81f802b31234b Author: Michael Meissner Date: Fri Jun 28 15:04:38 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..bf4edca66c7 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work171-dmf, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..e8fb95125d2 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-dmf branch
[gcc/meissner/heads/work171-dmf] (5 commits) Merge commit 'refs/users/meissner/heads/work171-dmf' of git
The branch 'meissner/heads/work171-dmf' was updated to point to: 2d54858a7bb... Merge commit 'refs/users/meissner/heads/work171-dmf' of git It previously pointed to: 0afd530ede7... Merge commit 'refs/users/meissner/heads/work171-dmf' of git Diff: Summary of changes (added commits): --- 2d54858... Merge commit 'refs/users/meissner/heads/work171-dmf' of git d9c3752... Add ChangeLog.dmf and update REVISION. a80d1d3... Update ChangeLog.* (*) 58db14c... Add -mcpu=power11 tests. (*) 6b86afa... Revert changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-bugs)] Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:cb841ff9503005daeae92ceba50a83b7ce709210 commit cb841ff9503005daeae92ceba50a83b7ce709210 Merge: df3392b59a5 e972f29adad Author: Michael Meissner Date: Wed Jul 3 13:34:59 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work171-bugs Diff:
[gcc(refs/users/meissner/heads/work171-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:df3392b59a5a9c1cc6ebf03ee910d6c011758c0a commit df3392b59a5a9c1cc6ebf03ee910d6c011758c0a Author: Michael Meissner Date: Fri Jun 28 15:07:19 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..d2c5d2ab118 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work171-bugs, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..7a2e248f4d4 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-bugs branch
[gcc/meissner/heads/work171-bugs] (5 commits) Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
The branch 'meissner/heads/work171-bugs' was updated to point to: cb841ff9503... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi It previously pointed to: e972f29adad... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi Diff: Summary of changes (added commits): --- cb841ff... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi df3392b... Add ChangeLog.bugs and update REVISION. a80d1d3... Update ChangeLog.* (*) 58db14c... Add -mcpu=power11 tests. (*) 6b86afa... Revert changes (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-bugs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171)] Update ChangeLog.*
https://gcc.gnu.org/g:a80d1d3d96c859779f55c5d9593edccc42e1dc96 commit a80d1d3d96c859779f55c5d9593edccc42e1dc96 Author: Michael Meissner Date: Wed Jul 3 13:31:17 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 781999c4e75..8ec458af54a 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -4,7 +4,7 @@ Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. -2024-06-17 Michael Meissner +2024-07-03 Michael Meissner gcc/ @@ -30,7 +30,7 @@ This patch allows GCC to be configured with the --with-cpu=future and This patch passes -mfuture to the assembler if the user uses -mcpu=future. -2024-06-17 Michael Meissner +2024-07-03 Michael Meissner gcc/ @@ -70,15 +70,13 @@ This patch adds some simple tests for -mcpu=power11 support. In order to run these tests, you need an assembler that supports the appropriate option for supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). -2024-06-17 Michael Meissner +2024-07-03 Michael Meissner gcc/testsuite/ * gcc.target/powerpc/power11-1.c: New test. * gcc.target/powerpc/power11-2.c: Likewise. * gcc.target/powerpc/power11-3.c: Likewise. - * lib/target-supports.exp (check_effective_target_power11_ok): Add new - effective target. Branch work171, patch #2 @@ -86,7 +84,7 @@ Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. -2024-06-17 Michael Meissner +2024-07-02 Michael Meissner gcc/ @@ -115,7 +113,7 @@ This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. -2024-06-17 Michael Meissner +2024-07-03 Michael Meissner gcc/
[gcc(refs/users/meissner/heads/work171)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:58db14cbdb5ad06a1571499bce99c64610b712bf
commit 58db14cbdb5ad06a1571499bce99c64610b712bf
Author: Michael Meissner
Date: Wed Jul 3 13:28:34 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support.
2024-07-03 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 12
gcc/testsuite/gcc.target/powerpc/power11-2.c | 22 ++
gcc/testsuite/gcc.target/powerpc/power11-3.c | 11 +++
3 files changed, 45 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..a1bd9538cba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..4521c2a37c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,22 @@
+/* Require VSX and Linux to eliminate systems where you can't do
+ __attribute__((__target__(...))). */
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..abf0c5866a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* Require VSX and Linux to eliminate systems where you can't do
+ __attribute__((__target_clones__(...))). */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
[gcc(refs/users/meissner/heads/work171)] Revert changes
https://gcc.gnu.org/g:6b86afaa700af66757f1d40b64e5f9e9e54e8d5c
commit 6b86afaa700af66757f1d40b64e5f9e9e54e8d5c
Author: Michael Meissner
Date: Wed Jul 3 13:27:36 2024 -0400
Revert changes
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 12
gcc/testsuite/gcc.target/powerpc/power11-2.c | 22 --
gcc/testsuite/gcc.target/powerpc/power11-3.c | 11 ---
3 files changed, 45 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
deleted file mode 100644
index a5aa32490df..000
--- a/gcc/testsuite/gcc.target/powerpc/power11-1.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* { dg-do assemble { target powerpc*-*-* } } */
-/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
-
-/* Basic check to see if the compiler supports -mcpu=power11. */
-
-#ifndef _ARCH_PWR11
-#error "-mcpu=power11 is not supported"
-#endif
-
-void foo (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
deleted file mode 100644
index 4521c2a37c7..000
--- a/gcc/testsuite/gcc.target/powerpc/power11-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Require VSX and Linux to eliminate systems where you can't do
- __attribute__((__target__(...))). */
-/* { dg-do compile { target { powerpc*-*-linux* } } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2" } */
-
-/* Check if we can set the power11 target via a target attribute. */
-
-__attribute__((__target__("cpu=power9")))
-void foo_p9 (void)
-{
-}
-
-__attribute__((__target__("cpu=power10")))
-void foo_p10 (void)
-{
-}
-
-__attribute__((__target__("cpu=power11")))
-void foo_p11 (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
deleted file mode 100644
index abf0c5866a9..000
--- a/gcc/testsuite/gcc.target/powerpc/power11-3.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* Require VSX and Linux to eliminate systems where you can't do
- __attribute__((__target_clones__(...))). */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Check if we can set the power11 target via a target_clones attribute. */
-
-__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
-void foo (void)
-{
-}
[gcc(refs/users/meissner/heads/work171-vpair)] Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:e073a26637aec326be6b8565fff1037497ddb86f commit e073a26637aec326be6b8565fff1037497ddb86f Merge: 3423779e10f 39334c0bdf6 Author: Michael Meissner Date: Wed Jul 3 00:15:19 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work171-vpair Diff:
[gcc(refs/users/meissner/heads/work171-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:3423779e10f870776ff94a4da5dcd4dc41d1003e commit 3423779e10f870776ff94a4da5dcd4dc41d1003e Author: Michael Meissner Date: Fri Jun 28 15:05:36 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..eb6dd427796 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work171-vpair, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..6cef7066a80 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-vpair branch
[gcc/meissner/heads/work171-vpair] (8 commits) Merge commit 'refs/users/meissner/heads/work171-vpair' of g
The branch 'meissner/heads/work171-vpair' was updated to point to: e073a26637a... Merge commit 'refs/users/meissner/heads/work171-vpair' of g It previously pointed to: 39334c0bdf6... Merge commit 'refs/users/meissner/heads/work171-vpair' of g Diff: Summary of changes (added commits): --- e073a26... Merge commit 'refs/users/meissner/heads/work171-vpair' of g 3423779... Add ChangeLog.vpair and update REVISION. ab44a03... Update ChangeLog.* (*) 16ed0e6... Add -mcpu=future tuning support. (*) 32dbcb6... Add -mcpu=future support. (*) 2f47c52... Add -mcpu=power11 tests. (*) 351f249... Add -mcpu=power11 tuning support. (*) b815028... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-test)] Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:16f55933794e469e9618ba32e9a471c011aa3af1 commit 16f55933794e469e9618ba32e9a471c011aa3af1 Merge: d527ea85663 7b7938f8984 Author: Michael Meissner Date: Wed Jul 3 00:13:35 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work171-test Diff:
[gcc(refs/users/meissner/heads/work171-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:d527ea85663af086065490fc44df79e78263f438 commit d527ea85663af086065490fc44df79e78263f438 Author: Michael Meissner Date: Fri Jun 28 15:08:09 2024 -0400 Add ChangeLog.test and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..c2893a28120 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work171-test, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..78d94f8c4ae 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-test branch
[gcc/meissner/heads/work171-test] (8 commits) Merge commit 'refs/users/meissner/heads/work171-test' of gi
The branch 'meissner/heads/work171-test' was updated to point to: 16f55933794... Merge commit 'refs/users/meissner/heads/work171-test' of gi It previously pointed to: 7b7938f8984... Merge commit 'refs/users/meissner/heads/work171-test' of gi Diff: Summary of changes (added commits): --- 16f5593... Merge commit 'refs/users/meissner/heads/work171-test' of gi d527ea8... Add ChangeLog.test and update REVISION. ab44a03... Update ChangeLog.* (*) 16ed0e6... Add -mcpu=future tuning support. (*) 32dbcb6... Add -mcpu=future support. (*) 2f47c52... Add -mcpu=power11 tests. (*) 351f249... Add -mcpu=power11 tuning support. (*) b815028... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-tar)] Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:e2490ea055127380e7604d9dbf91f86d43662fe2 commit e2490ea055127380e7604d9dbf91f86d43662fe2 Merge: a1634e9ffa4 52e709fbd0f Author: Michael Meissner Date: Wed Jul 3 00:12:32 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work171-tar Diff:
[gcc(refs/users/meissner/heads/work171-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:a1634e9ffa4c0d8887d33b0a789dac091619dc53 commit a1634e9ffa4c0d8887d33b0a789dac091619dc53 Author: Michael Meissner Date: Fri Jun 28 15:06:24 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..dbdff04e2fa --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work171-tar, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..da2e6621959 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-tar branch
[gcc/meissner/heads/work171-tar] (8 commits) Merge commit 'refs/users/meissner/heads/work171-tar' of git
The branch 'meissner/heads/work171-tar' was updated to point to: e2490ea0551... Merge commit 'refs/users/meissner/heads/work171-tar' of git It previously pointed to: 52e709fbd0f... Merge commit 'refs/users/meissner/heads/work171-tar' of git Diff: Summary of changes (added commits): --- e2490ea... Merge commit 'refs/users/meissner/heads/work171-tar' of git a1634e9... Add ChangeLog.tar and update REVISION. ab44a03... Update ChangeLog.* (*) 16ed0e6... Add -mcpu=future tuning support. (*) 32dbcb6... Add -mcpu=future support. (*) 2f47c52... Add -mcpu=power11 tests. (*) 351f249... Add -mcpu=power11 tuning support. (*) b815028... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-tar' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-dmf)] Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:0afd530ede7bd32fc538d3039b8073bddfa78fe0 commit 0afd530ede7bd32fc538d3039b8073bddfa78fe0 Merge: 07773b57e29 25538188182 Author: Michael Meissner Date: Wed Jul 3 00:11:29 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work171-dmf Diff:
[gcc(refs/users/meissner/heads/work171-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:07773b57e296292f412cc89691116db07b19e43a commit 07773b57e296292f412cc89691116db07b19e43a Author: Michael Meissner Date: Fri Jun 28 15:04:38 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..bf4edca66c7 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work171-dmf, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..e8fb95125d2 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-dmf branch
[gcc/meissner/heads/work171-dmf] (8 commits) Merge commit 'refs/users/meissner/heads/work171-dmf' of git
The branch 'meissner/heads/work171-dmf' was updated to point to: 0afd530ede7... Merge commit 'refs/users/meissner/heads/work171-dmf' of git It previously pointed to: 25538188182... Merge commit 'refs/users/meissner/heads/work171-dmf' of git Diff: Summary of changes (added commits): --- 0afd530... Merge commit 'refs/users/meissner/heads/work171-dmf' of git 07773b5... Add ChangeLog.dmf and update REVISION. ab44a03... Update ChangeLog.* (*) 16ed0e6... Add -mcpu=future tuning support. (*) 32dbcb6... Add -mcpu=future support. (*) 2f47c52... Add -mcpu=power11 tests. (*) 351f249... Add -mcpu=power11 tuning support. (*) b815028... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-bugs)] Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:e972f29adad180ce0cef9ba1d2e15947d3abdadb commit e972f29adad180ce0cef9ba1d2e15947d3abdadb Merge: 370311a7cc5 d33f66a9a6b Author: Michael Meissner Date: Wed Jul 3 00:09:57 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work171-bugs Diff:
[gcc(refs/users/meissner/heads/work171-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:370311a7cc5a47a25f0e65ecef9f345232b39141 commit 370311a7cc5a47a25f0e65ecef9f345232b39141 Author: Michael Meissner Date: Fri Jun 28 15:07:19 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..d2c5d2ab118 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work171-bugs, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..7a2e248f4d4 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-bugs branch
[gcc/meissner/heads/work171-bugs] (8 commits) Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
The branch 'meissner/heads/work171-bugs' was updated to point to: e972f29adad... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi It previously pointed to: d33f66a9a6b... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi Diff: Summary of changes (added commits): --- e972f29... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi 370311a... Add ChangeLog.bugs and update REVISION. ab44a03... Update ChangeLog.* (*) 16ed0e6... Add -mcpu=future tuning support. (*) 32dbcb6... Add -mcpu=future support. (*) 2f47c52... Add -mcpu=power11 tests. (*) 351f249... Add -mcpu=power11 tuning support. (*) b815028... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work171-bugs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171)] Update ChangeLog.*
https://gcc.gnu.org/g:ab44a03123195ee4af15f393a7f3d509d533c9c0 commit ab44a03123195ee4af15f393a7f3d509d533c9c0 Author: Michael Meissner Date: Wed Jul 3 00:08:45 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 151 + 1 file changed, 151 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index ff5bdb5ac0a..781999c4e75 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,154 @@ + Branch work171, patch #11 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work171, patch #10 + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work171, patch #3 + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-17 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work171, patch #2 + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work171, patch #1 + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + *
[gcc(refs/users/meissner/heads/work171)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:16ed0e6c8420e3a91dd66b9e59715e8c960c26ca commit 16ed0e6c8420e3a91dd66b9e59715e8c960c26ca Author: Michael Meissner Date: Wed Jul 3 00:05:01 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-07-03 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 90312643858..1ec1bef0726 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM POWER10 and POWER11 processors. +;; Scheduling description for the IBM POWER10 and POWER11 processors as well as +;; potential future processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update
[gcc(refs/users/meissner/heads/work171)] Add -mcpu=future support.
https://gcc.gnu.org/g:32dbcb628fc58051d7c4cf2322a3cb16a12e1f58
commit 32dbcb628fc58051d7c4cf2322a3cb16a12e1f58
Author: Michael Meissner
Date: Wed Jul 3 00:04:08 2024 -0400
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfuture to the assembler if the user uses -mcpu=future.
2024-07-03 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
15 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7c283f59e36..fe59f33370c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -534,7 +534,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5643,7 +5643,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work171)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:2f47c52f2a32757f9a453c74cd58ffc8dc91d6e8
commit 2f47c52f2a32757f9a453c74cd58ffc8dc91d6e8
Author: Michael Meissner
Date: Tue Jul 2 20:07:28 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support.
2024-07-02 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 12
gcc/testsuite/gcc.target/powerpc/power11-2.c | 22 ++
gcc/testsuite/gcc.target/powerpc/power11-3.c | 11 +++
3 files changed, 45 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..a5aa32490df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,12 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..4521c2a37c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,22 @@
+/* Require VSX and Linux to eliminate systems where you can't do
+ __attribute__((__target__(...))). */
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..abf0c5866a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* Require VSX and Linux to eliminate systems where you can't do
+ __attribute__((__target_clones__(...))). */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
[gcc(refs/users/meissner/heads/work171)] Add -mcpu=power11 tuning support.
https://gcc.gnu.org/g:351f2494837de9c9005abf96a20c9848a62199f1 commit 351f2494837de9c9005abf96a20c9848a62199f1 Author: Michael Meissner Date: Tue Jul 2 19:42:09 2024 -0400 Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. 2024-07-02 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alternative to power10. Diff: --- gcc/config/rs6000/power10.md | 144 +-- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab29..90312643858 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,4 @@ -;; Scheduling description for the IBM POWER10 processor. +;; Scheduling description for the IBM POWER10 and POWER11 processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11"))
[gcc(refs/users/meissner/heads/work171)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:b815028b7e98c1f482c2b5cf3fa737f0dacccd3c
commit b815028b7e98c1f482c2b5cf3fa737f0dacccd3c
Author: Michael Meissner
Date: Tue Jul 2 19:41:37 2024 -0400
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-07-02 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 32
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 +++--
17 files changed, 56 insertions(+), 16 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index bc45615741b..7c283f59e36 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5641,7 +5643,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work171-orig)] Merge commit 'refs/users/meissner/heads/work171-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:93ac8b42d90dba3807b962066bc11b855f629bc4 commit 93ac8b42d90dba3807b962066bc11b855f629bc4 Merge: c99feba8ef7 f745ee5a0dd Author: Michael Meissner Date: Tue Jul 2 19:32:03 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work171-orig Diff:
[gcc(refs/users/meissner/heads/work171-orig)] Add REVISION.
https://gcc.gnu.org/g:c99feba8ef7cc0650378610b29029f48d81cae52 commit c99feba8ef7cc0650378610b29029f48d81cae52 Author: Michael Meissner Date: Fri Jun 28 15:09:42 2024 -0400 Add REVISION. 2024-06-28 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..546b088ed52 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work171-orig branch
[gcc/meissner/heads/work171-orig] (41 commits) Merge commit 'refs/users/meissner/heads/work171-orig' of gi
The branch 'meissner/heads/work171-orig' was updated to point to:
93ac8b42d90... Merge commit 'refs/users/meissner/heads/work171-orig' of gi
It previously pointed to:
f745ee5a0dd... Merge commit 'refs/users/meissner/heads/work171-orig' of gi
Diff:
Summary of changes (added commits):
---
93ac8b4... Merge commit 'refs/users/meissner/heads/work171-orig' of gi
c99feba... Add REVISION.
895bbc0... aarch64: Add vector popcount besides QImode [PR113859] (*)
a7ad9cb... aarch64: Add testcase for vectorconvert lowering [PR110473] (*)
36852a1... Rename expand_powcabs pass to expand_pow (*)
a17ce10... Add some optimizations to gimple_expand_builtin_cabs (*)
d8fe4f0... Move cabs expansion from powcabs to complex lowering [PR115 (*)
578ccc7... Small optimization for complex addition, real/imag parts th (*)
1250540... c++: Fix ICE on constexpr placement new [PR115754] (*)
beb7a41... c++: Implement C++26 P3144R2 - Deleting a Pointer to an Inc (*)
f30bdb1... c++: Implement C++26 P0963R3 - Structured binding declarati (*)
cc63b59... Regenerate common.opt.urls (*)
189d0f1... bpf,btf: enable BTF pruning by default for BPF (*)
b8977d9... btf: add -gprune-btf option (*)
616c44f... btf: refactor and simplify implementation (*)
36774ce... ctf: use pointers instead of IDs internally (*)
d3f586e... ctf, btf: restructure CTF/BTF emission (*)
d04c553... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
bd9c550... build: Fix "make install" for MinGW (*)
fef7b8c... gcc: docs: Fix documentation of two hooks (*)
9bd5135... tree-optimization/115741 - ICE with VMAT_CONTIGUOUS_REVERSE (*)
4996c5f... ada: Use static allocation for small dynamic string concate (*)
78fe228... ada: Fix generic renaming table low bound on reset (*)
5621e90... ada: Compiler accepts an illegal Unchecked_Access attribute (*)
404f1f7... ada: Use clause (or use type clause) in a protected operati (*)
15d3f36... ada: Put_Image aspect spec ignored for null extension. (*)
0330830... ada: Allow mutably tagged types to work with qualified expr (*)
d331044... ada: Bug box for expression function with list comprehensio (*)
772fcf4... ada: Call memcmp instead of Compare_Array_Unsigned_8 and... (*)
487c9df... ada: Fix analysis of Extensions_Visible (*)
693985f... ada: Fix bogus error on allocator in instantiation with pri (*)
9fbf651... ada: Miscomputed bounds for inner null array aggregates (*)
29e10c5... ada: Fix crash on box-initialized component with No_Default (*)
fe29260... ada: Document that -gnatdJ is unused (*)
68e0349... amdgcn: invent target feature flags (*)
49058fe... c++: Relax too strict assert in stabilize_expr [PR60] (*)
e9c0cbf... i386: Support APX NF and NDD for imul/mul (*)
39e679e... sparc: define SPARC_LONG_DOUBLE_TYPE_SIZE for vxworks [PR11 (*)
90c8782... LoongArch: Define loongarch_insn_cost and set the cost of m (*)
20909c9... LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests. (*)
5667028... isel: Fold more in gimple_expand_vec_cond_expr [PR115659] (*)
(*) This commit already exists in another branch.
Because the reference `refs/users/meissner/heads/work171-orig' matches
your hooks.email-new-commits-only configuration,
no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work171-vpair)] Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:39334c0bdf6854ad4bef9979125deaf636b3a8f4 commit 39334c0bdf6854ad4bef9979125deaf636b3a8f4 Merge: be0c0a6727f 08f8a254f51 Author: Michael Meissner Date: Tue Jul 2 19:30:01 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work171-vpair Diff:
[gcc(refs/users/meissner/heads/work171-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:be0c0a6727fe739b07c12e820448ad2704193a55 commit be0c0a6727fe739b07c12e820448ad2704193a55 Author: Michael Meissner Date: Fri Jun 28 15:05:36 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..eb6dd427796 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work171-vpair, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..6cef7066a80 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-vpair branch
[gcc/meissner/heads/work171-vpair] (43 commits) Merge commit 'refs/users/meissner/heads/work171-vpair' of g
The branch 'meissner/heads/work171-vpair' was updated to point to:
39334c0bdf6... Merge commit 'refs/users/meissner/heads/work171-vpair' of g
It previously pointed to:
08f8a254f51... Merge commit 'refs/users/meissner/heads/work171-vpair' of g
Diff:
Summary of changes (added commits):
---
39334c0... Merge commit 'refs/users/meissner/heads/work171-vpair' of g
be0c0a6... Add ChangeLog.vpair and update REVISION.
5390876... Update ChangeLog.* (*)
cc83c11... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
276337a... Add ChangeLog.meissner and REVISION. (*)
a7ad9cb... aarch64: Add testcase for vectorconvert lowering [PR110473] (*)
36852a1... Rename expand_powcabs pass to expand_pow (*)
a17ce10... Add some optimizations to gimple_expand_builtin_cabs (*)
d8fe4f0... Move cabs expansion from powcabs to complex lowering [PR115 (*)
578ccc7... Small optimization for complex addition, real/imag parts th (*)
1250540... c++: Fix ICE on constexpr placement new [PR115754] (*)
beb7a41... c++: Implement C++26 P3144R2 - Deleting a Pointer to an Inc (*)
f30bdb1... c++: Implement C++26 P0963R3 - Structured binding declarati (*)
cc63b59... Regenerate common.opt.urls (*)
189d0f1... bpf,btf: enable BTF pruning by default for BPF (*)
b8977d9... btf: add -gprune-btf option (*)
616c44f... btf: refactor and simplify implementation (*)
36774ce... ctf: use pointers instead of IDs internally (*)
d3f586e... ctf, btf: restructure CTF/BTF emission (*)
d04c553... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
bd9c550... build: Fix "make install" for MinGW (*)
fef7b8c... gcc: docs: Fix documentation of two hooks (*)
9bd5135... tree-optimization/115741 - ICE with VMAT_CONTIGUOUS_REVERSE (*)
4996c5f... ada: Use static allocation for small dynamic string concate (*)
78fe228... ada: Fix generic renaming table low bound on reset (*)
5621e90... ada: Compiler accepts an illegal Unchecked_Access attribute (*)
404f1f7... ada: Use clause (or use type clause) in a protected operati (*)
15d3f36... ada: Put_Image aspect spec ignored for null extension. (*)
0330830... ada: Allow mutably tagged types to work with qualified expr (*)
d331044... ada: Bug box for expression function with list comprehensio (*)
772fcf4... ada: Call memcmp instead of Compare_Array_Unsigned_8 and... (*)
487c9df... ada: Fix analysis of Extensions_Visible (*)
693985f... ada: Fix bogus error on allocator in instantiation with pri (*)
9fbf651... ada: Miscomputed bounds for inner null array aggregates (*)
29e10c5... ada: Fix crash on box-initialized component with No_Default (*)
fe29260... ada: Document that -gnatdJ is unused (*)
68e0349... amdgcn: invent target feature flags (*)
49058fe... c++: Relax too strict assert in stabilize_expr [PR60] (*)
e9c0cbf... i386: Support APX NF and NDD for imul/mul (*)
39e679e... sparc: define SPARC_LONG_DOUBLE_TYPE_SIZE for vxworks [PR11 (*)
90c8782... LoongArch: Define loongarch_insn_cost and set the cost of m (*)
20909c9... LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests. (*)
5667028... isel: Fold more in gimple_expand_vec_cond_expr [PR115659] (*)
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[gcc(refs/users/meissner/heads/work171-test)] Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:7b7938f8984eece2ac6e36c95305577a0ce631d5 commit 7b7938f8984eece2ac6e36c95305577a0ce631d5 Merge: 0e5d73a9f5a 610c6e705cf Author: Michael Meissner Date: Tue Jul 2 19:28:32 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-test' of git+ssh://gcc.gnu.org/git/gcc into me/work171-test Diff:
[gcc(refs/users/meissner/heads/work171-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:0e5d73a9f5ae4a8abd95dc7ff81698011e8d3b83 commit 0e5d73a9f5ae4a8abd95dc7ff81698011e8d3b83 Author: Michael Meissner Date: Fri Jun 28 15:08:09 2024 -0400 Add ChangeLog.test and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..c2893a28120 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work171-test, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..78d94f8c4ae 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-test branch
[gcc/meissner/heads/work171-test] (43 commits) Merge commit 'refs/users/meissner/heads/work171-test' of gi
The branch 'meissner/heads/work171-test' was updated to point to:
7b7938f8984... Merge commit 'refs/users/meissner/heads/work171-test' of gi
It previously pointed to:
610c6e705cf... Merge commit 'refs/users/meissner/heads/work171-test' of gi
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Summary of changes (added commits):
---
7b7938f... Merge commit 'refs/users/meissner/heads/work171-test' of gi
0e5d73a... Add ChangeLog.test and update REVISION.
5390876... Update ChangeLog.* (*)
cc83c11... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
276337a... Add ChangeLog.meissner and REVISION. (*)
a7ad9cb... aarch64: Add testcase for vectorconvert lowering [PR110473] (*)
36852a1... Rename expand_powcabs pass to expand_pow (*)
a17ce10... Add some optimizations to gimple_expand_builtin_cabs (*)
d8fe4f0... Move cabs expansion from powcabs to complex lowering [PR115 (*)
578ccc7... Small optimization for complex addition, real/imag parts th (*)
1250540... c++: Fix ICE on constexpr placement new [PR115754] (*)
beb7a41... c++: Implement C++26 P3144R2 - Deleting a Pointer to an Inc (*)
f30bdb1... c++: Implement C++26 P0963R3 - Structured binding declarati (*)
cc63b59... Regenerate common.opt.urls (*)
189d0f1... bpf,btf: enable BTF pruning by default for BPF (*)
b8977d9... btf: add -gprune-btf option (*)
616c44f... btf: refactor and simplify implementation (*)
36774ce... ctf: use pointers instead of IDs internally (*)
d3f586e... ctf, btf: restructure CTF/BTF emission (*)
d04c553... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
bd9c550... build: Fix "make install" for MinGW (*)
fef7b8c... gcc: docs: Fix documentation of two hooks (*)
9bd5135... tree-optimization/115741 - ICE with VMAT_CONTIGUOUS_REVERSE (*)
4996c5f... ada: Use static allocation for small dynamic string concate (*)
78fe228... ada: Fix generic renaming table low bound on reset (*)
5621e90... ada: Compiler accepts an illegal Unchecked_Access attribute (*)
404f1f7... ada: Use clause (or use type clause) in a protected operati (*)
15d3f36... ada: Put_Image aspect spec ignored for null extension. (*)
0330830... ada: Allow mutably tagged types to work with qualified expr (*)
d331044... ada: Bug box for expression function with list comprehensio (*)
772fcf4... ada: Call memcmp instead of Compare_Array_Unsigned_8 and... (*)
487c9df... ada: Fix analysis of Extensions_Visible (*)
693985f... ada: Fix bogus error on allocator in instantiation with pri (*)
9fbf651... ada: Miscomputed bounds for inner null array aggregates (*)
29e10c5... ada: Fix crash on box-initialized component with No_Default (*)
fe29260... ada: Document that -gnatdJ is unused (*)
68e0349... amdgcn: invent target feature flags (*)
49058fe... c++: Relax too strict assert in stabilize_expr [PR60] (*)
e9c0cbf... i386: Support APX NF and NDD for imul/mul (*)
39e679e... sparc: define SPARC_LONG_DOUBLE_TYPE_SIZE for vxworks [PR11 (*)
90c8782... LoongArch: Define loongarch_insn_cost and set the cost of m (*)
20909c9... LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests. (*)
5667028... isel: Fold more in gimple_expand_vec_cond_expr [PR115659] (*)
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[gcc(refs/users/meissner/heads/work171-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:efe2591c0078f2aaa7139ed86154c5ba0d32c16c commit efe2591c0078f2aaa7139ed86154c5ba0d32c16c Author: Michael Meissner Date: Fri Jun 28 15:06:24 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..dbdff04e2fa --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work171-tar, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..da2e6621959 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-tar branch
[gcc(refs/users/meissner/heads/work171-tar)] Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:52e709fbd0f6ca5b430b16c0b31be4fad11702b7 commit 52e709fbd0f6ca5b430b16c0b31be4fad11702b7 Merge: efe2591c007 c70c1d9fef8 Author: Michael Meissner Date: Tue Jul 2 19:27:06 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work171-tar Diff:
[gcc/meissner/heads/work171-tar] (43 commits) Merge commit 'refs/users/meissner/heads/work171-tar' of git
The branch 'meissner/heads/work171-tar' was updated to point to:
52e709fbd0f... Merge commit 'refs/users/meissner/heads/work171-tar' of git
It previously pointed to:
c70c1d9fef8... Merge commit 'refs/users/meissner/heads/work171-tar' of git
Diff:
Summary of changes (added commits):
---
52e709f... Merge commit 'refs/users/meissner/heads/work171-tar' of git
efe2591... Add ChangeLog.tar and update REVISION.
5390876... Update ChangeLog.* (*)
cc83c11... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
276337a... Add ChangeLog.meissner and REVISION. (*)
a7ad9cb... aarch64: Add testcase for vectorconvert lowering [PR110473] (*)
36852a1... Rename expand_powcabs pass to expand_pow (*)
a17ce10... Add some optimizations to gimple_expand_builtin_cabs (*)
d8fe4f0... Move cabs expansion from powcabs to complex lowering [PR115 (*)
578ccc7... Small optimization for complex addition, real/imag parts th (*)
1250540... c++: Fix ICE on constexpr placement new [PR115754] (*)
beb7a41... c++: Implement C++26 P3144R2 - Deleting a Pointer to an Inc (*)
f30bdb1... c++: Implement C++26 P0963R3 - Structured binding declarati (*)
cc63b59... Regenerate common.opt.urls (*)
189d0f1... bpf,btf: enable BTF pruning by default for BPF (*)
b8977d9... btf: add -gprune-btf option (*)
616c44f... btf: refactor and simplify implementation (*)
36774ce... ctf: use pointers instead of IDs internally (*)
d3f586e... ctf, btf: restructure CTF/BTF emission (*)
d04c553... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
bd9c550... build: Fix "make install" for MinGW (*)
fef7b8c... gcc: docs: Fix documentation of two hooks (*)
9bd5135... tree-optimization/115741 - ICE with VMAT_CONTIGUOUS_REVERSE (*)
4996c5f... ada: Use static allocation for small dynamic string concate (*)
78fe228... ada: Fix generic renaming table low bound on reset (*)
5621e90... ada: Compiler accepts an illegal Unchecked_Access attribute (*)
404f1f7... ada: Use clause (or use type clause) in a protected operati (*)
15d3f36... ada: Put_Image aspect spec ignored for null extension. (*)
0330830... ada: Allow mutably tagged types to work with qualified expr (*)
d331044... ada: Bug box for expression function with list comprehensio (*)
772fcf4... ada: Call memcmp instead of Compare_Array_Unsigned_8 and... (*)
487c9df... ada: Fix analysis of Extensions_Visible (*)
693985f... ada: Fix bogus error on allocator in instantiation with pri (*)
9fbf651... ada: Miscomputed bounds for inner null array aggregates (*)
29e10c5... ada: Fix crash on box-initialized component with No_Default (*)
fe29260... ada: Document that -gnatdJ is unused (*)
68e0349... amdgcn: invent target feature flags (*)
49058fe... c++: Relax too strict assert in stabilize_expr [PR60] (*)
e9c0cbf... i386: Support APX NF and NDD for imul/mul (*)
39e679e... sparc: define SPARC_LONG_DOUBLE_TYPE_SIZE for vxworks [PR11 (*)
90c8782... LoongArch: Define loongarch_insn_cost and set the cost of m (*)
20909c9... LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests. (*)
5667028... isel: Fold more in gimple_expand_vec_cond_expr [PR115659] (*)
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[gcc(refs/users/meissner/heads/work171-dmf)] Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work17
https://gcc.gnu.org/g:255381881825fecc01dc7578716e08529fdb144a commit 255381881825fecc01dc7578716e08529fdb144a Merge: 93a0b8616fe 306ab5def69 Author: Michael Meissner Date: Tue Jul 2 18:51:18 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work171-dmf Diff:
[gcc(refs/users/meissner/heads/work171-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:93a0b8616fe20524374952c406840e242de89b18 commit 93a0b8616fe20524374952c406840e242de89b18 Author: Michael Meissner Date: Fri Jun 28 15:04:38 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..bf4edca66c7 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work171-dmf, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..e8fb95125d2 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-dmf branch
[gcc/meissner/heads/work171-dmf] (43 commits) Merge commit 'refs/users/meissner/heads/work171-dmf' of git
The branch 'meissner/heads/work171-dmf' was updated to point to:
25538188182... Merge commit 'refs/users/meissner/heads/work171-dmf' of git
It previously pointed to:
306ab5def69... Merge commit 'refs/users/meissner/heads/work171-dmf' of git
Diff:
Summary of changes (added commits):
---
2553818... Merge commit 'refs/users/meissner/heads/work171-dmf' of git
93a0b86... Add ChangeLog.dmf and update REVISION.
5390876... Update ChangeLog.* (*)
cc83c11... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
276337a... Add ChangeLog.meissner and REVISION. (*)
a7ad9cb... aarch64: Add testcase for vectorconvert lowering [PR110473] (*)
36852a1... Rename expand_powcabs pass to expand_pow (*)
a17ce10... Add some optimizations to gimple_expand_builtin_cabs (*)
d8fe4f0... Move cabs expansion from powcabs to complex lowering [PR115 (*)
578ccc7... Small optimization for complex addition, real/imag parts th (*)
1250540... c++: Fix ICE on constexpr placement new [PR115754] (*)
beb7a41... c++: Implement C++26 P3144R2 - Deleting a Pointer to an Inc (*)
f30bdb1... c++: Implement C++26 P0963R3 - Structured binding declarati (*)
cc63b59... Regenerate common.opt.urls (*)
189d0f1... bpf,btf: enable BTF pruning by default for BPF (*)
b8977d9... btf: add -gprune-btf option (*)
616c44f... btf: refactor and simplify implementation (*)
36774ce... ctf: use pointers instead of IDs internally (*)
d3f586e... ctf, btf: restructure CTF/BTF emission (*)
d04c553... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
bd9c550... build: Fix "make install" for MinGW (*)
fef7b8c... gcc: docs: Fix documentation of two hooks (*)
9bd5135... tree-optimization/115741 - ICE with VMAT_CONTIGUOUS_REVERSE (*)
4996c5f... ada: Use static allocation for small dynamic string concate (*)
78fe228... ada: Fix generic renaming table low bound on reset (*)
5621e90... ada: Compiler accepts an illegal Unchecked_Access attribute (*)
404f1f7... ada: Use clause (or use type clause) in a protected operati (*)
15d3f36... ada: Put_Image aspect spec ignored for null extension. (*)
0330830... ada: Allow mutably tagged types to work with qualified expr (*)
d331044... ada: Bug box for expression function with list comprehensio (*)
772fcf4... ada: Call memcmp instead of Compare_Array_Unsigned_8 and... (*)
487c9df... ada: Fix analysis of Extensions_Visible (*)
693985f... ada: Fix bogus error on allocator in instantiation with pri (*)
9fbf651... ada: Miscomputed bounds for inner null array aggregates (*)
29e10c5... ada: Fix crash on box-initialized component with No_Default (*)
fe29260... ada: Document that -gnatdJ is unused (*)
68e0349... amdgcn: invent target feature flags (*)
49058fe... c++: Relax too strict assert in stabilize_expr [PR60] (*)
e9c0cbf... i386: Support APX NF and NDD for imul/mul (*)
39e679e... sparc: define SPARC_LONG_DOUBLE_TYPE_SIZE for vxworks [PR11 (*)
90c8782... LoongArch: Define loongarch_insn_cost and set the cost of m (*)
20909c9... LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests. (*)
5667028... isel: Fold more in gimple_expand_vec_cond_expr [PR115659] (*)
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[gcc(refs/users/meissner/heads/work171-bugs)] Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:d33f66a9a6befb6a2b0a12dd5b0b4d088a3b1d83 commit d33f66a9a6befb6a2b0a12dd5b0b4d088a3b1d83 Merge: 3e3164cdc9b eea8d7b482a Author: Michael Meissner Date: Tue Jul 2 18:48:51 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work171-bugs Diff:
[gcc/meissner/heads/work171-bugs] (43 commits) Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
The branch 'meissner/heads/work171-bugs' was updated to point to:
d33f66a9a6b... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
It previously pointed to:
eea8d7b482a... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
Diff:
Summary of changes (added commits):
---
d33f66a... Merge commit 'refs/users/meissner/heads/work171-bugs' of gi
3e3164c... Add ChangeLog.bugs and update REVISION.
5390876... Update ChangeLog.* (*)
cc83c11... Merge commit 'refs/users/meissner/heads/work171' of git+ssh (*)
276337a... Add ChangeLog.meissner and REVISION. (*)
a7ad9cb... aarch64: Add testcase for vectorconvert lowering [PR110473] (*)
36852a1... Rename expand_powcabs pass to expand_pow (*)
a17ce10... Add some optimizations to gimple_expand_builtin_cabs (*)
d8fe4f0... Move cabs expansion from powcabs to complex lowering [PR115 (*)
578ccc7... Small optimization for complex addition, real/imag parts th (*)
1250540... c++: Fix ICE on constexpr placement new [PR115754] (*)
beb7a41... c++: Implement C++26 P3144R2 - Deleting a Pointer to an Inc (*)
f30bdb1... c++: Implement C++26 P0963R3 - Structured binding declarati (*)
cc63b59... Regenerate common.opt.urls (*)
189d0f1... bpf,btf: enable BTF pruning by default for BPF (*)
b8977d9... btf: add -gprune-btf option (*)
616c44f... btf: refactor and simplify implementation (*)
36774ce... ctf: use pointers instead of IDs internally (*)
d3f586e... ctf, btf: restructure CTF/BTF emission (*)
d04c553... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
bd9c550... build: Fix "make install" for MinGW (*)
fef7b8c... gcc: docs: Fix documentation of two hooks (*)
9bd5135... tree-optimization/115741 - ICE with VMAT_CONTIGUOUS_REVERSE (*)
4996c5f... ada: Use static allocation for small dynamic string concate (*)
78fe228... ada: Fix generic renaming table low bound on reset (*)
5621e90... ada: Compiler accepts an illegal Unchecked_Access attribute (*)
404f1f7... ada: Use clause (or use type clause) in a protected operati (*)
15d3f36... ada: Put_Image aspect spec ignored for null extension. (*)
0330830... ada: Allow mutably tagged types to work with qualified expr (*)
d331044... ada: Bug box for expression function with list comprehensio (*)
772fcf4... ada: Call memcmp instead of Compare_Array_Unsigned_8 and... (*)
487c9df... ada: Fix analysis of Extensions_Visible (*)
693985f... ada: Fix bogus error on allocator in instantiation with pri (*)
9fbf651... ada: Miscomputed bounds for inner null array aggregates (*)
29e10c5... ada: Fix crash on box-initialized component with No_Default (*)
fe29260... ada: Document that -gnatdJ is unused (*)
68e0349... amdgcn: invent target feature flags (*)
49058fe... c++: Relax too strict assert in stabilize_expr [PR60] (*)
e9c0cbf... i386: Support APX NF and NDD for imul/mul (*)
39e679e... sparc: define SPARC_LONG_DOUBLE_TYPE_SIZE for vxworks [PR11 (*)
90c8782... LoongArch: Define loongarch_insn_cost and set the cost of m (*)
20909c9... LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests. (*)
5667028... isel: Fold more in gimple_expand_vec_cond_expr [PR115659] (*)
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[gcc(refs/users/meissner/heads/work171-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:3e3164cdc9b69011c24bc441992218388960eeb6 commit 3e3164cdc9b69011c24bc441992218388960eeb6 Author: Michael Meissner Date: Fri Jun 28 15:07:19 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-06-28 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..d2c5d2ab118 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work171-bugs, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 060d0f9e831..7a2e248f4d4 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work171 branch +work171-bugs branch
[gcc(refs/users/meissner/heads/work171)] Update ChangeLog.*
https://gcc.gnu.org/g:539087641cbf542ec599d5b6a8daeb45c1cdaf78 commit 539087641cbf542ec599d5b6a8daeb45c1cdaf78 Author: Michael Meissner Date: Tue Jul 2 18:48:12 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 36 +++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 1418e34ed1c..ff5bdb5ac0a 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,40 @@ Branch work171, baseline +2024-07-02 Michael Meissner + + Merge up to a7ad9cb813063ddf51269910f33b56116c10462c. + +2024-06-28 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + 2024-06-28 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work171)] Merge commit 'refs/users/meissner/heads/work171' of git+ssh://gcc.gnu.org/git/gcc into me/work171
https://gcc.gnu.org/g:cc83c118961603036cc518b908052a5b887b0348 commit cc83c118961603036cc518b908052a5b887b0348 Merge: 276337ad39d 1f0d0b5085c Author: Michael Meissner Date: Tue Jul 2 18:44:38 2024 -0400 Merge commit 'refs/users/meissner/heads/work171' of git+ssh://gcc.gnu.org/git/gcc into me/work171 Diff:
[gcc/meissner/heads/work171] (40 commits) Merge commit 'refs/users/meissner/heads/work171' of git+ssh
The branch 'meissner/heads/work171' was updated to point to:
cc83c118961... Merge commit 'refs/users/meissner/heads/work171' of git+ssh
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1f0d0b5085c... Merge commit 'refs/users/meissner/heads/work171' of git+ssh
Diff:
Summary of changes (added commits):
---
cc83c11... Merge commit 'refs/users/meissner/heads/work171' of git+ssh
276337a... Add ChangeLog.meissner and REVISION.
a7ad9cb... aarch64: Add testcase for vectorconvert lowering [PR110473] (*)
36852a1... Rename expand_powcabs pass to expand_pow (*)
a17ce10... Add some optimizations to gimple_expand_builtin_cabs (*)
d8fe4f0... Move cabs expansion from powcabs to complex lowering [PR115 (*)
578ccc7... Small optimization for complex addition, real/imag parts th (*)
1250540... c++: Fix ICE on constexpr placement new [PR115754] (*)
beb7a41... c++: Implement C++26 P3144R2 - Deleting a Pointer to an Inc (*)
f30bdb1... c++: Implement C++26 P0963R3 - Structured binding declarati (*)
cc63b59... Regenerate common.opt.urls (*)
189d0f1... bpf,btf: enable BTF pruning by default for BPF (*)
b8977d9... btf: add -gprune-btf option (*)
616c44f... btf: refactor and simplify implementation (*)
36774ce... ctf: use pointers instead of IDs internally (*)
d3f586e... ctf, btf: restructure CTF/BTF emission (*)
d04c553... Arm: Fix disassembly error in Thumb-1 relaxed load/store [P (*)
bd9c550... build: Fix "make install" for MinGW (*)
fef7b8c... gcc: docs: Fix documentation of two hooks (*)
9bd5135... tree-optimization/115741 - ICE with VMAT_CONTIGUOUS_REVERSE (*)
4996c5f... ada: Use static allocation for small dynamic string concate (*)
78fe228... ada: Fix generic renaming table low bound on reset (*)
5621e90... ada: Compiler accepts an illegal Unchecked_Access attribute (*)
404f1f7... ada: Use clause (or use type clause) in a protected operati (*)
15d3f36... ada: Put_Image aspect spec ignored for null extension. (*)
0330830... ada: Allow mutably tagged types to work with qualified expr (*)
d331044... ada: Bug box for expression function with list comprehensio (*)
772fcf4... ada: Call memcmp instead of Compare_Array_Unsigned_8 and... (*)
487c9df... ada: Fix analysis of Extensions_Visible (*)
693985f... ada: Fix bogus error on allocator in instantiation with pri (*)
9fbf651... ada: Miscomputed bounds for inner null array aggregates (*)
29e10c5... ada: Fix crash on box-initialized component with No_Default (*)
fe29260... ada: Document that -gnatdJ is unused (*)
68e0349... amdgcn: invent target feature flags (*)
49058fe... c++: Relax too strict assert in stabilize_expr [PR60] (*)
e9c0cbf... i386: Support APX NF and NDD for imul/mul (*)
39e679e... sparc: define SPARC_LONG_DOUBLE_TYPE_SIZE for vxworks [PR11 (*)
90c8782... LoongArch: Define loongarch_insn_cost and set the cost of m (*)
20909c9... LoongArch: Fix explicit-relocs-{extreme-,}tls-desc.c tests. (*)
5667028... isel: Fold more in gimple_expand_vec_cond_expr [PR115659] (*)
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[gcc(refs/users/meissner/heads/work171)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:276337ad39d148f73f62e21913ba3bfca0d81b2c commit 276337ad39d148f73f62e21913ba3bfca0d81b2c Author: Michael Meissner Date: Fri Jun 28 15:03:42 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-06-28 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 6 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 6 ++ gcc/c/ChangeLog.meissner | 6 ++ gcc/cp/ChangeLog.meissner| 6 ++ gcc/fortran/ChangeLog.meissner | 6 ++ gcc/testsuite/ChangeLog.meissner | 6 ++ libgcc/ChangeLog.meissner| 6 ++ libstdc++-v3/ChangeLog.meissner | 6 ++ 9 files changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..060d0f9e831 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work171 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch + diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index 000..1418e34ed1c --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work171, baseline + +2024-06-28 Michael Meissner + + Clone branch +
[gcc(refs/users/meissner/heads/work171-orig)] Merge commit 'refs/users/meissner/heads/work171-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:f745ee5a0dde7a43b384dcd9bfac7b9a74c8826c commit f745ee5a0dde7a43b384dcd9bfac7b9a74c8826c Merge: ebaf415b9e1 547ef5be3d3 Author: Michael Meissner Date: Mon Jul 1 23:00:18 2024 -0400 Merge commit 'refs/users/meissner/heads/work171-orig' of git+ssh://gcc.gnu.org/git/gcc into me/work171-orig Diff:
