[gcc r15-2411] RISC-V: Add basic support for the Zacas extension
https://gcc.gnu.org/g:11c2453a16b725b7fb67778e1ab4636a51a1217d
commit r15-2411-g11c2453a16b725b7fb67778e1ab4636a51a1217d
Author: Gianluca Guida
Date: Mon Jul 29 15:13:46 2024 -0700
RISC-V: Add basic support for the Zacas extension
This patch adds support for amocas.{b|h|w|d}. Support for amocas.q
(64/128 bit cas for rv32/64) will be added in a future patch.
Extension: https://github.com/riscv/riscv-zacas
Ratification: https://jira.riscv.org/browse/RVS-680
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zacas extension.
* config/riscv/arch-canonicalize: Make zacas imply zaamo.
* config/riscv/riscv.opt: Add zacas.
* config/riscv/sync.md (zacas_atomic_cas_value): New pattern.
(atomic_compare_and_swap): Use new pattern for
compare-and-swap ops.
(zalrsc_atomic_cas_value_strong): Rename
atomic_cas_value_strong.
* doc/sourcebuild.texi: Add Zacas documentation.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add zacas testsuite infra support.
*
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c:
Remove zacas to continue to test the lr/sc pairs.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c:
Ditto.
*
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto.
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c:
Ditto.
*
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c:
Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c:
Ditto.
*
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto.
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c:
Ditto.
* gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: New
test.
* gcc.target/riscv/amo/zacas-char-requires-zabha.c: New test.
* gcc.target/riscv/amo/zacas-char-requires-zacas.c: New test.
* gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c:
New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c:
New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: New
test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c:
New test.
* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c:
New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: New test.
*
gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c:
New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: New test.
*
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c:
New test.
*
gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: New
test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c:
New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: New test.
* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c:
New test.
*
[gcc r15-2410] RISC-V: Remove configure check for zabha
https://gcc.gnu.org/g:c0af64af636a801850fc8fabee12635ec73daa22
commit r15-2410-gc0af64af636a801850fc8fabee12635ec73daa22
Author: Patrick O'Neill
Date: Mon Jul 29 19:52:02 2024 -0700
RISC-V: Remove configure check for zabha
This patch removes the zabha configure check since it's not a breaking
change
and updates the existing zaamo/zalrsc comment.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Remove zabha configure check
handling and clarify zaamo/zalrsc comment.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Remove zabha configure check.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 12 +++-
gcc/config.in | 6 --
gcc/configure | 31 ---
gcc/configure.ac| 5 -
4 files changed, 3 insertions(+), 51 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 682826c0e344..d2912877784d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -855,7 +855,6 @@ riscv_subset_list::to_string (bool version_p) const
bool skip_zifencei = false;
bool skip_zaamo_zalrsc = false;
- bool skip_zabha = false;
bool skip_zicsr = false;
bool i2p0 = false;
@@ -884,13 +883,11 @@ riscv_subset_list::to_string (bool version_p) const
skip_zifencei = true;
#endif
#ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC
- /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */
+ /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc.
+ Expanding 'a' to zaamo/zalrsc would otherwise break compilations
+ for users with an older version of binutils. */
skip_zaamo_zalrsc = true;
#endif
-#ifndef HAVE_AS_MARCH_ZABHA
- /* Skip since binutils 2.42 and earlier don't recognize zabha. */
- skip_zabha = true;
-#endif
for (subset = m_head; subset != NULL; subset = subset->next)
{
@@ -908,9 +905,6 @@ riscv_subset_list::to_string (bool version_p) const
if (skip_zaamo_zalrsc && subset->name == "zalrsc")
continue;
- if (skip_zabha && subset->name == "zabha")
- continue;
-
/* For !version_p, we only separate extension with underline for
multi-letter extension. */
if (!first &&
diff --git a/gcc/config.in b/gcc/config.in
index bc819005bd62..3af153eaec5c 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -635,12 +635,6 @@
#endif
-/* Define if the assembler understands -march=rv*_zabha. */
-#ifndef USED_FOR_TARGET
-#undef HAVE_AS_MARCH_ZABHA
-#endif
-
-
/* Define if the assembler understands -march=rv*_zifencei. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_MARCH_ZIFENCEI
diff --git a/gcc/configure b/gcc/configure
index 01acca7fb5cc..7541bdeb7248 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -30882,37 +30882,6 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then
$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h
-fi
-
-{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for
-march=rv32i_zabha support" >&5
-$as_echo_n "checking assembler for -march=rv32i_zabha support... " >&6; }
-if ${gcc_cv_as_riscv_march_zabha+:} false; then :
- $as_echo_n "(cached) " >&6
-else
- gcc_cv_as_riscv_march_zabha=no
- if test x$gcc_cv_as != x; then
-$as_echo '' > conftest.s
-if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zabha -o conftest.o
conftest.s >&5'
- { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
- (eval $ac_try) 2>&5
- ac_status=$?
- $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
- test $ac_status = 0; }; }
-then
- gcc_cv_as_riscv_march_zabha=yes
-else
- echo "configure: failed program was" >&5
- cat conftest.s >&5
-fi
-rm -f conftest.o conftest.s
- fi
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_zabha"
>&5
-$as_echo "$gcc_cv_as_riscv_march_zabha" >&6; }
-if test $gcc_cv_as_riscv_march_zabha = yes; then
-
-$as_echo "#define HAVE_AS_MARCH_ZABHA 1" >>confdefs.h
-
fi
;;
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 3f20c107b6aa..52c1780379d5 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5461,11 +5461,6 @@ configured with --enable-newlib-nano-formatted-io.])
[-march=rv32i_zaamo_zalrsc],,,
[AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1,
[Define if the assembler understands
-march=rv*_zaamo_zalrsc.])])
-gcc_GAS_CHECK_FEATURE([-march=rv32i_zabha support],
- gcc_cv_as_riscv_march_zabha,
- [-march=rv32i_zabha],,,
- [AC_DEFINE(HAVE_AS_MARCH_ZABHA, 1,
-[Define if the assembler understands -march=rv*_zabha.])])
;;
loongarch*-*-*)
gcc_GAS_CHECK_FEATURE([.dtprelword support],
[gcc r15-1897] Remove trailing whitespace from invoke.texi
https://gcc.gnu.org/g:a0e64a043ec498f959a214b5b02d6c7177984a0f
commit r15-1897-ga0e64a043ec498f959a214b5b02d6c7177984a0f
Author: Patrick O'Neill
Date: Tue Jul 2 18:28:00 2024 -0700
Remove trailing whitespace from invoke.texi
gcc/ChangeLog:
* doc/invoke.texi: Remove trailing whitespace.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/doc/invoke.texi | 392 ++--
1 file changed, 196 insertions(+), 196 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b37c7af7a390..4d671c4f6d89 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -94,9 +94,9 @@ that option with all supported languages.
The usual way to run GCC is to run the executable called @command{gcc}, or
@command{@var{machine}-gcc} when cross-compiling, or
@command{@var{machine}-gcc-@var{version}} to run a specific version of GCC.
-When you compile C++ programs, you should invoke GCC as @command{g++}
-instead. @xref{Invoking G++,,Compiling C++ Programs},
-for information about the differences in behavior between @command{gcc}
+When you compile C++ programs, you should invoke GCC as @command{g++}
+instead. @xref{Invoking G++,,Compiling C++ Programs},
+for information about the differences in behavior between @command{gcc}
and @command{g++} when compiling C++ programs.
@cindex grouping options
@@ -3623,8 +3623,8 @@ unambiguous base classes.
Mixing code compiled with @option{-frtti} with that compiled with
@option{-fno-rtti} may not work. For example, programs may
-fail to link if a class compiled with @option{-fno-rtti} is used as a base
-for a class compiled with @option{-frtti}.
+fail to link if a class compiled with @option{-fno-rtti} is used as a base
+for a class compiled with @option{-frtti}.
@opindex fsized-deallocation
@item -fsized-deallocation
@@ -4176,7 +4176,7 @@ As an example:
@smallexample
template void f(T t) @{ t(); @};
void g() noexcept;
-void h() @{ f(g); @}
+void h() @{ f(g); @}
@end smallexample
@noindent
@@ -4443,10 +4443,10 @@ But this use is not portable across different compilers.
@item -Wno-non-template-friend @r{(C++ and Objective-C++ only)}
Disable warnings when non-template friend functions are declared
within a template. In very old versions of GCC that predate implementation
-of the ISO standard, declarations such as
+of the ISO standard, declarations such as
@samp{friend int foo(int)}, where the name of the friend is an unqualified-id,
could be interpreted as a particular specialization of a template
-function; the warning exists to diagnose compatibility problems,
+function; the warning exists to diagnose compatibility problems,
and is enabled by default.
@opindex Wold-style-cast
@@ -5197,7 +5197,7 @@ value, if any.
Traditionally, diagnostic messages have been formatted irrespective of
the output device's aspect (e.g.@: its width, @dots{}). You can use the
options described below
-to control the formatting algorithm for diagnostic messages,
+to control the formatting algorithm for diagnostic messages,
e.g.@: how many characters per line, how often source location
information should be reported. Note that some language front ends may not
honor these options.
@@ -8039,7 +8039,7 @@ This warning is enabled by @option{-Wall} or
@option{-Wextra}.
@cindex unknown pragmas, warning
@cindex pragmas, warning of unknown
@item -Wunknown-pragmas
-Warn when a @code{#pragma} directive is encountered that is not understood by
+Warn when a @code{#pragma} directive is encountered that is not understood by
GCC@. If this command-line option is used, warnings are even issued
for unknown pragmas in system header files. This is not the case if
the warnings are only enabled by the @option{-Wall} command-line option.
@@ -8077,7 +8077,7 @@ This option is only active when
@option{-fstrict-aliasing} is active.
It warns about code that might break the strict aliasing rules that the
compiler is using for optimization.
Higher levels correspond to higher accuracy (fewer false positives).
-Higher levels also correspond to more effort, similar to the way @option{-O}
+Higher levels also correspond to more effort, similar to the way @option{-O}
works.
@option{-Wstrict-aliasing} is equivalent to @option{-Wstrict-aliasing=3}.
@@ -9298,7 +9298,7 @@ enabled by @option{-Wextra}.
@opindex Wno-bad-function-cast
@item -Wbad-function-cast @r{(C and Objective-C only)}
Warn when a function call is cast to a non-matching type.
-For example, warn if a call to a function returning an integer type
+For example, warn if a call to a function returning an integer type
is cast to a pointer type.
@opindex Wc90-c99-compat
@@ -9696,13 +9696,13 @@ Do not warn about stray tokens after @code{#else} and
@code{#endif}.
@item -Wenum-compare
Warn about a comparison between values of different enumerated types.
In C++ enumerated type mismatches in conditional expressions are also
[gcc r15-1825] RISC-V: Describe -march behavior for dependent extensions
https://gcc.gnu.org/g:70f6bc39c4b0e147a816ad1dad583f944616c367
commit r15-1825-g70f6bc39c4b0e147a816ad1dad583f944616c367
Author: Palmer Dabbelt
Date: Tue Jul 2 18:20:39 2024 -0700
RISC-V: Describe -march behavior for dependent extensions
gcc/ChangeLog:
* doc/invoke.texi: Describe -march behavior for dependent
extensions on
RISC-V.
Diff:
---
gcc/doc/invoke.texi | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 68ebd79d676..b37c7af7a39 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31063,6 +31063,10 @@ If both @option{-march} and @option{-mcpu=} are not
specified, the default for
this argument is system dependent, users who want a specific architecture
extensions should specify one explicitly.
+When the RISC-V specifications define an extension as depending on other
+extensions, GCC will implicitly add the dependent extensions to the enabled
+extension set if they weren't added explicitly.
+
@opindex mcpu
@item -mcpu=@var{processor-string}
Use architecture of and optimize the output for the given processor, specified
[gcc r15-1824] RISC-V: Add support for Zabha extension
https://gcc.gnu.org/g:7b2b2e3d660edc8ef3a8cfbdfc2b0fd499459601 commit r15-1824-g7b2b2e3d660edc8ef3a8cfbdfc2b0fd499459601 Author: Gianluca Guida Date: Tue Jul 2 18:05:14 2024 -0700 RISC-V: Add support for Zabha extension The Zabha extension adds support for subword Zaamo ops. Extension: https://github.com/riscv/riscv-zabha.git Ratification: https://jira.riscv.org/browse/RVS-1685 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Skip zabha when not supported by the assembler. * config.in: Regenerate. * config/riscv/arch-canonicalize: Make zabha imply zaamo. * config/riscv/iterators.md (amobh): Add iterator for amo byte/halfword. * config/riscv/riscv.opt: Add zabha. * config/riscv/sync.md (atomic_): Add subword atomic op pattern. (zabha_atomic_fetch_): Add subword atomic_fetch op pattern. (lrsc_atomic_fetch_): Prefer zabha over lrsc for subword atomic ops. (zabha_atomic_exchange): Add subword atomic exchange pattern. (lrsc_atomic_exchange): Prefer zabha over lrsc for subword atomic exchange ops. * configure: Regenerate. * configure.ac: Add zabha assembler check. * doc/sourcebuild.texi: Add zabha documentation. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add zabha testsuite infra support. * gcc.target/riscv/amo/inline-atomics-1.c: Remove zabha to continue to test the lr/sc subword patterns. * gcc.target/riscv/amo/inline-atomics-2.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto. * gcc.target/riscv/amo/zabha-all-amo-ops-char-run.c: New test. * gcc.target/riscv/amo/zabha-all-amo-ops-short-run.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: New test. * gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: New test. * gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: New test. * gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: New test. Co-Authored-By: Patrick O'Neill Signed-Off-By: Gianluca Guida Tested-by: Andrea Parri Diff: --- gcc/common/config/riscv/riscv-common.cc| 12 gcc/config.in | 6 ++ gcc/config/riscv/arch-canonicalize | 3 + gcc/config/riscv/iterators.md | 3 + gcc/config/riscv/riscv.opt | 2 + gcc/config/riscv/sync.md | 81 +- gcc/configure | 31 + gcc/configure.ac | 5 ++ gcc/doc/sourcebuild.texi | 12 +++- .../gcc.target/riscv/amo/inline-atomics-1.c| 1 + .../gcc.target/riscv/amo/inline-atomics-2.c| 1 + .../riscv/amo/zabha-all-amo-ops-char-run.c | 5 ++ .../riscv/amo/zabha-all-amo-ops-short-run.c| 5 ++ .../riscv/amo/zabha-rvwmo-all-amo-ops-char.c | 23 ++ .../riscv/amo/zabha-rvwmo-all-amo-ops-short.c | 23 ++ .../riscv/amo/zabha-rvwmo-amo-add-char.c | 57 +++ .../riscv/amo/zabha-rvwmo-amo-add-short.c | 57 +++ .../gcc.target/riscv/amo/zabha-ztso-amo-add-char.c | 57 +++ .../riscv/amo/zabha-ztso-amo-add-short.c | 57 +++ .../zalrsc-rvwmo-subword-amo-add-char-acq-rel.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-acquire.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-relaxed.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-release.c| 1 + .../zalrsc-rvwmo-subword-amo-add-char-seq-cst.c| 1 + .../amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c | 1 + .../amo/zalrsc-ztso-subword-amo-add-char-acquire.c | 1 +
[gcc r15-1661] RISC-V: Update testcase comments to point to PSABI rather than Table A.6
https://gcc.gnu.org/g:86a3dbeb6c6a36f8cf97c66cef83c9bc3ad82027 commit r15-1661-g86a3dbeb6c6a36f8cf97c66cef83c9bc3ad82027 Author: Patrick O'Neill Date: Tue Jun 25 14:14:18 2024 -0700 RISC-V: Update testcase comments to point to PSABI rather than Table A.6 Table A.6 was originally the source of truth for the recommended mappings. Point to the PSABI doc since the memory model mappings have been moved there. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/a-rvwmo-fence.c: Replace A.6 reference with PSABI. * gcc.target/riscv/amo/a-rvwmo-load-acquire.c: Ditto. * gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: Ditto. * gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: Ditto. * gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: Ditto. * gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: Ditto. * gcc.target/riscv/amo/a-rvwmo-store-release.c: Ditto. * gcc.target/riscv/amo/a-ztso-fence.c: Ditto. * gcc.target/riscv/amo/a-ztso-load-acquire.c: Ditto. * gcc.target/riscv/amo/a-ztso-load-relaxed.c: Ditto. * gcc.target/riscv/amo/a-ztso-load-seq-cst.c: Ditto. * gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: Ditto. * gcc.target/riscv/amo/a-ztso-store-relaxed.c: Ditto. * gcc.target/riscv/amo/a-ztso-store-release.c: Ditto. * gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c: Ditto. * gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto. Signed-off-by: Patrick O'Neill Diff: --- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c | 3 ++- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c | 3 ++- gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c | 2 +- gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
[gcc r15-1660] RISC-V: Consolidate amo testcase variants
https://gcc.gnu.org/g:aa89e86f70ac65e2d51f33ac45849d05a4f30524 commit r15-1660-gaa89e86f70ac65e2d51f33ac45849d05a4f30524 Author: Patrick O'Neill Date: Tue Jun 25 14:14:17 2024 -0700 RISC-V: Consolidate amo testcase variants Many riscv/amo/ testcases use check-function-bodies. These testcases can be consolidated with related testcases (memory ordering variants) without affecting the assertions. Give functions descriptive names so testsuite failures are obvious from the 'FAIL:' line. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-fence-1.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-fence-2.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-fence-3.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-fence-4.c: Removed. * gcc.target/riscv/amo/amo-table-a-6-fence-5.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-fence-1.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-fence-2.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-fence-3.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-fence-4.c: Removed. * gcc.target/riscv/amo/amo-table-ztso-fence-5.c: Removed. * gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Removed. * gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Removed. * gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Removed. * gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Removed. * gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Removed. * gcc.target/riscv/amo/a-rvwmo-fence.c: New test. * gcc.target/riscv/amo/a-ztso-fence.c: New test. * gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c: New test. * gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: New test. * gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c: New test. * gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c: New test. Signed-off-by: Patrick O'Neill Diff: --- gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c | 56 gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c | 52 +++ .../gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c | 17 - .../gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c | 17 - .../gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c | 17 - .../gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c | 17 - .../gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c | 17 - .../gcc.target/riscv/amo/amo-table-a-6-fence-1.c | 15 - .../gcc.target/riscv/amo/amo-table-a-6-fence-2.c | 16 - .../gcc.target/riscv/amo/amo-table-a-6-fence-3.c | 16 - .../gcc.target/riscv/amo/amo-table-a-6-fence-4.c | 16 - .../gcc.target/riscv/amo/amo-table-a-6-fence-5.c | 16 - .../riscv/amo/amo-table-ztso-amo-add-1.c | 17 - .../riscv/amo/amo-table-ztso-amo-add-2.c | 17 - .../riscv/amo/amo-table-ztso-amo-add-3.c | 17 - .../riscv/amo/amo-table-ztso-amo-add-4.c | 17 - .../riscv/amo/amo-table-ztso-amo-add-5.c | 17 - .../gcc.target/riscv/amo/amo-table-ztso-fence-1.c | 15 - .../gcc.target/riscv/amo/amo-table-ztso-fence-2.c | 15 - .../gcc.target/riscv/amo/amo-table-ztso-fence-3.c | 15 - .../gcc.target/riscv/amo/amo-table-ztso-fence-4.c | 15 - .../gcc.target/riscv/amo/amo-table-ztso-fence-5.c | 16 - .../gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c| 22 -- .../gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c| 22 -- .../gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c| 22 -- .../gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c| 22 -- .../gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c| 22 -- .../gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c | 57 .../gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c | 57 .../riscv/amo/zalrsc-rvwmo-amo-add-int.c | 78 ++ .../gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c | 78 ++ 31 files changed, 378 insertions(+), 435 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c new file
[gcc r15-1659] RISC-V: Rename amo testcases
https://gcc.gnu.org/g:08498f81f0595eb8a90ea33afd7dab44bb76b293
commit r15-1659-g08498f81f0595eb8a90ea33afd7dab44bb76b293
Author: Patrick O'Neill
Date: Tue Jun 25 14:14:16 2024 -0700
RISC-V: Rename amo testcases
Rename riscv/amo/ testcases to follow a '{ext}-{model}-{name}-{memory
order}.c'
naming convention.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo/amo-table-a-6-load-2.c: Move to...
* gcc.target/riscv/amo/a-rvwmo-load-acquire.c: ...here.
* gcc.target/riscv/amo/amo-table-a-6-load-1.c: Move to...
* gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: ...here.
* gcc.target/riscv/amo/amo-table-a-6-load-3.c: Move to...
* gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: ...here.
* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Move to...
* gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: ...here.
* gcc.target/riscv/amo/amo-table-a-6-store-1.c: Move to...
* gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: ...here.
* gcc.target/riscv/amo/amo-table-a-6-store-2.c: Move to...
* gcc.target/riscv/amo/a-rvwmo-store-release.c: ...here.
* gcc.target/riscv/amo/amo-table-ztso-load-2.c: Move to...
* gcc.target/riscv/amo/a-ztso-load-acquire.c: ...here.
* gcc.target/riscv/amo/amo-table-ztso-load-1.c: Move to...
* gcc.target/riscv/amo/a-ztso-load-relaxed.c: ...here.
* gcc.target/riscv/amo/amo-table-ztso-load-3.c: Move to...
* gcc.target/riscv/amo/a-ztso-load-seq-cst.c: ...here.
* gcc.target/riscv/amo/amo-table-ztso-store-3.c: Move to...
* gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: ...here.
* gcc.target/riscv/amo/amo-table-ztso-store-1.c: Move to...
* gcc.target/riscv/amo/a-ztso-store-relaxed.c: ...here.
* gcc.target/riscv/amo/amo-table-ztso-store-2.c: Move to...
* gcc.target/riscv/amo/a-ztso-store-release.c: ...here.
* gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: Move to...
* gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c: ...here.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: Move
to...
*
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: Move
to...
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: Move
to...
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: Move
to...
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: Move
to...
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: Move
to...
*
gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: Move
to...
* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Move to...
* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Move to...
* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Move to...
* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Move to...
* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c:
...here.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Move to...
* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c:
...here.
* gcc.target/riscv/amo/amo-table-ztso-compare-exchange-6.c: Move
to...
*
gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c:
...here.
* gcc.target/riscv/amo/amo-table-ztso-compare-exchange-3.c: Move
to...
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c:
...here.
* gcc.target/riscv/amo/amo-table-ztso-compare-exchange-2.c: Move
to...
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c:
...here.
* gcc.target/riscv/amo/amo-table-ztso-compare-exchange-1.c: Move
to...
* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c:
[gcc r15-1586] RISC-V: Add dg-remove-option for z* extensions
https://gcc.gnu.org/g:580c37f1ef7db8e7a398184eb8f5d7555124d30a
commit r15-1586-g580c37f1ef7db8e7a398184eb8f5d7555124d30a
Author: Patrick O'Neill
Date: Mon Jun 24 12:06:15 2024 -0700
RISC-V: Add dg-remove-option for z* extensions
This introduces testsuite support infra for removing extensions.
Since z* extensions don't have ordering requirements the logic for
adding/removing those extensions has also been consolidated.
This fixes RVWMO compile testcases failing on Ztso targets by removing
the extension from the -march string.
gcc/ChangeLog:
* doc/sourcebuild.texi (dg-remove-option): Add documentation.
(dg-add-option): Add documentation for riscv_{a,zaamo,zalrsc,ztso}
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Add
dg-remove-options
for ztso.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-fence-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-fence-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-fence-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-fence-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-fence-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-load-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Replace manually
specified -march string with dg-add/remove-options directives.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Ditto.
* lib/target-supports-dg.exp: Add dg-remove-options.
* lib/target-supports.exp: Add dg-remove-options and consolidate z*
extension add/remove-option code.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/doc/sourcebuild.texi | 43 +
.../gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c | 1 +
.../riscv/amo/amo-table-a-6-compare-exchange-1.c | 1 +
.../riscv/amo/amo-table-a-6-compare-exchange-2.c | 1 +
.../riscv/amo/amo-table-a-6-compare-exchange-3.c | 1 +
.../riscv/amo/amo-table-a-6-compare-exchange-4.c | 1 +
.../riscv/amo/amo-table-a-6-compare-exchange-5.c | 1 +
.../riscv/amo/amo-table-a-6-compare-exchange-6.c | 1 +
.../riscv/amo/amo-table-a-6-compare-exchange-7.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-fence-1.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-fence-2.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-fence-3.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-fence-4.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-fence-5.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-load-1.c| 1 +
.../gcc.target/riscv/amo/amo-table-a-6-load-2.c| 1 +
.../gcc.target/riscv/amo/amo-table-a-6-load-3.c| 1 +
.../gcc.target/riscv/amo/amo-table-a-6-store-1.c | 1 +
.../gcc.target/riscv/amo/amo-table-a-6-store-2.c | 1 +
.../riscv/amo/amo-table-a-6-store-compat-3.c | 1 +
.../riscv/amo/amo-table-a-6-subword-amo-add-1.c
[gcc r15-1456] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils
https://gcc.gnu.org/g:e03583e7ee99552276a90a4094776fda55ab2e02
commit r15-1456-ge03583e7ee99552276a90a4094776fda55ab2e02
Author: Patrick O'Neill
Date: Tue Jun 18 14:40:15 2024 -0700
RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils
Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify
both Zaamo and Zalrsc, promote them to 'a' in the -march string.
This does not affect testsuite results for users with old versions of
binutils.
Testcases that failed due to 'call'/isa string continue to fail after this
PATCH
when using an old version of binutils.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add 'a' extension to
riscv_combine_info.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 1dc1d9904c7b..410e673f5e01 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -401,6 +401,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
/* Combine extensions defined in this table */
static const struct riscv_ext_version riscv_combine_info[] =
{
+ {"a", ISA_SPEC_CLASS_20191213, 2, 1},
{"zk", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkn", ISA_SPEC_CLASS_NONE, 1, 0},
{"zks", ISA_SPEC_CLASS_NONE, 1, 0},
[gcc r15-1379] RISC-V: Add configure check for Zaamo/Zalrsc assembler support
https://gcc.gnu.org/g:4f18f75c5648d0b46a72f18e321bec279a6964be
commit r15-1379-g4f18f75c5648d0b46a72f18e321bec279a6964be
Author: Patrick O'Neill
Date: Mon Jun 17 09:46:05 2024 -0700
RISC-V: Add configure check for Zaamo/Zalrsc assembler support
Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure
check to prevent emitting Zaamo/Zalrsc in the arch string when the
assember does not support it.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Skip zaamo/zalrsc when not
supported by the assembler.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add zaamo/zalrsc assmeber check.
Signed-off-by: Patrick O'Neill
Acked-by: Palmer Dabbelt # RISC-V
Reviewed-by: Palmer Dabbelt # RISC-V
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 11 +++
gcc/config.in | 6 ++
gcc/configure | 31 +++
gcc/configure.ac| 5 +
4 files changed, 53 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 78dfd6b1470d..1dc1d9904c7b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -916,6 +916,7 @@ riscv_subset_list::to_string (bool version_p) const
riscv_subset_t *subset;
bool skip_zifencei = false;
+ bool skip_zaamo_zalrsc = false;
bool skip_zicsr = false;
bool i2p0 = false;
@@ -943,6 +944,10 @@ riscv_subset_list::to_string (bool version_p) const
a mistake in that binutils 2.35 supports zicsr but not zifencei. */
skip_zifencei = true;
#endif
+#ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC
+ /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */
+ skip_zaamo_zalrsc = true;
+#endif
for (subset = m_head; subset != NULL; subset = subset->next)
{
@@ -954,6 +959,12 @@ riscv_subset_list::to_string (bool version_p) const
subset->name == "zicsr")
continue;
+ if (skip_zaamo_zalrsc && subset->name == "zaamo")
+ continue;
+
+ if (skip_zaamo_zalrsc && subset->name == "zalrsc")
+ continue;
+
/* For !version_p, we only separate extension with underline for
multi-letter extension. */
if (!first &&
diff --git a/gcc/config.in b/gcc/config.in
index e41b6dc97cdd..acab3c0f1263 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -629,6 +629,12 @@
#endif
+/* Define if the assembler understands -march=rv*_zaamo_zalrsc. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_MARCH_ZAAMO_ZALRSC
+#endif
+
+
/* Define if the assembler understands -march=rv*_zifencei. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_MARCH_ZIFENCEI
diff --git a/gcc/configure b/gcc/configure
index 94970e24051f..9dc0b65dfaac 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -30820,6 +30820,37 @@ if test $gcc_cv_as_riscv_march_zifencei = yes; then
$as_echo "#define HAVE_AS_MARCH_ZIFENCEI 1" >>confdefs.h
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for
-march=rv32i_zaamo_zalrsc support" >&5
+$as_echo_n "checking assembler for -march=rv32i_zaamo_zalrsc support... " >&6;
}
+if ${gcc_cv_as_riscv_march_zaamo_zalrsc+:} false; then :
+ $as_echo_n "(cached) " >&6
+else
+ gcc_cv_as_riscv_march_zaamo_zalrsc=no
+ if test x$gcc_cv_as != x; then
+$as_echo '' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zaamo_zalrsc -o
conftest.o conftest.s >&5'
+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }
+then
+ gcc_cv_as_riscv_march_zaamo_zalrsc=yes
+else
+ echo "configure: failed program was" >&5
+ cat conftest.s >&5
+fi
+rm -f conftest.o conftest.s
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result:
$gcc_cv_as_riscv_march_zaamo_zalrsc" >&5
+$as_echo "$gcc_cv_as_riscv_march_zaamo_zalrsc" >&6; }
+if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then
+
+$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h
+
fi
;;
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 35475cf5aae3..b2243e9954aa 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5452,6 +5452,11 @@ configured with --enable-newlib-nano-formatted-io.])
[-march=rv32i_zifencei2p0],,,
[AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1,
[Define if the assembler understands -march=rv*_zifencei.])])
+gcc_GAS_CHECK_FEATURE([-march=rv32i_zaamo_zalrsc support],
+ gcc_cv_as_riscv_march_zaamo_zalrsc,
+ [-march=rv32i_zaamo_zalrsc],,,
+ [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1,
+[Define if the assembler understands
-march=rv*_zaamo_zalrsc.])])
;;
loongarch*-*-*)
[gcc r15-1302] RISC-V: Add support for subword atomic loads/stores
https://gcc.gnu.org/g:5476853b225e1327ec857ee34fdec64429af84f6 commit r15-1302-g5476853b225e1327ec857ee34fdec64429af84f6 Author: Patrick O'Neill Date: Wed Jun 12 17:10:13 2024 -0700 RISC-V: Add support for subword atomic loads/stores Andrea Parri recently pointed out that we were emitting overly conservative fences for seq_cst atomic loads/stores. This adds support for the optimized fences specified in the PSABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/2092568f7896ceaa1ec0f02569b19eaa42cd51c9/riscv-atomic.adoc gcc/ChangeLog: * config/riscv/sync-rvwmo.md: Add support for subword fenced loads/stores. * config/riscv/sync-ztso.md: Ditto. * config/riscv/sync.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Increase test coverage to include longs, shorts, chars, and bools. * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. Signed-off-by: Patrick O'Neill Tested-by: Andrea Parri Diff: --- gcc/config/riscv/sync-rvwmo.md | 24 +- gcc/config/riscv/sync-ztso.md | 20 gcc/config/riscv/sync.md | 8 ++-- .../gcc.target/riscv/amo/amo-table-a-6-load-1.c| 48 ++- .../gcc.target/riscv/amo/amo-table-a-6-load-2.c| 52 +++- .../gcc.target/riscv/amo/amo-table-a-6-load-3.c| 56 +- .../gcc.target/riscv/amo/amo-table-a-6-store-1.c | 48 ++- .../gcc.target/riscv/amo/amo-table-a-6-store-2.c | 52 +++- .../riscv/amo/amo-table-a-6-store-compat-3.c | 56 +- .../gcc.target/riscv/amo/amo-table-ztso-load-1.c | 48 ++- .../gcc.target/riscv/amo/amo-table-ztso-load-2.c | 48 ++- .../gcc.target/riscv/amo/amo-table-ztso-load-3.c | 52 +++- .../gcc.target/riscv/amo/amo-table-ztso-store-1.c | 48 ++- .../gcc.target/riscv/amo/amo-table-ztso-store-2.c | 48 ++- .../gcc.target/riscv/amo/amo-table-ztso-store-3.c | 52 +++- 15 files changed, 610 insertions(+), 50 deletions(-) diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index e639a1e23924..5db94c8c27fa 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -47,9 +47,9 @@ ;; Atomic memory operations. (define_insn "atomic_load_rvwmo" - [(set (match_operand:GPR 0 "register_operand" "=r") - (unspec_volatile:GPR - [(match_operand:GPR 1 "memory_operand" "A") + [(set (match_operand:ANYI 0 "register_operand" "=r") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_LOAD))] "!TARGET_ZTSO" @@ -59,13 +59,13 @@ if (model == MEMMODEL_SEQ_CST) return "fence\trw,rw\;" -"l\t%0,%1\;" +"\t%0,%1\;" "fence\tr,rw"; if (model == MEMMODEL_ACQUIRE) - return "l\t%0,%1\;" + return "\t%0,%1\;" "fence\tr,rw"; else - return "l\t%0,%1"; + return "\t%0,%1"; } [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) @@ -73,9 +73,9 @@ ;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store_rvwmo" - [(set (match_operand:GPR 0 "memory_operand" "=A") - (unspec_volatile:GPR - [(match_operand:GPR 1 "reg_or_0_operand" "rJ") + [(set (match_operand:ANYI 0 "memory_operand" "=A") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "!TARGET_ZTSO" @@ -85,13 +85,13 @@ if (model == MEMMODEL_SEQ_CST) return "fence\trw,w\;" -"s\t%z1,%0\;" +"\t%z1,%0\;" "fence\trw,rw"; if (model == MEMMODEL_RELEASE) return "fence\trw,w\;" -"s\t%z1,%0"; +"\t%z1,%0"; else - return "s\t%z1,%0"; + return
[gcc r15-1221] Whitespace cleanup for target-supports.exp
https://gcc.gnu.org/g:eaff4d6714805ba2504270dfff51fca61854542d
commit r15-1221-geaff4d6714805ba2504270dfff51fca61854542d
Author: Patrick O'Neill
Date: Wed Jun 12 11:33:11 2024 -0700
Whitespace cleanup for target-supports.exp
This patch removes trailing whitespace and replaces leading groups of 8-16
spaces with tabs.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Cleanup whitespace.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 1168 -
1 file changed, 584 insertions(+), 584 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index e862a8932449..e307f4e69efb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -28,7 +28,7 @@
# If ARGS is not empty, its first element is a string that
# should be added to the command line.
#
-# Assume by default that CONTENTS is C code.
+# Assume by default that CONTENTS is C code.
# Otherwise, code should contain:
# "/* Assembly" for assembly code,
# "// C++" for c++,
@@ -39,12 +39,12 @@
# "// Go" for Go
# "// Rust" for Rust
# and "(* Modula-2" for Modula-2
-# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
+# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
# allow for ObjC/ObjC++ specific flags.
proc check_compile {basename type contents args} {
global tool
-verbose "check_compile tool: $tool for $basename"
+verbose "check_compile tool: $tool for $basename"
# Save additional_sources to avoid compiling testsuite's sources
# against check_compile's source.
@@ -100,7 +100,7 @@ proc check_compile {basename type contents args} {
global compiler_flags
set save_compiler_flags $compiler_flags
set lines [${tool}_target_compile $src $output $compile_type "$options"]
-set compiler_flags $save_compiler_flags
+set compiler_flags $save_compiler_flags
file delete $src
set scan_output $output
@@ -280,8 +280,8 @@ proc check_configured_with { pattern } {
set options [list "additional_flags=-v"]
set gcc_output [${tool}_target_compile "" "" "none" $options]
if { [ regexp "Configured with: \[^\n\]*$pattern" $gcc_output ] } {
-verbose "Matched: $pattern" 2
-return 1
+ verbose "Matched: $pattern" 2
+ return 1
}
verbose "Failed to match: $pattern" 2
@@ -301,19 +301,19 @@ proc check_weak_available { } {
# All mips targets should support it
if { [ string first "mips" $target_cpu ] >= 0 } {
-return 1
+ return 1
}
# All AIX targets should support it
if { [istarget *-*-aix*] } {
-return 1
+ return 1
}
# All solaris2 targets should support it
if { [istarget *-*-solaris2*] } {
-return 1
+ return 1
}
# Windows targets Cygwin and MingW32 support it
@@ -346,13 +346,13 @@ proc check_weak_available { } {
set objformat [gcc_target_object_format]
switch $objformat {
-elf { return 1 }
-ecoff{ return 1 }
-a.out{ return 1 }
+ elf { return 1 }
+ ecoff{ return 1 }
+ a.out{ return 1 }
mach-o { return 1 }
som { return 1 }
-unknown { return -1 }
-default { return 0 }
+ unknown { return -1 }
+ default { return 0 }
}
}
@@ -414,31 +414,31 @@ proc check_effective_target_vma_equals_lma { } {
if [string match "" $lines] then {
# No error messages
-set objdump_name [find_binutils_prog objdump]
-set output [remote_exec host "$objdump_name" "--section-headers
--section=.data $exe"]
-set output [lindex $output 1]
-
-remote_file build delete $exe
-
-# Example output of objdump:
-#vma_equals_lma9059.exe: file format elf32-littlearm
-#
-#Sections:
-#Idx Name Size VMA LMA File off Algn
-# 6 .data 0558 2000 08002658 0002 2**3
-# CONTENTS, ALLOC, LOAD, DATA
-
-# Capture LMA and VMA columns for .data section
-if ![ regexp {\d*\d+\s+\.data\s+\d+\s+(\d+)\s+(\d+)} $output dummy
vma lma ] {
-verbose "Could not parse objdump output" 2
-return 0
-} else {
-return [string equal $vma $lma]
-}
+ set objdump_name [find_binutils_prog objdump]
+ set output [remote_exec host "$objdump_name" "--section-headers
--section=.data $exe"]
+ set output [lindex $output 1]
+
+ remote_file build delete $exe
+
+ # Example output of objdump:
+ #vma_equals_lma9059.exe: file format elf32-littlearm
+ #
+ #Sections:
+ #Idx Name Size VMA
[gcc r15-1219] RISC-V: Allow any temp register to be used in amo tests
https://gcc.gnu.org/g:439c0cc9f7f6e83b898cabbd2e34f98484b432d3 commit r15-1219-g439c0cc9f7f6e83b898cabbd2e34f98484b432d3 Author: Patrick O'Neill Date: Mon Jun 10 17:00:38 2024 -0700 RISC-V: Allow any temp register to be used in amo tests We artifically restrict the temp registers to be a[0-9]+ when other registers like t[0-9]+ are valid too. Update to make the regex accept any register for the temp value. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo/amo-table-a-6-load-1.c: Update temp register regex. * gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto. * gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto. Signed-off-by: Patrick O'Neill Diff: --- gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c | 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c | 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c| 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c| 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c | 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c| 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c| 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c| 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c | 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c | 4 ++-- gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c | 4 ++-- 12 files changed, 24 insertions(+), 24 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c index 3c79035e46d6..53dd52344527 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c @@ -6,8 +6,8 @@ /* ** foo: -** lw\ta[0-9]+,0\(a0\) -** sw\ta[0-9]+,0\(a1\) +** lw\t[atx][0-9]+,0\(a0\) +** sw\t[atx][0-9]+,0\(a1\) ** ret */ void foo (int* bar, int* baz) diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c index 7d74841846fa..dda0f5415156 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c @@ -6,9 +6,9 @@ /* ** foo: -** lw\ta[0-9]+,0\(a0\) +** lw\t[atx][0-9]+,0\(a0\) ** fence\tr,rw -** sw\ta[0-9]+,0\(a1\) +** sw\t[atx][0-9]+,0\(a1\) ** ret */ void foo (int* bar, int* baz) diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c index ab95fa660d25..3279557fa4a9 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c @@ -7,9 +7,9 @@ /* ** foo: ** fence\trw,rw -** lw\ta[0-9]+,0\(a0\) +** lw\t[atx][0-9]+,0\(a0\) ** fence\tr,rw -** sw\ta[0-9]+,0\(a1\) +** sw\t[atx][0-9]+,0\(a1\) ** ret */ void foo (int* bar, int* baz) diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c index d852fddf03de..6b05429520bf 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c @@ -6,8 +6,8 @@ /* ** foo: -** lw\ta[0-9]+,0\(a1\) -** sw\ta[0-9]+,0\(a0\) +** lw\t[atx][0-9]+,0\(a1\) +** sw\t[atx][0-9]+,0\(a0\) ** ret */ void foo (int* bar, int* baz) diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c index ccb5e2af7cc1..1ad7dede931b 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c +++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c @@ -6,9 +6,9 @@ /* ** foo: -** lw\ta[0-9]+,0\(a1\) +** lw\t[atx][0-9]+,0\(a1\) ** fence\trw,w -** sw\ta[0-9]+,0\(a0\) +** sw\t[atx][0-9]+,0\(a0\) ** ret */ void foo (int* bar, int* baz) diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c
[gcc r15-1218] RISC-V: Fix amoadd call arguments
https://gcc.gnu.org/g:6343adcef7de1a1214c9b6dd845810aa4a0d19e5
commit r15-1218-g6343adcef7de1a1214c9b6dd845810aa4a0d19e5
Author: Patrick O'Neill
Date: Mon Jun 10 16:58:12 2024 -0700
RISC-V: Fix amoadd call arguments
Update __atomic_add_fetch arguments to be a pointer and value rather
than two pointers.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Update
__atomic_add_fetch args.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Ditto.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c | 2 +-
26 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c
b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c
index 9c2ba39789ae..2e53abf28aa2 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c
@@ -10,7 +10,7 @@
** amoadd\.w\tzero,a1,0\(a0\)
** ret
*/
-void foo (int* bar, int* baz)
+void foo (int* bar, int baz)
{
__atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
}
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c
[gcc r15-1217] RISC-V: Move amo tests into subfolder
https://gcc.gnu.org/g:8c944f2559ff279ed7e04c2a75881c04c0c31a9b commit r15-1217-g8c944f2559ff279ed7e04c2a75881c04c0c31a9b Author: Patrick O'Neill Date: Mon Jun 10 16:32:11 2024 -0700 RISC-V: Move amo tests into subfolder There's a large number of atomic related testcases in the riscv folder. Move them into a subfolder similar to what was done for rvv testcases. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: ...here. * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: ...here. * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: ...here. * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: ...here. * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: ...here. * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: ...here. * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: ...here. * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: ...here. * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: ...here. * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: ...here. * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: ...here. * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: ...here. * gcc.target/riscv/amo-table-a-6-fence-1.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-fence-1.c: ...here. * gcc.target/riscv/amo-table-a-6-fence-2.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-fence-2.c: ...here. * gcc.target/riscv/amo-table-a-6-fence-3.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-fence-3.c: ...here. * gcc.target/riscv/amo-table-a-6-fence-4.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-fence-4.c: ...here. * gcc.target/riscv/amo-table-a-6-fence-5.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-fence-5.c: ...here. * gcc.target/riscv/amo-table-a-6-load-1.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-load-1.c: ...here. * gcc.target/riscv/amo-table-a-6-load-2.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-load-2.c: ...here. * gcc.target/riscv/amo-table-a-6-load-3.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-load-3.c: ...here. * gcc.target/riscv/amo-table-a-6-store-1.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-store-1.c: ...here. * gcc.target/riscv/amo-table-a-6-store-2.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-store-2.c: ...here. * gcc.target/riscv/amo-table-a-6-store-compat-3.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: ...here. * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: ...here. * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: ...here. * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: ...here. * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: ...here. * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Move to... * gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: ...here. * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Move to... * gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: ...here. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Move to... * gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: ...here. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Move to... * gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: ...here. * gcc.target/riscv/amo-table-ztso-amo-add-4.c:
[gcc r15-1186] RISC-V: Add Zalrsc amo-op patterns
https://gcc.gnu.org/g:1588983be6112561c805a50eb7a3c585865beffa
commit r15-1186-g1588983be6112561c805a50eb7a3c585865beffa
Author: Patrick O'Neill
Date: Wed Feb 7 16:30:30 2024 -0800
RISC-V: Add Zalrsc amo-op patterns
All amo patterns can be represented with lrsc sequences.
Add these patterns as a fallback when Zaamo is not enabled.
gcc/ChangeLog:
* config/riscv/sync.md (atomic_): New expand
pattern.
(amo_atomic_): Rename amo pattern.
(atomic_fetch_): New lrsc sequence pattern.
(lrsc_atomic_): New expand pattern.
(amo_atomic_fetch_): Rename amo pattern.
(lrsc_atomic_fetch_): New lrsc sequence pattern.
(atomic_exchange): New expand pattern.
(amo_atomic_exchange): Rename amo pattern.
(lrsc_atomic_exchange): New lrsc sequence pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test.
* gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/config/riscv/sync.md | 124 -
.../riscv/amo-zaamo-preferred-over-zalrsc.c| 17 +++
.../gcc.target/riscv/amo-zalrsc-amo-add-1.c| 19
.../gcc.target/riscv/amo-zalrsc-amo-add-2.c| 19
.../gcc.target/riscv/amo-zalrsc-amo-add-3.c| 19
.../gcc.target/riscv/amo-zalrsc-amo-add-4.c| 19
.../gcc.target/riscv/amo-zalrsc-amo-add-5.c| 19
7 files changed, 231 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index c9544176ead5..4df9d0b5a5ff 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -86,7 +86,24 @@
DONE;
})
-(define_insn "atomic_"
+;; AMO ops
+
+(define_expand "atomic_"
+ [(any_atomic:GPR (match_operand:GPR 0 "memory_operand");; mem location
+ (match_operand:GPR 1 "reg_or_0_operand")) ;; value for op
+ (match_operand:SI 2 "const_int_operand")];; model
+ "TARGET_ZAAMO || TARGET_ZALRSC"
+{
+ if (TARGET_ZAAMO)
+emit_insn (gen_amo_atomic_ (operands[0], operands[1],
+ operands[2]));
+ else
+emit_insn (gen_lrsc_atomic_ (operands[0], operands[1],
+operands[2]));
+ DONE;
+})
+
+(define_insn "amo_atomic_"
[(set (match_operand:GPR 0 "memory_operand" "+A")
(unspec_volatile:GPR
[(any_atomic:GPR (match_dup 0)
@@ -98,7 +115,44 @@
[(set_attr "type" "atomic")
(set (attr "length") (const_int 4))])
-(define_insn "atomic_fetch_"
+(define_insn "lrsc_atomic_"
+ [(set (match_operand:GPR 0 "memory_operand" "+A")
+ (unspec_volatile:GPR
+ [(any_atomic:GPR (match_dup 0)
+(match_operand:GPR 1 "reg_or_0_operand" "rJ"))
+ (match_operand:SI 2 "const_int_operand")] ;; model
+UNSPEC_SYNC_OLD_OP))
+ (clobber (match_scratch:GPR 3 "="))] ;; tmp_1
+ "!TARGET_ZAAMO && TARGET_ZALRSC"
+ {
+return "1:\;"
+ "lr.%I2\t%3, %0\;"
+ "\t%3, %3, %1\;"
+ "sc.%J2\t%3, %3, %0\;"
+ "bnez\t%3, 1b";
+ }
+ [(set_attr "type" "atomic")
+ (set (attr "length") (const_int 16))])
+
+;; AMO fetch ops
+
+(define_expand "atomic_fetch_"
+ [(match_operand:GPR 0 "register_operand") ;; old value at mem
+ (any_atomic:GPR (match_operand:GPR 1 "memory_operand");; mem location
+ (match_operand:GPR 2 "reg_or_0_operand")) ;; value for op
+ (match_operand:SI 3 "const_int_operand")];; model
+ "TARGET_ZAAMO || TARGET_ZALRSC"
+ {
+if (TARGET_ZAAMO)
+ emit_insn (gen_amo_atomic_fetch_ (operands[0],
operands[1],
+ operands[2],
operands[3]));
+else
+ emit_insn (gen_lrsc_atomic_fetch_ (operands[0],
operands[1],
+operands[2],
operands[3]));
+DONE;
+ })
+
+(define_insn "amo_atomic_fetch_"
[(set (match_operand:GPR 0 "register_operand" "=")
(match_operand:GPR 1 "memory_operand" "+A"))
(set (match_dup 1)
@@ -112,6 +166,27 @@
[(set_attr "type" "atomic")
(set (attr "length") (const_int 4))])
+(define_insn "lrsc_atomic_fetch_"
+ [(set (match_operand:GPR 0 "register_operand" "=")
+ (match_operand:GPR 1 "memory_operand" "+A"))
+ (set (match_dup 1)
+ (unspec_volatile:GPR
+ [(any_atomic:GPR (match_dup 1)
+(match_operand:GPR 2 "reg_or_0_operand" "rJ"))
+ (match_operand:SI 3
[gcc r15-1185] RISC-V: Add Zalrsc and Zaamo testsuite support
https://gcc.gnu.org/g:0fea902b1b5311c8b34ae8e789f1733bd8429904 commit r15-1185-g0fea902b1b5311c8b34ae8e789f1733bd8429904 Author: Patrick O'Neill Date: Mon Jun 10 14:12:40 2024 -0700 RISC-V: Add Zalrsc and Zaamo testsuite support Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A. gcc/ChangeLog: * doc/sourcebuild.texi: Add docs for atomic extension testsuite infra. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A. * gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather than A. * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto. * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather than A. * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc rather than A. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto. * lib/target-supports.exp: Add testsuite infrastructure support for Zaamo and Zalrsc. Signed-off-by: Patrick O'Neill Diff: --- gcc/doc/sourcebuild.texi | 16 +++- .../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 2 +- .../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 2 +- .../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 2 +- .../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 2 +- .../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-1.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-2.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-3.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-4.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-5.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-6.c | 2 +- .../riscv/amo-table-a-6-compare-exchange-7.c | 2 +- .../riscv/amo-table-a-6-subword-amo-add-1.c| 2 +- .../riscv/amo-table-a-6-subword-amo-add-2.c| 2 +- .../riscv/amo-table-a-6-subword-amo-add-3.c| 2 +- .../riscv/amo-table-a-6-subword-amo-add-4.c| 2 +- .../riscv/amo-table-a-6-subword-amo-add-5.c| 2 +- .../gcc.target/riscv/amo-table-ztso-amo-add-1.c| 2 +- .../gcc.target/riscv/amo-table-ztso-amo-add-2.c| 2 +- .../gcc.target/riscv/amo-table-ztso-amo-add-3.c| 2 +- .../gcc.target/riscv/amo-table-ztso-amo-add-4.c| 2 +- .../gcc.target/riscv/amo-table-ztso-amo-add-5.c| 2 +- .../riscv/amo-table-ztso-compare-exchange-1.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-2.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-3.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-4.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-5.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-6.c | 2 +- .../riscv/amo-table-ztso-compare-exchange-7.c | 2 +-
[gcc r15-1184] RISC-V: Add basic Zaamo and Zalrsc support
https://gcc.gnu.org/g:af139b3fc19fbdd7caa649bcb2cb75cc5a254143
commit r15-1184-gaf139b3fc19fbdd7caa649bcb2cb75cc5a254143
Author: Edwin Lu
Date: Wed Feb 7 16:30:28 2024 -0800
RISC-V: Add basic Zaamo and Zalrsc support
There is a proposal to split the A extension into two parts: Zaamo and
Zalrsc.
This patch adds basic support by making the A extension imply Zaamo and
Zalrsc.
Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
* config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
* config/riscv/riscv.opt: Add Zaamo and Zalrsc
* config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
TARGET_ZALRSC.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/attribute-15.c: Adjust expected arch string.
* gcc.target/riscv/attribute-16.c: Ditto.
* gcc.target/riscv/attribute-17.c: Ditto.
* gcc.target/riscv/attribute-18.c: Ditto.
* gcc.target/riscv/pr110696.c: Ditto.
* gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.
Signed-off-by: Edwin Lu
Co-authored-by: Patrick O'Neill
Diff:
---
gcc/common/config/riscv/riscv-common.cc| 11 ++--
gcc/config/riscv/arch-canonicalize | 1 +
gcc/config/riscv/riscv.opt | 6 -
gcc/config/riscv/sync.md | 30 +++---
gcc/testsuite/gcc.target/riscv/attribute-15.c | 2 +-
gcc/testsuite/gcc.target/riscv/attribute-16.c | 2 +-
gcc/testsuite/gcc.target/riscv/attribute-17.c | 2 +-
gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +-
gcc/testsuite/gcc.target/riscv/pr110696.c | 2 +-
.../gcc.target/riscv/rvv/base/pr114352-1.c | 4 +--
.../gcc.target/riscv/rvv/base/pr114352-3.c | 8 +++---
11 files changed, 41 insertions(+), 29 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 88204393fde0..78dfd6b1470d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"f", "zicsr"},
{"d", "zicsr"},
+ {"a", "zaamo"},
+ {"a", "zalrsc"},
+
{"zdinx", "zfinx"},
{"zfinx", "zicsr"},
{"zdinx", "zicsr"},
@@ -255,6 +258,8 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"za64rs", ISA_SPEC_CLASS_NONE, 1, 0},
{"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
{"zicond", _options::x_riscv_zi_subext, MASK_ZICOND},
- {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
+ {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
{"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
- {"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
+ {"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
+ {"zaamo", _options::x_riscv_za_subext, MASK_ZAAMO},
+ {"zalrsc", _options::x_riscv_za_subext, MASK_ZALRSC},
{"zba",_options::x_riscv_zb_subext, MASK_ZBA},
{"zbb",_options::x_riscv_zb_subext, MASK_ZBB},
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index 8f7d040cdeb9..6c10d1aa81b5 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
#
IMPLIED_EXT = {
"d" : ["f", "zicsr"],
+ "a" : ["zaamo", "zalrsc"],
"f" : ["zicsr"],
"zdinx" : ["zfinx", "zicsr"],
"zfinx" : ["zicsr"],
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 78cb1c37e69f..b13e993c47a2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -256,7 +256,11 @@ Mask(ZICCRSE) Var(riscv_zi_subext)
TargetVariable
int riscv_za_subext
-Mask(ZAWRS) Var(riscv_za_subext)
+Mask(ZAWRS) Var(riscv_za_subext)
+
+Mask(ZAAMO) Var(riscv_za_subext)
+
+Mask(ZALRSC) Var(riscv_za_subext)
Mask(ZA64RS) Var(riscv_za_subext)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 6f0b5aae08dc..c9544176ead5 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -93,7 +93,7 @@
(match_operand:GPR 1 "reg_or_0_operand" "rJ"))
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
- "TARGET_ATOMIC"
+ "TARGET_ZAAMO"
"amo.%A2\tzero,%z1,%0"
[(set_attr "type" "atomic")
(set (attr "length") (const_int 4))])
[gcc r15-116] RISC-V: Add testcase for pr114734
https://gcc.gnu.org/g:ff4dc8b10a421cdb0c56f7f8c238609de4f9fbe2
commit r15-116-gff4dc8b10a421cdb0c56f7f8c238609de4f9fbe2
Author: Patrick O'Neill
Date: Tue Apr 30 13:26:45 2024 -0700
RISC-V: Add testcase for pr114734
gcc/testsuite/ChangeLog:
PR middle-end/114734
* gcc.target/riscv/rvv/autovec/pr114734.c: New test.
Signed-off-by: Patrick O'Neill
Diff:
---
.../gcc.target/riscv/rvv/autovec/pr114734.c| 25 ++
1 file changed, 25 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
new file mode 100644
index 000..b605d992aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -O3
-mrvv-vector-bits=zvl } } */
+
+int f[18];
+int g[18];
+int h[18][18][18];
+int a[324];
+long b[18];
+int *i = g;
+int (*j)[18][18] = h;
+int z;
+int main() {
+ for (int m = 0; m < 18; ++m)
+f[m] = 3;
+ for (int m = 0; m < 18; m += 1)
+for (int n = 0; n < 18; n += 3) {
+ a[m * 8 + n] = j[m][m][0] ? i[n] : 0;
+ b[n] = f[n] ? -i[m] : 0;
+}
+ for (long n = 0; n < 8; ++n)
+z = a[n];
+ if (b[15] != 0)
+__builtin_abort();
+}
[gcc r14-9628] RISC-V: Require a extension for ztso testcases with atomic insns
https://gcc.gnu.org/g:65107faad79354a75844d8dba053be6509200504
commit r14-9628-g65107faad79354a75844d8dba053be6509200504
Author: Patrick O'Neill
Date: Thu Mar 21 09:47:21 2024 -0700
RISC-V: Require a extension for ztso testcases with atomic insns
Use dg_add_options riscv_a to add atomic extension when running compile
tests on non-a targets.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add
dg_add_options riscv_a
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c | 1 +
gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c | 1 +
17 files changed, 17 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
index 65a4351025d..a9edc33ff39 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings match the Ztso suggested mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-add-options riscv_ztso } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
index 03da6b04de0..ad843402bcc 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings the Ztso suggested mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-add-options riscv_ztso } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
index 695306e9d6f..bdae5bb83a6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* Verify that atomic op mappings match the Ztso suggested mapping. */
/* { dg-options "-O3" } */
+/* { dg-add-options riscv_a } */
/* { dg-add-options riscv_ztso } */
/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
/* { dg-final { check-function-bodies "**" "" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
index
