Re: How to implement conditional execution
On Friday 27 June 2008, Julian Brown wrote: On Fri, 27 Jun 2008 15:52:22 +0530 Mohamed Shafi [EMAIL PROTECTED] wrote: If the condition in the 'if' instruction is satisfied the processor will execute the next instruction or it will replace with a nop. So this means that i can instructions similar to: if eq Rx, Ry add Rx, Ry add Rx, 2 Will it be possible to implement this in the Gcc backend ? Does any other targets have similar instructions? This is very much like (a simpler version of) the ARM Thumb-2 IT instruction. Look how config/arm/thumb2.md handles that. I think the basic idea should be that you should define conditional instruction patterns which emit assembly for both instructions simultaneously. Not quite. For Thumb-2 we describe most instruction as having conditional variants using define_cond_exec. Then arrange for the necessary IfThen instructions to be generated via ASM_OUTPUT_OPCODE. Multiple assembly instructions from the same pattern are either a historical leftover, or when it's inconvenient to describe the operation with proper cond_exec RTL. Thumb-2 is a bit different to the machine described above because because the conditional execution is based on the condition code register, with the comparison occurring as a separate instruction, and the IT instruction can skip multiple subsequent instructions. I'd expect the same technique to be applicable though. Paul
Re: How to implement conditional execution
On Fri, Jun 27, 2008 at 03:52:22PM +0530, Mohamed Shafi wrote: Hello all, For the 16-bit target that i porting now to gcc 4.1.2 doesn't have any branch instructions. It only has jump instructions. For comparison operation it has this instruction: if cond Rx Ry execute this insn So compare and branch is implemented as if cond Rx Ry jmp Label If the condition in the 'if' instruction is satisfied the processor will execute the next instruction or it will replace with a nop. So this means that i can instructions similar to: if eq Rx, Ry add Rx, Ry add Rx, 2 This is similar to conditional execution. This way any instruction can be executed conditionally. But this is different from normal. Normally the comparison operations set the status flags. An instruction gets conditionally executed based on these flags. This means that GCC can schedule instructions between the comparison instruction and the conditional instruction, provided none of the scheduled instructions are altering the status flags. This is not possible in my case as there shouldn't be any instruction between 'if eq Rx, Ry' and 'add Rx, Ry' and this is not as such an comparison operation and 'if' instruction doesn't set any status flags. Will it be possible to implement this in the Gcc backend ? Does any other targets have similar instructions? This is do-able. The usual method is to store the operands to the comparison in global variables, and then when you issue the branch, conditional move, etc. use the global variables, and recreate appropriate branch. Be sure to mark the global variables with the GTY(()) macro. I would suggest having the JUMP insn patterns look like other ports, using the IF_THEN_ELSE pattern, and then add the full COND_EXEC support. -- Michael Meissner email: [EMAIL PROTECTED] http://www.the-meissners.org
How to implement conditional execution
Hello all, For the 16-bit target that i porting now to gcc 4.1.2 doesn't have any branch instructions. It only has jump instructions. For comparison operation it has this instruction: if cond Rx Ry execute this insn So compare and branch is implemented as if cond Rx Ry jmp Label If the condition in the 'if' instruction is satisfied the processor will execute the next instruction or it will replace with a nop. So this means that i can instructions similar to: if eq Rx, Ry add Rx, Ry add Rx, 2 This is similar to conditional execution. This way any instruction can be executed conditionally. But this is different from normal. Normally the comparison operations set the status flags. An instruction gets conditionally executed based on these flags. This means that GCC can schedule instructions between the comparison instruction and the conditional instruction, provided none of the scheduled instructions are altering the status flags. This is not possible in my case as there shouldn't be any instruction between 'if eq Rx, Ry' and 'add Rx, Ry' and this is not as such an comparison operation and 'if' instruction doesn't set any status flags. Will it be possible to implement this in the Gcc backend ? Does any other targets have similar instructions? Regards, Shafi
Re: How to implement conditional execution
On Fri, 27 Jun 2008 15:52:22 +0530 Mohamed Shafi [EMAIL PROTECTED] wrote: If the condition in the 'if' instruction is satisfied the processor will execute the next instruction or it will replace with a nop. So this means that i can instructions similar to: if eq Rx, Ry add Rx, Ry add Rx, 2 Will it be possible to implement this in the Gcc backend ? Does any other targets have similar instructions? This is very much like (a simpler version of) the ARM Thumb-2 IT instruction. Look how config/arm/thumb2.md handles that. I think the basic idea should be that you should define conditional instruction patterns which emit assembly for both instructions simultaneously, e.g. (excuse my pseudocode): (define_insn ... [(...)] if eq Rx, Ry\;add Rx, Ry) then there's no possibility for scheduling or other optimisations to split the second instruction away from the first. Julian
