[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer

[aries.nah at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413

--- Comment #1 from Anatoly  2011-09-15 08:44:57 
UTC ---
Created attachment 25289
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=25289
C++ source code

[Bug tree-optimization/50413] New: Incorrect instruction is used to shift value of 128 bit xmm0 registrer

[aries.nah at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413

 Bug #: 50413
   Summary: Incorrect instruction is used to shift value of 128
bit xmm0 registrer
Classification: Unclassified
   Product: gcc
   Version: 4.6.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: tree-optimization
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: aries@gmail.com


After compilation an attached code with -O2 and -ftree-vectorize flags, it
doesn't work properly.

Assembler code shows that G++ tries to replace the following code 

  V.uint128.uint64_lower = (V.uint128.uint64_lower >> 1);
  V.bitmap.b63 = V.bitmap.b64;
  V.uint128.uint64_upper = (V.uint128.uint64_upper >> 1);

with SSE instructions:

  400a10:   movdqa 0x103d8(%rip),%xmm0# 410df0 
  400a17:   and$0x1,%edi
  400a1b:   psrlq  $0x1,%xmm0
  400a20:   movdqa %xmm0,0x103c8(%rip)# 410df0 


But psrlq shifts 64 bit value, it's necessary to use psrldq here

[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer

[aries.nah at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413

--- Comment #2 from Anatoly  2011-09-15 09:05:03 
UTC ---
Forgot to mention: Intel(R) Core(TM) i5 CPU 760 @ 2.80GHz LGA1156
And there's no such bug in GCC 4.3.4

[Bug tree-optimization/50413] Incorrect instruction is used to shift value of 128 bit xmm0 registrer

[aries.nah at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50413

Anatoly  changed:

   What|Removed |Added

 Status|RESOLVED|UNCONFIRMED
 Resolution|INVALID |

--- Comment #4 from Anatoly  2011-09-15 13:42:05 
UTC ---
It's not serious. 
Yes, I'm not an expert in SSE instructions (and in ASM at all), and it seems
you're right about shifting.
But, the bug is a real. GCC losts lower bit of upper quadword during shifting
by psrlq.
Try to compile my code and check it out.

We have V.bitmap.b63 = V.bitmap.b64; to shift a lower bit of the upper quadword
but GCC has decided not to do this.