[Bug c/39393] New: invalid instructions accepted in inline assembly language on 32 bit machines
On an x86_64 bit machine, if an attempt to compile code containing an invalid
instruction is attempted, an error will correctly occur:
cat /etc/testasm.c
int main(void)
{
asm(cpuid); /* Invalid on the i386 */
}
gcc -march=i386 -Wa,-march=i386 testasm.c
Error: `cpuid' is not supported on `i386'
However on a 32 bit machine, the error trap does not occur, and the invalid
instruction ends up producing an invalid binary file:
gcc -march=i386 -Wa,-march=i386 testasm.c
No error occurs and invalid opcodes are placed in the resultant binary.
--
Summary: invalid instructions accepted in inline assembly
language on 32 bit machines
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: markhobley at yahoo dot co dot uk
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39393
[Bug inline-asm/39393] invalid instructions accepted in inline assembly language on 32 bit machines
--- Comment #3 from markhobley at yahoo dot co dot uk 2009-03-07 02:40 --- Subject: Re: invalid instructions accepted in inline assembly language on 32 bit machines --- On Sat, 7/3/09, hjl dot tools at gmail dot com gcc-bugzi...@gcc.gnu.org wrote: I got h...@gnu-9 tmp]$ gcc -march=i386 -Wa,-march=i386 a.c /tmp/cciG1xw8.s: Assembler messages: /tmp/cciG1xw8.s:17: Error: `cpuid' is not supported on `i386' on Linux/ia32 with the current Linux binutils. Hmmm. There is definitely something weird going on. My machines do not error, even with the latest binutils. Maybe there is some problem with a library or with some configuration option that is not being made effective on my machine, causing the error trap to skip somehow. I am conducting further tests on this. Mark. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39393
[Bug target/38959] Additional switches to disallow processor supplementary instructions
--- Comment #2 from markhobley at yahoo dot co dot uk 2009-01-27 00:36 --- Subject: Re: Additional switches to disallow processor supplementary instructions --- Comment #1 from pinskia at gcc dot gnu dot org 2009-01-26 19:15 --- I think this is a bad idea. Also most if not all x86 CPUs released in the last 10 years support these instructions These instructions make the binaries non-portable, The switches aid portability. You do not have to apply these. If the switches are not applied, the compiler behaves exactly as it does now, so the compiled code remains the same, if required. The advantage of the switches is that they can be used to enable system builders to trap invalid instructions at compile time, rather than waiting for reports of system crashes at runtime. Applying the fix has no detrimental effects to anyone, since the compiler behaves as it does now. However the fix does benefit people wanting to produce portable code. Mark. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38959
[Bug inline-asm/38959] New: Additional switches to disallow processor supplementary instructions
This is a proposal for additional switches to be included on the command line to prevent inclusion of processor supplementary instructions. This enhancement provides greater support for compilation of code to be utilized between different generations of CPU. Proposed switches: --nocpuid This option causes the compiler to not generate cpuid opcodes --nocmov This option causes the compiler to not generate cmov opcodes --nofcmov This option causes the compiler to not generate fcmov opcodes --nofcomi This option causes the compiler to not generate fcomi opcodes --nonopl This option causes the compiler to not generate fcomi opcodes --nordpmc This option causes the compiler to not generate rdpmc opcodes --nordtsc This option causes the compiler to not generate rdtsc opcodes Possibly a general switch that is equivalent to all of the above --nosupplementaryinstructions Rationale It is possible that a developer still wants to compile for a particular architecture (for example the i486), but does not wish to generate code with supplementary instructions (such as cpuid), that may be present on that architecture. -- Summary: Additional switches to disallow processor supplementary instructions Product: gcc Version: unknown Status: UNCONFIRMED Severity: enhancement Priority: P3 Component: inline-asm AssignedTo: unassigned at gcc dot gnu dot org ReportedBy: markhobley at yahoo dot co dot uk http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38959
