[Bug c++/85533] Missing optimization for right-shift of unsigned int (avr-g++)

[randy.brecker64 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85533

Randy Brecker  changed:

   What|Removed |Added

 Target|avr |x86 avr
 Status|RESOLVED|VERIFIED
Version|7.3.0   |8.0.1

--- Comment #3 from Randy Brecker  ---
This is also true von x86_64, where we get:

   movzbl  x(%rip), %eax
sarl%eax
movb%al, x(%rip)
movzbl  y(%rip), %eax
shrb%al
movb%al, y(%rip)
xorl%eax, %eax

Looks like a FE bug here.

[Bug c++/82658] Suboptimal codegen on AVR when right-shifting 8-bit unsigned integers.

[randy.brecker64 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82658

--- Comment #5 from Randy Brecker  ---
I confirm this is still true for x86 (!) with gcc-7.3.1 and gcc-8.0.1 in
language-mode c++.

[Bug c++/85533] New: Missing optimization for right-shift of unsigned int (avr-g++)

[randy.brecker64 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85533

Bug ID: 85533
   Summary: Missing optimization for right-shift of unsigned int
(avr-g++)
   Product: gcc
   Version: 7.3.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: c++
  Assignee: unassigned at gcc dot gnu.org
  Reporter: randy.brecker64 at gmail dot com
  Target Milestone: ---

If the following snippet is compiled as C++-Code

volatile unsigned char x;
volatile unsigned char y;

int main() {
x >>= 1;
y /= 2;
}

it gives the assembler code:

   lds r24,x;  x.0_1, x
ldi r25,0;  x.0_1
asr r25  ;  tmp50
ror r24  ;  tmp50
sts x,r24;  x, tmp50
lds r24,y;  y.1_5, y
lsr r24  ;  _6
sts y,r24;  y, _6

If it is compiled as C-Code it gives a better optimizatoion for the right
shift:

   lds r24,x;  x.0_1, x
lsr r24  ;  _2
sts x,r24;  x, _2
lds r24,y;  y.1_3, y
lsr r24  ;  _4
sts y,r24;  y, _4